CHAPTER 10

PLC Math
Instructions

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Chapter Outline
10.1 Addition
10.2 Subtraction
10.3 Multiplication
10.4 Division
10.5 Advanced Math Instructions
10.6 LogixPro Simulator Examples terekhov igor/Shutterstock.com

Technical Terms
add (ADD) instruction
divide (DIV) instruction
P multiply (MUL) instruction
subtract (SUB) instruction
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Learning Objectives
After completing this chapter, you will be able to:
• Program the add instruction in the PLC ladder logic diagram.
A

• Program the subtract instruction in the PLC ladder logic diagram.

• Program the multiply instruction in the PLC ladder logic diagram.
• Program the divide instruction in the PLC ladder logic diagram.
• List advanced math instructions that are available in the
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Allen-Bradley SLC 5/03, SLC 5/04, and SLC 5/05 processors to

perform mathematical computations.

Introduction

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n Chapter 9, you learned how to program the PLC counter instructions
and use them in industrial control systems. In this chapter, you will learn
how to use PLC math instructions such as add, subtract, multiply, and divide
to calculate the sum, difference, product, and quotient of the content of registers
in two PLC counter instructions. Examples are used to illustrate the use of
these math instructions in PLC ladder logic diagrams. The usual interval to
update the results of PLC arithmetic instructions is one scan period.

218 Copyright Goodheart-Willcox Co., Inc.

 Chapter 10 PLC Math Instructions    219

10.1 Addition
When parts on two separate conveyors are placed onto a single larger conveyor, the
total parts on the large conveyor may need to be calculated. This calculation can be
done with the add instruction. The add (ADD) instruction calculates the sum of
two operands (Source A and Source B). Figure 10‑1 displays an add instruction for
the Allen-Bradley SLC 500 series PLC. Add instructions in SLC 500 series PLCs
are displayed in block format.

Switch
I:0 ADD
0000 Add
0 Source A N7:0

LE
0<
Source B N7:1
0<
Dest N7:2
0<

0001 End

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Figure 10‑1. Add (ADD) instruction for an Allen-Bradley SLC 500 series PLC and ControlLogix Programmable
Automation Controllers (PACs). P
The add instruction has three operands. Two operands hold the source data
(Source A and Source B), which are added together. Both sources can be registers,
or one source can be a register while the other one is a number. The third operand
is the destination, which holds the sum of Source A and Source B. The destination
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must be a register. In Figure 10‑1, Sources A and B are the content of integer
registers N7:0 and N7:1. The destination register is N7:2. Example 10-1 illustrates
how to use the add instruction to calculate the content of the accumulated register for
two PLC counter instructions. After a math, logic, or move instruction is executed,
the status bits in the status file are updated. The status bits S2:0/0 through S2:0/3
are in word S2:0 in the processor status file (S2). General descriptions of these bits
are listed in Table 10‑1.
A

Bit Address Description

Carry (C) S2:0/0 Set when carry is generated.
Otherwise, it is clear.
Overflow (O) S2:0/1 Set when the result is too large to fit in
S

the destination register.

Zero (Z)  S2:0/2 Set when the result of math/logic or
move instructions is zero.
Sign (S) S2:0/3 Set when the result of math/logic
or move instructions is a negative
number.
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Table 10-1. Description of bits in the processor status file (S2).

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220    Programmable Logic Controllers: Hardware and Programming

Table 10-2 describes how status bits are affected when ADD instruction is carried out.

Bit Address Description

Carry (C) S2:0/0 Set if a carry is generated and cleared
otherwise.
Overflow (O) S2:0/1 Set if the result does not fit in the
destination location.
Zero (Z)  S2:0/2 Set if the result is zero.
Sign (S) S2:0/3 Set if the result is negative.
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Table 10-2. Status bit descriptions for the ADD instruction.

Example 10‑1

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Figure 10‑2 shows a section of a manufacturing plant with three conveyors. The number of parts in
conveyor A and the number of parts in conveyor B are added to get the number of parts on the main conveyor.
Figure 10‑3 displays the PLC ladder diagram for Example 10-1.
Counter B
input
Conveyor B

P
M
Main
conveyor

Counter A
A

input
S

Conveyor A
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Figure 10‑2. Conveyor diagram for Example 10-1.

The green pushbutton (Green_PB) represents the proximity switch input for counter A. The red push-
button (Red_PB) represents the proximity switch input for counter B. Pressing the green pushbutton
increments the content of the accumulated register in counter instruction zero (C5:0). Pressing the red
pushbutton increments the content of the accumulated register in counter instruction one (C5:1). The add
instruction in rung 0002 places the sum of the content of the accumulated registers in the integer register
N7:2. When the content of the accumulated register for either counter instruction is equal to 1000, the
reset (RES) instruction in rung 0003 enables, resetting both counter instructions to zero.
 221

Green_PB Counter A
I:0 CTU
0000 Count up CU
1 Counter C5:0
Preset 1000< DN
Accum 0<

Red_PB Counter B
I:0 CTU
0001 Count up CU
2 Counter C5:1
Preset 1000< DN
Accum 0<

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Register N2 holds the number of parts in the main conveyor.
ADD
0002 Add
Source A C5:0.ACC
0<
Source B C5:1.ACC
0<
Dest N7:2
0<

Counter A

0003
C5:0

DN

C5:1
P C5:0
RES

Counter B
C5:1
RES
M
DN
0004 End
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Figure 10‑3. PLC ladder logic diagram for Example 10-1.

10.2 Subtraction
A

A factory has three conveyors: A, B, and C. Conveyors A and B merge together into
the larger C. You want to know how many parts are coming off conveyor A, but
you are unable to place a sensor near the end of the conveyor. By using sensors on
conveyors B and C and the subtract instruction, you can calculate the number of
parts on conveyor A. The subtract (SUB) instruction calculates the difference
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between two sources: Source A and Source B. Figure 10‑4 displays a subtract
instruction for the Allen-Bradley SLC 500 series PLC. Subtract instructions in the
SLC 500 series PLC are displayed in block format.
The subtract instruction has three operands. Two operands, Source A and Source B,
hold the source data. The content of Source B is subtracted from the content of Source A.
The result is placed in the destination. Both sources can be registers, or one source
can be a register while the other one is a number. The destination must be a register.
Table 10-3 describes how status bits are affected when SUB instruction is carried out.
In Figure 10‑4, Sources A and B are the content of integer registers N7:0 and N7:1.
The destination register is N7:2. Example 10-2 illustrates how to use the subtract instruc-
tion to calculate the content of an accumulated register for two counter instructions.

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222    Programmable Logic Controllers: Hardware and Programming

Bit Address Description

Carry (C) S2:0/0 Set if a borrow is generated and
cleared otherwise.
Overflow (O) S2:0/1 Set if the result underflows.
Zero (Z)  S2:0/2 Set if the result is zero.
Sign (S) S2:0/3 Set if the result is negative.
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Table 10-3. Status bit descriptions for the SUB instruction.

Switch
I:0 SUB
0000 Subtract
Source A N7:0

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0 0<
Source B N7:1
0<
Dest N7:2
0<
0001 End
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Figure 10‑4. Subtract (SUB) instruction for an Allen-Bradley SLC 500 series PLC and ControlLogix Programmable
Automation Controllers (PACs).

Example 10‑2
P
Figure 10‑5 shows a section of a manufacturing plant with three conveyors. It is not convenient to install
and maintain a proximity switch in conveyor B. Therefore, the number of parts on conveyor A are subtracted
from the number of parts on conveyor C to calculate the number of parts on conveyor B. Figure 10‑6
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displays the PLC ladder diagram for Example 10-2.

Conveyor
B
A

Counter C
input
S

Conveyor
C

Counter A
input

Conveyor
A
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Figure 10‑5. Conveyor diagram for Example 10-2.

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The green pushbutton (Green_PB) represents the proximity switch input for counter A. The red push-
button (Red_PB) represents the proximity switch input for counter C. Pressing the green pushbutton
increments the content of the accumulated register in counter instruction zero (C5:0). Pressing the red
pushbutton increments the content of the accumulated register in counter instruction one (C5:1). The subtract
instruction in rung 0002 places the difference of the content of the accumulated registers in the integer
register N7:2. When the content of the accumulated register for either counter instruction is equal to 1000,
the reset (RES) instruction in rung 0003 enables, resetting both counter instructions to zero.

Green_PB Counter A
I:0 CTU
0000 Count up CU
1 Counter C5:0
Preset 1000< DN

LE
Accum 0<

Red_PB Counter C
I:0 CTU
0001 Count up CU
2 Counter C5:1
Preset 1000< DN
Accum 0<

Register N7:2 holds the number of parts on conveyor B.

SUB
0002
P Subtract
Source A C5:1.ACC

Dest
0<
Source B C5:0.ACC
0<
N7:2
M
0<

Counter A
C5:0 C5:0
0003 RES
DN
Counter C
C5:1
A

C5:1
RES
DN
0004 End
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Figure 10‑6. PLC ladder logic diagram for Example 10-2.

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10.3 Multiplication
When multiple parts are packed in containers, the number of parts per container,
the number of containers, and the multiply instruction will give you the total number
of parts. The multiply (MUL) instruction calculates the product of two sources:
Source A and Source B. Figure 10‑7 displays a multiply instruction for the Allen-
Bradley SLC 500 series PLC. Multiply instructions in SLC 500 series PLCs are
displayed in block format.

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224    Programmable Logic Controllers: Hardware and Programming

Table 10-4 describes how status bits are affected when MUL instruction is
carried out.

Bit Address Description

Carry (C) S2:0/0 Always cleared.
Overflow (O) S2:0/1 Set if the result overflows at the
destination address. S:14 and S:13
words are used to contain the full
32-bit integer result of the multiply
operation. These values are used in the
event of an overflow.
Zero (Z)  S2:0/2 Set if the result is zero.
Sign (S) S2:0/3 Set if the result is negative.

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Table 10-4. Status bit descriptions for the MUL instruction.

Switch
I:0 MUL
0000 Multiply
Source A N7:0
0
0<
Source B N7:1
0<

0001
P Dest N7:2
0<

End
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Figure 10‑7. Multiply (MUL) instruction for an Allen-Bradley SLC 500 series PLC and ControlLogix Programmable
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Automation Controllers (PACs).

The multiply instruction has three operands. Two operands hold the source data
(Source A and Source B). The content of Source B is multiplied by the content of
Source A. The result is placed in the destination. Both sources can be registers, or one
source can be a register while the other one is a number. The destination must be
a register.
A
S

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 Chapter 10 PLC Math Instructions    225

Example 10‑3
Figure 10‑8 displays the PLC ladder diagram for Example 10-3. Pressing the green pushbutton (Green_PB)
increments the content of the accumulated register in counter instruction zero (C5:0). Pressing the red push-
button (Red_PB) increments the content of the accumulated register in counter instruction one (C5:1). The
multiply instruction in rung 0002 places the result of the multiplication in the integer register N7:2. When
the content of the accumulated register for either of the counter instructions is equal to 100, the reset (RES)
instructions in rung 0003 enables, resetting both counter instructions to zero.

Green_PB Counter A
I:0 CTU
0000 Count up CU
1 Counter C5:0
DN

LE
Preset 100<
Accum 0<

Red_PB Counter B
I:0 CTU
0001 Count up CU
2 Counter C5:1
Preset 100< DN
Accum 0<

Register N7:2 holds the result.

0002
P Multiply
Source A

Source B
MUL

C5:0.ACC
0<
C5:1.ACC
0<
M
Dest N7:2
0<

Counter A
C5:0 C5:0
0003 RES
DN
A

Counter B
C5:1 C5:1
RES
DN
0004 End
S

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Figure 10‑8. PLC ladder logic diagram for Example 10-3.

In Figure 10‑7, Sources A and B are the content of integer registers N7:0 and
N7:1. The destination register is N7:2. (Notice that if both sources contain the same
number, then the multiply instruction acts like a square instruction.) Example 10-3
illustrates how to use the multiply instruction to calculate the content of accumulated
registers for two PLC counter instructions.

10.4 Division
Assume that a machine is counting the number of inches of steel that pass by. The
machine needs to calculate the length in feet or yards before it makes some engravings.
226    Programmable Logic Controllers: Hardware and Programming

The divide instruction is the perfect PLC instruction for this task. The divide (DIV)
instruction calculates the integer value that results from dividing Source A by
Source B. Figure 10‑9 displays a divide instruction for the Allen-Bradley SLC 500
series PLCs. Divide instructions in SLC 500 series PLCs are displayed in block format.

Switch
I:0 DIV
0000 Divide
0 Source A N7:0
0<
Source B N7:1
0<
Dest N7:2

LE
0<

0001 End
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Figure 10‑9. Divide (DIV) instruction for the Allen-Bradley SLC 500 series PLC and ControlLogix Programmable
Automation Controllers (PACs).

The divide instruction has three operands. Two registers hold the source data
(Source A and Source B). The content of Source A is divided by the content of Source B.
The integer quotient is placed in the destination. As with the other instructions,
P
both sources can be registers, or one source can be a register while the other one is
a number. The destination must be a register. Table 10-5 describes how status bits
are affected when DIV instruction is carried out.

Bit Address Description

M
Carry (C) S2:0/0 Always cleared.
Overflow (O) S2:0/1 Set if the result overflows at the
destination address. S:14 and S:13
words are used. The unrounded quotient
is placed in the most significant word
(S:14). The remainder is placed in the
least significant word (S:13).
A

Zero (Z)  S2:0/2 Set if the result is zero.

Sign (S) S2:0/3 Set if the result is negative.
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Table 10-5. Status bit descriptions for the DIV instruction.

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In Figure 10‑9, Sources A and B are the content of integer registers N7:0 and
N7:1. The destination register is N7:2. Example 10-4 illustrates how to use the
divide instructionto calculate the content of the accumulated registers for two
counter instructions.

Example 10‑4
Figure 10‑10 displays the PLC ladder diagram for Example 10-4. Pressing the green pushbutton (Green_PB)
increments the content of the accumulated register in counter instruction zero (C5:0). Pressing the red
pushbutton (Red_PB) increments the content of the accumulated register in counter instruction one (C5:1).
The divide instruction in rung 0002 places the quotient in the integer register N7:2. When the content of the
accumulated register for either counter instructions is equal to 100, the reset (RES) instruction in rung 0003
enables, resetting both counter instructions to zero.

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 227

Green_PB Counter A
I:0 CTU
0000 Count up CU
1 Counter C5:0
Preset 100< DN
Accum 0<

Red_PB Counter B
I:0 CTU
0001 Count up CU
2 Counter C5:1
Preset 100< DN
Accum 0<

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Register N7:2 holds the quotient.
DIV
0002 Divide
Source A C5:0.ACC
0<
Source B C5:1.ACC
0<
Dest N7:2
0<

0003
C5:0

DN

C5:1
P Counter A
C5:0
RES

Counter B
C5:1
M
RES
DN
0004 End
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Figure 10‑10. PLC ladder logic diagram for Example 10-4.

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10.5 Advanced Math Instructions

Several advanced math instructions are available in the Allen-Bradley SLC 5/03,
SLC 5/04, and SLC 5/05 processors. Table 10‑6 lists most of these instructions.
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Advanced math instructions are used to perform mathematical computations.

The compute (CPT) instruction may be used to solve mathematical equations.
Figure 10‑11 illustrates that the first entry in this instruction is the destination
register. The second entry in the compute instruction must be the equation. In
Figure 10‑11, the destination register is the integer register N7:0. The tangent of
integer register N7:1 is multiplied by the cosine of integer register N7:2. Example
10-5 illustrates how you can use the CPT instruction to solve an equation.
228    Programmable Logic Controllers: Hardware and Programming

Instruction Name
ACS (source, destination) Arc Cosine
COS (source, destination) Cosine
ASN (source, destination) Arc Sine
SIN (source, destination) Sine
ATN (source, destination) Arc Tangent
TAN (source, destination) Tangent
XPY (source, source, destination) X to the Power of Y
LN (source, destination) Natural Log
LOG (source, destination) Log to the Base of 10
CPT (destination, expression) Compute
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Table 10-6. List of advanced math instructions available for SLC 5/03, SLC 5/04, and
SLC 5/05 processors and ControlLogix Programmable Automation Controllers (PACs).

Compute
I:1 CPT
0000 Compute
0 Dest N7:0
1746-IB16 0<

0001
P Expression (TAN N7:1)*(COS N7:2)

End
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Figure 10‑11. Using the compute (CPT) instruction to solve an equation. Notice that the first entry is the
destination register.

Example 10‑5
Given the following equation, you can use the CPT instruction to solve it.
A

Y = (A × (ln B) × eC) + (tan D)

You must first assign floating point register locations for the parameters in the equation. Note that integer
registers such as N7:0 hold integer numbers. Floating point registers, such as F8:0, hold real numbers that
have both integer and fractional parts. These assigned registers are listed below.
A = F8:0
S

B = F8:1
C = F8:2
D = F8:3
Y = F8:4
Figure 10‑12 displays the PLC ladder diagram for Example 10-5. When the normally open contact I:1/0
is closed, the equation in the CPT instruction block is calculated and the result is placed in the floating point
register four (F8:4). A list of other commonly used math instructions is displayed in Table 10‑7.
 229

Compute
I:1 XPY
0000 X to Power of Y
0 Source A 2.718
1746-IB16 2.718<
Source B F8:2
0.0<
Dest F8:5
0.0<
CPT
Compute
Dest F8:4
0.0<
Expression ((F8:0 * LN F8:1)* F8:5)+

LE
(TAN F8:3)

0001 End
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Figure 10‑12. PLC ladder logic diagram for Example 10-5.

Function Name Description

CLR (register) Clear Clears the memory location.
DDV (source, destination) Double Divide Performs a double divide by dividing 32-bit data in
P S:13 & S:14 by a 16-bit source.
DCD (source, destination) Decode 4 to 1 of 16 Decodes a 4-bit number (0–15) in the source and turns
the corresponding bit(s) on in the destination.
NEG (source, destination) Negate Reverses the sign from positive to negative or from
negative to positive.
TOD (source, destination) Convert to BCD Converts a 16-bit integer value to BCD.
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FRD (source, destination) From BCD to Binary Converts a BCD value to a binary value.
SQR (source, destination) Square Root Finds the square root of a value.
COP Copy Data Causes the entire data file, pointer to by the source address,
to be copied to the destination addresses. The number of
locations moved is determined by the length value.
FILL Fill Data Contents of the source register or a constant value is
copied to the destination register in an ascending order
A

until the value entered in the length variable is zero.

SCL Scale Data Multiplied by the rate value. The rounded result is added
to the offset value and placed in the destination.
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Table 10-7. Other commonly used math instructions.

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10.6 LogixPro Simulator Examples

The following examples show PLC ladder logic diagrams built in the LogixPro 500
simulation software for common math applications. Study and reproduce these
examples to become familiar with use of math instructions in ladder logic diagrams.

Example 10‑6
Figure 10‑13 shows a ladder logic diagram programmed with various math functions. The G-PB (I:1/0) and
R-PB (I:1/1) inputs are used to control counter up functions on rungs 000 and 001. Each time one of these in-
puts is closed, its corresponding counter up function increments its accumulated register (C5:0 or C5:1). These
counter up functions allow the user to select two numbers and store them in the counter accumulated registers
to use with the math functions.
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230

The inputs at addresses I:1/2, I:1/3, I:1/4, I:1/5, and I:1/6 are used to activate the math functions. Each math
function has its own integer register (N7:0 through N7:4) where it stores the answer to its function. Actuating the
master switch (MSW) at address I:1/7 resets the accumulated registers (C5:0.ACC and C5:1.ACC) of both counters
to zero. Each math function holds its calculated answer until a new set of numbers is calculated.

PLC Math Functions

I:1/7 I:1/0 CTU
000 Count Up CU
MSW G-PB Counter C5:0
Preset 1000 DN
Accum 0

I:1/7 I:1/1 CTU

001 Count Up CU
MSW R-PB Counter C5:1

LE
Preset 1000 DN
Accum 0

I:1/7 I:1/2 ADD

002 Add
MSW Addition Source C5:0.ACC
?
Source B C5:1.ACC
?
Dest N7:0
?

I:1/7 I:1/3 SUB

003
MSW Subtraction
P Subtract
Source C5:0.ACC

Dest
?
Source B C5:1.ACC
?
N7:1
?
M
I:1/7 I:1/4 MUL
004 Multiply
MSW Multiplication Source C5:0.ACC
?
Source B C5:1.ACC
?
Dest N7:2
?
A

I:1/7 I:1/5 DIV

005 Divide
MSW Division Source C5:0.ACC
?
Source B C5:1.ACC
?
Dest N7:3
S

I:1/7 I:1/6 SQR

006 Square Root
MSW Square Root Source C5:0.ACC
?
Dest N7:4
?

I:1/7 C5:0
007 RES
MSW
C5:1
RES

008 End

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Figure 10‑13. PLC ladder logic diagram for Example 10-6. Using math functions for data manipulation.

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 Chapter 10 PLC Math Instructions    231

Example 10‑7
Figure 10‑14 shows data conversion programming in a ladder logic diagram for TOD and FRD data conversion
functions and their corresponding input/output (I/O) configurations. Input module three (I:3) provides a 16-bit
integer value (0000000000000101) to the TOD function, which converts that value to a BCD value displayed
in output O:6. Closing the NO switch G-PB at address I:1/0 initiates the conversion of the I:3 input into BCD.
Output module six (O:6) displays the BCD value by energizing its individual outputs (O:6/0 through O:6/15),
which also feed a 7-segment display that shows the decimal form of the number (5).

Convert from integer to BCD

I:1/0 TOD
000 To BCD
G-PB Source I:3
5

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Dest O:6
5

Convert from BCD to binary

I:1/1 FRD
001 From BCD
R-PB Source I:5
33
Dest O:4
21

002 End
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Figure 10‑14. PLC ladder logic diagram and input/output (I/O) configuration for Example 10-7. Using PLC data
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conversion functions.

The thumbwheel connected to input module five (I:5) is used to enter a 4-digit decimal number (21) that
is converted to BCD (00100001) in the individual inputs (I:5/0 through I:5/15). This BCD number is entered
into the FRD function. Closing the NO switch R-PB at address I:1/1 converts the I:5 BCD number to binary
and displays it on LEDs connected to output module four (O:4): 0000000000010101.
A
S

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232    Programmable Logic Controllers: Hardware and Programming

Summary
• The add, subtract, multiply, and • The multiply instruction calculates the product
divide instructions each have three of Source A and Source B and places this value
operands: two for source data and one for in the destination register.
the destination. • The divide instruction calculates the integer
• The add instruction calculates the sum of value that results from dividing Source A
Source A and Source B and places this value in by Source B and places this value in the
the destination register. destination register.
• The subtract instruction calculates the • Advanced math instructions, such as the
difference between Source A and Source B and compute (CPT) instruction, can be used to solve
places this value in the destination register. mathematical equations.

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Know and Understand
1. Based on the following ADD function block, 3. In the ladder logic diagram displayed, when
which of the following statements is false? SW1 is closed, the content of register T4:0 is
equal to _____.
ADD
Source A
I:1/0 CTU
Source B C5:0 Pre
LS1 150
Destination P
A. Source A can be either a number or a register.
B. Source B can be either a number or a register.
I:1/1
C5:0 ACC

CTU
100

C5:1 Pre
C. Destination can be either a number or 45
M
LS2
a register. C5:1 ACC
50
D. Source A, Source B, and Destination can
be registers.
I:3/1 ADD
2. In the ladder logic diagram displayed, when C5:0 ACC
SW1 is closed, the content of register N7:1 is SW1
C5:1 ACC
equal to _____. T4:0 Pre
A

I:1/1 ADD
T4: 0·Acc A. 200
SW1 120 B. 195
N7: 0
C. 150
35
S

N7: 1 D. 145

A. 156
B. 155
C. 246
D. 256

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 Chapter 10 PLC Math Instructions    233

4. For the following SUB function block, which 8. Which status bit is not used in an
statement is true? arithmetic instruction?
A. Overflow (OV)
SUB B. Underflow (UN)
Source A C. Zero (Z)
D. Sign (S)
Source B
9. Status word S:13 contains the _____.
Destination A. most significant word of the 32-bit result of
MUL instruction
B. un-rounded quotient of a 32-bit DIV
A. Source A and Destination can be numbers. instruction
B. Source A, Source B, and Destination can C. least significant word of the 32-bit result of

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be numbers. MUL instruction
C. Source A, Source B, and Destination can D. None of the above.
be registers.
10. Status word S:14 contains the _____.
D. None of the above. A. remainder of a 32-bit DIV instruction
5. Binary subtraction is done _____. B. unrounded quotient of a 32-bit DIV
A. using the same method as decimal instruction
subtraction C. least significant word of a 32-bit result of
B. using the inverse method of MUL instruction
decimal subtraction D. None of the above.
C. by adding one to the decimal P 11. Which of the following Allen-Bradley PLC has
subtraction result
4-byte registers?
D. by subtracting one from the decimal A. SLC 503
subtraction result
B. SLC 505
6. Which of the following binary number C. PLC 5
M
multiplications is correct?
D. ControlLogix
A. 11101100 × 11 = 11000100
B. 11101100 × 11 = 01100100 12. Which of the following instruction is used to
multiply source by rate value, adds an offset to
C. 11101100 × 11 = 11000011
it, then stores the result in destination?
D. 11101100 × 11 = 11000001 A. SWP (Swap data)
7. In the following ladder logic diagram, when B. CPI (Compute)
A

SW1 is closed, the content of N7: 0 is _____. C. SCP (Scale with Parameters)
D. SCL (Scale Data)
I:3/1 CTU 13. What type of instructions are math
Count up instructions?
Counter C5:0 A. Input
PB1
S

Preset 10
Accum 9 B. Output
C. Hexadecimal (HEX)
I:1/1 MUL D. Binary coded decimal (BCD)
C5:0 acc
14. The FIL instruction is used to _____.
19
SW1
N7:0
A. copy data from one register to another
register
B. copy a constant value into a register
A. 224 C. copy a constant value into a group of registers
B. 190 D. None of the above.
C. 171
D. 180

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234    Programmable Logic Controllers: Hardware and Programming

15. The NEG instruction _____.

A. moves data from source to destination
Apply and Analyze
B. moves one’s complement of source 1. How many operands does an add
to destination instruction have?
C. moves two’s complement of source 2. Check the _____ status bit to find out if an
to destination overflow has occurred.
D. clears source content 3. True or False? Status bit S2:0/2 is cleared if the
16. After MUL instruction is carried out, _____. result of a PLC math instruction is zero.
A. overflow status (OV) bit is always cleared 4. Can both sources in a subtract instruction be
B. sign status (S) bit is always cleared numbers? Explain.
C. carry status (C) bit is always set 5. In a subtract instruction, Source _____ is
D. carry status (C) bit is always cleared deducted from Source _____.

LE
6. In a multiply instruction, what is the largest
17. After DIV instruction is carried out, _____.
number that can be held in the destination
A. overflow status (OV) bit is always cleared
register? (Hint: Think about the destination
B. sign status (S) bit is always cleared register.)
C. carry status (C) bit is always cleared
7. At least one of the _____ in a multiply
D. carry status (C) bit is always set instruction must be a register.
18. FRD instruction converts _____. 8. Can both sources in a divide instruction be
A. binary to HEX registers? Explain.
B. binary to BCD 9. How many status bits are available for math
C. BCD to binary P functions in Allen-Bradley programmable logic
D. BCD to HEX controllers? Name them.
19. What math instruction must you use if you want 10. Describe the use of the overflow bit (S2:0/1) in
to change the sign of source value to its opposite? an Allen-Bradley PLC add instruction.
A. SUB 11. Describe the use of the sign bit (S2:0/3) in an
M
B. MUL Allen-Bradley PLC subtract instruction.
C. NEG 12. Describe the SQR instruction.
D. SQR 13. Which instruction is used to erase a number
from an Allen-Bradley PLC memory?
20. After the following instruction is carried out,
the content of N7:2 would be _____. 14. Describe the DCD instruction.
15. True or False? Source values are inputs to
A

DIV math instructions.

N7:0
55
N7:1
10
N7:2
S

A. 11
B. 6
C. 5
D. 550

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 Chapter 10 PLC Math Instructions    235

Critical Thinking 4. Write a program using add, subtract, multiply,

and divide instructions to calculate the value
Using the timer instructions, draw the PLC ladder of the following equation:
logic diagram for the following problems. Y= [ρ (L1 /A1)] + [ρ (L2/A 2)]
1. Use the compute (CPT) instruction to 5. Water freezes at 0°C (32°F) and boils at 100°C
implement the following equation: (212°F). The following equation can be used to
R1 /T1 = R2/T2 convert degrees Celsius to Fahrenheit:
where °C = 5/9(°F – 32)
R1 represents the resistance value for A temperature sensor and analog-to-digital
temperature t1 converter is used to send degree Celsius (°C)
R 2 represents the resistance value for data in BCD to PLC input module five (I:5).
temperature t2 Write a PLC program to convert the degree
Celsius input to degree Fahrenheit. Notice that

LE
T1 is temperature in degree Kelvin (°K): first your program should convert the data from
T1 = t1 + 273 BCD to binary. Then, use the equation in your
T 2 is temperature in degree Kelvin (°K): program to convert the temperature to Fahren-
T 2 = t 2 + 273 heit. Finally, convert the data to BCD and place
Assume that three counters provide the vari- it on the 7-segment display that is connected to
ables labeled R1, t1, and t2. output module six (O:6).
Your PLC program should calculate R2.
2. Write a program that will add the content of
two counters every 45 seconds and place the
result in an integer register. P
3. Four conveyors are delivering the same parts
in different packages. A package can hold 6,
8, 12, or 18 parts. Four proximity switches
are used to advance the values of counters.
M
Write a program that uses multiply and add
instructions to calculate the sum of parts.
A
S

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