DI-124 Design Idea

LinkSwitch-TN
™

Ultrawide Input Range (57 – 580 VAC) Flyback Power Supply

Application Device Power Output Input Voltage Output Voltage Topology

Metering / Industrial LNK304PN 3W 57 – 580 VAC 12 V, 250 mA StackFET Flyback

Design Highlights while the drain of Q1 drives the transformer primary. The drain
• StackFETTM flyback topology delivers full load over extremely voltage of U1 is limited to 450 V by VR1-3. This extends the
wide input voltage range maximum peak composite drain voltage of U1 and Q1 to 1050 V.
• E-ShieldTM transformer construction for reduced common-mode The resistor chain R6-R8 provides startup charge for the gate of
EMI (>10 dBmV margin) Q1 and R9 dampens high-frequency ringing. Once the converter
• 66 kHz switching frequency with jitter reduces conducted EMI is operating, the gate is largely driven by the charge stored in the
• Simple ON/OFF controller – no feedback compensation capacitance of VR1-3. Zener VR4 limits the gate to source
required voltage of Q1. Leakage inductance energy is clamped by VR5 and
• Auto-restart function for automatic and self-resetting open-loop, D9 with R10 added to reduce ringing and thereby, EMI.
overload and short-circuit protection
• Built-in hysteretic thermal shutdown at 135 ºC The operation of U1 is unaffected by the StackFET configuration.
When the internal MOSFET turns on, Q1 is also turned on,
Operation applying the input voltage across the transformer primary. Once
The AC input is rectified and filtered and the resultant DC applied the primary current reaches the internal current limit of U1, the
to one end of the transformer primary winding. The 450 V input MOSFET is turned off and the energy stored is delivered to the
capacitors are stacked with parallel balancing resistors to meet output. Regulation is maintained using ON/OFF control. Switching
the required voltage rating. Resistors R1 to R4 provide fusing in cycles are enabled/disabled based on current into the FEEDBACK
case of a catastrophic failure. Inductor L1, C1 and transformer pin of U1. This is ideal as it results in a lowering of the effective
E-Shield windings allow the design to meet EN55022 B conducted switching frequency with load, scaling switching losses and
limits with good margin. maximizing efficiency. The use of LinkSwitch-TN further improves
efficiency due to its 66 kHz switching frequency.
A 600 V MOSFET, Q1, and U1 are arranged in the StackFET
configuration (cascode). The drain of U1 drives the source of Q1

C1
2.2 nF
250 VAC

D1 D2 D3 D4 R13 R6 VR5 D10

1N4007 1N4007 1N4007 1N4007 475 kΩ 680 kΩ P6KE150A UF4004 L2
C5 0.5 W 12 V, 250 mA
0.5 W R14 NC 4
15 µF 475 kΩ D9 Ferrite
450 V C6 R7
15 µF 0.5 W UF4007 Bead
PH1 R1 680 kΩ 5
450 V 0.5 W
10 Ω 1 W R10 C2 C3
C9 200 Ω 470 µF 100 µF
PH2 R2 5.6 nF R8 7
16 V 16 V
1 kV 680 kΩ 9
10 Ω 1 W C8 0.5 W
PH3 15 µF R16
R3 C7 450 V 10 1
15 µF 475 kΩ T1
10 Ω 1 W 0.5 W RTN
450 V R15 EEL16
475 kΩ R9 Q1
N R4 IRFBC20
0.5 W 10 Ω
10 Ω 1 W R11
R5 330 Ω
1k VR4
VR1 1N5245B
D5 D6 D7 D8 P6KE150A 15 V U2B U2A
1N4007 1N4007 1N4007 1N4007 D PC817A PC817A
L1 FB
1 mH LinkSwitch-TN
U1 BP
LNK304PN R12
S 1 kΩ
VR2
P6KE150A
C4 VR6
VR3 100 nF BZX79-C11
P6KE150A 50 V 11 V

PI-4487-010208

Figure 1. Schematic Diagram of 3 W Bias Supply Using LinkSwitch-TN in StackFET Configuration.

www.powerint.com July 2012

Key Design Points 80

PI-4493-081806
• The input stage (to the left of C9) can be omitted in applications
that have a high-voltage DC bus. Capacitor C9 is still required 75
to provide local decoupling. 70
• Long cores (EEL) are ideal for this application to provide greater

Efficiency (%)
bobbin width to accommodate the increased margins required 65
to meet safety spacings at the high operating voltage. 60
• Zener diodes VR1-3 should have a combined voltage rating of
less than 80% of the BVDSS of the LinkSwitch-TN IC (<560 V). 55
A single high-voltage Zener may also be used. 50
• The value of capacitors C5 to C8 can be reduced to 10 mF if
operation down to 57 VAC is not required (100 VAC minimum). 45
• Use 0.5 W resistors for R13-16 and R6-8 to provide adequate 40
voltage rating. 50 150 250 350 450 550
• Efficiency falls at high line due to switching losses. Reducing
AC Input Voltage (V)
transformer capacitance by adding layers of tape between the
primary winding layers minimizes this. Figure 3. Full Load Efficiency vs. Input Voltage.

80

PI-4492-090706
EN55022B Limits
70 Transformer Parameters
QP
60 Core Material EEL16, gapped for ALG of 70 nH/t²
AV 6+4 pin (Ying Chin YC-1604-1) with 3 mm +
50
Bobbin
3 mm tape margins
40
Shield: 23T, 2 × 36 AWG
dBµV

30 QP Primary: 184T, 36 AWG

Winding Details
Shield: 12T, 2 × 36 AWG
20
Secondary: 30T, 29 AWG
10 AV
Shield (5–NC), tape
Winding Order
0 Primary (7–5), tape between layers
(pin numbers)
Shield (9–10), tape, 12 V / (4–1), tape 12 V (8– 6)
-10
Primary: 3.5 mH ±10%
Inductance
-20 Leakage: 160 mH (maximum)
0.15 1.0 10.0 100.0
Primary Resonant
MHz 500 kHz (minimum)
Frequency
Figure 2. Conducted EMI (230 VAC, EN55022B Limits, AV and QP Results). Table 1. Transformer Parameters. (TIW = Triple Insulated Wire, NC = No
Connection, FL = Flying Lead)

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07/12 DI-124