a Experiment No: 01 i Name of the Experiment: Verification of the Basie Logic Gates Characteristics. yi &y° Objective: 1. Understanding the symbols and characteristics of various basic logic gates. Theory: 1. AND Gate: F= AB Truth Table State Taput Output A B 0 0 0 0 1 0 1 0 2 1 0 0 A 1 1 2. OR Gate: FA+B > ‘Truth Table : ‘State Input ‘Output A B 0 0 oO 0 1 0 1 1 2 1 0 1 3 1 1 T 3. Not Gate: FeA’ Truth Table A F 0 re 1 0; 2) Equipments Required: 1, Logic Trainer board AND Gate (7408) . OR Gate (7432) |. NOT Gate Inverter (7404) . Connecting Wires (As required) ¢ waeDCircuit Diagram: Working Procedures: (a) AND Gate Characteristics Verification (IC 7408) 1, Connect 5 V to lead 14 & ground to lead 7, 2. Connect inputs A & B to lead 1 & 2 respectively & output F to lead 3. 3. Then verify the following truth table, Fig 1-2 Obl State Tnputs Outputs a B F 0 0 0 0 1 0 1 0 2 1 0 0 3 1 1 1(b) OR Gate Characteristics Verification (IC 7432) 1, Connect $ V to lead 14 & ground to lead 7. 2. Connect inputs A & B to lead | & 2 respectively & output F to lead 3. 3, Then verify the following truth table, State Tnputs Outputs wlro|—lo) A 0 0 1 1 B 0 1 0 1 —|-|-|o} (c) Not Gate Characteristics Verification (IC 7404) 1. Connect 5 V to lead 14 & ground to lead 7. 2. Connect inputs A to lead 1 & output F to lead 2, 3. Then verify the following truth table. Student Works: State Taputs Outputs | A F 0 1 0 1. Verify the Basic Gate Characteristics.Experiment No: 02 Name of the Experiment: AND-OR-INVERTER (A-O-1) Gate Circuits Objective: 1. Understanding the basie principle of combined logic Theory: The Boolean expression for the output is F=(AB+CDy Equipments Required: 1, Trainer Board 2. AND Gate (7408) 3. OR Gate (7432) 4. NOT Gate Inverter (7404) 5. Connecting Wires (As required) Circuit Diagram: cpl ee =f se Ee nA +E Lg ky we on Fig3-2Working Procedures: 1, Connect 5 V to lead 14 & ground to lead 7. (All the ICs) 2. Connect the inputs according to the fig 3-1 to the leads of the ICs & verify the following truth table, State Inputs Outputs A B cS. D F 0 0 0 0 0 1 fezesel 0 0 0 1 i a 0 0 1 0 1 3 0 0 1 1 0 4 oO 1 oO 0 1 3 0 1 o 1 1 6 0 1 1 0 1 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 1 1 0 1 1 0 12 1 1 0 0 0 13 1 L oO 1 o 14 1 1 1 0 0 15 1 I 1 1 0 Student Works: 1, A-O-I gate also be constructed using two AND gates and NOR gate. 2. Construct a “Product of Sum” circuit with F= (A'+B') x (C'+D’) and “Sum of Product” circuit with Y = A’BC+AB’C’+A’B'C’+AB’C+ABC. 3. The output of an A-O-I gate is A'B'+C’D’, what is the output if C= A’ and D=B'?Experiment No: 03 Name of the Experiment: De Morgan's Laws using the Logic Gates. Objective: 1. Understanding the De Morgan's laws using the logic gates, Theory: De Morgan's theorem states, if in a logic function each OR) is replaced by a (AND) and ~each (AND) is replaced by a OR) & each variable is replaced by it’s compliments, the result is the compliment of the given function ie. a B=TT vd. AB=A+5 Apparatus Required: 1. Trainer Board 2. AND Gate (7408) 3. OR Gate (7432) 4. NAND Gate (7400) 5. NOR Gate (7402) 6. NOT Gate Inverter (7404) 7. Connecting Wires Circuit Diagram: Aco Output Y=AeB Boo Fig 3-1 (De Morgan’s 1" Theorem) 2 ‘This sheet for Digital Electronics Laboratory has been prepared by: ‘Chayan Mondat Lecturer, EEE Department BSMRSTUSlap 29 oe fice 2 of Fig3-2 Working Procedures: 1, Connect 5 V to lead 14 & ground to lead 7. 2. Construct the circuit according to the fig 3-1 & prove the De Morgan's * theorem using the following truth table. State Inputs ‘Outputs AL BI (A¥B)! ALB! 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 Student Works: 1. Prove the De-Morgan’s 2" theorem with the help of NAND gate, OR gate & NOT gate & verify their truth tables, Questions: 1. What are the implications of De Morgan’s theorem? 2. Write down one logic expression using four variables & simplify the same with the help of de Morgan’s theorems & also draw the simplified logic diagram. ‘This sheet for Digital Electronies Laboratory has been prepared by: ‘Chayan Mondal Lecturer, EEE Department BSMRSTUExperiment No: 04 Name of the Experiment : Karnaugh Map (K- Object 1. Understanding the minimization technique ‘using Karnaugh Map (K-Map). Theory: K-Map: A truth table arranged so that terms which differ by exactly one variable are adjacent to one another so we can see potential reductions easily. K-Map minimization can be performed by using following rules. Finding Subcubes: 1) A group or subcube must contain either 1,2,4,8 or 16 cells (i.e. 2" cells). 2) Each cell in a group must be adjacent to one or more cells in that same group, but all cells in the group do not have to be adjacent to each other. 3) Always include the largest possible number of Is in a group in accordance with rule 1. 4) Each 1 on the map must be included in at least one group. Truth Table Here's the layout of a 3-variable K-map filled Inwith the valueo from our truth table: Write Down Equation: : 1) Group the cells that have 1s, Each group of cells containing 1s creates one product term composed of all variables that occur in only form (either uncomplemented or complemented within the group are eliminated), 2) Determine minimum product terms for each group, 3) When all the minimum product terms are derived from the Karnaugh map, they are summed to form the minimum SOP expression. ‘This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mond: Lecturer, EEE Department BSMRSTU ‘Apparatus Required: 1. Trainer Board 2. 2-input AND Gate (7408) 3. 3-input AND Gate (7411)7 4, OR Gate (7432) 5. NOT Gate Inverter (7404) 6. Connecting Wires Cireuit Diagram: e B : are . = ay rc a Ve AY De a ly a os we OVE Fig 4-3 Working Procedures: 1, Connect 5 V to lead 14 & ground to lead 7, 2, Construct the circuit according tothe fig 4-2, “This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTU vodStudent Works: 1, Simy the following problem using K-map and draw and construct the circuit iagram. Implement your simplified circuit in the breadboard and verify the functionality of the circuit, i: 100} 01 [at] 0] Questions: 1, Why K-map is used in digital electronics? 2. It is possible to implement all the basic logic gates using only NAND gate. That is why it is called universal gate, With necessary circuit diagram, show how AND, OR, NOT and XOR gates can be implemented using NAND gates only. ‘This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTUExperiment No: 05 Name of the Experiment: Design of Half- Adder & Full - Adder Circuit. Objective: 1, Understanding the characteristics of half - adder & full - adder in the arithmetic unit. Theory: Adders are important not only in computers but also in many types of digital systems in which numerical data are processed. The half adder accepts two binary digits on it's inputs (A, B) and produces two binary digits on it's output a sum bit and a carry bit (8,C.). The full adder accepts more than two binary digits as input (Ci, A, B) and generates two binary digits on its output a sum and a carry (S, Ce). Half adder Sum: S=A@B=A'B+ABY And Carry: C=AB ‘Truth Table (Half-Adder): Input Apparatus Required: 1, Logic Trainer Board 2. AND Gate (7408) * 3. XOR Gate (7486) 4. Connecting Wires (As required) Circuit Diagram: > Fig 5-1 t This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTUEMS s(] ze Bigg 2H st a[e a)e BBY eg Fig 5-2 Working Procedures: 1. Connect 5 V to lead 14 & ground to lead 7. 2. Construct the circuit according to the fig 5-1. 3. Verify the truth table of the Half Adder circuit, Student Works: 1. Construct truth table for full - adder circuit. 2. Design the full-adder circuit. Questions: 1. What is parallel adder? How can you add two binary numbers where, AzAi = 10 & ¢ B:Bi= 11. Draw the circuit diagram forthe operation. 3 2. Write down the SOP expression of full adder from the truth table, Minimize the ‘expression using Kamaugh map. Draw the minimized logic diagram. “This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTUExperiment No. : 06 ‘Name of the Experiment: Design and Implementation of Comparators. Objective: 1, Understanding the operating principles and construction of comparator. Theory: ____ The comparison of two numbers is an operation that determines whether one number ‘greater than, less than, or equal to the other number. A comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The outcome ‘of the comparison is specified by three binary variables that indicate where A>B, AS. Apparatus Required: 1, Logic Trainer Board 2. 2-input AND Gate (7408) 3. NOT Gate Inverter (7404) 4, 2-input XOR Gate (7486) 5. Connecting Wires(As req Circuit Diagram: BAD to \ 8am r-bit comparator =H as 5E) o i e Dee Ze GV wee ‘ ope a hy ED, © Sei ee ve oe » Gy a Le = ey 3G VE aE ct 8 =}; 8G oy Figure 2: Vin diagram of diferent 1C3 Electronics Laboratory has been prepared by: ei ‘Chayan Mondal Lecturer, EEE Department BSMRSTUWorking Procedures: (a) Constructing a 1-bit comparator with basic logic gates 1. Connect 5 V to lead 14 & ground to lead 7. 2. Construct the circuit according to the fig-1. 3. Compare the results with the following true table, Student Works: 1, Design & implement a 2-bit comparator. This sheet for Digital Electronics Laboratory has been prepared by: hayan Mondal Lecturer, EEE Department BSMRSTUExperiment No: 07 Name of the Experiment: Design and Implementation of Decoder Circuit Objective: 1. Understanding the operating principles of decoder circuits, Theory: ‘A decoder is a logic circuit that will detect the presence of a specific binary number or word. The input to the decoder is a parallel binary number and the output is a parallel binary number and the output is a binary signal that indicates the presence or absence of that specific number. Apparatus Required: 4, Logic Trainer Board 5. 3-input AND Gate (7411) 6. NOT Gate Inverter (7404) 7. Connecting Wires Circuit Diagram: Fig 7-1 “This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTUWorking Procedures: (a) Constructing a 3-to-8 Decoder with Basic Gates 1. Connect 5 V to lead 14 & ground to lead 7. 2. Construct the circuit according to the fig 7-1. 3. Find the output of the following table. Inputs Outputs A B c Dr De Ds De Ds Dr De Do 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 oO 1 1 1 0 1 1 1 Questions: 1, What is the purpose of decoder? Draw the logic diagram of 2-to-4 decoder. 2, How many numbers of outputs if the input number is 5 of a decoder? This sheet for Chayan Mondal Lecturer, EEE Department BSMRSTU al Electronics Laboratory as been prepared bytExperiment No: 08 Name of the Experiment: Design and Implementation of Encoder Circuit Objective: 1. Understanding the operating principles of encoder cireuits. Theory: ‘An encoder is a combinational logic gate that accepts one or multiple inputs and generates a specific output code. Only one input is triggered at atime, Apparatus Required: 1. Logic Trainer Board 2. OR Gate (7432) 3. Connecting Wires (As required) an Circuit Diagram: De LP = FS] never does $$) p= pre D+ Derds = Det ol on Sy ay re tc lz Working Procedures: (a) Constructing a 8-to-3 encoder with basic gates 1, Connect 5 V to lead 14 & ground to lead 7, 2. Construct the circuit according to the fig 6-1. 3. Find the output of the following table. ‘This sheet for Digital Electronics Laboratory has been prepared by: ‘Chayan Mondal Lecturer, EEE Department BSMRSTUInputs Outputs Questions: 1. What is the purpose of encoder? Draw the logic diagram of 4-to-2 priority encoder. 2. How many numbers of outputs if the input number is 12 of an encoder? ‘This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTU_Experiment No: 09 Name of the Experiment: Design and Implementation of Multiplexer Circuit, Objective: 1, Understanding the operating prineiples and construction of multiplexers. Theory: Multiplexer, or MUX, is a logic circuit that select and route any number of inputs to a single output. One of the multiple inputs are selected by the selector gate and routed to the Ie output. The number of selector determines the capacity of a multiplexer. For example, iffa certain MUX has only one selector gate, itis referred to as a “2-to-1 MUX" because one selector can only select from two inputs. A MUX with 3 selector gates is called "8-to-1 MUX’; since 3 selectors are capable of selecting an output from 8 inputs (2?=8). MUX is also referred to as “Data Selector" because it selects one output from among many inputs. Apparatus Required: . Logic Trainer Board 3-input AND Gate (7411) NOT Gate Inverter (7404) OR Gate (7432) Connecting Wires (As required) yeee Circuit Diagram: Data selector Data output wee By ps Ce Fig 8-2 This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTUWorking Procedures: 1) Constructing a 4-to-1 Multiplexer 1. Connect 5 V to lead 14 & ground to lead 7. 2! Construct the circuit according to the fig 8-2. 3. Find the output of the following table, Data Selector Data Output Ss: So Y 0 ° 0 1 1 o 1 1 Student Works: 1. Design & implement a 8-to-1 Multiplexer. Questions: 1, How many selection lines are required to design a 16-to-1 MUX? This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondal Lecturer, EEE Department BSMRSTUExperiment No. : 10 Namie of the Experiment: Design and Implementation of De-ntultiplexer Circuit. Objective: 1, Understanding the operating principles and construction of de-multiplexer circuits Theory: A de-multiplexer, or DMUX, is basically a logic circuit that is exact opposite of a multiplexer. DMUX has a single input and multiple outputs, The input can be connected to any one of the many outputs through the selector terminal. Apparatus Required: Logic Trainer Board 3input AND Gate (7411) NOT Gate Inverter (7404) ‘Connecting Wires(As required) Pepe Circuit Diagram: Data input I ‘This sheet for Digital Electronics Laboratory has been prepared by: ‘Chayan Mondal Lecturer, EEE Department BSMRSTUWorking Procedures: {a) Constructing a 1-0-4 line de-multiplexer with basic logic gates 1. Connect $V to lead 14 & ground to lead 7. 2. Construct the circuit according to the fig 9-1. 3. Find the output of the following table. Si | So | Output o}o oli 1} 0 1. Design & implement a 1-to-8 line de-multiplexer. ‘This sheet for Digital Electronics Laboratory has been prepared by: Chayan Mondat Lecturer, EEE Department BSMRSTU