A B C D E

LCFC Confidential
1 1

L350 RENOIR+N18P-G61/G62 MB Schematics Document

RENOIR-H with DDR4 + N18P-G61/G62
2 2

2020-05-09
REV:1.0

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 1 of 68
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LCFC confidential

NV N18P-G61/G62 DDR4 SO-DIMM x1

Page 12
PCI-Express
8x Gen3 Memory Bus (Dual Channel)
1
GDDR6*4 4GB 1.2V DDR4 3200MT/s DDR4 SO-DIMM x2 1

Page 13

Page 31~34

USB3.0 x1 USB3.0 Left Conn

HDMI 2.0 USB3.0 Port1
HDMI Conn. USB2.0 x1
USB2.0 Port1 Page 46
Page 39

AMD USB3.0 x1 USB3.0 Right Conn

USB3.0 Redriver
RENOIR H USB2.0 x1 PI3EQX7502MZDEX USB3.0 Port5
USB2.0 Port5 FFC cable to SB
eDP Conn USB3.0 Port5
eDP x4 Lane
Int. Camera Conn. USB2.0 x1
2
USB2.0 Port2 2

CC logic&Mux
Int. MIC Conn. USB 3.0 1x USB 3.0 2x
Realtek RTS5449E
USB 3.0 Port0 Type C Conn
Page 38 Page 21
USB 2.0 1x USB 2.0 Port0
Page 21

SATA HDD SATA Gen3 x1

Page 47 SATA Port0

PCIe Gen1 x1 NGFF WLAN&BT

PCIE SSD1 PCIe Port1
USB2.0 x1
USB2.0 Port6
PCIe Port 4~7 Page 45
M.2 CRF Module Page 45

PCIE SSD2 LAN Chip

PCIe Gen1 x1 RJ45 Conn.
Realtek_RTL8111GUL Page 43
PCIe Port8~11 Page 45
3 3
PCIe Port0 Page 42

SPK Conn. SPI SPI ROM (16MB)

Page 35 Codec W25Q128JWSIQ
HD Audio Page 18
I2C
HP&Mic Combo Conn. Realtek ALC3287
Page 35 Page 3~16

LPC
Page 35 TPM (Reserved)
NPCT750LABYX Page 37
EC Touch Pad
IT8227E-128/CX LQFP
Page 49 Page 50

4 4

Int.KBD Thermal Sensor

Page 50 Page 44

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 2 of 68

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Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VALW +5VS

+5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.0VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn Left @ Not stuff
2 USB Type-C 14@ For 14" part
3 USB3.0 Conn Left 15@ For 15" part
USB3.0
4 NC 17@ For 17" part
S0 O O O O 5 NC 15or17@ For 15" or 17" part
6 NC
1 USB3.0 Conn Left
S3 O O O X 2 USB Type-C Cannonlake@ For Cannonlake part
3 USB3.0 Conn Left CD@ For C cost down

S3 4 Finger Print DUALMIC@ For Dual MIC part

2
Battery only O O O X USB2.0 5 Cardreader EMC@ For EMC part 2

6 Touch Panel EMC_15@ For EMC 15" part

S5 S4 7 Bluetooth EMC_NS@ For EMC nu-stuff part

AC Only O O X X 8 Camera EMC_PX@ For EMC PX part

9 NC EMC_PXNS@ For EMC PX nu-stuff part

S5 S4 10 NC ES@ For ES CPU

Battery only O X X X EXO@ For EXO GPU

1~4 DGPU
S5 S4 X4 PCIE
ME@ For ME part
TS@ For touch screen part
AC & Battery X X X X 5 LAN TS_NS@ For nu-touch part
don't exist
PCIE 6 WLAN DIS@ For GPU part
7 SATA HDD OPT@ For NV GPU part
SMBUS Control Table 8 SATA ODD PX@ For AMD GPU part
RANKA@ For VRAM rank A part
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN RANKB@ For VRAM rank B part
Down Sensor WiMAX 9~12 Optane Memory
Realtek_SD@ For Realtek SD part
X4 PCIE
3
SINGLEMIC@ For single MIC part
3
EC_SMB_CK1 IT8586E
V V X V X X X X X X 0 HDD SINGLERANK@ For single VRAN rank part
EC_SMB_DA1 +3VL_EC +3VL_EC 1A ODD DUALRANK@ For dual VRAN rank part
SATA 1B used as PCIE
EC_SMB_CK2 IT8586E
X X V V X V X X V X 2 used as PCIE TPM@ For TPM part
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH UMA@ For UMA part

EC_SMB_CK3 IT8586E
X X X V X X V X X X
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH
X X X X X V X V X V
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b PCH need to update Wlan Reserved
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 3 of 68
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 5 4 3 2 1

+3VALW +3VL_EC

2.2K 2.2K

EC_SMB_CK0
EC_SMB_DA0
D D

+3VL_EC

Battery JBATT1 Change IC PU101

2.2K
BQ24780SRUYR

EC
EC_SMB_CK1
IT8227 EC_SMB_DA1
+1.8VS_AON

2.2K
NV GPU( UV1 )
+3VS_APU VGA_SMB_CK2
VGA_SMB_DA2
C C

Thermal sensor US1

Dual MOS
+1.8VS_AON
Control
APU( UC1 ) NCT7719W
1K

EC_SMB_CK2
EC_SMB_DA2

DDR1 DDR2
+3VS

2.2K
B B

PCH_SMBCLK SMB_CLK_S3 SMBUS Control Table

PCH_SMBDATA SMB_DATA_S3 WLAN Thermal
SOURCE VGA BATT IT8227E SODIMM APU TP charger
WiMAX Sensor Module
TP_PWR
EC_SMB_CK1 IT8227 V
EC_SMB_DA1 +3VL_EC X V +3VL_EC X X X X X V

EC_SMB_CK2 IT8227 V V
2.2K X X X V V X X
APU
EC_SMB_DA2 +3VS_APU +1.8VS_AON +3VS_APU
TP ( JTP1 ) PCH_SMB_CLK APU
X X V X X V X
PCH_SMB_DATA +3VS X +3VS X
+3VALW_APU TP_I2C3_SCL
TP_I2C3_SDA
TP_I2C3_SCL_R APU
X X X X X X V V X
TP_I2C3_SDA_R +3VALW_APU +3VALW_APU TP_PWR
TP_PWR
2.2K
Dual MOS Control

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

A
Device Address A

Device Device Address DDR DIMMA 1010 000Xb

Smart Battery 0X16 Thermal Sensor NCT7719W 1001_101xb DDR DIMMB 1010 010Xb
TP_I2C3_SCL_R Charger 0001 0010 b VGA 0x9E(default)
TP_I2C3_SDA_R APU 0x98

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/26 Deciphered Date 2018/09/20 I2C Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 4 of 68
5 4 3 2 1
 5 4 3 2 1

25 PCIE_CRX_GTX_N[0..7]

25 PCIE_CRX_GTX_P[0..7]

PCIE_CTX_C_GRX_N[0..7] 25

PCIE_CTX_C_GRX_P[0..7] 25

D D

UC1A

PCIE_CRX_GTX_P0 G13 F4 PCIE_CTX_GRX_P0 OPT@ CC153 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0

PCIE_CRX_GTX_N0 F13 P_GFX_RXP0 P_GFX_TXP0 F2 PCIE_CTX_GRX_N0 OPT@ CC1 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_CRX_GTX_P1 J14 F3 PCIE_CTX_GRX_P1 OPT@ CC152 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 H14 P_GFX_RXP1 P_GFX_TXP1 E4 PCIE_CTX_GRX_N1 OPT@ CC2 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N1
P_GFX_RXN1 P_GFX_TXN1
PCIE_CRX_GTX_P2 G15 E1 PCIE_CTX_GRX_P2 OPT@ CC19 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 F15 P_GFX_RXP2 P_GFX_TXP2 C1 PCIE_CTX_GRX_N2 OPT@ CC3 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N2
P_GFX_RXN2 P_GFX_TXN2
PCIE_CRX_GTX_P3 J15 D5 PCIE_CTX_GRX_P3 OPT@ CC20 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
PCIE_CRX_GTX_N3 K15 P_GFX_RXP3 P_GFX_TXP3 E6 PCIE_CTX_GRX_N3 OPT@ CC4 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N3
P_GFX_RXN3 P_GFX_TXN3
PCIE_CRX_GTX_P4 H16 C6 PCIE_CTX_GRX_P4 OPT@ CC151 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 J16 P_GFX_RXP4 P_GFX_TXP4 D6 PCIE_CTX_GRX_N4 OPT@ CC5 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N4
P_GFX_RXN4 P_GFX_TXN4
PCIE_CRX_GTX_P5 F18 B6 PCIE_CTX_GRX_P5 OPT@ CC150 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 G18 P_GFX_RXP5 P_GFX_TXP5 C7 PCIE_CTX_GRX_N5 OPT@ CC6 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N5
P_GFX_RXN5 P_GFX_TXN5
PCIE_CRX_GTX_P6 J18 D8 PCIE_CTX_GRX_P6 OPT@ CC149 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 K18 P_GFX_RXP6 P_GFX_TXP6 B8 PCIE_CTX_GRX_N6 OPT@ CC7 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N6
P_GFX_RXN6 P_GFX_TXN6
C C
PCIE_CRX_GTX_P7 H19 C8 PCIE_CTX_GRX_P7 OPT@ CC148 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P7
PCIE_CRX_GTX_N7 G19 P_GFX_RXP7 P_GFX_TXP7 A8 PCIE_CTX_GRX_N7 OPT@ CC8 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N7
P_GFX_RXN7 P_GFX_TXN7

PCIE_PRX_DTX_P0 G11 L3 PCIE_PTX_DRX_P0 CC157 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P0

42 PCIE_PRX_DTX_P0 PCIE_PRX_DTX_N0 P_GPP_RXP0 P_GPP_TXP0 PCIE_PTX_DRX_N0 PCIE_PTX_C_DRX_N0 PCIE_PTX_C_DRX_P0 42
LAN F11 L1 CC158 1 2 0.1U_0201_6.3V6-K LAN
42 PCIE_PRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PTX_C_DRX_N0 42
PCIE_PRX_DTX_P1 J10 L4 PCIE_PTX_DRX_P1 CC159 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P1
45 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 45
WLAN H10 L2 CC160 1 2 0.1U_0201_6.3V6-K WLAN
45 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 45
SATA_PRX_DTX_P0 G8 M4 SATA_PTX_DRX_P0
47 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 P_GPP_RXP2/SATA0_RXP P_GPP_TXP2/SATA0_TXP SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 47
F8 M2
HDD 47 SATA_PRX_DTX_N0 P_GPP_RXN2/SATA0_RXN P_GPP_TXN2/SATA0_TXN SATA_PTX_DRX_N0 47 HDD
G6 N3
F7 P_GPP_RXP3/SATA1_RXP P_GPP_TXP3/SATA1_TXP N1
P_GPP_RXN3/SATA1_RXN P_GPP_TXN3/SATA1_TXN

PCIE_PRX_DTX_P4 M9 T2 PCIE_PTX_DRX_P4
45 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 M8 P_GPP_RXP4 P_GPP_TXP4 T4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 45
45 PCIE_PRX_DTX_N4 P_GPP_RXN4 P_GPP_TXN4 PCIE_PTX_DRX_N4 45
PCIE_PRX_DTX_P5 L7 R1 PCIE_PTX_DRX_P5
45 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 L6 P_GPP_RXP5 P_GPP_TXP5 R3 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 45
45 PCIE_PRX_DTX_N5 P_GPP_RXN5 P_GPP_TXN5 PCIE_PTX_DRX_N5 45
PCIE_PRX_DTX_P6 K7 P2 PCIE_PTX_DRX_P6 M.2 SSD0
M.2 SSD1 45 PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 K8 P_GPP_RXP6 P_GPP_TXP6 P4 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 45
45 PCIE_PRX_DTX_N6 P_GPP_RXN6 P_GPP_TXN6 PCIE_PTX_DRX_N6 45
PCIE_PRX_DTX_P7 H6 N2 PCIE_PTX_DRX_P7
45 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 P_GPP_RXP7 P_GPP_TXP7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 45
H7 N4
45 PCIE_PRX_DTX_N7 P_GPP_RXN7 P_GPP_TXN7 PCIE_PTX_DRX_N7 45

PCIE_SATA_PRX_DTX_P8 L9 K2 PCIE_SATA_PTX_DRX_P8
45 PCIE_SATA_PRX_DTX_P8 PCIE_SATA_PRX_DTX_N8 P_GPP_RXP8/SATA2_RXP P_GPP_TXP8/SATA2_TXP PCIE_SATA_PTX_DRX_N8 PCIE_SATA_PTX_DRX_P8 45
L10 K4
45 PCIE_SATA_PRX_DTX_N8 P_GPP_RXN8/SATA2_RXN P_GPP_TXN8/SATA2_TXN PCIE_SATA_PTX_DRX_N8 45
PCIE_PRX_DTX_P9 K11 J4 PCIE_PTX_DRX_P9
B 45 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 P_GPP_RXP9/SATA3_RXP P_GPP_TXP9/SATA3_TXP PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 45 B
J11 J2
45 PCIE_PRX_DTX_N9 P_GPP_RXN9/SATA3_RXN P_GPP_TXN9/SATA3_TXN PCIE_PTX_DRX_N9 45
PCIE_PRX_DTX_P10 J12 H3 PCIE_PTX_DRX_P10
45 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 H12 P_GPP_RXP10 P_GPP_TXP10 H1 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 45
45 PCIE_PRX_DTX_N10 P_GPP_RXN10 P_GPP_TXN10 PCIE_PTX_DRX_N10 45 M.2 SSD1
M.2 SSD2 PCIE_PRX_DTX_P11 J13 H4 PCIE_PTX_DRX_P11
45 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 K13 P_GPP_RXP11 P_GPP_TXP11 H2 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 45
45 PCIE_PRX_DTX_N11 P_GPP_RXN11 P_GPP_TXN11 PCIE_PTX_DRX_N11 45
FP6 REV0.92
PART 2/13

AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 (PCIE SATA I/F)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document Number
Document Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date:
Date: Saturday, May 09, 2020 Sheet
Sheet 5 of 68
5 4 3 2 1
 5 4 3 2 1

UC1B
UC1C

17 DDRA_MA[0..13] DDRA_MA0 DDRA_DQ[0..63] 17

AK26 DDRB_DQ[0..63] 18
DDRA_MA1 MA_ADD0/RSVD DDRA_DQ0 18 DDRB_MA[0..13] DDRB_MA0
AG24 K27 AM29
DDRA_MA2 AG23 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 L26 DDRA_DQ1 DDRB_MA1 AH31 MB_ADD0/RSVD C27 DDRB_DQ0
DDRA_MA3 AG26 MA_ADD2/MAB_CA0 MA_DATA1/MAA_DATA9 N26 DDRA_DQ2 DDRB_MA2 AJ30 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 A28 DDRB_DQ1
DDRA_MA4 AG27 MA_ADD3/MAA_CA4 MA_DATA2/MAA_DATA13 N27 DDRA_DQ3 DDRB_MA3 AH29 MB_ADD2/MBB_CA0 MB_DATA1/MBA_DATA9 F29 DDRB_DQ2
DDRA_MA5 AF21 MA_ADD4/MAA_CA5 MA_DATA3/MAA_DATA12 G27 DDRA_DQ4 DDRB_MA4 AG32 MB_ADD3/MBA_CA4 MB_DATA2/MBA_DATA13 F31 DDRB_DQ3
DDRA_MA6 AF22 MA_ADD5/MAA_CA3 MA_DATA4/MAA_DATA11 H27 DDRA_DQ5 DDRB_MA5 AG30 MB_ADD4/MBA_CA5 MB_DATA3/MBA_DATA12 B27 DDRB_DQ4
DDRA_MA7 AF25 MA_ADD6/MAA_CA2 MA_DATA5/MAA_DATA10 M27 DDRA_DQ6 DDRB_MA6 AG31 MB_ADD5/MBA_CA3 MB_DATA4/MBA_DATA11 D27 DDRB_DQ5
DDRA_MA8 AF24 MA_ADD7/RSVD MA_DATA6/MAA_DATA15 N24 DDRA_DQ7 DDRB_MA7 AF30 MB_ADD6/MBA_CA2 MB_DATA5/MBA_DATA10 E32 DDRB_DQ6
D DDRA_MA9 AE21 MA_ADD8/RSVD MA_DATA7/MAA_DATA14 DDRB_MA8 AG29 MB_ADD7/RSVD MB_DATA6/MBA_DATA15 F30 DDRB_DQ7 D
DDRA_MA10 AL21 MA_ADD9/RSVD L23 DDRA_DQ8 DDRB_MA9 AF29 MB_ADD8/RSVD MB_DATA7/MBA_DATA14
DDRA_MA11 AF27 MA_ADD10/MAB_CS_L1 MA_DATA8/MAA_DATA0 N21 DDRA_DQ9 DDRB_MA10 AM30 MB_ADD9/RSVD H31 DDRB_DQ8
DDRA_MA12 AE23 MA_ADD11/MAA_CKE1 MA_DATA9/MAA_DATA1 T21 DDRA_DQ10 DDRB_MA11 AF31 MB_ADD10/MBB_CS_L1 MB_DATA8/MBA_DATA0 H30 DDRB_DQ9
DDRA_MA13 AM23 MA_ADD12/MAA_CKE0 MA_DATA10/MAA_DATA5 T22 DDRA_DQ11 DDRB_MA12 AE32 MB_ADD11/MBA_CKE1 MB_DATA9/MBA_DATA1 K31 DDRB_DQ10
AM21 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 M22 DDRA_DQ12 DDRB_MA13 AP30 MB_ADD12/MBA_CKE0 MB_DATA10/MBA_DATA5 L30 DDRB_DQ11
17 DDRA_MA14_WE# MA_WE_L_ADD14/MAB_CKE1 MA_DATA12/MAA_DATA7 DDRA_DQ13 MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 DDRB_DQ12
AL27 L24 AP31 G30
17 DDRA_MA15_CAS# MA_CAS_L_ADD15/RSVD MA_DATA13/MAA_DATA6 DDRA_DQ14 18 DDRB_MA14_WE# MB_WE_L_ADD14/MBB_CKE1 MB_DATA12/MBA_DATA7 DDRB_DQ13
AL24 R21 AP29 H29
17 DDRA_MA16_RAS# MA_RAS_L_ADD16/MAB_CKE0 MA_DATA14/MAA_DATA2 DDRA_DQ15 18 DDRB_MA15_CAS# MB_CAS_L_ADD15/RSVD MB_DATA13/MBA_DATA6 DDRB_DQ14
R23 AN29 K30
MA_DATA15/MAA_DATA3 18 DDRB_MA16_RAS# MB_RAS_L_ADD16/MBB_CKE0 MB_DATA14/MBA_DATA2 DDRB_DQ15
K29
AL22 P24 DDRA_DQ16 MB_DATA15/MBA_DATA3
17 DDRA_BA0 MA_BANK0/MAB_CS_L0 MA_DATA16/MAA_DATA17 DDRA_DQ17 DDRB_DQ16
AK27 R26 AN31 N32
17 DDRA_BA1 MA_BANK1/MAB_CA1 MA_DATA17/MAA_DATA16 DDRA_DQ18 18 DDRB_BA0 MB_BANK0/MBB_CS_L0 MB_DATA16/MBA_DATA21 DDRB_DQ17
T27 AM32 N29
MA_DATA18/MAA_DATA21 DDRA_DQ19 18 DDRB_BA1 MB_BANK1/MBB_CA1 MB_DATA17/MBA_DATA22 DDRB_DQ18
AE27 V27 P30
17 DDRA_BG0 MA_BG0/MAA_CS_L1 MA_DATA19/MAA_DATA20 DDRA_DQ20 MB_DATA18/MBA_DATA20 DDRB_DQ19
AE26 P25 AD29 L32
17 DDRA_BG1 MA_BG1/MAA_CS_L0 MA_DATA20/MAA_DATA19 DDRA_DQ21 18 DDRB_BG0 MB_BG0/MBA_CS_L1 MB_DATA19/MBA_DATA19 DDRB_DQ20
P27 AD31 L31
MA_DATA21/MAA_DATA18 DDRA_DQ22 18 DDRB_BG1 MB_BG1/MBA_CS_L0 MB_DATA20/MBA_DATA17 DDRB_DQ21
AD22 V23 M30
17 DDRA_ACT# MA_ACT_L/RSVD MA_DATA22/MAA_DATA23 DDRA_DQ23 MB_DATA21/MBA_DATA16 DDRB_DQ22
T25 AD30 L29
MA_DATA23/MAA_DATA22 18 DDRB_ACT# MB_ACT_L/RSVD MB_DATA22/MBA_DATA18 DDRB_DQ23
L27 N31
17 DDRA_DM0 MA_DM0/MAA_DM1 DDRA_DQ24 MB_DATA23/MBA_DATA23
N23 W22 C30
17 DDRA_DM1 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 DDRA_DQ25 18 DDRB_DM0 MB_DM0/MBA_DM1 DDRB_DQ24
R27 Y23 H32 R30
17 DDRA_DM2 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 DDRA_DQ26 18 DDRB_DM1 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 DDRB_DQ25
Y24 AC24 M29 R32
17 DDRA_DM3 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 DDRA_DQ27 18 DDRB_DM2 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 DDRB_DQ26
AP27 AC23 T29 V30
17 DDRA_DM4 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 DDRA_DQ28 18 DDRB_DM3 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 DDRB_DQ27
AW23 V21 AU30 V32
17 DDRA_DM5 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 DDRA_DQ29 18 DDRB_DM4 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 DDRB_DQ28
AT21 W21 BD28 P29
17 DDRA_DM6 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 DDRA_DQ30 18 DDRB_DM5 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 DDRB_DQ29
AV18 AA24 BB23 P31
17 DDRA_DM7 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 DDRA_DQ31 18 DDRB_DM6 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 DDRB_DQ30
W24 AA22 BD20 U31
MA_DM8/RSVD_52 MA_DATA31/MAA_DATA25 18 DDRB_DM7 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 DDRB_DQ31
W31 U29
DDRA_DQS0 M25 AP26 DDRA_DQ32 MB_DM8/RSVD_57 MB_DATA31/MBA_DATA24
17 DDRA_DQS0 DDRA_DQS#0 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA17 DDRA_DQ33 DDRB_DQS0 DDRB_DQ32
M24 AN24 E29 AT29
17 DDRA_DQS#0 DDRA_DQS1 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA16 DDRA_DQ34 18 DDRB_DQS0 DDRB_DQS#0 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 DDRB_DQ33
P22 AR25 D28 AU32
17 DDRA_DQS1 DDRA_DQS#1 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA21 DDRA_DQ35 18 DDRB_DQS#0 DDRB_DQS1 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 DDRB_DQ34
P21 AU26 J31 AW31
17 DDRA_DQS#1 DDRA_DQS2 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 DDRA_DQ36 18 DDRB_DQS1 DDRB_DQS#1 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 DDRB_DQ35
T24 AN25 J29 AW30
17 DDRA_DQS2 DDRA_DQS#2 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 DDRA_DQ37 18 DDRB_DQS#1 DDRB_DQS2 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 DDRB_DQ36
R24 AN27 N30 AR30
17 DDRA_DQS#2 DDRA_DQS3 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 DDRA_DQ38 18 DDRB_DQS2 DDRB_DQS#2 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 DDRB_DQ37
AA21 AR27 M31 AT31
C 17 DDRA_DQS3 DDRA_DQS#3 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 DDRA_DQ39 18 DDRB_DQS#2 DDRB_DQS3 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 DDRB_DQ38 C
Y21 AU27 T30 AV30
17 DDRA_DQS#3 DDRA_DQS4 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA22 18 DDRB_DQS3 DDRB_DQS#3 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 DDRB_DQ39
AP23 T31 AW29
17 DDRA_DQS4 DDRA_DQS#4 MA_DQS_H4/MAB_DQS_H2 DDRA_DQ40 18 DDRB_DQS#3 DDRB_DQS4 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22
AP24 AV25 AU29
17 DDRA_DQS#4 DDRA_DQS5 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 DDRA_DQ41 18 DDRB_DQS4 DDRB_DQS#4 MB_DQS_H4/MBB_DQS_H2 DDRB_DQ40
AW22 AW25 AU31 AY29
17 DDRA_DQS5 DDRA_DQS#5 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 DDRA_DQ42 18 DDRB_DQS#4 DDRB_DQS5 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA29 DDRB_DQ41
AV22 AV20 BA27 AY32
17 DDRA_DQS#5 DDRA_DQS6 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 DDRA_DQ43 18 DDRB_DQS5 DDRB_DQS#5 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA28 DDRB_DQ42
AT20 AW20 BB27 BC27
17 DDRA_DQS6 DDRA_DQS#6 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 DDRA_DQ44 18 DDRB_DQS#5 DDRB_DQS6 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA24 DDRB_DQ43
AR20 AV27 BC23 BB26
17 DDRA_DQS#6 DDRA_DQS7 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 DDRA_DQ45 18 DDRB_DQS6 DDRB_DQS#6 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA25 DDRB_DQ44
AR18 AW26 BA23 BC25
17 DDRA_DQS7 DDRA_DQS#7 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 DDRA_DQ46 18 DDRB_DQS#6 DDRB_DQS7 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA27 DDRB_DQ45
AT18 AU21 BC20 BA25
17 DDRA_DQS#7 MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 DDRA_DQ47 18 DDRB_DQS7 DDRB_DQS#7 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA26 DDRB_DQ46
Y26 AW21 BA20 BB30
MA_DQS_H8/RSVD_58 MA_DATA47/MAB_DATA25 18 DDRB_DQS#7 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA30 DDRB_DQ47
Y27 Y32 BA28
MA_DQS_L8/RSVD_59 AT22 DDRA_DQ48 Y30 MB_DQS_H8/RSVD_61 MB_DATA47/MBB_DATA31
DDRA_CLK0 AJ25 MA_DATA48/MAB_DATA11 AP21 DDRA_DQ49 MB_DQS_L8/RSVD_60 BA24 DDRB_DQ48
17 DDRA_CLK0 DDRA_CLK0# MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 DDRA_DQ50 DDRB_CLK0 MB_DATA48/MBB_DATA11 DDRB_DQ49
AJ24 AN19 AJ31 BC24
17 DDRA_CLK0# DDRA_CLK1 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA14 DDRA_DQ51 18 DDRB_CLK0 DDRB_CLK0# MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDRB_DQ50
AJ22 AN18 AK30 BC22
17 DDRA_CLK1 DDRA_CLK1# MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA15 DDRA_DQ52 18 DDRB_CLK0# DDRB_CLK1 MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 DDRB_DQ51
AJ21 AU23 AK32 BA22
17 DDRA_CLK1# MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 DDRA_DQ53 18 DDRB_CLK1 DDRB_CLK1# MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 DDRB_DQ52
AR22 AL31 BB25
MA_DATA53/MAB_DATA13 DDRA_DQ54 18 DDRB_CLK1# MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 DDRB_DQ53
AN20 BD25
MA_DATA54/MAB_DATA9 AP19 DDRA_DQ55 MB_DATA53/MBB_DATA13 BB22 DDRB_DQ54
MA_DATA55/MAB_DATA8 MB_DATA54/MBB_DATA9 BD22 DDRB_DQ55
AT19 DDRA_DQ56 MB_DATA55/MBB_DATA8
DDRA_CS0# AL25 MA_DATA56/MAB_DATA6 AW18 DDRA_DQ57 BA21 DDRB_DQ56
17 DDRA_CS0# DDRA_CS1# MA_CS_L0/MAB_CA2 MA_DATA57/MAB_DATA7 DDRA_DQ58 MB_DATA56/MBB_DATA4 DDRB_DQ57
AM26 AU16 AN30 BC21
17 DDRA_CS1# MA_CS_L1/MAB_CA5 MA_DATA58/MAB_DATA2 DDRA_DQ59 18 DDRB_CS0# MB_CS_L0/MBB_CA2 MB_DATA57/MBB_DATA5 DDRB_DQ58
AW16 AR31 BC18
MA_DATA59/MAB_DATA3 DDRA_DQ60 18 DDRB_CS1# MB_CS_L1/MBB_CA5 MB_DATA58/MBB_DATA2 DDRB_DQ59
AW19 BB18
MA_DATA60/MAB_DATA4 AU19 DDRA_DQ61 MB_DATA59/MBB_DATA3 BB20 DDRB_DQ60
MA_DATA61/MAB_DATA5 AP16 DDRA_DQ62 MB_DATA60/MBB_DATA6 BB21 DDRB_DQ61
MA_DATA62/MAB_DATA1 AT16 DDRA_DQ63 MB_DATA61/MBB_DATA7 BB19 DDRB_DQ62
DDRA_CKE0 AD24 MA_DATA63/MAB_DATA0 MB_DATA62/MBB_DATA1 BA18 DDRB_DQ63
17 DDRA_CKE0 DDRA_CKE1 MA_CKE0/MAA_CA1 MB_DATA63/MBB_DATA0
AD25 W27 AC31
17 DDRA_CKE1 MA_CKE1/MAA_CA0 MA_CHECK0/RSVD_54 18 DDRB_CKE0 MB_CKE0/MBA_CA1
W25 AC29 W30
MA_CHECK1/RSVD_53 18 DDRB_CKE1 MB_CKE1/MBA_CA0 MB_CHECK0/RSVD_56
AC26 W29
MA_CHECK2/RSVD_68 AC27 MB_CHECK1/RSVD_55 AA30
DDRA_ODT0 AM24 MA_CHECK3/RSVD_69 V26 MB_CHECK2/RSVD_65 AB29
17 DDRA_ODT0 DDRA_ODT1 MA_ODT0/MAB_CA3 MA_CHECK4/RSVD_49 MB_CHECK3/RSVD_67
B AM27 V24 AP32 V29 B
17 DDRA_ODT1 MA_ODT1/MAB_CA4 MA_CHECK5/RSVD_48 18 DDRB_ODT0 MB_ODT0/MBB_CA3 MB_CHECK4/RSVD_50
AA27 AR29 V31
MA_CHECK6/RSVD_63 18 DDRB_ODT1 MB_ODT1/MBB_CA4 MB_CHECK5/RSVD_51
AA25 AA29
MA_CHECK7/RSVD_62 MB_CHECK6/RSVD_64 AA31
DDRA_ALERT# AE24 +1.2V MB_CHECK7/RSVD_66
17 DDRA_ALERT# MA_ALERT_L/TEST31A AK24 DDRA_PARITY 17 18 DDRB_ALERT# AE30
DDRA_EVENT# AK23 MA_PAROUT/RSVD MB_ALERT_L/TEST31B AM31
17 DDRA_EVENT# DDRA_DRAMRST# MA_EVENT_L MB_PAROUT/RSVD DDRB_PARITY 18
AD27 AN21 AL30
17 DDRA_DRAMRST# MA_RESET_L M_DDR4 18 DDRB_EVENT# MB_EVENT_L
FP6 REV0.92 AN22 AC32 FP6 REV0.92
PART 1/13 M_LPDDR4 18 DDRB_DRAMRST# MB_RESET_L PART 9/13

AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 (MEM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 6 of 68

5 4 3 2 1
 5 4 3 2 1

+1.8VS +1.8VS
UC1D

2
APU_EDP_TX0+ D11 A22 DP_ENBKL PD FOR CUSTOMER
38 APU_EDP_TX0+ APU_EDP_TX0- B11 DP0_TXP0 DP_BLON D23 DP_ENVDD PU FOR INTERNAL
RC52 RC49
+1.8VALW 38 APU_EDP_TX0- DP0_TXN0 DP_DIGON C23 DP_EDP_PWM
DP_VARY_BL 39.2_0402_1% 1K_0402_5%
APU_EDP_TX1+ C11 @
38 APU_EDP_TX1+ APU_EDP_TX1- A11 DP0_TXP1 D12 APU_EDP_AUX APU_EDP_HPD @
RC53 1 @ 2 100K_0402_5%

APU_TEST31
38 APU_EDP_TX1- DP0_TXN1 DP0_AUXP APU_EDP_AUX 38

1
1

B12 APU_EDP_AUX# APU_TEST31 DP_STEREOSYNC

RC50
eDP APU_EDP_TX2+ D10 DP0_AUXN C12 APU_EDP_HPD APU_EDP_AUX# 38 eDP Pull down on EDP conn page
M_TEST CONNECTION TBD
38 APU_EDP_TX2+ DP0_TXP2 DP0_HPD APU_EDP_HPD 38

2
1/20W_4.7K_5%_0201 APU_EDP_TX2- B10 +1.8VS
38 APU_EDP_TX2- DP0_TXN2 J20 RC54 RC51
APU_EDP_TX3+ D9 DP1_AUXP K20
38 APU_EDP_TX3+ DP0_TXP3 DP1_AUXN HDMI 39.2_0402_1% 1K_0402_5%
2

APU_RST# APU_EDP_TX3- B9 L21 @

38 APU_EDP_TX3- DP0_TXN3 DP1_HPD RPC7

1
D APU_TEST16 D
PLACE CC30 CAPS CLOSE TO APU,CRB reserve 27pf G23 L19 4 5
H23 DP1_TXP0 DP2_AUXP M19 APU_TEST15 3 6
1 DP1_TXN0 DP2_AUXN M20 Type C APU_TEST17 2 7
CC30 F22 DP2_HPD APU_TEST14 1 8
56P_50V_J_NPO_0201 G22 DP1_TXP1 M14 Pls Pull down if your project doesn’t support HDMI 12/24
2 @ DP1_TXN1 DP3_AUXP L14
HDMI G21 DP3_AUXN L16
10K_0804_8P4R_5%
10/16 david Modify
DP1_TXP2 DP3_HPD @
H21
DP1_TXN2 B23 DP_STEREOSYNC
F20 DP_STEREOSYNC
+1.8VS +1.8VALW G20 DP1_TXP3
DP1_TXN3 To EDP panel +3VS
1

RC56 4.7K Change to 1K(2020.02.13)

1
PU FOR INTERNAL
RC55
RC416 1/20W_4.7K_5%_0201
PD FOR CUSTOMER +3VALW_APU RC56
300_0402_5% 1K_0402_5%
@
2

2
APU_PWROK RC147
10K_0402_5%
PCH_EDP_PWM 38
PLACE CC31 CAPS CLOSE TO APU,CRB reserve 27pf
1 BB6 TEST4 1 @ TC4
TEST4

3
BD5 TEST5 1 @ TC5 QC1B
CC31 TEST5

D2
56P_50V_J_NPO_0201 AG12 5
2 @ TEST6 G2
G25 APU_TEST14

S2
TEST14

6
K25 APU_TEST15
APU_TEST15
QC1A
TEST15 F25 APU_TEST16

D1
TEST16

4
F26 APU_TEST17
APU_TEST17 DP_EDP_PWM 2 PJT7838_SOT363-6
TEST17 G1
+3VS_APU H26 APU_TEST311 @ TC7

S1
TEST31

1
RC58
PJT7838_SOT363-6

1
RPC8 AK9 1 @ TC8 100K_0402_5%
8 1 APU_PROCHOT#_R TEST41
7 2 APU_SID APU_TDI AP3 AK21 TEST470 1 @ TC9
TDI ANALOGIO_0

2
6 3 APU_SIC APU_TDO AU1 AG21 TEST471 1 @ TC10
C 5 4 ALERT# APU_TCK AR2 TDO ANALOGIO_1 C
APU_TMS AU3 TCK
1/16W_1K_5%_8P4R_0804 APU_TRST# AR4 TMS
APU_DBREQ# AT2 TRST_L
DBREQ_L +0.75VS

APU_RST# AW3 P3 SMU_ZVDDP RC60 1 2 196_0402_1%

APU_PWROK AW4 RESET_L SMU_ZVDD
62 APU_PWROK PWROK
RC62 1 @ 2 0_0402_5% APU_SIC B22
+3VS_APU 28,44,49 EC_SMB_CK2 1 2 0_0402_5% APU_SID D22 SIC
28,44,49 EC_SMB_DA2 RC63 @
ALERT# C22 SID AK7 VDDP_S5_SENSE 1 @ TC25
APU_THERMTRIP# AN9 ALERT_L VDDP_S5_SENSE AK12 APU_VDDP_RUN_FB_H 1 @ TC11
25,49 APU_THERMTRIP# 1 2 0_0402_5% APU_PROCHOT#_R B25 THERMTRIP_L VDDP_SENSE J23 VDDCR_SOC_VCC_SENSE
RC66 @
49
2 1K_0402_1% APU_THERMTRIP# APU_PROCHOT# PROCHOT_L VDDCR_SOC_SENSE VDDCR_VCC_SENSE VDDCR_SOC_VCC_SENSE 62
RC67 1 K22
VDDCR_SENSE J21 VDDCR_VCC_SENSE 62
RC68 1 @ 2 0_0402_5% APU_SVC_RA D25 VDDIO_MEM_S3_SENSE
62 APU_SVC 1 2 0_0402_5% APU_SVD_RA C25 SVC0 J22 VDDCR_VSS_SENSE
RC69 @
62 APU_SVD 1 2 0_0402_5% APU_SVT_RA A25 SVD0 FP6 REV0.92 VSS_SENSE_A AJ12 VSS_SENSEB 1 @ VDDCR_VSS_SENSE 62
RC70 @ TC12
62 APU_SVT SVT0 PART 3/13 VSS_SENSE_B

APU_SVC APU_SVD APU_SVT AMD-RENOIR-FP6_BGA1140

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

@
1 1 1
CC34 CC35 CC36
@

2 2 2
DP_ENVDD RC72 1 @ 2 0_0402_5%
PCH_EDP_ENVDD 38

1
RC71
100K_0402_5%

2
@

B +1.8VALW +1.8VS B

2
New HDT conn +1.8VALW
RC3284
0_0402_5%
RC3285
0_0402_5%
@ @
JHDT1 +1.8VALW +1.8VALW

1
1 CC358 1 2 1U_0402_6.3V6K
1 2 @ RPC9
2 3 APU_TCK 8 1
3 1
2

1
4 APU_TMS 7 2 RC74 @ @
4 5 APU_TDI 6 3 1K_0402_5% CC1274 @ RC3282 RC3283
5 6 APU_TDO 1 HDT@ 2 APU_DBREQ# 5 4 HDT@ 0.1U_6.3V_K_X5R_0201 1K_0402_5% 1K_0402_5%
6 7 APU_PWROK_BUF RC78 2
7 8 APU_RST#_BUF 33_0402_5% 1/16W_1K_5%_8P4R_0804
8
1

2
9 APU_DBREQ#_R UC6
9 HDT@
10 APU_TRST#_R RC79 1 HDT@ 2 33_0402_5% APU_TRST# APU_PWROK 3 4 APU_PWROK_BUF
13 10 11 2A 2Y
GND1 11 1
14 12 CC38 2 5 DP_ENBKL RC81 1 @ 2 0_0402_5%
GND2 12 0.01U_6.3V_K_X7R_0201 GND VCC PCH_EDP_ENBKL 38
HIGHS_FC1AF121-1151H HDT@ APU_RST# 1 6 APU_RST#_BUF
2 1A 1Y

1
ME@
@ SN74LVC2G07YZPR_WCSP6 RC80
100K_0402_5%

2
APU_PWROK RC3286 2 HDT@ 1 APU_PWROK_BUF
@
0_0402_5%
APU_RST# RC3287 2 HDT@ 1 APU_RST#_BUF
0_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 (DP/JTAG/SIV2/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 7 of 68

5 4 3 2 1
 5 4 3 2 1

Mirror code: Platform allows RSMRST# = 0 to SPI tri-state

add reserved QC11,RC3268 For mirror 07/31 +1.8VALW +3VALW_APU

1
RC3 1 @ 2 0_0402_5% 1 RC6 PCIE_WAKE#_RA RC5 1 @ 2 0_0402_5% PCIE_WAKE# 42,45,49

1
10K_0402_5%
RC4 CC21 @ DC2
10K_0402_5% 10U 6.3V M X5R 0402 SYS_RESET# 1 2 SYS_PWRGD_R
2

2
RB751V-40_SOD323-2

2
RSMRST#_R RC8 1 @ 2 0_0402_5% SYS_PWRGD_R @
49 EC_RSMRST# 49 EC_SYS_PWRGD 1
1
1 CC23
CC22 CC24 0.1U_0201_6.3V6-K
+3VL 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 2
2
2
D D

1
需要确认 RC3268
@ 10K_0402_5% RC9 1 2 33_0402_5% PCIE_RST0#_R
28,37,42,45 PLT_RST#

1
QC11A D

2
2 RC10 1
G
2N7002KDWH_SOT363-6
100K_0402_5%
@
CC25
150P_25V_J_NPO_0402 ADD TYPE-C HPD/PCH_FB_GC6_EN 2019 0910
S

2
2

3
5
QC11B D
@ ADD F2_KET
G
2N7002KDWH_SOT363-6
S UC1E

4
AM3
@ SFH_IPIO271 AT4
SFH_IPIO272 AM1
SFH_IPIO273 AJ8
SFH_IPIO274 AW7
SFH_IPIO39 AU2
PCIE_RST0#_R AP6 SFH_IPIO41
PCIE_RST1#_R AT13 PCIE_RST0_L/EGPIO26 AP14 BOARD_ID0
RSMRST#_R AR8 PCIE_RST1_L/EGPIO27 I2C0_SCL/EGPIO145 AN14 BOARD_ID1
RSMRST_L I2C0_SDA/EGPIO146
PBTN_OUT# RC11 1 @ 2 0_0402_5% PWRBTN#_R AT12 AP2 BOARD_ID2
49 PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0 I2C1_SCL/EGPIO147 VGA_ALERT#_PCH
AW2 AN3
SYS_RESET# AL2 PWR_GOOD I2C1_SDA/EGPIO148
14 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 PCH_SMBCLK
AW12 AN12
WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SMBUS0_I2C_SCL AP12 PCH_SMBDATA
PM_SLP_S3# RC14 1 @ 2 0_0402_5% PM_SLP_S3#_R AT11 I2C2_SDA/EGPIO114/SMBUS0_I2C_SDA
49 PM_SLP_S3# PM_SLP_S5# RC15 PM_SLP_S5#_R SLP_S3_L TP_I2C3_SCL_R
1 @ 2 0_0402_5% AV11 AM9
14,49 PM_SLP_S5# SLP_S5_L I2C3_SCL/AGPIO19/SMBUS1_I2C_SCL TP_I2C3_SDA_R TP_I2C3_SCL_R 14,50
AM10
AW13 I2C3_SDA/AGPIO20/SMBUS1_I2C_SDA TP_I2C3_SDA_R 14,50 Touch Pad
S0A3_GPIO/AGPIO10 D24
AC_PRESENTRC328 1 @ 2 0_0402_5% AC_PRESENT_R BA8 SFH1_SCL B24
49 AC_PRESENT PXS_PWREN_R AC_PRES/AGPIO23 SFH1_SDA
RH934 1 @ 2 0_0201_5% AV6
PM_SLP_S3# 28,51 PXS_PWREN LLB_L/AGPIO12
C CC146 @1 2 2200P_25V_K_X7R_0201 C
PM_SLP_S5# CC147 @1 2 2200P_25V_K_X7R_0201 BB7 Mute _CTL
Mic _CTL AW8 AGPIO3 BA6 SSD_SATA_PCIE_DET1# Mute _CTL 50
50 Mic _CTL EGPIO42 AGPIO4/SATAE_IFDET SSD_SATA_PCIE_DET1# 45
AK10 SATA_DEVSLP0
AGPIO5/DEVSLP0 SATA_DEVSLP0 45
BC6 OD,Pull high 3VALW?
AGPIO6/DEVSLP1 AW15 PCH_TP_INT#
SATA_ACT_L/AGPIO130 PCH_TP_INT# 50
删除DMIC AG6 AU4 PCH_TP_INT1#
ACP_WOV_CLK AGPIO9 APU_SSD_RST# PCH_TP_INT1# 50
AG7 AP7
@ 1 AJ6 ACP_WOV_MIC0_MIC1_DATA AGPIO40 AV13 PXS_RST#_R RH315 1 @ APU_SSD_RST#
2 0_0201_5% 45
Board ID Description Stuff R TC17 ACP_WOV_MIC2_MIC3_DATA AGPIO69 BB12 EC_SMI# PXS_RST# 28
+3VS_APU
HDA_BITCLK AN6 AGPIO86/SPI_CLK2 EC_SMI# 49
RC19 1 @ 2 0_0402_5% HDA_SDIN0_R AL6 AZ_BITCLK/TDM_BCLK_MIC
35 HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/CODEC_GPI INTRUDER_ALERT EC_SMI#
0 APU R5 RC42 TC1 @ 1 AM7
AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT
AU7 RC20 2 @ 1 20M_0402_5% VCCRTC RC21 1 2 2.2K_0402_5%
TC2 @ 1 HDA_SDIN2 AJ9 AR11
BOARD_ID0 HDA_RST# AM6 AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK/ACP_WOV_MIC4_MIC5_DATA SPKR/AGPIO91 AW11 BLINK
PCH_BEEP 35 PXS_PWREN RC3277 1 2 10K_0402_5%
HDA_SYNC AN8 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11
1 APU R7 RC35 AZ_SYNC/TDM_FRM_MIC
HDA_SDOUT AK6 AV15 PCH_FB_GC6_EN
AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 PCH_GPU_EVENT# PCH_FB_GC6_EN 28
AU14 +3VALW_APU
GENINT2_L/AGPIO90 PCH_GPU_EVENT# 28
0 Non_DCC RC43 AM4
SW_MCLK/TDM_BCLK_BT
AL3
BOARD_ID1 BOARD_ID3 AM2 SW_DATA0/TDM_DOUT_BT AT10 RPC3
AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84 VGA_PWRGD
PXS_PWREN 25,28 TP_I2C3_SDA_R
1 DCC RC36 46 USBDEBUG
USBDEBUG AL4
AGPIO8/FCH_ACP_I2S_LRCLK_BT
FP6 REV0.92
FANOUT0/AGPIO85
AU10 RH935 1 @ 2 0_0201_5% 1 4
PART 4/13 TP_I2C3_SCL_R 2 3

0 Reserve RC44 AMD-RENOIR-FP6_BGA1140 2.2K_0404_4P2R_5%

BOARD_ID2 @
+3VALW_APU
1 Reserve RC37 RPC4
PBTN_OUT# 1 8
PCIE_WAKE#_RA 2 7
0 G62 GPU RC48 AC_PRESENT 3 6
PXS_PWREN_R 4 5
BOARD_ID3 +1.8VS_AON
1 G61 GPU RC41 RPC5 10K_0804_8P4R_5%
TC3 @ 1 HDA_RST_AUDIO# 1 8 HDA_RST#
2 7 HDA_SYNC BLINK RC24 1 @ 2 10K_0402_5%
B 35 HDA_SYNC_AUDIO B
0 Reserve RH923 3 6 HDA_BITCLK PM_SLP_S3#_R RC25 1 @ 2 2.2K_0402_5%
35 HDA_BITCLK_AUDIO HDA_SDOUT PM_SLP_S5#_R
BOARD_ID4 35 HDA_SDOUT_AUDIO
4 5 RC26 1 @ 2 2.2K_0402_5%

2
APU_SSD_RST# RC27 1 @ 2 10K_0402_5%
1 Reserve RH924 1/16W_33_5%_8P4R_0804 Mute _CTL RC3276 1 @ 2 10K_0402_5%
Mic _CTL RC3279 1 @ 2 10K_0402_5%
3 1 VGA_ALERT#_PCH SATA_DEVSLP0 RC415 1 2 10K_0402_5%
28 VGA_ALERT#
2

2
0 Non_E15P RH927 PCH_TP_INT1# RC3281 1 2 10K_0402_5%

1K_0402_5%

1K_0402_5%

1K_0402_5%
BOARD_ID5
RC29

RC30

RC31
QH22 PCH_TP_INT# RC28 1 2
1 E15P RH926 @ 10K_0201_5%
LSI1012XT1G_SC-89-3 RSMRST#_R RC32 1 @ 2 100K_0402_5%
1

1
@ SYS_PWRGD_R RC33 1 2 100K_0402_5%
@ @ @
PCIE_RST1#_R RC34 1 @ 2 10K_0201_5%

DIMM1, DIMM2

+1.8VS +3VALW_APU

RPH7
2N7002KDWH 1 4 +3VS
Vth= min 1V, max 2.5V 2 3
ESD 2KV
2.2K_0404_4P2R_5%
2

RC35 RC37
10K_0201_5% RC36 10K_0201_5% G61@ RC41
10K_0201_5% 10K_0201_5%
DCC@
For EMI
1

@ @ HDA_BITCLK
BOARD_ID0
1
BOARD_ID1 CC27 PCH_SMBCLK RH929 1 @ 2 0_0201_5%
BOARD_ID2 10P_0201_25V8G SMB_CLK_S3 17,18
BOARD_ID3 EMC@ PCH_SMBDATA RH930 1 @ 2 0_0201_5%
2 SMB_DATA_S3 17,18
A A

Close to PCH
2

RC42 RC44
10K_0201_5% RC43 10K_0201_5% G62@ RC48
10K_0201_5% 10K_0201_5%
Non_DCC@
1

@ @ Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 AZ/I2C/ACPI/GPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
Document Number
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date:
Date: Saturday, May 09, 2020 Sheet
Sheet 8 of 68
5 4 3 2 1
 5 4 3 2 1

+3VS_APU LPCCLK0 PCH_SPI_CLK

RPC11
1 8 SSD_CLKREQ1#

2
2 7 WLAN_CLKREQ# RC82 1 2 33_0402_5% LPC_RST#_R
SSD_CLKREQ# 14,37,49 APU_LPC_RST#
3 6 RC83
4 5 1 0_0201_5% RC90
CC41 EMC_NS@ 10_0402_5%
10K_0804_8P4R_5% 150P_25V_J_NPO_0402 EMC_NS@

1
+3VS_APU
2
RPC58 1 1
1 4 GPU_CLKREQ# CC42 CC43
2 3 LAN_CLKREQ# 22P_0201_25V8 10P_0201_25V8G
EMC_NS@ EMC_NS@
10K_0404_4P2R_5% 2 2
EMC EMC
D D
UC1F

+3VS_APU
+3VS_APU +3VS_APU SSD_CLKREQ1# AR13
45 SSD_CLKREQ1# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
AP10
45 WLAN_CLKREQ# SSD_CLKREQ# CLK_REQ1_L/AGPIO115 LPC_FRAME#
AR15 RC94 1 @ 2 10K_0201_5%
45 SSD_CLKREQ# BOARD_ID4 RH925 1 CLK_REQ2_L/AGPIO116
@ 2 0_0201_5%
AT14
BOARD_ID5 AN11 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 KBRST# RC96 1 2 10K_0201_5%
CLK_REQ4_L/OSCIN/EGPIO132 10/16 david Modify
1

GPU_CLKREQ# AN13
25 GPU_CLKREQ# LAN_CLKREQ# CLK_REQ5_L/EGPIO120
@ AN15 LDRQ0# RC3272 1 2 10K_0201_5%
42 LAN_CLKREQ# CLK_REQ6_L/EGPIO121
RH924 RH926
10K_0201_5% 10K_0201_5% AW14 RC3278 1 FP@ 2 0_0402_5% FPR_RESET
EGPIO70 BB13 FPR_RESET 50
E15P@ LPCPD# LPCPD# 14
LPC_PD_L/AGPIO21
2

CLK_PCIE_SSD1 RC84 1 @ 2 0_0402_5% CLK_PCIE_SSD1_R AF11 BA16 LAD0 RC85 1 2 10_0402_5%

45 CLK_PCIE_SSD1 CLK_PCIE_SSD1# GPP_CLK0P LAD0/ESPI1_DATA0/EGPIO104 LPC_AD0 49
PCIE CLK0 SSD1 RC86 1 @ 2 0_0402_5% CLK_PCIE_SSD1#_R AF12 BA15 LAD1 RC87 1 2 10_0402_5%
BOARD_ID4 BOARD_ID5 45 CLK_PCIE_SSD1# GPP_CLK0N LAD1/ESPI1_DATA1/EGPIO105 LPC_AD1 49
BC13 LAD2 RC88 1 2 10_0402_5% LPC_AD2 49
LAD2/ESPI1_DATA2/EGPIO106
1

CLK_PCIE_WLAN RC89 1 @ 2 0_0402_5% CLK_PCIE_WLAN_R AG4 BB14 LAD3 RC91 1 2 10_0402_5% LPC_AD3 49
45 CLK_PCIE_WLAN CLK_PCIE_WLAN# RC92 1 2 0_0402_5% CLK_PCIE_WLAN#_R AG2 GPP_CLK1P LAD3/ESPI1_DATA3/EGPIO107 BB15 2 1
PCIE CLK1 WLAN @ LPCCLK0RC93 3.3_0402_1%
45 CLK_PCIE_WLAN# GPP_CLK1N LPCCLK0/EGPIO74 BD13 CLK_PCI_EC 49 1 2 0_0201_5%
RH923 RH927 RC57 @
CLK_PCIE_SSD LPC_CLKRUN_L/AGPIO88 LPC_CLKRUN# 14
10K_0201_5% 10K_0201_5% RC417 1 @ 2 0_0402_5% CLK_PCIE_SSD_R AG3 BA12 PCH_WLAN_OFF# RC3280 1 TPM@ 2 0_0201_5% TPM_SPI_IRQ# 37
45 CLK_PCIE_SSD CLK_PCIE_SSD# GPP_CLK2P LPCCLK1/EGPIO75 PCH_WLAN_OFF# 45
@ Non_E15P@ PCIE CLK2 SSD0 RC418 1 @ 2 0_0402_5% CLK_PCIE_SSD#_R AG1 BC15 SERIRQ 14,49
45 CLK_PCIE_SSD# GPP_CLK2N SERIRQ/AGPIO87
2

BA13
AF2 LFRAME_L/EGPIO109 LPC_FRAME# 49
AF4 GPP_CLK3P BC12 LPC_RST#_R
PCIE CLK3 Card Reader GPP_CLK3N LPC_RST_L/AGPIO32 AU12 RC3271 1 @ 2 1/16W_0_5%_0402
AGPIO68 EC_SCI# FPR_DELINK 50 7/18 Connect to PD
AH2 AP4
GPP_CLK4P LPC_PME_L/AGPIO22 EC_SCI# 49
AH4
GPP_CLK4N
CLK_PCIE_GPU RC419 1 @ 2 0_0402_5% CLK_PCIE_GPU_R AJ2
25 CLK_PCIE_GPU CLK_PCIE_GPU# GPP_CLK5P +3VALW_APU
PCIE CLK5 dGPU RC420 1 @ 2 0_0402_5% CLK_PCIE_GPU#_R AJ4 BA11 EGPIO67
25 CLK_PCIE_GPU# GPP_CLK5N SPI_ROM_REQ/EGPIO67 BB11
CLK_PCIE_LAN RC421 1 @ 2 0_0402_5% CLK_PCIE_LAN_R AF8 SPI_ROM_GNT/EGPIO76 EC_SCI# RC100 1 @ 2 10K_0201_5%
42 CLK_PCIE_LAN CLK_PCIE_LAN# 1 2 0_0402_5% CLK_PCIE_LAN#_R AF9 GPP_CLK6P/WIFIBT_CLKP AT15
PCIE CLK5 LAN RC422 @ KBRST# KBRST# 49
42 CLK_PCIE_LAN# GPP_CLK6N/WIFIBT_CLKN ESPI_RESET_L/KBRST_L/AGPIO129 BC11 1 2 0_0201_5%
Follow CRB 0Ω resistor pull down RC101 @ LDRQ0# LDRQ0# 14 EGPIO67 RC3288 1 @ 2 10K_0402_5%
TC16 @ 1 48M_OSC AK1 ESPI_ALERT_L/LDRQ0_L/EGPIO108
RC99 1 2 0_0201_5% XGBECLK0 X48M_OSC BC10 SPI_CLK RC102 1 @ 2 0_0201_5% PCH_SPI_CLKM
C SPI_CLK/ESPI_CLK C
RC98 1 2 0_0201_5% XGBECLK1 BA10 SPI_D1 RC103 1 @ 2 0_0201_5% SPI_SO_C
X48M_X1 SPI_DI/ESPI_DATA SPI_D0 SPI_SI_C SPI_SO_C 37,49
BB3 BB8 RC104 1 @ 2 0_0201_5% SPI_SI_C 37,49
X48M_X1 SPI_DO BA9 SPI_D2 RC105 1 @ 2 0_0201_5% PCH_SPI_D2
SPI_WP_L/ESPI_DAT2 BC8 SPI_D3 RC106 1 @ 2 0_0201_5% PCH_SPI_D3 SPI_CS2# CC1275 1 2 22P_0402_50V8-J
SPI_HOLD_L/ESPI_DAT3 BD11 SPI_CS1# RC107 1 @ 2 0_0201_5% SPI_CS1#_R TPM@
X48M_X2 BA5 SPI_CS1_L BC9 AGPIO30
X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 BB10 RC3275 1 @ 2 0_0201_5% TPM_SPI_IRQ#
SPI_CS3_L/AGPIO31 BD8 SPI_CS2#
SPI_TPM_CS_L/AGPIO29 SPI_CS2# 37 +3VS_APU

XGBECLK0 AG10
XGBECLK1 AG9 RSVD_71
RSVD_70

1 RC108 2

1 RC109 2

1 RC112 2
1K_0402_1%

1K_0402_1%

1K_0402_1%
AW10
45 SUSCLK RTCCLK

X32K_X1 AY1 BA17 APU_UART0_RXD

X32K_X1 EGPIO141/UART0_RXD APU_UART0_TXD @ @ @
BC16
EGPIO143/UART0_TXD BD15 PCH_BT_OFF#
EGPIO142/UART0_RTS_L/UART1_RXD PCH_BT_OFF# 45
BC17 RH933 1 @ 2 0_0201_5%
RC113 X32K_X2 AY4 EGPIO140/UART0_CTS_L/UART1_TXD BB16 PCH_SPI_PIRQ# PCH_FNLK 49,50
1 2 X32K_X2 AGPIO144/SHUTDOWN_L/UART0_INTR
20M_0402_5% FP6 REV0.92
YC1 PART 5/13
1 2 ADD QC7 For Mirror required 09/27
AMD-RENOIR-FP6_BGA1140
32.768KHZ_12.5PF_202740-PG14 @
+3VALW_APU
1 1

48MHz/10pF Crystal X48M_X1

CC44
9P_50V_B_NPO_0402
CC45
9P_50V_B_NPO_0402 Modify QC7 to SB00000ZI00 0805
2 2

2
X48M_X2

PCH_SPI_CLKM 3 1 SPI_CLK_PCH_C
B SPI_CLK_PCH_C 14,37,49 B
RC115 1 2 1M_0402_5%
Kevin H: change YC1 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00
YC2 QC7
LSI1012XT1G_SC-89-3
+1.8V_SPI +1.8VALW
1 4 RC3270 1 2 0_0402_5%
OSC1 NC2 UC3
SPI_CS1#_R +1.8V_SPI
0.085 A
2 3 1 8 RC118 1 @ 2 0_0402_5% @
NC1 OSC2 /CS VCC
PCH_SPI_D1 2 7 PCH_SPI_D3
1 1 DO /RESET 1
48MHZ 10PF +-10PPM 7V48000023
CC46 CC47 PCH_SPI_D2 3 6 PCH_SPI_CLK CC48 FPR_DELINK RC114 1 @ 2 10K_0201_5%
5.6P_50V_C_NPO_0402 5.6P_50V_C_NPO_0402 /WP CLK 0.1U_0201_6.3V6-K
2 2 4 5 PCH_SPI_D0 2 AGPIO30 RC3273 1 @ 2 10K_0201_5%
Need change to ±10ppm GND DI

W25Q128JWSIQ_SO8
16MB(128Mb)
+1.8V_SPI

RC119 1 2 10K_0402_5% SPI_CS1#_R SPI_CLK_PCH_C RC159 1 @ 2 0_0201_5% PCH_SPI_CLK

RC120 1 2 10K_0402_5% PCH_SPI_D1
RC121 1 @ 2 10K_0402_5% PCH_SPI_D2
RC122 1 @ 2 10K_0402_5% PCH_SPI_D3 SPI_CS1#_R RC162 1 @ 2 0_0201_5% EC_SPI_CS1#_R
EC_SPI_CS1#_R 49

SPI_SI_C RC163 1 @ 2 0_0201_5% PCH_SPI_D0

SPI_SO_C RC166 1 @ 2 0_0201_5% PCH_SPI_D1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 CLK/LPC/SD/EMMC/UART

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 9 of 68

5 4 3 2 1
 5 4 3 2 1

UC1G

N7 P8
R7 AGPIO256/WIFIBT_BT_DATA EGPIO267/RFIC_SPI_CLK R9
N6 AGPIO257/WIFIBT_BT_VALID EGPIO268/RFIC_SPI_SS R6
T6 AGPIO258/WIFIBT_BT_SYNC AGPIO269/RFIC_SPI_DATA
AGPIO259/WIFIBT_BT_CLK

D R10 P9 D
T12 AGPIO260/WIFIBT_QSPI_DATA0
AGPIO270/WIFIBT_RFIC_WAKEUP T9
P12 AGPIO261/WIFIBT_QSPI_DATA1 EGPIO271/WIFIBT_BUCKEN T8
P11 AGPIO262/WIFIBT_QSPI_DATA2 EGPIO266/WIFIBT_FLOW
T11 AGPIO263/WIFIBT_QSPI_DATA3
P6 AGPIO264/WIFIBT_QSPI_CLK
AGPIO265/WIFIBT_QSPI_SS V7
WIFIBT_DATA_RXP V6
WIFIBT_DATA_RXN
V9
WIFIBT_DATA_TXP V10
WIFIBT_DATA_TXN
FP6 REV0.92
PART 12/13

AMD-RENOIR-FP6_BGA1140
@

UC1H

USB20_P0 AC6 AA1 TYPE-C_USB3_TX_P0

48 USB20_P0 USB20_N0 USBC0_DP/USB0_DP USBC0_TX1P/USB0_TXP/DP2_TXP2 TYPE-C_USB3_TX_N0 TYPE-C_USB3_TX_P0 48
AC7 AA3
USB-C 48 USB20_N0 USBC0_DN/USB0_DN USBC0_TX1N/USB0_TXN/DP2_TXN2 TYPE-C_USB3_TX_N0 48
USB20_P1 AA8 AA2 TYPE-C_USB3_RX_P0 TYPE-C USB (3.0)
46 USB20_P1 USB1_DP USBC0_RX1P/USB0_RXP/DP2_TXP3 TYPE-C_USB3_RX_P0 48
USB20_N1 AA9 AA4 TYPE-C_USB3_RX_N0
LEFT USB3.0(MB) 46 USB20_N1 USB1_DN USBC0_RX1N/USB0_RXN/DP2_TXN3 TYPE-C_USB3_RX_N0 48
USB20_P2 Y10 AC2
38 USB20_P2 USB20_N2 USB2_DP USBC0_TX2P/DP2_TXP1
Y9 AC4
Camera 38 USB20_N2 USB2_DN USBC0_TX2N/DP2_TXN1
USB20_P3 Y7 AC1
50 USB20_P3 USB20_N3 Y6 USB3_DP USBC0_RX2P/DP2_TXP0 AC3 Leakage USB3.0 Port for Right USB Port
FPR 50 USB20_N3 USB3_DN USBC0_RX2N/DP2_TXN0
AE1 USB30_TX_P1
USB1_TXP USB30_TX_N1 USB30_TX_P1 46
AE3
USB1_TXN USB30_TX_N1 46
AC9
删除 USBC4_DP/USB4_DP USB30_RX_P1
AC10 AD8
USB-C USBC4_DN/USB4_DN USB1_RXP AD9 USB30_RX_N1
USB30_RX_P1 46 LEFT USB (3.0)
C USB20_P5 AA11 USB1_RXN USB30_RX_N1 46 MB C
46 USB20_P5 USB20_N5 USB5_DP
AA12
Right USB (2.0) 46 USB20_N5 USB5_DN
USB20_P6 W8
45 USB20_P6 USB20_N6 USB6_DP
W9 V3
BT 45 USB20_N6 USB6_DN USBC4_TX1P/USB4_TXP/DP3_TXP2 V1
USB20_P7 W11 USBC4_TX1N/USB4_TXN/DP3_TXN2
46 USB20_P7 USB20_N7 W12 USB7_DP U4
删除 TYPE-C USB (3.0)
Cardreader 46 USB20_N7 USB7_DN USBC4_RX1P/USB4_RXP/DP3_TXP3 U2
+1.8VALW USBC4_RX1N/USB4_RXN/DP3_TXN3
RPC57
1 4 USBC_I2C_SCL AL9 W2
2 3 USBC_I2C_SCL USBC4_TX2P/DP3_TXP1 W4
USBC_I2C_SDA AL8 USBC4_TX2N/DP3_TXN1
4.7K_0404_4P2R_5% USBC_I2C_SDA W1
USBC4_RX2P/DP3_TXP0 W3
HDMI_HPD AE9 USBC4_RX2N/DP3_TXN0
39 HDMI_HPD USB_OC1# USB_OC0_L/AGPIO16 USB30_TX_P5
AE10 AD2
46 USB_OC1# USB_OC2# USB_OC1_L/AGPIO17 USB5_TXP USB30_TX_N5 USB30_TX_P5 46
AE6 AD4
46 USB_OC2# TYPE_C_OCP# USB_OC2_L/AGPIO18 USB5_TXN USB30_TX_N5 46
AE7
48 TYPE_C_OCP# USB_OC3_L/AGPIO24 USB30_RX_P5
AD12
USB5_RXP AD11 USB30_RX_N5
USB30_RX_P5 46 Right USB (3.0)
USB5_RXN USB30_RX_N5 46

UPdate 20190910 FP6 REV0.92

PART 10/13

AMD-RENOIR-FP6_BGA1140
@

+3VALW_APU

RPC59
1 8
USB_OC2# 2 7
TYPE_C_OCP# 3 6
USB_OC1# 4 5

10K_0804_8P4R_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 USB/WIFI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size
D Document Number Rev 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 10 of 68
5 4 3 2 Date: 1 Sheet
 5 4 3 2 1

D D

UC1I

D21 A18
A20 CAM0_CSI2_CLOCKP CAM0_CLK
CAM0_CSI2_CLOCKN C18
D18 CAM0_I2C_SCL B17
B18 CAM0_CSI2_DATAP0 CAM0_I2C_SDA
C C
CAM0_CSI2_DATAN0 D17
C19 CAM0_SHUTDOWN
D20 CAM0_CSI2_DATAP1
CAM0_CSI2_DATAN1
C21
B21 CAM0_CSI2_DATAP2
CAM0_CSI2_DATAN2
C20
B20 CAM0_CSI2_DATAP3
CAM0_CSI2_DATAN3
C15 A13
A15 CAM1_CSI2_CLOCKP CAM1_CLK
CAM1_CSI2_CLOCKN B13
D16 CAM1_I2C_SCL D13
B16 CAM1_CSI2_DATAP0 CAM1_I2C_SDA
CAM1_CSI2_DATAN0 C14
D15 CAM1_SHUTDOWN
B15 CAM1_CSI2_DATAP1 C16
CAM1_CSI2_DATAN1 FP6 REV0.92 CAM_PRIV_LED C13
PART 13/13 CAM_IR_ILLU

AMD-RENOIR-FP6_BGA1140
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 CAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 11 of 68

5 4 3 2 1
 5 4 3 2 1

+VDDCR_VDD
+VDDCR_SOC +VDDCR_VDD
UC1J
15A N16 G7 58A
N18 VDDCR_SOC_1 VDDCR_1 G10
N20 VDDCR_SOC_2 VDDCR_2 G12

180P_50V_J_NPO_0402
P17 VDDCR_SOC_3 VDDCR_3 G14

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
P19 VDDCR_SOC_4 VDDCR_4 H8
VDDCR_SOC_5 VDDCR_5 1 1 1 1 1
R18 H11

CC60

CC165

CC166

CC167

1U_0201_6.3V6-M
R20 VDDCR_SOC_6 VDDCR_6 H15 CC169
T19 VDDCR_SOC_7 VDDCR_7 K6 @ @ @
U18 VDDCR_SOC_8 VDDCR_8 K12 2 2 2 2 2
@
U20 VDDCR_SOC_9 VDDCR_9 K14
D D
V19 VDDCR_SOC_10 VDDCR_10 L8
W18 VDDCR_SOC_11 VDDCR_11 M7
W20 VDDCR_SOC_12 VDDCR_12 M10
Y19 VDDCR_SOC_13 VDDCR_13 N14
VDDCR_SOC_14 VDDCR_14 P7
VDDCR_15 P10
+1.2V VDDCR_16 P13
VDDCR_17 P15
6A AC20 VDDCR_18 R8
AC28 VDDIO_MEM_S3_1 VDDCR_19 R14
AD23 VDDIO_MEM_S3_2 VDDCR_20 R16
AD26 VDDIO_MEM_S3_3 VDDCR_21 T7 +VDDCR_SOC
AD28 VDDIO_MEM_S3_4 VDDCR_22 T10
AD32 VDDIO_MEM_S3_5 VDDCR_23 T13
+3VS_APU AE20 VDDIO_MEM_S3_6 VDDCR_24 T15

22UC_6.3VC_MC_X5RC_0603
+3VS AE22 VDDIO_MEM_S3_7 VDDCR_25 T17

180P_50V_J_NPO_0402
AE25 VDDIO_MEM_S3_8 VDDCR_26 U14

0.1U_0201_6.3V6-K
AE28 VDDIO_MEM_S3_9 VDDCR_27 U16

22UC_6.3VC_MC_X5RC_0603
VDDIO_MEM_S3_10 VDDCR_28 1 1 1
RC125 1 @ 2 0_0402_5%1 AF23 V13

CC77

CC168
1 1 1

1U_0201_6.3V6-M
AF26 VDDIO_MEM_S3_11 VDDCR_29 V15 CC76

CC141
CC66

1U_0201_6.3V6-M

1U_0201_6.3V6-M
VDDIO_MEM_S3_12 VDDCR_30
22UC_6.3VC_MC_X5RC_0603

CC67 CC68 AF28 V17 @

AF32 VDDIO_MEM_S3_13 VDDCR_31 W7 2 2 2
2 2 2 2 AG20 VDDIO_MEM_S3_14 VDDCR_32 W10
AG22 VDDIO_MEM_S3_15 VDDCR_33 W14
+1.8VS BO BU AG25 VDDIO_MEM_S3_16 VDDCR_34 W16
AG28 VDDIO_MEM_S3_17 VDDCR_35 Y8
1 1 1
1A AJ20 VDDIO_MEM_S3_18 VDDCR_36 Y13
AJ23 VDDIO_MEM_S3_19 VDDCR_37 Y15
CC78

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC79 CC80 AJ26 VDDIO_MEM_S3_20 VDDCR_38 Y17

AJ28 VDDIO_MEM_S3_21 VDDCR_39 AA7
2 2 2 AJ32 VDDIO_MEM_S3_22 VDDCR_40 AA10
+1.8VS +1.8VALW VDDIO_MEM_S3_23 VDDCR_41
22UC_6.3VC_MC_X5RC_0603

AK22 AA14
BO BU AK25 VDDIO_MEM_S3_24 VDDCR_42 AA16
AK28 VDDIO_MEM_S3_25 VDDCR_43 AA18
+1.8VALW AL23 VDDIO_MEM_S3_26 VDDCR_44 AB13
VDDIO_MEM_S3_27 VDDCR_45

2
AL26 AB15
RC126 RC127 AL28 VDDIO_MEM_S3_28 VDDCR_46 AB17 +1.2V
1 1 VDDIO_MEM_S3_29 VDDCR_47
1 @ 0_0402_5%
0_0402_5% AL32 AB19
1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC82 CC83 AM22 VDDIO_MEM_S3_30 VDDCR_48 AC14

CC81

@ +VDD_AUD_ALW AM25 VDDIO_MEM_S3_31 VDDCR_49 AC16

2 2 VDDIO_MEM_S3_32 VDDCR_50

1
AM28 AC18

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

180P_50V_J_NPO_0402
0.22U_0201_6.3V6-K
2 VDDIO_MEM_S3_33 VDDCR_51
22UC_6.3VC_MC_X5RC_0603

AN28 AD7
BO BU AN32 VDDIO_MEM_S3_34 VDDCR_52 AD10
1 1 1 VDDIO_MEM_S3_35 VDDCR_53 1 1 1 1 1 1 1 1 1 1 1 1
AP28 AD13

CC88

CC89

CC90

CC91

CC93

CC95

CC161

CC162

CC163

CC98
CC84

CC85

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
C +3VALW_APU CC86 AR32 VDDIO_MEM_S3_36 VDDCR_54 AD15 CC96 CC97 C
VDDIO_MEM_S3_37 VDDCR_55 AD17
2 2 2 AC21 VDDCR_56 AD19 2 2 2 2 2 2 2 2 2 2 2 2
1 1 VDDIO_VPH_1 VDDCR_57
1 AD21 AE8
1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC100 CC101 BO BU VDDIO_VPH_2 VDDCR_58 AE14

0.2A
CC99

AP9 VDDCR_59 AE16

2 2 VDDIO_AUDIO VDDCR_60 AE18
2 0.25A VDDCR_61
22UC_6.3VC_MC_X5RC_0603

AL18 AF7
BO BU AM17 VDD_33_1 VDDCR_62 AF10
VDD_33_2 VDDCR_63 AF13
+0.75VALW 2.5A AL20 VDDCR_64 AF15
ALL BU(on bottom side under SOC)
AM19 VDD_18_1 VDDCR_65 AF17
VDD_18_2 VDDCR_66 AF19
1
1 1 1 1A AL19 VDDCR_67 AG14
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC103 CC104 CC105 AM18 VDD_18_S5_1 VDDCR_68 AG16

CC102

VDD_18_S5_2 VDDCR_69 AG18

2 2 2 0.25A AL17 VDDCR_70 AH13 +1.2V
2 AM16 VDD_33_S5_1 VDDCR_71 AH15
VDD_33_S5_2 VDDCR_72 AH17
2A VDDCR_73
22UC_6.3VC_MC_X5RC_0603

BO
22UC_6.3VC_MC_X5RC_0603

BU AL11 AH19
+0.75VS AL12 VDDP_S5_1 VDDCR_74 AJ7
AM12 VDDP_S5_2 VDDCR_75 AJ10

180P_50V_J_NPO_0402

180P_50V_J_NPO_0402
180P_50V_J_NPO_0402

VDDP_S5_3 VDDCR_76 AJ14

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 1 1
2A M15 VDDCR_77 AJ16 1 1 1 1 1 1
M16 VDDP_1 VDDCR_78 AJ18

CC117

CC118

CC119

CC120

CC121

CC122
CC106

CC107

CC116
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC108 CC109 CC110 CC111 CC112 CC113 CC114 CC115 M18 VDDP_2 VDDCR_79 AK13
VDDP_3 VDDCR_80 AK15
2 2 2 2 2 2 2 2 2 2 2 VDDCR_81 AK17 2 2 2 2 2 2
VDDCR_82 AK19
AJ11 VDDCR_83
BO(Bottom side outside SOC) BU VDDBT_RTC_G FP6 REV0.92
PART 6/13

VCCRTC +RTCBATT_APU AMD-RENOIR-FP6_BGA1140

Decoupling between processor and DIMMs
Across vddio and vss split
1 2
0.1A @
RC128 1K_0402_5%
0.22U_0201_6.3V6-K

1 1 +1.2V
CC124
1U_0201_6.3V6-M

CC123
2 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
B RC130 1 1 1 1 1 1 1 1 1 1 B
BU 470_0603_5%

CC125

CC164

CC127

CC128

CC129

CC130

CC131

CC132

CC133

CC134
@
2 2 2 2 2 2 2 2 2 2
12

D QC4
2 EC_RTCRST#_ON
G EC_RTCRST#_ON 49
2

S L2N7002KWT1G_SOT323-3 RC131 @ @ @ @ @ @ @ @ @ @
3

@ 10K_0402_5%
@
Reserved for debug
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 12 of 68
5 4 3 2 1
 5 4 3 2 1

D D

UC1K UC1L UC1M

AM20 K28 AR14 BD19 V5 AE13

A3 VSS_310 VSS_60 K32 AR16 VSS_246 VSS_305 BD21 V8 VSS_122 VSS_184 AE15
A5 VSS_1 VSS_61 L5 AR19 VSS_247 VSS_306 BD23 V11 VSS_123 VSS_185 AE17
A7 VSS_2 VSS_62 L13 AR21 VSS_248 VSS_307 BD26 V14 VSS_124 VSS_186 AE19
A10 VSS_3 VSS_63 L15 AR26 VSS_249 VSS_308 BD30 V16 VSS_125 VSS_187 AF1
A12 VSS_4 VSS_64 L18 AR28 VSS_250 VSS_309 V18 VSS_126 VSS_188 AF3
A14 VSS_5 VSS_65 L20 AT23 VSS_251 V20 VSS_127 VSS_189 AF5
A16 VSS_6 VSS_66 L25 AU5 VSS_252 V22 VSS_128 VSS_190 AF14
A19 VSS_7 VSS_67 L28 AU8 VSS_253 V25 VSS_129 VSS_191 AF16
A21 VSS_8 VSS_68 M1 AU11 VSS_254 V28 VSS_130 VSS_192 AF18
A23 VSS_9 VSS_69 M3 AU13 VSS_255 W5 VSS_131 VSS_193 AF20
A26 VSS_10 VSS_70 M5 AU15 VSS_256 W13 VSS_132 VSS_194 AG5
A30 VSS_11 VSS_71 M21 AU18 VSS_257 AV8 W15 VSS_133 VSS_195 AG8
C3 VSS_12 VSS_72 M23 AU20 VSS_258 RSVD_46 BD18 W17 VSS_134 VSS_196 AG11
C10 VSS_13 VSS_73 M26 AU22 VSS_259 RSVD_47 AV3 W19 VSS_135 VSS_197 AG13
C32 VSS_14 VSS_74 M28 AU25 VSS_260 RSVD_45 AU6 W23 VSS_136 VSS_198 AG15
E7 VSS_15 VSS_75 M32 AU28 VSS_261 RSVD_44 AR6 W26 VSS_137 VSS_199 AG17
E8 VSS_16 VSS_76 N5 AV1 VSS_262 RSVD_43 AR3 W28 VSS_138 VSS_200 AG19
E10 VSS_17 VSS_77 N8 AV5 VSS_263 RSVD_42 AP1 W32 VSS_139 VSS_201 AH14
E11 VSS_18 VSS_78 N11 AV7 VSS_264 RSVD_41 AN16 Y1 VSS_140 VSS_202 AH16
E12 VSS_19 VSS_79 N13 AV10 VSS_265 RSVD_40 AN4 Y3 VSS_141 VSS_203 AH18
E13 VSS_20 VSS_80 N15 AV12 VSS_266 RSVD_39 AN2 Y5 VSS_142 VSS_204 AH20
E14 VSS_21 VSS_81 N17 AV14 VSS_267 RSVD_38 AM14 Y11 VSS_143 VSS_205 AJ1
C C
E15 VSS_22 VSS_82 N22 AV16 VSS_268 RSVD_37 AM13 Y14 VSS_144 VSS_206 AJ3
E16 VSS_23 VSS_83 N25 AV19 VSS_269 RSVD_36 AL29 Y16 VSS_145 VSS_207 AJ5
E18 VSS_24 VSS_84 N28 AV21 VSS_270 RSVD_35 AL15 Y18 VSS_146 VSS_208 AJ13
E19 VSS_25 VSS_85 P1 AV23 VSS_271 RSVD_34 AL14 Y20 VSS_147 VSS_209 AJ15
E20 VSS_26 VSS_86 P5 AV26 VSS_272 RSVD_33 AL13 Y22 VSS_148 VSS_210 AJ17
E21 VSS_27 VSS_87 P14 AV28 VSS_273 RSVD_32 AK3 Y25 VSS_149 VSS_211 AJ19
E22 VSS_28 VSS_88 P16 AV32 VSS_274 RSVD_31 AJ29 Y28 VSS_150 VSS_212 AK5
E23 VSS_29 VSS_89 P18 AW5 VSS_275 RSVD_30 AJ27 AA5 VSS_151 VSS_213 AK8
E25 VSS_30 VSS_90 P20 AW28 VSS_276 RSVD_29 AF6 AA13 VSS_152 VSS_214 AK11
E26 VSS_31 VSS_91 P23 AY6 VSS_277 RSVD_28 AE12 AA15 VSS_153 VSS_215 AK14
E27 VSS_32 VSS_92 P26 AY7 VSS_278 RSVD_27 AD6 AA17 VSS_154 VSS_216 AK16
F5 VSS_33 VSS_93 P28 AY8 VSS_279 RSVD_26 AD3 AA19 VSS_155 VSS_217 AK18
F19 VSS_34 VSS_94 P32 AY10 VSS_280 RSVD_25 AC30 AA23 VSS_156 VSS_218 AK20
F21 VSS_35 VSS_95 R5 AY11 VSS_281 RSVD_24 AC12 AA26 VSS_157 VSS_219 AL1
F23 VSS_36 VSS_96 R11 AY12 VSS_282 RSVD_23 AB31 AA28 VSS_158 VSS_220 AL5
F28 VSS_37 VSS_97 R13 AY13 VSS_283 RSVD_22 AA20 AA32 VSS_159 VSS_221 AL7
G1 VSS_38 VSS_98 R15 AY14 VSS_284 RSVD_21 AA6 AB2 VSS_160 VSS_222 AL10
G3 VSS_39 VSS_99 R17 AY15 VSS_285 RSVD_20 Y12 AB4 VSS_161 VSS_223 AL16
G5 VSS_40 VSS_100 R19 AY16 VSS_286 RSVD_19 W6 AB14 VSS_162 VSS_224 AM5
G16 VSS_41 VSS_101 R22 AY18 VSS_287 RSVD_18 V12 AB16 VSS_163 VSS_225 AM8
G26 VSS_42 VSS_102 R25 AY19 VSS_288 RSVD_17 R12 AB18 VSS_164 VSS_226 AM11
G28 VSS_43 VSS_103 R28 AY20 VSS_289 RSVD_16 N19 AB20 VSS_165 VSS_227 AM15
G32 VSS_44 VSS_104 T1 AY21 VSS_290 RSVD_15 N12 AC5 VSS_166 VSS_228 AN1
H5 VSS_45 VSS_105 T3 AY22 VSS_291 RSVD_14 N10 AC8 VSS_167 VSS_229 AN5
H13 VSS_46 VSS_106 T5 AY23 VSS_292 RSVD_13 N9 AC11 VSS_168 VSS_230 AN7
H18 VSS_47 VSS_107 T14 AY25 VSS_293 RSVD_12 M13 AC13 VSS_169 VSS_231 AN10
H20 VSS_48 VSS_108 T16 AY26 VSS_294 RSVD_11 M12 AC15 VSS_170 VSS_232 AN23
H22 VSS_49 VSS_109 T18 AY27 VSS_295 RSVD_10 M11 AC17 VSS_171 VSS_233 AN26
H25 VSS_50 VSS_110 T20 BB1 VSS_296 RSVD_9 M6 AC19 VSS_172 VSS_234 AP5
H28 VSS_51 VSS_111 T23 BB32 VSS_297 RSVD_8 L12 AC22 VSS_173 VSS_235 AP8
J19 VSS_52 VSS_112 T26 BD3 VSS_298 RSVD_7 K19 AC25 VSS_174 VSS_236 AP13
K1 VSS_53 VSS_113 T28 BD7 VSS_299 RSVD_6 F16 AD1 VSS_175 VSS_237 AP15
K3 VSS_54 VSS_114 T32 BD10 VSS_300 RSVD_5 F14 AD5 VSS_176 VSS_238 AP18
K5 VSS_55 VSS_115 U13 BD12 VSS_301 RSVD_4 F12 AD14 VSS_177 VSS_239 AP20
K16 VSS_56 VSS_116 U15 BD14 VSS_302 RSVD_3 F10 AD16 VSS_178 VSS_240 AP25
K21 VSS_57 VSS_117 U17 BD16 VSS_303 RSVD_2 C26 AD18 VSS_179 VSS_241 AR1
K26 VSS_58 VSS_118 U19 VSS_304 RSVD_1 AD20 VSS_180 VSS_242 AR5
B VSS_59 VSS_119 V2 AE5 VSS_181 VSS_243 AR7 B
VSS_120 V4 FP6 REV0.92 AE11 VSS_182 VSS_244 AR12
FP6 REV0.92 VSS_121 PART 11/13 VSS_183 VSS_245
PART 7/13 FP6 REV0.92
AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140 PART 8/13
@ @ AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 13 of 68

5 4 3 2 1
 5 4 3 2 1

+1.8VS +1.8VALW +3VALW_APU

1
RC132 RC133 RC134
10K_0402_5% 10K_0402_5% 10K_0402_5%
@

2
D D
SPI_CLK_PCH_C
9,37,49 SPI_CLK_PCH_C 8 SYS_RESET#

1
RC135 RC136
2K_0402_5% 2K_0402_5%
@ @

2
STRAP PINS SYS_RESET#
1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
PCH_SPI_CLK 0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
GENERATE INTERNAL CLOCKS ONLY
C C

1:NORMAL RESET MODE(DEFAULT)

SYS_RESET# 0:SHORT RESET MODE

LPC ROM EMULATOR HEADER

+3VALW_APU +3VS_APU

PIN4 should be removed as a Key

2

RC138 RC139
0_0402_5% 0_0402_5%
DAISY CHAIN ROUTING FOR LPC SIGNALS
LPC@ LPC@
1

B B

LPC@
APU_LPC_RST# RC140 1 2 0_0201_5%
9,37,49 APU_LPC_RST# LPC_RST#_H 1 @ IT11 IT12 @ 1 RC141 1 @ 2 0_0201_5% PM_SLP_S5#
PM_SLP_S5# 8,49
LPCRUNPWR 1 @ IT13
LPC@ LPC@
RC142 1 2 0_0201_5% I2C3_SCL_LPC 1 @ IT15 IT14 @ 1 I2C3_SDA_LPC RC143 1 2 0_0201_5%
8,50 TP_I2C3_SCL_R TP_I2C3_SDA_R 8,50
1 @ IT17 IT16 @ 1 SERIRQ
SERIRQ 9,49
IT18 @ 1 LDRQ0#
LDRQ0# 9
2 2
CC142 CC143
0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
LPC@ 1 1 LPC@

CC142 CC143 should be put on APU side to reduce stub when MP

+3VS_APU

LPC@
RC144 1 2 10K_0201_5% LPCPD# LPCPD# 9

RC145 1 @ 2 10K_0201_5% LPC_CLKRUN#

LPC_CLKRUN# 9

RC146 2 1 100K_0201_5% APU_LPC_RST#

A A
CC138 1 @ 2 150P_0402_50V8-J

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 FP5 Straps

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Size DocumentNumber
Document Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date:
Date: Saturday, May 09, 2020 Sheet
Sheet 14 of 68
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 15 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 16 of 68

5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM A +1.2V

+1.2V +1.2V

1K_0402_5%
RD5
+1.2V +1.2V JDDRL1B

2
JDDRL1A DDRA_MA3 131 132 DDRA_MA2
6 DDRA_MA3 DDRA_MA1 A3 A2 DDRA_EVENT# DDRA_MA2 6 DDRA_EVENT#
133 134
6 DDRA_MA1 A1 EVENT_n/NF DDRA_EVENT# 6
135 136
1 2 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ12 VSS_1 VSS_2 DDRA_DQ13 6 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t/NF DDRA_CLK1# DDRA_CLK1 6
3 4 139 140
6 DDRA_DQ12 DQ5 DQ4 DDRA_DQ13 6 6 DDRA_CLK0# CK0_c CK1_c/NF DDRA_CLK1# 6
5 6 141 142
DDRA_DQ8 7 VSS_3 VSS_4 8 DDRA_DQ9 DDRA_PARITY 143 VDD_11 VDD_12 144 DDRA_MA0
6 DDRA_DQ8 DQ1 DQ0 DDRA_DQ9 6 6 DDRA_PARITY Parity A0 DDRA_MA0 6
9 10
DDRA_DQS#1 11 VSS_5 VSS_6 12
6 DDRA_DQS#1 DDRA_DQS1 DQS0_C DM0_n/DBl0_n DDRA_DM1 6 DDRA_BA1 DDRA_MA10
13 14 145 146
6 DDRA_DQS1 DQS0_t VSS_7 DDRA_DQ11 6 DDRA_BA1 BA1 A10/AP DDRA_MA10 6
15 16 147 148
DDRA_DQ10 VSS_8 DQ6 DDRA_DQ11 6 DDRA_CS0# VDD_13 VDD_14 DDRA_BA0
D 17 18 149 150 D
6 DDRA_DQ10 DQ7 VSS_9 DDRA_DQ15 6 DDRA_CS0# DDRA_MA14_WE# CS0_n BA0 DDRA_MA16_RAS# DDRA_BA0 6
19 20 151 152
DDRA_DQ14 VSS_10 DQ2 DDRA_DQ15 6 6 DDRA_MA14_WE# A14/WE_n A16/RAS_n DDRA_MA16_RAS# 6
21 22 153 154
6 DDRA_DQ14 DQ3 VSS_11 DDRA_DQ0 DDRA_ODT0 VDD_15 VDD_16 DDRA_MA15_CAS#
23 24 155 156
DDRA_DQ5 VSS_12 DQ12 DDRA_DQ0 6 6 DDRA_ODT0 DDRA_CS1# ODT0 A15/CAS_n DDRA_MA13 DDRA_MA15_CAS# 6
25 26 157 158
6 DDRA_DQ5 DQ13 VSS_13 DDRA_DQ1 6 DDRA_CS1# CS1_n A13 DDRA_MA13 6
27 28 159 160
DDRA_DQ4 VSS_14 DQ8 DDRA_DQ1 6 DDRA_ODT1 VDD_17 VDD_18
29 30 161 162
6 DDRA_DQ4 DQ9 VSS_15 DDRA_DQS#0 6 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMA
31 32 163 164
VSS_16 DQS1_c DDRA_DQS0 DDRA_DQS#0 6 VDD_19 VREFCA DDRA_SA2
6 DDRA_DM0
33 34 165 166
DM1_n/DBl_n DQS1_t DDRA_DQS0 6 C1/CS3_n/NC SA2
35 36 167 168
DDRA_DQ2 37 VSS_17 VSS_18 38 DDRA_DQ7 DDRA_DQ36 169 VSS_53 VSS_54 170 DDRA_DQ37
6 DDRA_DQ2 DQ15 DQ14 DDRA_DQ7 6 6 DDRA_DQ36 DQ37 DQ36 DDRA_DQ37 6 1 1
39 40 171 172 CD2 CD3
DDRA_DQ6 41 VSS_19 VSS_20 42 DDRA_DQ3 DDRA_DQ33 173 VSS_55 VSS_56 174 DDRA_DQ32
6 DDRA_DQ6 DQ10 DQ11 DDRA_DQ3 6 6 DDRA_DQ33 DQ33 DQ32 DDRA_DQ32 6
43 44 175 176 1000P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
DDRA_DQ20 45 VSS_21 VSS_22 46 DDRA_DQ17 DDRA_DQS#4 177 VSS_57 VSS_58 178 2 2
6 DDRA_DQ20 DQ21 DQ20 DDRA_DQ17 6 6 DDRA_DQS#4 DDRA_DQS4 DQS4_c DM4_n/DBl4_n DDRA_DM4 6
47 48 179 180
DDRA_DQ16 VSS_23 VSS_24 DDRA_DQ21 6 DDRA_DQS4 DQS4_t VSS_59 DDRA_DQ35
49 50 181 182
6 DDRA_DQ16 DQ17 DQ16 DDRA_DQ21 6 DDRA_DQ34 VSS_60 DQ39 DDRA_DQ35 6
51 52 183 184
DDRA_DQS#2 VSS_25 VSS_26 6 DDRA_DQ34 DQ38 VSS_61 DDRA_DQ38
53 54 185 186
6 DDRA_DQS#2 DDRA_DQS2 DQS2_c DM2_n/DBl2_n DDRA_DM2 6 DDRA_DQ39 VSS_62 DQ35 DDRA_DQ38 6
55 56 187 188
6 DDRA_DQS2 DQS2_t VSS_27 DDRA_DQ18 6 DDRA_DQ39 DQ34 VSS_63 DDRA_DQ41
57 58 189 190
DDRA_DQ23 VSS_28 DQ22 DDRA_DQ18 6 DDRA_DQ40 VSS_64 DQ45 DDRA_DQ41 6
59 60 191 192
6 DDRA_DQ23 DQ23 VSS_29 DDRA_DQ19 6 DDRA_DQ40 DQ44 VSS_65 DDRA_DQ44
61 62 193 194
DDRA_DQ22 VSS_30 DQ18 DDRA_DQ19 6 DDRA_DQ45 VSS_66 DQ41 DDRA_DQ44 6
63 64 195 196
6 DDRA_DQ22 DQ19 VSS_31 DDRA_DQ24 6 DDRA_DQ45 DQ40 VSS_67 DDRA_DQS#5
65 66 197 198
DDRA_DQ29 VSS_32 DQ28 DDRA_DQ24 6 VSS_68 DQS5_c DDRA_DQS5 DDRA_DQS#5 6
67 68 6 DDRA_DM5 199 200
6 DDRA_DQ29 DQ29 VSS_33 DDRA_DQ25 DM5_n/DBl5_n DQS5_t DDRA_DQS5 6
69 70 201 202
DDRA_DQ28 VSS_34 DQ24 DDRA_DQ25 6 DDRA_DQ43 VSS_69 VSS_70 DDRA_DQ46
71 72 203 204
6 DDRA_DQ28 DQ25 VSS_35 DDRA_DQS#3 6 DDRA_DQ43 DQ46 DQ47 DDRA_DQ46 6
73 74 205 206
VSS_36 DQS3_c DDRA_DQS3 DDRA_DQS#3 6 DDRA_DQ47 VSS_71 VSS_72 DDRA_DQ42
75 76 207 208
6 DDRA_DM3 DM3_n/DBl3_n DQS3_t DDRA_DQS3 6 6 DDRA_DQ47 DQ42 DQ43 DDRA_DQ42 6
77 78 209 210
DDRA_DQ31 79 VSS_37 VSS_38 80 DDRA_DQ27 DDRA_DQ53 211 VSS_73 VSS_74 212 DDRA_DQ52
6 DDRA_DQ31 DQ30 DQ31 DDRA_DQ27 6 6 DDRA_DQ53 DQ52 DQ53 DDRA_DQ52 6
81 82 213 214
DDRA_DQ30 83 VSS_39 VSS_40 84 DDRA_DQ26 DDRA_DQ49 215 VSS_75 VSS_76 216 DDRA_DQ48
6 DDRA_DQ30 DQ26 DQ27 DDRA_DQ26 6 6 DDRA_DQ49 DQ49 DQ48 DDRA_DQ48 6
85 86 217 218
87 VSS_41 VSS_42 88 DDRA_DQS#6 219 VSS_77 VSS_78 220
CB5/NC CB4/NC 6 DDRA_DQS#6 DDRA_DQS6 DQS6_c DM6_n/DBl6_n DDRA_DM6 6
89 90 221 222
VSS_43 VSS_44 6 DDRA_DQS6 DQS6_t VSS_79 DDRA_DQ50
91 92 223 224
CB1/NC CB0/NC DDRA_DQ55 VSS_80 DQ54 DDRA_DQ50 6
93 94 225 226
VSS_45 VSS_46 6 DDRA_DQ55 DQ55 VSS_81 DDRA_DQ54
95 96 227 228
DQS8_c DM8_n/DBl_n/NC DDRA_DQ51 VSS_82 DQ50 DDRA_DQ54 6
97 98 229 230
DQS8_t VSS_47 6 DDRA_DQ51 DQ51 VSS_83 DDRA_DQ56
99 100 231 232
VSS_48 CB6/NC DDRA_DQ60 VSS_84 DQ60 DDRA_DQ56 6
101 102 233 234
C CB2/NC VSS_49 6 DDRA_DQ60 DQ61 VSS_85 DDRA_DQ61 C
103 104 235 236
VSS_50 CB7/NC DDRA_DQ57 VSS_86 DQ57 DDRA_DQ61 6
105 106 237 238
CB3/NC VSS_51 DDRA_DRAMRST#_R 6 DDRA_DQ57 DQ56 VSS_87 DDRA_DQS#7
107 108 RD35 1 2 33_0402_5% 239 240
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 DDRA_DRAMRST# 6 VSS_88 DQS7_c DDRA_DQS7 DDRA_DQS#7 6
109 110 241 242
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6 6 DDRA_DM7 DM7_n/DBl7_n DQS7_t DDRA_DQS7 6
111 112 243 244
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# DDRA_DQ63 245 VSS_89 VSS_90 246 DDRA_DQ59
6 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 6 6 DDRA_DQ63 DQ62 DQ63 DDRA_DQ59 6
115 116 247 248
6 DDRA_BG0 BG0 ALERT_n DDRA_ALERT# 6 DDRA_DQ58 VSS_91 VSS_92 DDRA_DQ62
117 118 249 250
DDRA_MA12 VDD_3 VDD_4 DDRA_MA11 6 DDRA_DQ58 DQ58 DQ59 DDRA_DQ62 6
119 120 251 252
6 DDRA_MA12 DDRA_MA9 A12 A11 DDRA_MA7 DDRA_MA11 6 SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
121 122 1 8,18 SMB_CLK_S3 253 254
6 DDRA_MA9 A9 A7 DDRA_MA7 6 DDRA_VDDSPD SCL SDA DDRA_SA0 SMB_DATA_S3 8,18
123 124 RD18 1 @ 2 255 256
DDRA_MA8 VDD_5 VDD_6 DDRA_MA5 +3VS VDDSPD SA0
125 126 CD69 0_0402_5% 257 258
6 DDRA_MA8 DDRA_MA6 A8 A5 DDRA_MA4 DDRA_MA5 6 VPP_1 VTT DDRA_SA1 +0.6VS
127 128 0.1U_0402_10V7K 1 1 259 260
6 DDRA_MA6 A6 A4 DDRA_MA4 6 2 VPP_2 SA1
129 130
VDD_7 VDD_8 @
CD27 CD28 261 262
2.2U_0603_6.3V6K .1U_0402_10V6-K GND_1 GND_2
Layout Note: 2 2
ARGOS_D4AR0-26005-1P40
Place near DIMM ARGOS_D4AR0-26005-1P40 ME@
ME@

RD20 1 @ 2 0_0402_5%
+2.5V
+1.2V

+3VS +3VS +3VS V1.0

1
1

RD22 RD24 RD26 RD1

1K_0402_1%
0_0402_5% 0_0402_5% 0_0402_5%
2

@ @ @ +VREF_CA_DIMMA
2

0.1U_6.3V_K_X5R_0201

DDRA_SA0 DDRA_SA1 DDRA_SA2

1
RD3
1K_0402_1% CD21
1

RD23 RD25 RD27 2

@ 0_0402_5% @ 0_0402_5% @ 0_0402_5%
2

B B
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
SPD Address = 0H Layout Note:
Place near DIMM
+2.5V

+1.2V 1 1 1 1 1 1

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

180P_25V_J_NPO_0201

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
CD1 CD95 CD96 CD125 CD126
CD4
1 1 1 1 1 1 1 1 1 1 RF@ RF@
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201

CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD123 CD124 2 2 2 2 2 2
CD@ CD@
CD@ RF@ RF@
2 2 2 2 2 2 2 2 2 2

+1.2V +0.6VS

1 1

4.7U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD127 CD128
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
100U_6.3V_M_X5R_1206_H1.6

100U_6.3V_M_X5R_1206_H1.6

CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD129 CD122 CD22 CD23 CD24 CD25 CD26
EMC@ EMC@ EMC@ @ @ RF@ RF@
@ 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 DDRVI SO-DIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 17 of 68

5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM B
+1.2V +1.2V
+1.2V
JDDRH1A
+1.2V +1.2V

1K_0402_5%
RD34
JDDRH1B
1 2
DDRB_DQ0 3 VSS_1 VSS_2 4 DDRB_DQ4
6 DDRB_DQ0 DQ5 DQ4 DDRB_DQ4 6
5 6
VSS_3 VSS_4

2
DDRB_DQ5 7 8 DDRB_DQ1 DDRB_MA3 131 132 DDRB_MA2
6 DDRB_DQ5 DQ1 DQ0 DDRB_DQ1 6 6 DDRB_MA3 DDRB_MA1 A3 A2 DDRB_EVENT# DDRB_MA2 6 DDRB_EVENT#
9 10 133 134
DDRB_DQS#0 VSS_5 VSS_6 6 DDRB_MA1 A1 EVENT_n/NF DDRB_EVENT# 6
11 12 DDRB_DM0 6
135 136
6 DDRB_DQS#0 DDRB_DQS0 DQS0_C DM0_n/DBI0_n DDRB_CLK0 VDD_9 VDD_10 DDRB_CLK1
D 13 14 137 138 D
6 DDRB_DQS0 DQS0_t VSS_7 DDRB_DQ6 6 DDRB_CLK0 DDRB_CLK0# CK0_t CK1_t/NF DDRB_CLK1# DDRB_CLK1 6
15 16 139 140
DDRB_DQ7 VSS_8 DQ6 DDRB_DQ6 6 6 DDRB_CLK0# CK0_c CK1_c/NF DDRB_CLK1# 6
17 18 141 142
6 DDRB_DQ7 DQ7 VSS_9 DDRB_DQ3 DDRB_PARITY VDD_11 VDD_12 DDRB_MA0
19 20 143 144
DDRB_DQ2 VSS_10 DQ2 DDRB_DQ3 6 6 DDRB_PARITY Parity A0 DDRB_MA0 6
21 22
6 DDRB_DQ2 DQ3 VSS_11 DDRB_DQ8
23 24
DDRB_DQ13 VSS_12 DQ12 DDRB_DQ8 6 DDRB_BA1 DDRB_MA10
25 26 145 146
6 DDRB_DQ13 DQ13 VSS_13 DDRB_DQ9 6 DDRB_BA1 BA1 A10/AP DDRB_MA10 6
27 28 147 148
DDRB_DQ12 VSS_14 DQ8 DDRB_DQ9 6 DDRB_CS0# VDD_13 VDD_14 DDRB_BA0
29 30 6 DDRB_CS0#
149 150
6 DDRB_DQ12 DQ9 VSS_15 DDRB_DQS#1 DDRB_MA14_WE# CS0_n BA0 DDRB_MA16_RAS# DDRB_BA0 6
31 32 151 152
VSS_16 DQS1_c DDRB_DQS1 DDRB_DQS#1 6 6 DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# 6
6 DDRB_DM1 33 34 153 154
DM1_n/DBl1_n DQS1_t DDRB_DQS1 6 DDRB_ODT0 VDD_15 VDD_16 DDRB_MA15_CAS#
35 36 155 156
DDRB_DQ11 VSS_17 VSS_18 DDRB_DQ10 6 DDRB_ODT0 DDRB_CS1# ODT0 CAS_n/A15 DDRB_MA13 DDRB_MA15_CAS# 6
37 38 6 DDRB_CS1# 157 158
6 DDRB_DQ11 DQ15 DQ14 DDRB_DQ10 6 CS1_n A13 DDRB_MA13 6
39 40 159 160
DDRB_DQ14 41 VSS_19 VSS_20 42 DDRB_DQ15 DDRB_ODT1 161 VDD_17 VDD_18 162
6 DDRB_DQ14 DQ10 DQ11 DDRB_DQ15 6 6 DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMB
43 44 163 164
DDRB_DQ19 45 VSS_21 VSS_22 46 DDRB_DQ22 165 VDD_19 VREFCA 166 DDRB_SA2
6 DDRB_DQ19 DQ21 DQ20 DDRB_DQ22 6 C1/CS3_n/NC RFU/SA2
47 48 167 168
DDRB_DQ20 49 VSS_23 VSS_24 50 DDRB_DQ21 DDRB_DQ32 169 VSS_53 VSS_54 170 DDRB_DQ33
6 DDRB_DQ20 DQ17 DQ16 DDRB_DQ21 6 6 DDRB_DQ32 DQ37 DQ36 DDRB_DQ33 6
51 52 171 172 1 1
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQ37 173 VSS_55 VSS_56 174 DDRB_DQ36 CD30 CD130
6 DDRB_DQS#2 DDRB_DQS2 DQS2_c DM2_n/DBl2_n DDRB_DM2 6 6 DDRB_DQ37 DQ33 DQ32 DDRB_DQ36 6
55 56 175 176
6 DDRB_DQS2 DQS2_t VSS_27 DDRB_DQ17 DDRB_DQS#4 VSS_57 VSS_58
57 58 177 178 1000P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
DDRB_DQ23 VSS_28 DQ22 DDRB_DQ17 6 6 DDRB_DQS#4 DDRB_DQS4 DQS4_c DM4_n/DBl4_n DDRB_DM4 6 2 2
59 60 179 180
6 DDRB_DQ23 DQ23 VSS_29 DDRB_DQ16 6 DDRB_DQS4 DQS4_t VSS_59 DDRB_DQ39
61 62 181 182
DDRB_DQ18 VSS_30 DQ18 DDRB_DQ16 6 DDRB_DQ35 VSS_60 DQ39 DDRB_DQ39 6
63 64 183 184
6 DDRB_DQ18 DQ19 VSS_31 DDRB_DQ24 6 DDRB_DQ35 DQ38 VSS_61 DDRB_DQ34
65 66 185 186
DDRB_DQ25 VSS_32 DQ28 DDRB_DQ24 6 DDRB_DQ38 VSS_62 DQ35 DDRB_DQ34 6
67 68 187 188
6 DDRB_DQ25 DQ29 VSS_33 DDRB_DQ29 6 DDRB_DQ38 DQ34 VSS_63 DDRB_DQ46
69 70 189 190
DDRB_DQ28 VSS_34 DQ24 DDRB_DQ29 6 DDRB_DQ41 VSS_64 DQ45 DDRB_DQ46 6
71 72 191 192
6 DDRB_DQ28 DQ25 VSS_35 DDRB_DQS#3 6 DDRB_DQ41 DQ44 VSS_65 DDRB_DQ40
73 74 193 194
VSS_36 DQS3_c DDRB_DQS3 DDRB_DQS#3 6 DDRB_DQ47 VSS_66 DQ41 DDRB_DQ40 6
75 76 195 196
6 DDRB_DM3 DM3_n/DBl3_n DQS3_t DDRB_DQS3 6 6 DDRB_DQ47 DQ40 VSS_67 DDRB_DQS#5
77 78 197 198
DDRB_DQ31 VSS_37 VSS_38 DDRB_DQ27 VSS_68 DQS5_c DDRB_DQS5 DDRB_DQS#5 6
79 80 199 200
6 DDRB_DQ31 DQ30 DQ31 DDRB_DQ27 6 6 DDRB_DM5 DM5_n/DBl5_n DQS5_t DDRB_DQS5 6
81 82 201 202
DDRB_DQ26 83 VSS_39 VSS_40 84 DDRB_DQ30 DDRB_DQ45 203 VSS_69 VSS_70 204 DDRB_DQ44
6 DDRB_DQ26 DQ26 DQ27 DDRB_DQ30 6 6 DDRB_DQ45 DQ46 DQ47 DDRB_DQ44 6
85 86 205 206
87 VSS_41 VSS_42 88 DDRB_DQ42 207 VSS_71 VSS_72 208 DDRB_DQ43
CB5/NC CB4/NC 6 DDRB_DQ42 DQ42 DQ43 DDRB_DQ43 6
89 90 209 210
91 VSS_43 VSS_44 92 DDRB_DQ53 211 VSS_73 VSS_74 212 DDRB_DQ49
CB1/NC CB0/NC 6 DDRB_DQ53 DQ52 DQ53 DDRB_DQ49 6
93 94 213 214
95 VSS_45 VSS_46 96 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ52
DQS8_c DM8_n/DBI_n/NC 6 DDRB_DQ48 DQ49 DQ48 DDRB_DQ52 6
97 98 217 218
C 99 DQS8_t VSS_47 100 DDRB_DQS#6 219 VSS_77 VSS_78 220 C
VSS_48 CB6/NC 6 DDRB_DQS#6 DDRB_DQS6 DQS6_c DM6_n/DBl6_n DDRB_DM6 6
101 102 221 222
CB2/NC VSS_49 6 DDRB_DQS6 DQS6_t VSS_79 DDRB_DQ55
103 104 223 224
VSS_50 CB7/NC DDRB_DQ50 VSS_80 DQ54 DDRB_DQ55 6
105 106 225 226
CB3/NC VSS_51 DDRB_DRAMRST#_R 6 DDRB_DQ50 DQ55 VSS_81 DDRB_DQ54
107 108 RD36 1 2 33_0402_5% 227 228
DDRB_CKE0 VSS_52 RESET_n DDRB_CKE1 DDRB_DRAMRST# 6 DDRB_DQ51 VSS_82 DQ50 DDRB_DQ54 6
109 110 229 230
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6 6 DDRB_DQ51 DQ51 VSS_83 DDRB_DQ61
111 112 231 232
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT# DDRB_DQ57 VSS_84 DQ60 DDRB_DQ61 6
113 114 233 234
6 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDRB_ALERT# DDRB_ACT# 6 6 DDRB_DQ57 DQ61 VSS_85 DDRB_DQ62
115 116 235 236
6 DDRB_BG0 BG0 ALERT_n DDRB_ALERT# 6 DDRB_DQ56 VSS_86 DQ57 DDRB_DQ62 6
117 118 1 237 238
DDRB_MA12 VDD_3 VDD_4 DDRB_MA11 6 DDRB_DQ56 DQ56 VSS_87 DDRB_DQS#7
119 120 239 240
6 DDRB_MA12 DDRB_MA9 A12 A11 DDRB_MA7 DDRB_MA11 6 VSS_88 DQS7_c DDRB_DQS7 DDRB_DQS#7 6
121 122 CD70 241 242
6 DDRB_MA9 A9 A7 DDRB_MA7 6 6 DDRB_DM7 DM7_n/DBl7_n DQS7_t DDRB_DQS7 6
123 124 0.1U_0402_10V7K 243 244
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 2 DDRB_DQ60 245 VSS_89 VSS_90 246 DDRB_DQ63
6 DDRB_MA8 DDRB_MA6 A8 A5 DDRB_MA4 DDRB_MA5 6 @ 6 DDRB_DQ60 DQ62 DQ63 DDRB_DQ63 6
127 128 247 248
6 DDRB_MA6 A6 A4 DDRB_MA4 6 DDRB_DQ59 VSS_91 VSS_92 DDRB_DQ58
129 130 249 250
VDD_7 VDD_8 6 DDRB_DQ59 DQ58 DQ59 DDRB_DQ58 6
251 252
SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
SMB_DATA_S3 8,17
RD19 1 @8,17 2 SMB_CLK_S3 DDRB_VDDSPD 255 SCL SDA 256 DDRB_SA0
+3VS VDDSPD SA0
0_0402_5% 1 1 257 258
VPP_1 Vtt DDRB_SA1 +0.6VS
ARGOS_D4AS0-26005-1P40 CD53 259 260
2.2U_0603_6.3V6K CD54 VPP_2 SA1
ME@
.1U_0402_10V6-K 261 262
2 2 GND_1 GND_2
+3VS +3VS +3VS
+1.2V
ARGOS_D4AS0-26005-1P40
ME@
1

RD28 RD33
RD30
1

0_0402_5% @ 0_0402_5% RD21 1 @ 2

0_0402_5% RD11 +2.5V
@ @ 1K_0402_1% 0_0402_5%
2

+VREF_CA_DIMMB
DDRB_SA0 DDRB_SA1 DDRB_SA2
2

0.1U_6.3V_K_X5R_0201

1
1

RD31 CD47
RD29 RD32 RD13
@ @ 0_0402_5% @ 1K_0402_1%
0_0402_5% 0_0402_5%
2
2

B B

SPD Address = 2H CAD Note:

Trace width= 20 mil, Spcing=20 mils
+2.5V

+1.2V 1 1 1 1 1 1

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

180P_25V_J_NPO_0201

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
CD131 CD132 CD133 CD135 CD136
CD134
1 1 1 1 1 1 1 1 1 1 RF@ RF@
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201

CD137 CD138 CD139 CD140 CD141 CD142 CD143 CD144 CD145 CD146 2 2 2 2 2 2
CD@ CD@
CD@ RF@ RF@
2 2 2 2 2 2 2 2 2 2

+1.2V +0.6VS

1 1

4.7U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD147 CD148
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
100U_6.3V_M_X5R_1206_H1.6

100U_6.3V_M_X5R_1206_H1.6

CD149 CD150 CD151 CD152 CD153 CD154 CD155 CD156 CD157 CD158 CD159 CD160 CD161 CD162
EMC@ EMC@ EMC@ @ @ RF@ RF@
@ 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 DDRVI SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 18 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 19 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 20 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 21 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 22 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 23 of 68

5 4 3 2 1
 5 4 3 2 1

STRAP2 STRAP1 STRAP0 RAMCFG[4:0] H=High: Tied to 1.8V

N18P-G61 G62 GPIO M=Middle: Tied to 0.9V
L L L 00000
L=Low: Tied to 0V
GPIO I/O ACTIVE Function Description I/O Termination L H L 00010

GPIO0 OUT - PWM Output to control NVVDD L H H 00011

GPIO1 OUT - FB Enable for GC6 2.1 H H L 00110

GPIO2 IN - GPU EVENT H H H 00111

D D

GPIO3 OUT - GPU MUX controler

ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE
GPIO4 OUT - GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN
L L L 1111 DEFAULT SOR0/1/2/3 ENABLE
GPIO5 IN N/A Active low Frame Lock
L L H 1110
GPIO6 OUT - Phase Shedding, NVVDD_PSI
L H L 1101
GPIO7 OUT N/A Panel Backlight (PWM)enable
L H H 1100
GPIO8 OUT - Memory voltage Control
H L L 1011
GPIO9 I/O - Active Low Thermal Alert
H L H 1010
GPIO10 OUT - Memory VREF Control (100K pull Down)
H H L 1001
GPIO11 OUT - Panel Power (LCD_VDD)enable
H H H 1000
GPIO12 IN - AC power detect or power supply overdraw input (10K pull High)
L L M 0111
GPIO13 IN N/A IGPU Backlight Enable
L M L 0110
GPIO14 IN N/A Hot Plug Detect for IFPA(TYPE-C)
L M H 0101
C GPIO15 IN N/A Hot Plug Detect for IFPB(NA) C

L H M 0100
GPIO16 OUT - DGPU PWM switch select
H L M 0011
GPIO17 IN N/A Hot Plug Detect for IFPD(DGPU eDP HPD)
H M L 0010
GPIO18 IN N/A Hot Plug Detect for IFPE(NA)
H M H 0001
GPIO19 N/A NA
H H M 0000
GPIO20 N/A GC6_MODE

GPIO21 O N/A DGPU Backlight Enable

1:SMB_ALT_ADDR ENABLE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO22 O N/A ADC MUX select 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO23 OUT - GPU PCIe self-reset control 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
GPIO24 N/A NA
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO25 FVDDQ_PSI
0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
GPIO26 N/A FP-FUSE
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
GPIO27 IN N/A Hot Plug Detect for IFPC(HDMI) 0:VGA_DEVICE DISABLE
B B
L M H 1 0 1 0

L M L 1 0 0 1

L L M 1 0 0 0

H H H 0 1 1 1
N18P-G61 G62 Power Sequence
H H L 0 1 1 0

H L H 0 1 0 1

H L L 0 1 0 0

+1.8VS_AON NVVDDS/+1.0VGS L H H 0 0 1 1

+1.8VGS L H L 0 0 1 0
NVVDD
NVVDD L L H 0 0 0 1 DEFAULT

NVVDDS/+1.0VGS L L L 0 0 0 0

FBVDDQ

A A
1. All power rail ramp up time should be larger than 40us 1. NVVDDS/PEX_DVDD must ramp down before NVVDD, all
and is recommended to be less than 2ms. other power rails can ramp down together with NVVDD.

2. T (from 1V8_MAIN_EN to PEX_DVDD/NVVDD_Pgood) 2. All 3.3V devices that connect to the GPU must be
must NOT exceed 4ms. ramp down before 1V8_AON; GPU can NOT have any 3.3V
leakage path after 1V8_AON and 1.8V_MAIN power down.
3. All 3.3V devices that connect to the GPU must be
powered after 1V8_AON; GPU can NOT have any 3.3V 3. The previous power rail must ramp down to 10% before
leakage path before 1V8_AON present. the next power rail can start ramping down.
Security Classification LC Future Center Secret Data Title
4. The previous power rail must ramp up to 90% before
the next power rail can start ramping up.
Issued Date 2019/07/02 Deciphered Date 2019/07/02 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 24 of 68

5 4 3 2 1
 5 4 3 2 1

PEX_DVDD Decouling
UV1A 3A
+1.0VGS
1/17 FBA
2000mA MLCC N18 N17 location
Under GPU(below 150mils)
PEX_DVDD_1
AG21 Near GPU Mid way
1.0uF 12/6 4

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AG22 1 1
PEX_DVDD_2

33P_0402_50V8J

33P_0402_50V8J
AG24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Under
PEX_DVDD_3 4.7uF 3 0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AH25
TV12 1 PEX_WAKE# AJ11 PEX_DVDD_4 AG19

@
PEX_WAKE* PEX_CVDD_1 2 2

RF_NS@

RF_NS@
AH21
4.7uF

OPT@

OPT@

OPT@

OPT18@

OPT18@
OPT@
PLT_RST_VGA# AJ12 PEX_CVDD_2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2

OPT@

OPT@

OPT@

OPT@
OPT18@

OPT18@

OPT18@

OPT18@

CD85

CD86
28 PLT_RST_VGA# CLK_REQ_GPU# PEX_RST*

CV2

CV3

CV4

CV5
AK12

CV536

CV537

CV548

CV549

CV550

CV553

CV551

CV552

CV555

CV554
CV1448

CV1449

CV1450

CV1451

CV1452

CV1453
CLK_PCIE_GPU
PEX_CLKREQ* 10uF 3 0 Near
AL13
9 CLK_PCIE_GPU
9 CLK_PCIE_GPU#
CLK_PCIE_GPU# AK13 PEX_REFCLK
PEX_REFCLK* 22uF 2 0
D 5 PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
CV12 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
AK14
PEX_TX0 10uF 0 1 D
CV13 1 2 0.22U_0201_6.3V6-K OPT@ AJ14
5 PCIE_CRX_GTX_N0 PEX_TX0* Midway
PCIE_CTX_C_GRX_P0 AN12 22uF 0 1
5 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PEX_RX0
AM12
5 PCIE_CTX_C_GRX_N0 PEX_RX0*
PCIE_CRX_GTX_P1 CV17 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P1 AH14
5 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 CV19 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N1 AG14 PEX_TX1 PEX_HVDD Decouling
5 PCIE_CRX_GTX_N1

5 PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
AN14
PEX_TX1*

PEX_RX1
PEX_HVDD_1
PEX_HVDD_2
AG13
AG15
Near GPU +1.8VS_VGA
1A
AM14 AG16
5 PCIE_CTX_C_GRX_N1 PEX_RX1* PEX_HVDD_3 AG18 Under GPU(below 150mils) MLCC N18 N17 location
PCIE_CRX_GTX_P2 CV22 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P2 AK15 PEX_HVDD_4 AG25 Near GPU Mid way
1.0uF 13/6 4
5 PCIE_CRX_GTX_P2 OPT@
PCIE_CRX_GTX_N2 CV23 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N2 AJ15 PEX_TX2 PEX_HVDD_5 AH15
5 PCIE_CRX_GTX_N2 PEX_TX2* PEX_HVDD_6

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AH18
PCIE_CTX_C_GRX_P2 AP14 PEX_HVDD_7 AH26 Under
5 PCIE_CTX_C_GRX_P2 PEX_RX2 PEX_HVDD_8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4.7uF 3 0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PCIE_CTX_C_GRX_N2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AP15 AH27
5 PCIE_CTX_C_GRX_N2 PEX_RX2* PEX_HVDD_9 AJ27
PCIE_CRX_GTX_P3 PCIE_CRX_C_GTX_P3 AL16 PEX_HVDD_10 AK27 4.7uF

@
CV24 1 2 0.22U_0201_6.3V6-K OPT@
0 2

@
OPT@

OPT@

OPT18@

OPT18@

OPT18@

OPT@

OPT@
OPT18@
5 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_C_GTX_N3 PEX_TX3 PEX_HVDD_11 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV25 1 2 0.22U_0201_6.3V6-K OPT@ AK16 AL27
5 PCIE_CRX_GTX_N3 PEX_TX3* PEX_HVDD_12 AM28
10uF 3 0 Near

CV522

CV523

CV524

CV525

CV526

CV527

CV528

OPT@

OPT@

OPT@
OPT18@

OPT18@
CV532

CV533

CV534

CV302

CV535
CV1445

CV1446

CV1447

CV1444

CV1443

CV1442

CV1441

CV1381

CV1492

CV1493
PCIE_CTX_C_GRX_P3 AN15 PEX_HVDD_13 AN28
5 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PEX_RX3 PEX_HVDD_14
AM15
5 PCIE_CTX_C_GRX_N3 PEX_RX3* OPT@ 22uF 2 0
PCIE_CRX_GTX_P4 CV26 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P4 AK17
5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 CV27 1 2 0.22U_0201_6.3V6-K
OPT@
OPT@ PCIE_CRX_C_GTX_N4 AJ17 PEX_TX4 10uF 0 2
5 PCIE_CRX_GTX_N4 PEX_TX4*
Midway
5 PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
AN17
PEX_RX4
22uF 0 1
AM17
5 PCIE_CTX_C_GRX_N4 PEX_RX4*
PCIE_CRX_GTX_P5 CV28 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P5 AH17
5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_C_GTX_N5 PEX_TX5
CV29 1 2 0.22U_0201_6.3V6-K OPT@ AG17
5 PCIE_CRX_GTX_N5 PEX_TX5*
PCIE_CTX_C_GRX_P5 AP17
5 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PEX_RX5
AP18
5 PCIE_CTX_C_GRX_N5 PEX_RX5*
PCIE_CRX_GTX_P6 CV30 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P6 AK18
5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_C_GTX_N6 PEX_TX6
CV34 1 2 0.22U_0201_6.3V6-K OPT@ AJ18
5 PCIE_CRX_GTX_N6 PEX_TX6*
PCIE_CTX_C_GRX_P6 AN18
5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 AM18 PEX_RX6
MAX:100mA MAX:250mA
5 PCIE_CTX_C_GRX_N6 PEX_RX6*
PCIE_CRX_GTX_P7 CV35 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P7 AL19 +1.8VS_VGA +1.8VS_VGA
5 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_C_GTX_N7 PEX_TX7 CORE_PLLVDD
CV36 1 2 0.22U_0201_6.3V6-K OPT@ AK19 Near GPU CORE_PLLVDD
5 PCIE_CRX_GTX_N7 PEX_TX7*
PCIE_CTX_C_GRX_P7 AN20 AH12 PEX_PLL_HVDD RV7 1 @ 2 0_0402_5% UV1Q
5 PCIE_CTX_C_GRX_P7 PEX_RX7 PEX_PLL_HVDD

1U_6.3V_M_X5R_0201
PCIE_CTX_C_GRX_N7 AM20 11/17 XTAL_PLL
5 PCIE_CTX_C_GRX_N7 PEX_RX7*
1 1 2 Place Under GPU/1 cap per pin +1.8VS_AON
AK20 LV1 CORE_PLLVDD AD8
XSN_PLLVDD

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
AJ20 PEX_TX8 HCB1608KF-300T60_2P H26
PEX_TX8* AE8 GPCPLL_AVDD
C OPT@ 1 1 1 1 C

OPT18@
2 1 1 SP_PLLVDD

1U_6.3V_M_X5R_0201
22U_0805_6.3V6M

4.7U_0603_6.3V6K
AP20 30ohms (ESR=0.01) Bead

2
PEX_RX8 AD7

CV31
AP21
PEX_RX8* P/N;SM01000M300 VID_PLLVDD RV211

OPT18@

OPT18@

OPT18@

OPT18@
AH20 N18 change 2 2 2 2 2 2 10K_0402_5%
PEX_TX9

CV16

CV32

CV33

CV37
AG20 @

OPT@

OPT@
PEX_TX9*

CV11

CV15

1
AN21
AM21 PEX_RX9 XTALSSIN H1 J4 XTALOUT
PEX_RX9* EXT_REFCLK_FL XTAL_OUTBUFF
AK21 PEX_PLL_HVDD/Q Decouling Value
AJ21 PEX_TX10 XTAL_IN H3 H2 XTAL_OUT
XTAL_IN XTAL_OUT
Place near GPU

1
PEX_TX10*
AN23 MLCC N18 N17 location N18P-FCBGA960_BGA960 RV46
AM23 PEX_RX10 RV209 100K_0402_5%
@
PEX_RX10* CV31 1uf 0.1uf Near 1
10M_0402_5%
2 OPT@
AL22

2
AK22 PEX_TX11 OPT@
Change PEG from X16 to X8 2019/08/08 PEX_TX11* RV14
10K_0402_5%
AP23 OPT@
PEX_RX11 YV1
AP24
PEX_RX11*

1
AK23 Core_PLLVDD Decouling Value XTAL_IN 1 4
PEX_TX12 OSC1 GND2
AJ23
PEX_TX12* 2 3 XTAL_OUT
AN24 MLCC N18 N17 location GND1 OSC2
AM24 PEX_RX12
1 1
PEX_RX12* CV16 1uf 0.1uf Under CV262
27MHZ_10PF_7V27000050
OPT@ CV263
AH23
AG23 PEX_TX13 10P_0402_50V8J 10P_0402_50V8J
PEX_TX13* CV32 1uf 0.1uf Under
2 OPT@ 2 OPT@
AN26
AM26 PEX_RX13
PEX_RX13*
AK24
PEX_TX14
CV33 1uf 0.1uf Under
AJ24
PEX_TX14*
Change CV262&CV263 from 12P to 8P
AP26
AP27 PEX_RX14 CV37 1uf 0.1uf Under SIT 0129SF
PEX_RX14*
AL25
AK25 PEX_TX15
PEX_TX15*
AN27
AM27 PEX_RX15
PEX_RX15* AP29 PEX_TERMP 1 2
PEX_TERMP RV34
2.49K_0402_1%
OPT@
N18P-FCBGA960_BGA960
B B
@

1 2 +1.8VS_VGA
OVERT#_NVEN 28
RV1207
0_0402_5%
@

1 2

2
WRST# 49
RV20

+1.8VS_AON
0_0402_5% For SWG mode RV1243
5.6K_0402_1%
RV29
0_0402_5%
@

@
1 2 OPT@
APU_THERMTRIP# 7,49
RV1

1
+1.8VS_AON
1

0_0402_5%
@

1
For UMA mode 1 2
@

RV2 8,28 VGA_PWRGD

@

choose one
CV1 RV8
10K_0402_5%
1U_6.3V_K_X5R_0201 0_0402_5% 1
@

D 2 CV66
3

2
.1U_0402_10V6-K
2

5 QV1B LBSS138LT1G

@
G LBSS138DW1T1G_SOT363-6 Vds=50V 2
@

S Id=200mA
4

10K_0402_5%
D Rdson=Max10ohm
6

1
OVERT# 2 QV1A
Vgs= +-20V
28 OVERT# Vgs(th)=0.5V--1V

OPT@
RV31
G LBSS138DW1T1G_SOT363-6

2
@

S
1

1 3 CLK_REQ_GPU#
9 GPU_CLKREQ#
D
1

1
PLT_RST_VGA# 1 2 2 QV2
CV20 QV5
RV3 G LBSS139WT1G_SC70-3
A LSI1012XT1G_SC-89-3 A
0_0402_5% 1U_6.3V_K_X5R_0201
@

S OPT@
2
3
@

Vgs(th)≤0.9V
@

1
CV21
1U_6.3V_K_X5R_0201
2

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_(1/6):PEG I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 25 of 68
5 4 3 2 1
 5 4 3 2 1

Ref NV DG-08780-001
If an IFP link is unused, in general it should be left unconnected.
This includes Main and Aux links.
IFPxy_RSET and IFPxy_PLLVDD (xy=AB,CD,EF)
can be left unconnected if neither of IFPx /IFPy is in use

UV1K
5/17 IFPAB

DVI DP

SL/DL

TXC/TXC
TXC/TXC
AN6 UV1N
2 @ 1 IFPAB_RSET AJ8 IFPA_L3* AM6 8/17 IFPE
RV68 1K_0402_1% IFPAB_RSET IFPA_L3
AN3 2 @ 1 IFPEF_RSET AD6
TXD0/0 IFPA_L2* IFPE_RSET
D CORE_PLLVDD AP3 RV1140 1K_0402_1% D
TXD0/0 IFPA_L2
HDMI DP
RV69 1 @ 2 1/10W_0_+-5%_0603 +IFPAB_PLLVDD AH8 AM5 CORE_PLLVDD
IFPAB_PLLVDD IFPA_L1* AN5 AB4
TXD1/1 IFPA_L1 IFPE_AUX_SDA*
RV1124 1 @ +IFPEF_PLLVDD
2 1/10W _0_+-5%_0603 AB8 AB3
TXD1/1 IFPE_PLLVDD IFPE_AUX_SCL
1
CV7 AK6
@ IFPA_L0*

1U_6.3V_M_X5R_0201
TXD2/2
AL6 AC5
1U_6.3V_K_X5R_0201 IFPA_L0 TXC IFPE_L3* AC4
2 TXD2/2 1 TXC IFPE_L3

@
TXD0 AC3
AH6 IFPE_L2* AC2
IFPA_AUX_SDA* TXD0 IFPE_L2
AJ6 2
IFPA_AUX_SCL AC1

CV461
TXD1 IFPE_L1*
TXD1
AD1
IFPE_L1
TXC
+1.0VGS AH9 AD3
TXC IFPB_L3* TXD2 IFPE_L0*
AJ9 TXD2 AD2
RV72 1 @ 2 0_0603_5% +IFPAB_IOVDD AG8 IFPB_L3 +1.0VGS IFPE_L0
IFP_IOVDD_5 AP5
TXD0/3 IFPB_L2*
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

AG9 TXD0/3
AP6
IFP_IOVDD_6 IFPB_L2 +IFPF_IOVDD
1U_6.3V_K_X5R_0201

1 1 1 1 1 RV337 1 @ 2 0_0603_5% AC7

IFP_IOVDD_1
4.7U_0603_6.3V6K

AC8
@ AL7 IFP_IOVDD_2
TXD1/4 IFPB_L1* AM7
OPT@

OPT18@

OPT18@

TXD1/4 IFPB_L1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
2 2 2 2 2
N18P-FCBGA960_BGA960

1U_6.3V_K_X5R_0201
CV69

CV70

CV71

AM8
CV1175

IFPB_L0* 1 1 1 1 1 @
OPT@
CV445

AN8

4.7U_0603_6.3V6K
TXD2/5 IFPB_L0
TXD2/5 @

OPT18@

OPT18@
2 2 2 2 2
AL8

CV463

CV462

CV446
CV1176
IFPB_AUX_SDA* AK8

OPT@
CV460
IFPB_AUX_SCL
OPT@
near GPU under GPU
IFPAB
N18P-FCBGA960_BGA960 near GPU under GPU
@

C C

Decouling Value

MLCC N18 N17 location

CV7 1uf 0.1uf Under UV1L
7/17 IFPD

CV222 1uf 0.1uf Under

HDMI DP

CV461 1uf 0.1uf Under

IFPD_AUX_SDA*
AK2
AK3
IFPD_AUX_SCL
CV70 1uf 0.1uf Under
AK5
UV1M IFPD TXC IFPD_L3* AK4
6/17 IFPC CV71 1uf 0.1uf Under TXC IFPD_L3
AL4
IFPCD_RSET AF8 TXD0 IFPD_L2*
2 1 AL3
IFPCD_RSET TXD0 IFPD_L2
RV73 OPT@ 1K_0402_1%
HDMI DP
CV223 1uf 0.1uf Under
AM4
TXD1 IFPD_L1*
TXD1 AM3
IFPD_L1
IFPC_AUX_SDA*
AG2
AG3 HDMI1_DAT 39 CV68 1uf 0.1uf Under
AM2
CORE_PLLVDD IFPC_AUX_SCL HDMI1_CLK 39 TXD2 IFPD_L0* AM1
TXD2 IFPD_L0
AG4 HDMI1_TXC- CV462 1uf 0.1uf Under
+IFPCD_PLLVDD TXC IFPC_L3* HDMI1_TXC+ HDMI1_TXC- 39
LV4 1 @ 2 0_0603_5% AF7
IFPCD_PLLVDD TXC IFPC_L3
AG5
HDMI1_TXC+ 39 HDMI CLK CV484 1uf 0.1uf Under
AH4 HDMI1_TX0-
1 TXD0 IFPC_L2* HDMI1_TX0- 39
AH3 HDMI1_TX0+
OPT@ TXD0 IFPC_L2 HDMI1_TX0+ 39 HDMI D0
CV222 For HDMI
2
1U_6.3V_M_X5R_0201 IFPC TXD1 IFPC_L1*
AJ2 HDMI1_TX1-
HDMI1_TX1+ HDMI1_TX1- 39 N18P-FCBGA960_BGA960
AJ3 HDMI D1
TXD1 IFPC_L1 HDMI1_TX1+ 39 @
AJ1 HDMI1_TX2-
TXD2 IFPC_L0* HDMI1_TX2- 39
+1.0VGS AK1 HDMI1_TX2+
TXD2 IFPC_L0 HDMI1_TX2+ 39 HDMI D2
LV5 1 @ 2 0_0603_5% +IFPC_IOVDD AF6
IFP_IOVDD_3
B B
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

AG6
IFP_IOVDD_4
1U_6.3V_K_X5R_0201

1 1 1 1 1
4.7U_0603_6.3V6K
OPT@

OPT18@

OPT18@

2 2 2 2 2
N18P-FCBGA960_BGA960
CV68
CV459

CV223

ADD HDMI Port

OPT@
CV227

CV1174

@
@

Change HDMI PORT to IFPC follow Y550 wei 7/30

near GPU under GPU

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_(3/6):VRAM I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 26 of 68
5 4 3 2 1
 5 4 3 2 1

UV1C
3/17 FBB
UV1B
2/17 FBA
33,34 FBB_D[0..63]
+FB_PLLAVDD
FBB_D0 G9
31,32 FBA_D[0..63] FBB_D1 E9 FBB_D0 FBB_CMD[0..33] 33,34
D FBA_D0 L28 K27 FBB_D2 G8 FBB_D1 D13 FBB_CMD0 D

1U_6.3V_M_X5R_0201
FBA_D1 M29 FBA_D0 FB_REFPLL_AVDD FBB_D3 F9 FBB_D2 FBB_CMD0 E14 FBB_CMD1
FBA_D2 L29 FBA_D1 FBB_D4 F11 FBB_D3 FBB_CMD1 F14 FBB_CMD2
FBA_D2 1 FBB_D4 FBB_CMD2
FBA_D3 M28 FBB_D5 G11 A12 FBB_CMD3
FBA_D4 N31 FBA_D3 FBB_D6 F12 FBB_D5 FBB_CMD3 B12 FBB_CMD4
FBA_D5 FBA_D4 FBB_D7 FBB_D6 FBB_CMD4 FBB_CMD5

OPT18@
P29 G12 C14
FBA_D6 R29 FBA_D5 2 FBB_D8 G6 FBB_D7 FBB_CMD5 B14 FBB_CMD6
FBA_D6 FBB_D8 FBB_CMD6

CV64
FBA_D7 P28 Under GPU FBB_D9 F5 G15 FBB_CMD7
FBA_D8 J28 FBA_D7 FBB_D10 E6 FBB_D9 FBB_CMD7 F15 FBB_CMD8
FBA_D9 H29 FBA_D8 FBA_CMD[0..33] 31,32 FBB_D11 F6 FBB_D10 FBB_CMD8 E15 FBB_CMD9
FBA_D10 J29 FBA_D9 U30 FBA_CMD0 FBB_D12 F4 FBB_D11 FBB_CMD9 D15 FBB_CMD10
FBA_D11 H28 FBA_D10 FBA_CMD0 T31 FBA_CMD1 FBB_D13 G4 FBB_D12 FBB_CMD10 A14 FBB_CMD11
FBA_D12 G29 FBA_D11 FBA_CMD1 U29 FBA_CMD2 FBB_D14 E2 FBB_D13 FBB_CMD11 D14 FBB_CMD12
FBA_D13 E31 FBA_D12 FBA_CMD2 R34 FBA_CMD3 FBB_D15 F3 FBB_D14 FBB_CMD12 A15 FBB_CMD13
FBA_D14 E32 FBA_D13 FBA_CMD3 R33 FBA_CMD4 FBB_D16 C2 FBB_D15 FBB_CMD13 B15 FBB_CMD14
FBA_D15 F30 FBA_D14 FBA_CMD4 U32 FBA_CMD5 FBB_D17 D4 FBB_D16 FBB_CMD14 C17 FBB_CMD15
FBA_D16 C34 FBA_D15 FBA_CMD5 U33 FBA_CMD6 FBB_D18 D3 FBB_D17 FBB_CMD15 D18 FBB_CMD16
FBA_D17 D32 FBA_D16 FBA_CMD6 U28 FBA_CMD7 FBB_D19 C1 FBB_D18 FBB_CMD16 E18 FBB_CMD17
FBA_D18 B33 FBA_D17 FBA_CMD7 V28 FBA_CMD8 GDDR6 CMD Mapping FBB_D20 B3 FBB_D19 FBB_CMD17 F18 FBB_CMD18
x16 Mode
FBA_D19 C33 FBA_D18 FBA_CMD8 V29 FBA_CMD9 FBB_D21 C4 FBB_D20 FBB_CMD18 A20 FBB_CMD19
Lower 0..31 Upper 32..63
FBA_D20 F33 FBA_D19 FBA_CMD9 V30 FBA_CMD10 FBB_D22 B5 FBB_D21 FBB_CMD19 B20 FBB_CMD20
DRAM1 DRAM2
FBA_D21 F32 FBA_D20 FBA_CMD10 U34 FBA_CMD11 FBB_D23 C5 FBB_D22 FBB_CMD20 C18 FBB_CMD21
FBA_D22 H33 FBA_D21 FBA_CMD11 U31 FBA_CMD12 CHA-Byte 0,1 CHA-Byte 4,5 FBB_D24 A11 FBB_D23 FBB_CMD21 B18 FBB_CMD22
FBA_D23 H32 FBA_D22 FBA_CMD12 V34 FBA_CMD13 FBB_D25 C11 FBB_D24 FBB_CMD22 G18 FBB_CMD23
CA0_A CMD13 CMD29
FBA_D24 P34 FBA_D23 FBA_CMD13 V33 FBA_CMD14 FBB_D26 D11 FBB_D25 FBB_CMD23 G17 FBB_CMD24
CA1_A CMD15 CMD31
FBA_D25 P32 FBA_D24 FBA_CMD14 Y32 FBA_CMD15 FBB_D27 B11 FBB_D26 FBB_CMD24 F17 FBB_CMD25
CA2_A CMD0 CMD16
FBA_D26 P31 FBA_D25 FBA_CMD15 AA31 FBA_CMD16 FBB_D28 D8 FBB_D27 FBB_CMD25 D16 FBB_CMD26
CA3_A CMD9 CMD25
FBA_D27 P33 FBA_D26 FBA_CMD16 AA29 FBA_CMD17 FBB_D29 A8 FBB_D28 FBB_CMD26 A18 FBB_CMD27
CA4_A CMD11 CMD22
FBA_D28 L31 FBA_D27 FBA_CMD17 AA28 FBA_CMD18 FBB_D30 C8 FBB_D29 FBB_CMD27 D17 FBB_CMD28
CA5_A CMD12 CMD21
FBA_D29 L34 FBA_D28 FBA_CMD18 AC34 FBA_CMD19 FBB_D31 B8 FBB_D30 FBB_CMD28 A17 FBB_CMD29
CA6_A CMD3 CMD24
FBA_D30 L32 FBA_D29 FBA_CMD19 AC33 FBA_CMD20 FBB_D32 F24 FBB_D31 FBB_CMD29 B17 FBB_CMD30
CA7_A CMD4 CMD23
FBA_D31 L33 FBA_D30 FBA_CMD20 AA32 FBA_CMD21 FBB_D33 G23 FBB_D32 FBB_CMD30 E17 FBB_CMD31
CA8_A CMD6 CMD26
FBA_D32 AG28 FBA_D31 FBA_CMD21 AA33 FBA_CMD22 FBB_D34 E24 FBB_D33 FBB_CMD31 G14 FBB_CMD32
CA9_A CMD5 CMD17
FBA_D33 AF29 FBA_D32 FBA_CMD22 Y28 FBA_CMD23 FBB_D35 G24 FBB_D34 FBB_CMD32 G20 FBB_CMD33
CABI_A CMD8 CMD30
FBA_D34 AG29 FBA_D33 FBA_CMD23 Y29 FBA_CMD24 FBB_D36 D21 FBB_D35 FBB_CMD33 C12 FBB_DEBUG0 1 @ 2
FBA_D35 FBA_D34 FBA_CMD24 FBA_CMD25
CKE_A CMD7 CMD33
FBB_D37 FBB_D36 FBB_CMD34 FBVDDQ
AF28 W31 E21 C20 RV121
FBA_D36 AD30 FBA_D35 FBA_CMD25 Y30 FBA_CMD26 CHB-Byte 6,7 FBB_D38 G21 FBB_D37 FBB_CMD35 60.4_0402_1%
CHB-Byte 2,3
FBA_D37 AD29 FBA_D36 FBA_CMD26 AA34 FBA_CMD27 FBB_D39 F21 FBB_D38 FBB_DEBUG1 1 @ 2
CA0_B CMD10 CMD27
FBA_D38 AC29 FBA_D37 FBA_CMD27 Y31 FBA_CMD28 FBB_D40 G27 FBB_D39 RV122 1.55V
CA1_B CMD1 CMD28
C FBA_D39 AD28 FBA_D38 FBA_CMD28 Y34 FBA_CMD29 FBB_D41 D27 FBB_D40 60.4_0402_1% C
CA2_B CMD32 CMD19
FBA_D40 AJ29 FBA_D39 FBA_CMD29 Y33 FBA_CMD30 FBB_D42 G26 FBB_D41 D12
CA3_B CMD14 CMD20
FBA_D41 AK29 FBA_D40 FBA_CMD30 V31 FBA_CMD31 FBB_D43 E27 FBB_D42 FBB_CLK0 E12 FBB_CLK0 33
CA4_B CMD11 CMD22
FBA_D42 AJ30 FBA_D41 FBA_CMD31 R28 FBA_CMD32 FBB_D44 E29 FBB_D43 FBB_CLK0* E20 FBB_CLK0# 33
CA5_B CMD12 CMD21
FBA_D43 AK28 FBA_D42 FBA_CMD32 AC28 FBA_CMD33 FBB_D45 F29 FBB_D44 FBB_CLK1 F20 FBB_CLK1 34
CA6_B CMD3 CMD24
FBA_D44 AM29 FBA_D43 FBA_CMD33 R32 FBA_DEBUG0 1 2 FBB_D46 E30 FBB_D45 FBB_CLK1* FBB_CLK1# 34
FBA_D44 FBA_CMD34
@ FBVDDQ 1.55V CA7_B CMD4 CMD23
FBB_D46
FBA_D45 AM31 AC32 RV119 CA8_B CMD6 CMD26
FBB_D47 D30
FBA_D46 AN29 FBA_D45 FBA_CMD35 FBA_DEBUG1 FBB_D48 A32 FBB_D47
60.4_0402_1% CA9_B CMD5 CMD17
FBA_D47 AM30 FBA_D46 1 @ 2 FBB_D49 C31 FBB_D48
CABI_B CMD8 CMD30
FBA_D48 AN31 FBA_D47 RV120 FBB_D50 C32 FBB_D49 F8 FBB_WCK01
CKE_B CMD7 CMD33
FBA_D49 AN32 FBA_D48 60.4_0402_1% FBB_D51 B32 FBB_D50 FBB_WCK01 E8 FBB_WCK01_N FBB_WCK01 33
FBA_D50 AP30 FBA_D49 FBB_D52 D29 FBB_D51 FBB_WCK01* A5 FBB_WCK23 FBB_WCK01_N 33
RESET* CMD2 CMD18
FBA_D51 AP32 FBA_D50 R30 FBA_CLK0 FBB_D53 A29 FBB_D52 FBB_WCK23 A6 FBB_WCK23_N FBB_WCK23 33
FBA_D52 AM33 FBA_D51 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 31 FBB_D54 C29 FBB_D53 FBB_WCK23* D24 FBB_WCK45 FBB_WCK23_N 33
FBA_D53 AL31 FBA_D52 FBA_CLK0* AB31 FBA_CLK1 FBA_CLK0# 31 FBB_D55 B29 FBB_D54 FBB_WCK45 D25 FBB_WCK45_N FBB_WCK45 34
FBA_D54 AK33 FBA_D53 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 32 FBB_D56 B21 FBB_D55 FBB_WCK45* B27 FBB_WCK67 FBB_WCK45_N 34
FBA_D55 AK32 FBA_D54 FBA_CLK1* FBA_CLK1# 32 FBB_D57 C23 FBB_D56 FBB_WCK67 C27 FBB_WCK67_N FBB_WCK67 34
FBA_D56 AD34 FBA_D55 FBB_D58 A21 FBB_D57 FBB_WCK67* FBB_WCK67_N 34
FBA_D57 AD32 FBA_D56 FBB_D59 C21 FBB_D58
FBA_D58 AC30 FBA_D57 FBB_D60 B24 FBB_D59
FBA_D59 AD33 FBA_D58 FBB_D61 C24 FBB_D60
FBA_D60 AF31 FBA_D59 FBB_D62 B26 FBB_D61 D6 FBB_WCKB01
FBA_D61 AG34 FBA_D60 FBB_D63 C26 FBB_D62 FBB_WCKB01 D7 FBB_WCKB01_N FBB_WCKB01 33
FBA_D62 AG32 FBA_D61 FBB_D63 FBB_WCKB01* C6 FBB_WCKB23 FBB_WCKB01_N 33
FBA_D63 AG33 FBA_D62 FBB_WCKB23 B6 FBB_WCKB23_N FBB_WCKB23 33
FBA_D63 K31 FBA_WCK01 FBB_DBI0# E11 FBB_WCKB23* F26 FBB_WCKB45 FBB_WCKB23_N 33
FBA_WCK01 L30 FBA_WCK01_N FBA_WCK01 31 33 FBB_DBI0# FBB_DBI1# E3 FBB_DQM0 FBB_WCKB45 E26 FBB_WCKB45_N FBB_WCKB45 34
FBA_DBI0# P30 FBA_WCK01* H34 FBA_WCK23 FBA_WCK01_N 31 33 FBB_DBI1# FBB_DBI2# A3 FBB_DQM1 FBB_WCKB45* A26 FBB_WCKB67 FBB_WCKB45_N 34
31 FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 FBA_WCK23 J34 FBA_WCK23_N FBA_WCK23 31 33 FBB_DBI2# FBB_DBI3# C9 FBB_DQM2 FBB_WCKB67 A27 FBB_WCKB67_N FBB_WCKB67 34
31 FBA_DBI1# FBA_DBI2# F34 FBA_DQM1 FBA_WCK23* AG30 FBA_WCK45 FBA_WCK23_N 31 33 FBB_DBI3# FBB_DBI4# F23 FBB_DQM3 FBB_WCKB67* FBB_WCKB67_N 34
31 FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 FBA_WCK45 AG31 FBA_WCK45_N FBA_WCK45 32 34 FBB_DBI4# FBB_DBI5# F27 FBB_DQM4
31 FBA_DBI3# FBA_DBI4# AD31 FBA_DQM3 FBA_WCK45* AJ34 FBA_WCK67 FBA_WCK45_N 32 34 FBB_DBI5# FBB_DBI6# C30 FBB_DQM5
32 FBA_DBI4# FBA_DBI5# AL29 FBA_DQM4 FBA_WCK67 AK34 FBA_WCK67_N FBA_WCK67 32 34 FBB_DBI6# FBB_DBI7# A24 FBB_DQM6
32 FBA_DBI5# FBA_DBI6# AM32 FBA_DQM5 FBA_WCK67* FBA_WCK67_N 32 34 FBB_DBI7# FBB_DQM7
32 FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 +FB_PLLAVDD
32 FBA_DBI7# FBA_DQM7 FBB_EDC0 D10
33 FBB_EDC0 FBB_EDC1 D5 FBB_DQS_WP0
FBA_EDC0 M31 33 FBB_EDC1 FBB_EDC2 C3 FBB_DQS_WP1
31 FBA_EDC0 FBA_EDC1 G31 FBA_DQS_WP0 J30 FBA_WCKB01 33 FBB_EDC2 FBB_EDC3 B9 FBB_DQS_WP2 H17 +FB_PLLAVDD
31 FBA_EDC1 FBA_EDC2 E33 FBA_DQS_WP1 FBA_WCKB01 J31 FBA_WCKB01_N FBA_WCKB01 31 33 FBB_EDC3 FBB_EDC4 E23 FBB_DQS_WP3 FBB_PLL_AVDD

1U_6.3V_M_X5R_0201
B 31 FBA_EDC2 FBA_EDC3 M33 FBA_DQS_WP2 FBA_WCKB01* J32 FBA_WCKB23 FBA_WCKB01_N 31 34 FBB_EDC4 FBB_EDC5 E28 FBB_DQS_WP4 B
31 FBA_EDC3 FBA_EDC4 AE31 FBA_DQS_WP3 FBA_WCKB23 J33 FBA_WCKB23_N FBA_WCKB23 31 34 FBB_EDC5 FBB_EDC6 B30 FBB_DQS_WP5
32 FBA_EDC4 FBA_EDC5 AK30 FBA_DQS_WP4 FBA_WCKB23* AH31 FBA_WCKB45 FBA_WCKB23_N 31 34 FBB_EDC6 FBB_EDC7 A23 FBB_DQS_WP6 1
32 FBA_EDC5 FBA_EDC6 AN33 FBA_DQS_WP5 FBA_WCKB45 AJ31 FBA_WCKB45_N FBA_WCKB45 32 34 FBB_EDC7 FBB_DQS_WP7
32 FBA_EDC6 FBA_EDC7 AF33 FBA_DQS_WP6 FBA_WCKB45* AJ32 FBA_WCKB67 FBA_WCKB45_N 32

OPT18@
32 FBA_EDC7 FBA_DQS_WP7 FBA_WCKB67 AJ33 FBA_WCKB67_N FBA_WCKB67 32
FBA_WCKB67* FBA_WCKB67_N 32 2

CV1161
N18P-FCBGA960_BGA960
@

Under GPU

+FB_PLLAVDD

U27
FBA_PLL_AVDD
1U_6.3V_M_X5R_0201

1 FBVDDQ FBVDDQ
H31
FB_VREF
OPT18@

N18P-FCBGA960_BGA960
2
2

1
1 OPT18@ CKE_A CKE_A
CV1160

OPT@ RC702 @ RV1286 RV1287 RV1288 RV1289

CV1522 1/20W_49.9_1%_0201 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
3.9P_50V_B_NPO_0402 OPT@ OPT@ OPT@ OPT@
2
1

2
FBA_CMD7 FBB_CMD7
Under GPU FBA_CMD33 FBB_CMD33

FBA_CMD2 FBB_CMD2
FBA_CMD18 FBB_CMD18
+FB_PLLAVDD
A A
30ohms (ESR=0.01) Bead

1
P/N;SM01000M300 RESET RV76 RV80 RESET RV87 RV88
N18 change
22U_0603_6.3V6-M

1 1 1
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

+1.8VS_VGA +FB_PLLAVDD 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%

2 OPT@ OPT@ OPT@ OPT@

2
2 2 2
1 2 +FB_PLLAVDD
OPT@

OPT18@

OPT18@
CV475

CV474

CV562

LV7
HCB1608KF-300T60_2P
OPT@ Title
Security Classification LC Future Center Secret Data
Place close to BGA Near GPU Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_(3/6):VRAM I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 27 of 68
5 4 3 2 1
 5 4 3 2 1

+1.8VS_AON

2
UV1P RV197 RV1202 RV199
12/17 MISC2 +1.8VS_AON +1.8VS_AON 100K_0402_5% 10K_0402_1% 100K_0402_5%
@ @ OPT17@ 1:ENABLE 0:DISABLE
SOR0 DISABLE

1
SOR1/2/3 ENABLE
ROM_CS# ROM_SI

2
H6
ROM_CS* RV1105 1 1 GPU ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0]
H5 ROM_SI 10K_0402_5% CV465 CV464 ROM_SO
ROM_SI H7 ROM_SO OPT18@ 10U 6.3V M X5R 0402 .1U_0402_10V6-K
J2 ROM_SO H4 ROM_SCLK OPT18@ ROM_SCLK N17P L L H 1110
STRAP0 @ OPT18@
STRAP0 ROM_SCLK

1
STRAP1 J7 UV3 2 2
STRAP2 J6 STRAP1 ROM_CS# RV1102 2 OPT18@ 1 33_0402_5% ROM_CS#_R 1 8
STRAP3 J5 STRAP2 ROM_SO RV1101 2 @ 1 0_0402_5% ROM_SO_R 2 CS# VCC 7 N18P L L L ENABLE
STRAP3 DO HOLD# ROM_SCLK_R ROM_SCLK

2
STRAP4 J3 3 6 RV1103 2 OPT18@ 1 33_0402_5%
STRAP5 1
RV17 @ 2 MULTI_STRAP J1 STRAP4 4 WP# CLK 5 ROM_SI_R RV1104 2 OPT18@ 1 33_0402_5% ROM_SI RV200 RV1203 RV202
STRAP5 GND DI 100K_0402_5% 10K_0402_1% 100K_0402_5%
1

0_0402_5% W25Q80EWSNIG_SO8 OPT@ OPT@ OPT18@

RV16

1
40.2K_0402_1% E1
@ BUFRST*

1
NV RVL
2

RV203
N18P-FCBGA960_BGA960 10K_0402_5%
@ @ SPI ROM need doublecheck
change to SA00009RB00_0928SF

2
D D

+1.8VS_AON

+1.8VS_AON
I2CB_SCL RV22 1 OPT@ 2 2.2K_0402_5%
+1.8VS_AON
I2CB_SDA RV25 1 OPT@ 2 2.2K_0402_5%
VRAMCFG
1V8_MAIN_EN

2
RV1201 1 @ 2 0_0402_5% RV27 2 OPT@ 1 10K_0402_5%
RV187 RV188 RV189
NVVDD_PSI RV28 1 2
@ 10K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% GPU VRAM FB Memory (GDDR6) RAMCFG[4:0] STRAP2 STRAP1 STRAP0
+1.8VS_AON X76@ X76@ X76@
VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5%
1

1
OPT18@ VGA_AC_DET_R Samsung 8Gb K4Z80325BC-HC14 0(0x0000) L L L
UV1O RV26 1 OPT@ 2 100K_0402_5% 4GB
CV1185 STRAP2
10/17 MISC1
1U_0402_6.3V6K ADC_MUX_SEL
2

2 RV381 1 OPT18@ 2 10K_0402_5% Micron 8Gb MT61K256M32JE-14:A 1(0x0001) L L H

RV214 STRAP1
100K_0402_5%
OPT@ T4 VGA_SMB_CK2 STRAP0
AG10 I2CS_SCL T3 VGA_SMB_DA2
TS_AVDD I2CS_SDA Internal Thermal Sensor
1

I2CC_SCL

2
OVERT# M1 R2
25 OVERT# OVERT I2CC_SCL I2CC_SDA
R3 RV192 RV193 RV194
TV5 @ 1 AP9 I2CC_SDA 100K_0402_5% 100K_0402_5% 100K_0402_5%
TS_VREF R7 I2CB_SCL X76@ X76@ X76@
K4 I2CB_SCL R6 I2CB_SDA
THERMDN I2CB_SDA

1
K3
THERMDP
P6 NVVDD_PWM_VID
GPIO0 M3 FB_GC6_EN NVVDD_PWM_VID 67
MEM_VREF RV32 2 OPT@ 1 100K_0402_5%
TV1 @ 1 AM10 GPIO1 L6 GPU_EVENT#
TV2 @ 1 AP11 JTAG_TCK GPIO2 P5 删掉GPU_MUX_CNTL NB_FGC6 RV758 2 OPT18@ 1 10K_0402_5%
TV3 @ 1 AM11 JTAG_TMS GPIO3 P7 1V8_MAIN_EN
RV37 TV4 @ 1 AP12 JTAG_TDI GPIO4 L7
OPT@ 1 2 10K_0402_5% JTAG_TRST AN11 JTAG_TDO GPIO5 M7 NVVDD_PSI_GPU RV107 1 @ 2 0_0402_5%
NVJTAG_SEL AK11 JTAG_TRST* GPIO6 NVVDD_PSI 67
RV24 1 2 10K_0402_5% N8
OPT@ NVJTAG_SEL GPIO7 L3 VRAM_VDDQ_ADJ
GPIO8 M2 VGA_ALERT# VRAM_VDDQ_ADJ 64
RV12281 OPT18@ 2 0_0402_5% ADC_IN_P_GPU AN9 GPIO9 L1 MEM_VREF
68 ADC_IN_P ADC_IN GPIO10 MEM_VREF 31,33
M5
RV12291 OPT18@ 2 0_0402_5% ADC_IN_N_GPU AM9 GPIO11 N3 VGA_AC_DET_R +1.8VS_AON
68 ADC_IN_N ADC_IN* GPIO12 M4 删掉iGPU_EDP_ENBKL
GPIO13 N4 VGA_DEVICE
GPIO14 P2
GPIO15 R8
GPIO16 STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
M6
GPIO17 IFPE_HPD

2
R1 1
PAD @ TV16 port swap, HDMI change to C port
GPIO18 P3 del E-port HPD GPIO +1.8VS_AON
GPIO19
RV19 RV21 RV74 L L H 0 0 0 1
P4 NB_FGC6 yong 07/12 100K_0402_5% 100K_0402_5% 100K_0402_5%
GPIO20 P1 OPT@ @ @
GPIO21 P8 ADC_MUX_SEL_R RV1239 1 @ 2 0_0402_5% VRAM_VDDQ_ADJ 2 @ 1 10K_0402_5%
GPIO22 T8 GPU_PEX_RST_HOLD#_R ADC_MUX_SEL 68

1
@ 1 RV41 1: SMB_ALT_ADDR ENABLE
GPIO23 L2 PAD STRAP5
TV14
GPIO24 R4 FBVDDQ_PSI @ 1 OPT@ 2 1 10K_0402_5%
GPIO25 PAD 0: SMB_ALT_ADDR DISABLE
R5 GPIO26_FP_FUSE TV15 RV43 STRAP4
GPIO26 U3 IFPC_HPD GPIO26_FP_FUSE 29
GPIO27 IFPC_HPD 39 STRAP3 1: DEVID_SEL REBRAND
N18P-FCBGA960_BGA960
@ VGA_ALERT# 8 0: DEVID_SEL ORIGNAL

2
@
VGA_ALERT# 2 1 RV78 RV75 RV77 1: PCIE_CFG LOW POWER
DV6 RB751V-40_SOD323-2 100K_0402_5% 100K_0402_5% 100K_0402_5%
VGA_AC_DET_R OPT@ 2
@ OPT@ OPT@ 0: PCIE_CFG HIGH POWER
1
VGA_AC_DET 49

1
DV1 RB751V-40_SOD323-2
1: VGA_DEVICE ENABLE
0: VGA_DEVICE DISABLE

+1.8VS_AON
+1.8VS_AON +3VS
C C

+3VS
2
2

RV1208 +3VALW RV12

RV1209 2.2K_0402_5% RV1212 RV1213 10K_0402_5% RV51 1 @ 2
PCH_FB_GC6_EN 8
2.2K_0402_5% OPT@ 2.2K_0402_5% 2.2K_0402_5% OPT@
5

OPT@ OPT@ OPT@ 0_0402_5%

1

RV57
G2
1

10K_0402_5%
I2CC_SCL 4
S2 D2
3
NVDD_SCL 67
OPT@ FB_GC6_EN_R
DG Power on/off sequence discharger circuit
1

QV35B D @
5 DV10 +1.8VS_VGA +3VS
PJT7838_SOT363-6 QV7B OVERT#_NVEN 1 2
OPT@ G LBSS138DW1T1G_SOT363-6 25 OVERT#_NVEN
2 1 S OPT@
RB751V-40_SOD323-2
4

RV1211

1
2

0_0402_5%
RV13 RV334
6

@ D
G1

FB_GC6_EN 2 OPT@ 0_0402_5% 10K_0402_1%

QV7A
I2CC_SDA 1 6 DV9 @
G LBSS138DW1T1G_SOT363-6
S1 D1 NVDD_SDA 67
OPT@ PXS_PWREN RV220 1 @ 2
1

2
3
1

Vgs(th)≤1.0V RV313 8,51 PXS_PWREN 1 OPT@

QV35A 1V8_MAIN_EN_R 0_0402_5% 2 NVVDD_EN 29,30,67
10K_0402_5%
PJT7838_SOT363-6
OPT@
OPT@

1
BAT54AW_SOT323-3
2

2 1 RV335
1 @ 2 0_0402_5% 100K_0402_1%
RV1210 RV55 1 @ 2 0_0402_5%
RV333 @
0_0402_5%
@

2
+1.8VS_AON +1.8VS_AON +3VS

PLT_RST_VGA#

1
2
PXS_PWREN RV331
2

1 2
For Optimus Power OFF OPT@
2

RV89 8.2K_0402_1%
RV1241 RV1138 RV1240
RV1136 DV8 10K_0402_5% OPT@
10K_0402_5% @ 0_0402_5%@ 0_0402_5% RB751V-40_SOD323-2
+1.8VS_AON 10K_0402_5% 1V8_MAIN_EN_R @
@ RV1135 1 @ 2 0_0402_5%

2
@
DV7

1
1

1V8_MAIN_EN
1

For GC6 Power OFF RV1134 1 @ 2 0_0402_5% 2

1 RV98 2 @ 1
1V0_MAIN_EN 30,65
NVVDD_PWRGD 3
For Power ON 67 NVVDD_PWRGD 0_0402_5%

1
+1.8VS_AON
2

+1.8VS_AON +3VS
RV5 RV6 1 OPT@ 2 BAT54AW_SOT323-3
+3VS RV4 RV330
2.2K_0402_5% 2.2K_0402_5%
10K_0402_5% OPT@ 10K_0402_1%
5

OPT@ OPT@ +3VS

OPT@
RV59
1

2
G2
1

@ 0_0402_5%
VGA_SMB_CK2 4 3 RV319
1

S2 D2 EC_SMB_CK2 7,44,49

2
10K_0402_5% +3VALW RV1129
OPT@ RV320
1

10K_0402_5%
QV3B 10K_0402_5% OPT@
2

OPT@
PJT7838_SOT363-6
2

2
OPT@ RV1132
2

1
10K_0402_5%
2 @ 1 OPT@ 1V8_MAIN_EN_R
GPU_EVENT# 3 1 GPU_EVENT#_R 1V8_MAIN_EN_R 29
2

RV1238 RV318 1 @ 2 PCH_GPU_EVENT# 8

0_0402_5%
G1

3
0_0402_5% D
VGA_SMB_DA2 1 6 QV8 5 QV32B
S1 D1 EC_SMB_DA2 7,44,49 LSI1012XT1G_SC-89-3
GC6@ For GC6 20180827 ref Y540 change0927SF G LBSS138DW1T1G_SOT363-6
Vgs(th)≤1.0V Vgs(th)≤0.9V S OPT@

4
QV3A PU AT EC SIDE, +3VS AND 4.7K
PJT7838_SOT363-6

6
OPT@ RV317 1 @ 2 0_0402_5% D
1V8_MAIN_EN 2 QV32A
2 @ 1 G LBSS138DW1T1G_SOT363-6
B RV1235 UV12 OPT@ B
S
FB_GC6_EN_R FBVDDQ_PWR_EN

1
0_0402_5% RV110 1 @ 2 0_0402_5% 1 4
1.0VGS_PG IN B OUT Y FBVDDQ_PWR_EN 30,64
RV325 1 @ 2 0_0402_5% 2 RV1133
IN A 10K_0402_5%
NVVDD_PWRGDRV1123 1 @ 2 0_0402_5% 3 5 RV1218 1 @ 2 0_0402_5% @
GND Vcc +3VS

0.1U_0402_25V6

2
MC74VHC1G32DFT2G_SC70-5 1
follow 330G-ICH NV review result SF0926
1

OPT@
@ CV1189
CV458

.1U_0402_10V6-K
2

2 OPT@

+3VS

1V8_MAIN_EN RV12311 @ 2 0_0402_5% 1V8_MAIN_EN_R

1

RV38
@ 0_0402_5%
2

+3VS

1 +1.8VS_AON

CV58
2

.1U_0402_10V6-K
BAT54AW RV104
2

2 OPT@ VF=0.32V @ IF=1mA 10K_0402_5%

RV50
DV3 OPT@
10K_0402_5%
OPT@ RV49 2 @ 1 0_0402_5% 2
1

64 FBVDDQ_PWROK
5

UV2 1
PLT_RST# VGA_PWRGD 8,25
1

1 RV64 2 @ 1 0_0402_5% 3
8,37,42,45 PLT_RST#
P

B 4 VGA_RST# PLT_RST_VGA# 65 1.0VGS_PG

RV44 1 @ 2
2 Y PLT_RST_VGA# 25
8 PXS_RST# A BAT54AW_SOT323-3
G

0_0402_5%
MC74VHC1G09DFT2G_SC70-5 OPT@
3

OPT@
1

1
CC171 RV324
1000P_0402_50V7K RV217 100K_0402_5%
100K_0402_5% OPT@
2 OPT@
OPT@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_(4/6):GPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 28 of 68

5 4 3 2 1
 5 4 3 2 1

1.8V Total 1A (AON+MAIN)

5A Peak 8A 0.5A +1.8VS_AON
FBVDDQ
Cost down list: UV1H UV1I
1U 4Pcs for N18P reserve 0928sf 14/17 FBVDDQ 17/17 1V8_AON
+1.8VS_AON

Partition A Under GPU(below 150mils) AA27

AA30 FBVDDQ_01 under GPU near GPU

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AB27 FBVDDQ_02 J8

CV99
CV112

CV113

CV100

CV101

CV102

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
AB33 FBVDDQ_03 1V8_AON_1 K8
1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ_04 1V8_AON_2
AC27 1 1 1 1 1 1 1 1 2 1 1 1 1

1U_0603_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AD27 FBVDDQ_05 AG12
AE27 FBVDDQ_06 FP_FUSE_SRC

OPT@

OPT@
@ @ OPT@ @ @ @
CD@
CV114

CV103

OPT@

2 2 2 2 2 2 2 2 2 2 2 2 AF27 FBVDDQ_07

OPT18@

OPT18@
FBVDDQ_08 2 2 2 2 2 2 2 2 1 2 2 @2 @ 2
CV104

CV105

CV106

CV115
AG27 @

OPT@

OPT@

OPT@

OPT@
OPT18@

OPT18@
FBVDDQ_09

CV205

CV206
@ @ B13 @ @

CV203

CV207

CV211

CV204

CV208

CV213
CV1475

CV1476

CV1477

CV1478

CV1479
D D
B16 FBVDDQ_10
B19 FBVDDQ_11
E13 FBVDDQ_12
E16 FBVDDQ_13
Partition B Under GPU(below 150mils) FBVDDQ_14
E19
H10 FBVDDQ_15
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

H11 FBVDDQ_16

CV1486

CV1487

CV1488

CV1489

CV1490

CV1491
H12 FBVDDQ_17
1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ_18
H13 N18P-FCBGA960_BGA960
H14 FBVDDQ_19
OPT@ H15 FBVDDQ_20 @ 1.8VS_AON Decouling Value
CD@

CD@

CD@

@ @ @ OPT@ @ @
CV873

CV862

2 2 2 2 2 2 2 2 2 2 2 2 H16 FBVDDQ_21
FBVDDQ_22
CV863

CV864

CV868

CV865

H18
@ @ H19 FBVDDQ_23 FP_FUSE_GPU MLCC N18 N17 location
H20 FBVDDQ_24
H21 FBVDDQ_25 1 CV205 1uf 0.1uf Under

1
H22 FBVDDQ_26
FBVDDQ FBVDDQ_27 RV1200 CV1104
H23
H24 FBVDDQ_28
FBVDDQ_29
1/16W_2.21K_1%_0402
OPT18@
2.2U_0402_6.3V6M
OPT18@ 2 CV206 1uf 0.1uf Under
Under GPU(below 150mils) H8
H9 FBVDDQ_30

2
FBVDDQ_31
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
2 2 2 2 L27
M27 FBVDDQ_32
FBVDDQ_33
CV1475 @ @ Under
N27
P27 FBVDDQ_34
1 1 1 1 R27 FBVDDQ_35
@
CV1476 @ @ Under
OPT@

OPT@

OPT@
FBVDDQ_36
T27
CALIBRATION PIN N17P N18P
CV94

CV86

CV87

CV88
T30 FBVDDQ_37
T33 FBVDDQ_38
FBVDDQ FBVDDQ_39
V27
FBVDDQ_40 FB_CAL_x_PD_VDDQ 40.2Ohm 40.2Ohm
Near GPU W27
W30 FBVDDQ_41 RV94 40.2ohm 60.4ohm
FBVDDQ_42
Near GPU W33
Y27 FBVDDQ_43 FB_CAL_x_PU_GND 40.2Ohm 40.2Ohm
FBVDDQ_44
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
10U_0603_6.3V6M

10U_0603_6.3V6M

2 2 1 1 1 1 1
FB_CAL_xTERM_GND 60.4Ohm 40.2Ohm only for N18P
33P_0402_50V8J

33P_0402_50V8J

1 1

OPT@ 2 CD@2
OPT@

1 1 2 2 2 +1.8VS_AON
CD@
RF_NS@

RF_NS@

CD@
CV90

CV91

CV97

CV92

CV93
OPT@

2 2
CV95

CV89

OPT@ F1 FBVDDQ_SENSE_GPU RV90 1 OPT@ 2 0_0402_5%

CD89

CD90

FBVDDQ_SENSE FBVDDQ_VCC_SENSE 64
UV11
C F2 FBVDDQ_SENSE_GND_GPU FP_FUSE_GPU C
RV91 1 @ 2 0_0402_5% CV1103 1 2 OPT18@ A2 A1
PROBE_FB_GND 2.2U_0402_6.3V6M VIN Vout
J27 FBCAL_VDDQ 1 2 B1 B2 GPIO26_FP_FUSE
FB_CAL_PD_VDDQ FBVDDQ GND ON GPIO26_FP_FUSE 28
RV92 40.2_0402_1% OPT@
H27 FBCAL_GND 1 2
FB_CAL_PU_GND

1
RV93 40.2_0402_1% OPT@ AP22913CN4-7_X1-WLB0909-4
H25 FBCAL_TERM 1 2 OPT18@ RV1198
FB_CAL_TERM_GND RV94 40.2_0402_1% OPT18@ 10K_0402_5%
OPT18@
Place near balls

2
N18P-FCBGA960_BGA960
@

FBVDDQ

FBVDDQ_VCC_SENSE @
RV310 1 2 2_0402_5%

PLACE MIDWAY BETWEEN FBA AND FBB

UV1J
4/17 NC

AC6 AK9
AD4 NC_1 NC_20 AL10
AD5 NC_2 NC_21 AL11
AE3 NC_3 NC_22 AL9
AE4 NC_4 NC_23 AN2
AF1 NC_5 NC_24 AP8
+1.8VS_VGA AF2 NC_6 NC_25 C15
AF3 NC_7 NC_26 D19
B B
AF4 NC_8 NC_27 D20
AF5 NC_9 NC_28 D23
AG1 NC_10 NC_29 D26
AG26 NC_11 NC_30 L8
AG7 NC_12 NC_31 M8
AH11 NC_13 NC_32 V32
AJ26 NC_14 NC_33 U2
AJ28 NC_15
RSVD_GNDS_SENSE U1
AJ4 NC_16RSVD_VDDS_SENSE
AJ5 NC_17
AK26 NC_18
AG26,AJ28 NC pin, NC_19
only for under GPU 1.8VS_VGA layout trace

2A
AON7408L
Vds=30V
+1.8VS_AON +1.8VS_VGA Ids=15A
V20B+ QV16 Rdson=28mohm@Vgs=4.66V
AON7380_DFN8-5 =20mohm@Vgs=6V N18P-FCBGA960_BGA960
=18mohm@Vgs>10V @
Vgs=+-20V
2

RV42 1
2 Vgsth=1~3V
47K_0402_5% 5 3
OPT@
1

+5VALW
2 1 1 CV74
4

OPT@ CV73 RV85

CV72 10U_0603_6.3V6M
Vg=16.4V@AC 0.01U_0402_25V7K 47_0603_5%
OPT@
1

Vg=7.38V@Battery @ 0.1U_0402_25V6 @ OPT@

RV86 1 2 2
2

47K_0402_5% 1 2
OPT@ RV83
1K_0402_5% 2
2

D
3

OPT@
1

+1.8VGS_PWR_EN# 5 RV47 CV75 D

G 210K_0402_1% 0.1U_0402_25V6 +1.8VGS_PWR_EN# 2
1
LBSS138DW1T1G_SOT363-6

S QV9B OPT@ OPT@ G QV20

4
LBSS138DW1T1G_SOT363-6

OPT@ 2N7002KW _SOT323-3

RV1285
2

D
6

RV58 2 @ 1 0_0402_5% OPT@ 2 1 0_0402_5% S OPT@

3

A 28 1V8_MAIN_EN_R 2 QV9A A
G OPT@
S
0.1U_0402_25V6

1
1

2
PD3 0_0402_5% @ RV84 +1.8V_MAIN discharger circuit
CV38

3 PR4 1 @ 2 100K_0402_5%
RV1284 @
1 1
2 @ 1 0_0402_5%
2

28,30,67 NVVDD_EN 0_0402_5%

2 PR5 1 @ 2

LBAT54SW T1G_SOT323-3
@
Security Classification LC Future Center Secret Data Title
Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_(5/6):PWR
Reserve PD3/PR4/PR5/CV38 for NV sequence requirement THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document
Document Number
Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date:
Date: Saturday, May 09, 2020 Sheet
Sheet 29 of 68
5 4 3 2 1
 5 4 3 2 1

BOTH GP107 AND N18P-G5 NEED

NC AF30,AF32,AK31,AM34,E34,H30,M30,M34, NVVDD
A30,A9,B2,B23,D22,D28,D9,E4 NVVDD
NVVDD NVVDD
UNDER GPU NEAR GPU
UV1D UV1F UV1E
15/17 GND_1/2 16/17 GND_2/2 UV1G 9/17 XVDD
AG11 AL18 13/17 NVVDD NVVDD
A2 GND_001 GND_071 AL2 G25 P18 AA12 P12

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
CONFIGURABLE
GND_002 GND_072 GND_141 GND_190 VDD_01 VDD_51

33P_0402_50V8J

33P_0402_50V8J
1 1 1 1 1 1 1 1

330U_B2_2.5VM_R9M
A30 AL20 G28 P20 AA14 P14 POWER 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A33 GND_003 GND_073 AL21 G3 GND_142 GND_191 P22 AA16 VDD_02 VDD_52 P16 CHANNELS

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
GND_004 GND_074 GND_143 GND_192 VDD_03 VDD_53 +
A9 AL23 G30 P24 AA19 P19 U4
GND_005 GND_075 GND_144 GND_193 VDD_04 VDD_54 XVDD_01

RF_NS@

RF_NS@
AA11 AL24 G32 R12 AA21 P21 U5

OPT18@

OPT18@

OPT18@

OPT18@
CD@
GND_006 GND_076 GND_145 GND_194 VDD_05 VDD_55 XVDD_02 2 2 2 2 2 2 2
AA13 AL26 G33 R14 AA23 P23 U6 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CV137

CV134

CV149

CV1148

CV1149
GND_007 GND_077 GND_146 GND_195 VDD_06 VDD_56 XVDD_03 2

CV139

CV140

CV141

CV142

CV143

CV144

CV145

CV146

CV1114

CV1115

CV1116

CV1118

CV1117

CV1119

CD94

CD93
AA15 AL28 G5 R16 AB11 R11 U7

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@

CD@

CD@

CD@
GND_008 GND_078 GND_147 GND_196 VDD_07 VDD_57 XVDD_04

CV1422
AA17 AL30 G7 R19 AB13 R13 U8
D
AA18 GND_009 GND_079 AL32 H30 GND_148 GND_197 R21 AB15 VDD_08 VDD_58 R15 XVDD_05 V1 D
AA20 GND_010 GND_080 AL33 K2 GND_149 GND_198 R23 AB17 VDD_09 VDD_59 R17 XVDD_06 V2

@
AA22 GND_011 GND_081 AL5 K28 GND_150 GND_199 T11 AB18 VDD_10 VDD_60 R18 XVDD_07 V3
AA24 GND_012 GND_082 AM13 K30 GND_151 GND_200 T13 AB20 VDD_11 VDD_61 R20 XVDD_08 V4
AB12 GND_013 GND_083 AM16 K32 GND_152 GND_201 T15 AB22 VDD_12 VDD_62 R22 XVDD_09
AB14 GND_014 GND_084 AM19 K33 GND_153 GND_202 T17 AB24 VDD_13 VDD_63 R24
AB16 GND_015 GND_085 AM22 K5 GND_154 GND_203 T18 AC12 VDD_14 VDD_64 T12 V5
AB19 GND_016 GND_086 AM25 K7 GND_155 GND_204 T2 AC14 VDD_15 VDD_65 T14 XVDD_10 V6
GND_017 GND_087 GND_156 GND_205 VDD_16 VDD_66 XVDD_11

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AB2 AM34 L12 T20 AC16 T16 V7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AB21 GND_018 GND_088 AN1 L14 GND_157 GND_206 T22 AC19 VDD_17 VDD_67 T19 XVDD_12 V8

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
AB23 GND_019 GND_089 AN10 L16 GND_158 GND_207 T24 AC21 VDD_18 VDD_68 T21 XVDD_13 W2
AB28 GND_020 GND_090 AN13 L19 GND_159 GND_208 T28 AC23 VDD_19 VDD_69 T23 XVDD_14 W3

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
GND_021 GND_091 GND_160 GND_209 VDD_20 VDD_70 XVDD_15

CD@

CD@

CD@

CD@
AB30 AN16 L21 T32 AD11 U11 W4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CV1150

CV1153

CV1151

CV1152

CV1155

CV1154

CV1156

CV1158

CV1157

CV1159
GND_022 GND_092 GND_161 GND_210 VDD_21 VDD_71 XVDD_16

CV1508

CV1509

CV1510

CV1511

CV1512

CV1513

CV1514

CV1515

CV1516

CV1517

CV1518

CV1519
AB32 AN19 L23 T5 AD13 U13 W5

@
AB5 GND_023 GND_093 AN22 M11 GND_162 GND_211 T7 AD15 VDD_22 VDD_72 U15 XVDD_17 W7
AB7 GND_024 GND_094 AN25 M13 GND_163 GND_212 U12 AD17 VDD_23 VDD_73 U17 XVDD_18
AC11 GND_025 GND_095 AN30 M15 GND_164 GND_213 U14 AD18 VDD_24 VDD_74 U18
AC13 GND_026 GND_096 AN34 M17 GND_165 GND_214 U16 AD20 VDD_25 VDD_75 U20 W8
AC15 GND_027 GND_097 AN4 M18 GND_166 GND_215 U19 AD22 VDD_26 VDD_76 U22 XVDD_19 Y1
AC17 GND_028 GND_098 AN7 M20 GND_167 GND_216 U21 AD24 VDD_27 VDD_77 U24 XVDD_20 Y2
AC18 GND_029 GND_099 AP2 M22 GND_168 GND_217 U23 L11 VDD_28 VDD_78 V11 XVDD_21 Y3
AC20 GND_030 GND_100 AP33 Y23 GND_169 GND_218 V12 L13 VDD_29 VDD_79 V13 XVDD_22 Y4
AC22 GND_031 GND_101 B1 M24 GND_239 GND_219 V14 L15 VDD_30 VDD_80 V15 XVDD_23 Y5
AC24 GND_032 GND_102 B10 M30 GND_170 GND_220 V16 L17 VDD_31 VDD_81 V17 XVDD_24 Y6
AD12 GND_033 GND_103 B2 M34 GND_171 GND_221 V19 L18 VDD_32 VDD_82 V18 XVDD_25 Y7
GND_034 GND_104 GND_172 GND_222 VDD_33 VDD_83 XVDD_26

10U_0603_6.3V6M

10U_0603_6.3V6M
AD14 B22 N12 V21 L20 V20 Y8 2 2 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AD16 GND_035 GND_105 B23 N14 GND_173 GND_223 V23 L22 VDD_34 VDD_84 V22 XVDD_27
AD19 GND_036 GND_106 B25 N16 GND_174 GND_224 W11 L24 VDD_35 VDD_85 V24
AD21 GND_037 GND_107 B28 N19 GND_175 GND_225 W13 M12 VDD_36 VDD_86 W12 AA1
AD23 GND_038 GND_108 B31 N2 GND_176 GND_226 W15 M14 VDD_37 VDD_87 W14 XVDD_28 AA2 1 1 2 2 2 2 2 2 2 2

OPT18@
GND_039 GND_109 GND_177 GND_227 VDD_38 VDD_88 XVDD_29

CD@
AE2 B34 N21 W17 M16 W16 AA3

OPT@

OPT@

OPT@
CV433

CV434

CV435

CV436

CV437

CV1120

CV1121

CV1122
CD@

CD@

CD@

CD@

CD@
GND_040 GND_110 GND_178 GND_228 VDD_39 VDD_89 XVDD_30

CV428

CV429
AE28 B4 N23 W18 M19 W19 AA4
AE30 GND_041 GND_111 B7 N28 GND_179 GND_229 W20 M21 VDD_40 VDD_90 W21 XVDD_31 AA5
AE32 GND_042 GND_112 C10 N30 GND_180 GND_230 W22 M23 VDD_41 VDD_91 W23 XVDD_32 AA6
AE33 GND_043 GND_113 C13 N32 GND_181 GND_231 W24 N11 VDD_42 VDD_92 Y11 XVDD_33 AA7
AE5 GND_044 GND_114 C19 N33 GND_182 GND_232 W28 N13 VDD_43 VDD_93 Y13 XVDD_34 AA8
AE7 GND_045 GND_115 C22 N5 GND_183 GND_233 Y12 N15 VDD_44 VDD_94 Y15 XVDD_35
AF30 GND_046 GND_116 C25 N7 GND_184 GND_234 Y14 N17 VDD_45 VDD_95 Y17
C C
AF32 GND_047 GND_117 C28 P11 GND_185 GND_235 Y16 N18 VDD_46 VDD_96 Y18
AH10 GND_048 GND_118 C7 P13 GND_186 GND_236 Y19 N20 VDD_47 VDD_97 Y20
AH13 GND_049 GND_119 D2 P15 GND_187 GND_237 Y21 N22 VDD_48 VDD_98 Y22 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AH16 GND_050 GND_120 D22 P17 GND_188 GND_238 N24 VDD_49 VDD_99 Y24
AH19 GND_051 GND_121 D28 GND_189 VDD_50 VDD_100
AH2 GND_052 GND_122 D31 C16
AH22 GND_053 GND_123 D33 GND_OPT_1 W32 N18P-FCBGA960_BGA960 2 2 2 2 2 2 2 2 2 2 2 2 2
AH24 GND_054 GND_124 D9 GND_OPT_2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

CV1123

CV1124

CV1125

CV1126

CV1127

CV1128

CV1129

CV1130

CV1131

CV1132

CV1133

CV1134

CV1135
CD@

CD@

CD@

CD@

CD@

CD@

CD@
AH28 GND_055 GND_125 E10
AH29 GND_056 GND_126 E22 Optional CMD GNDs (2)
AH30 GND_057 GND_127 E25 NC for 4-Lyr cards
AH32 GND_058 GND_128 E34
AH33 GND_059 GND_129 E4 N18P-FCBGA960_BGA960
AH5 GND_060 GND_130 E5 @
AH7 GND_061 GND_131 E7
AJ7 GND_062 GND_132 F28
AK10 GND_063 GND_133 F7
AK31 GND_064 GND_134 G10 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AK7 GND_065 GND_135 G13
AL12 GND_066 GND_136 G16
AL14 GND_067 GND_137 G19
AL15 GND_068 GND_138 G2 2 2 2 2 2 2 2 2 2 2 2
AL17 GND_069 GND_139 G22

OPT@

OPT@

OPT@

OPT@

OPT@
CV1136

CV1137

CV1138

CV1139

CV1140

CV1141

CV1142

CV1143

CV1144

CV1145

CV1146
CD@

CD@

CD@

CD@

CD@

CD@
GND_070 GND_140 trace width: 16mils
differential voltage sensing.
N18P-FCBGA960_BGA960
differential signal routing.
@ L4 NVVDD_VDD_SENSE NVVDD_VDD_SENSE 67
VDD_SENSE

L5 NVVDD_VSS_SENSE NVVDD_VSS_SENSE 67
GND_SENSE

N18P-FCBGA960_BGA960
Add RV332 for NVVDDS discharge Hai Y520 SVT @

B Change NVVDDS & +1.0VGS discharge circuit B

HLZ SIV 0725

NVVDD
15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%
2 RV332 1

RV45 1

2 RV326 1

2 RV327 1

@ @ @ @
+5VALW
+1.0VGS Change QV6/RV48/QV4/RV62 from REV@ to ns Hai Y520 SVT
2
1

RV1292 FBVDDQ
47K_0402_5%
@
1

+5VALW
15_0805_1%

15_0805_1%

15_0805_1%
2

RV61
RV63 1

2 RV328 1

2 RV329 1

NVVDD_EN# 470_0603_5%
2
OPT@

OPT@

OPT@

G
RV48
2
LBSS139WT1G_SC70-3

QV49 47K_0402_5%
S

D QV29
1

@
2

2 @ AO3402_SOT-23-3
3

28,29,67 NVVDD_EN
2

G D QV6B
@
S 5
2N7002KDWH_SOT363-6
3

G
1

S
D

4
6

D QV6A
+5VALW 2
G 2
28,64 FBVDDQ_PWR_EN G 2N7002KDWH_SOT363-6
@

A A
S

QV12
1

S
1

RV60 AO3402_SOT-23-3
3

47K_0402_5%
OPT@
OPT@
2

1V0_MAIN_EN#
LBSS139WT1G_SC70-3

QV11 Title
D Security Classification LC Future Center Secret Data
1

2
N18P_(6/6):PWR,VSS
OPT@

28,65 1V0_MAIN_EN
G
Issued Date 2019/07/02 Deciphered Date 2019/07/02
S THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
3

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 30 of 68

5 4 3 2 1
 5 4 3 2 1

UV4D
?
? UV4C
COMMON ?
?
FBVDDQ COMMON

27,32 FBA_CMD[0..33]
A11 A1 UV4B FBA_CMD13 H3 K1 +FBA_VREFC
A13 VSS_1 VDD_1 A14 UV4A FBA_CMD15 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 FBA_CMD0 G4 CA1_A
NORMAL
A4 VSS_3 VDD_3 E5 FBA_CMD9 H12 CA2_A
VSS_4 VDD_4 27 FBA_D[0..15] NORMAL 27 FBA_D[16..31] CA3_A
B1 H13 x16 x8 FBA_CMD11 H5
B14 VSS_5 VDD_5 H2 FBA_D3 G2 FBA_D29 N2 FBA_CMD12 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBA_D4 B3 DQ7_A FBA_D28 P3 DQ6_B FBA_CMD3 J12 CA5_A
C12 VSS_7 VDD_7 L2 FBA_D7 F2 DQ2_A FBA_D31 M2 DQ4_B FBA_CMD4 J11 CA6_A
D VSS_8 VDD_8 FBA_D5 DQ6_A BYTE3 FBA_D30 DQ7_B FBA_CMD6 CA7_A D
C3 P10 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBA_D2 B4 DQ4_A FBA_D25 U3 DQ5_B FBA_CMD5 J3 CA8_A
VSS_10 VDD_10 BYTE0 FBA_D0 DQ0_A FBA_D24 DQ2_B FBA_CMD8 CA9_A
D1 V1 B2 V3 J5
D12 VSS_11 VDD_11 V14 FBA_D6 E2 DQ3_A FBA_D26 U4 DQ1_B FBA_CMD7 G10 CABI_n_A
D14 VSS_12 VDD_12 FBA_D1 A3 DQ5_A FBA_D27 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBA_EDC0 C2 FBA_EDC3 T2 TCK
VSS_15 FBVDDQ 27 FBA_EDC0 FBA_DBI0# EDC0_A 27 FBA_EDC3 FBA_DBI3# EDC0_B
E4 D2 R2 F10
F1 VSS_16 27 FBA_DBI0# DBI0_n_A 27 FBA_DBI3# DBI0_n_B TDI N10
F12 VSS_17 FBA_WCK01 D4 FBA_WCKB23 R4 TDO
VSS_18 27 FBA_WCK01 FBA_WCK01_N WCK_t_A 27 FBA_WCKB23 FBA_WCKB23_N NC3
F14 B10 D5 R5 F5
F3 VSS_19 VDDQ_1 B5 27 FBA_WCK01_N WCK_c_A 27 FBA_WCKB23_N NC4 FBA_CMD10 L3 TMS
G1 VSS_20 VDDQ_2 C1 FBA_D19 P13 FBA_CMD1 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBA_D17 U13 DQ13_B FBA_CMD32 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBA_D10 B11 FBA_D20 M13 DQ11_B FBA_CMD14 L12 CA2_B
VSS_23 VDDQ_5 FBA_D11 DQ8_A
NC BYTE2 FBA_D21 DQ15_B FBA_CMD11 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBA_D15 E13 DQ15_A FBA_D16 U12 DQ14_B FBA_CMD12 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBA_D12 F13 DQ13_A FBA_D23 P12 DQ10_B FBA_CMD3 K12 CA5_B
VSS_26 VDDQ_8 BYTE1 FBA_D13 DQ14_A
NC
FBA_D18 DQ12_B FBA_CMD4 CA6_B
L11 F11 E12 NC V12 K11
L4 VSS_27 VDDQ_9 F4 FBA_D8 B12 DQ12_A FBA_D22 U11 DQ9_B FBA_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBA_D9 B13 DQ10_A DQ8_B FBA_CMD5 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBA_D14 A12 DQ11_A FBA_EDC2 T13 FBA_CMD8 K5 CA9_B J14FBA_ZQ_1_A RV1290 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 27 FBA_EDC2 FBA_DBI2# EDC1_B FBA_CMD7 CABI_n_B ZQ_A
M14 J13 R13 M10
M3 VSS_31 VDDQ_13 J2 FBA_EDC1 C13 27 FBA_DBI2# DBI1_n_B CKE_n_B K14FBA_ZQ_1_B RV1122 1 OPT@ 2 121_0402_1%
GND
VSS_32 VDDQ_14 27 FBA_EDC1 FBA_DBI1# EDC1_A FBA_WCK23 ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 27 FBA_DBI1# DBI1_n_A NC 27 FBA_WCK23 FBA_WCK23_N WCK_t_B
N12 K2 R10
N14 VSS_34 VDDQ_16 L1 FBA_WCKB01 D11 27 FBA_WCK23_N WCK_c_B
NC
VSS_35 VDDQ_17 27 FBA_WCKB01 FBA_WCKB01_N D10 NC1
N3 L14 NC
P11 VSS_36 VDDQ_18 N11 27 FBA_WCKB01_N NC2 FBA_CMD2 J1
VSS_37 VDDQ_19 MT61K256M32JE-14-A_FBGA180 RESET_n
P4 N4
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBA_CLK0# K10
VSS_41 VDDQ_23 27 FBA_CLK0# CK_c
R3 T11 FBA_CLK0 J10
VSS_42 VDDQ_24 27 FBA_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10 @
VPP_1
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
A5
VPP_2
4.7U_0603_6.3V6K

V10 1 1 1 1 1 1 1 1
VPP_3 V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV588

CV589

CV590

CV591

CV592

CV1523

CV1524

CV1525
MT61K256M32JE-14-A_FBGA180 2 2 2 2 2 2 2 2
@

FBVDDQ

1
RV97
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 @ 2 +FBA_VREFC
RV1291 +FBA_VREFC 32
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM 16 mil

1
931_0402_1% 1
RV99 CV1521
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2
1

2
CD@
2
@

QV48
@

@
CV587

CV576

CV577

CV578

CV582

CV579

CV580

CV581

CV585

CV583

CV584

CV586
28 MEM_VREF
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 LSI1012XT1G_SC-89-3
B
@

@
@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@

OPT@
CV234

CV235

CV236

CV237

CV238

CV563

@
CV178

CV220

CV221

CV228

CV490

CV491

3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
FBVDDQ FBVDDQ
1K OHM PULL-DOWN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLACE OF THE 1.33K
FOR RV99
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@
CV564

CV565

CV566

CV567

CV571

CV568

CV569

CV570

CV575

CV572

CV573

CV574

CV492

CV493

CV494

CV239

CV240

CV241

CV242

CV243

CV244

CV245

CV246

CV247

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_GDDR6_A_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 31 of 68

5 4 3 2 1
 5 4 3 2 1

UV5D
?
? UV5C
COMMON ?
?
FBVDDQ COMMON
UV5A
27,31 FBA_CMD[0..33]
UV5B
A11 A1 NORMAL FBA_CMD29 H3 K1 +FBA_VREFC
A13 VSS_1 VDD_1 A14 27 FBA_D[32..47] FBA_CMD31 G11 CA0_A VREFC +FBA_VREFC 31
NORMAL
A2 VSS_2 VDD_2 E10 FBA_D40 G2 FBA_CMD16 G4 CA1_A
VSS_3 VDD_3 DQ7_A 27 FBA_D[48..63] CA2_A 1
A4 E5 FBA_D44 B3 x16 x8 FBA_CMD25 H12 CV172
B1 VSS_4 VDD_4 H13 FBA_D41 F2 DQ2_A FBA_D52 N2 FBA_CMD22 H5 CA3_A 820P_0402_25V7
B14 VSS_5 VDD_5 H2 FBA_D46 E3 DQ6_A FBA_D53 P3 DQ6_B FBA_CMD21 H10 CA4_A @
VSS_6 VDD_6 BYTE5 FBA_D42 DQ4_A FBA_D54 DQ4_B FBA_CMD24 CA5_A 2
C10 L13 B4 M2 J12
C12 VSS_7 VDD_7 L2 FBA_D47 B2 DQ0_A FBA_D55 P2 DQ7_B FBA_CMD23 J11 CA6_A
D VSS_8 VDD_8 FBA_D43 DQ3_A BYTE6 FBA_D49 DQ5_B FBA_CMD26 CA7_A D
C3 P10 E2 U3 J4
C5 VSS_9 VDD_9 P5 FBA_D45 A3 DQ5_A FBA_D51 V3 DQ2_B FBA_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBA_D50 U4 DQ1_B FBA_CMD30 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBA_EDC5 C2 FBA_D48 U2 DQ0_B FBA_CMD33 G10 CABI_n_A
VSS_12 VDD_12 27 FBA_EDC5 FBA_DBI5# EDC0_A DQ3_B CKE_n_A
D14 D2
VSS_13 27 FBA_DBI5# DBI0_n_A FBA_EDC6
D3 T2 N5
E11 VSS_14 FBA_WCKB45 D4 27 FBA_EDC6 FBA_DBI6# R2 EDC0_B TCK
VSS_15 FBVDDQ 27 FBA_WCKB45 FBA_WCKB45_N WCK_t_A 27 FBA_DBI6# DBI0_n_B
E4 D5 F10
F1 VSS_16 27 FBA_WCKB45_N WCK_c_A FBA_WCK67 R4 TDI N10
VSS_17 27 FBA_WCK67 FBA_WCK67_N NC3 TDO
F12 R5
VSS_18 27 FBA_WCK67_N NC4
F14 B10 x16 x8 F5
F3 VSS_19 VDDQ_1 B5 FBA_D34 B11 FBA_D58 P13 FBA_CMD27 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBA_D38 G13 DQ8_A FBA_D60 U13 DQ13_B FBA_CMD28 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBA_D36 E13 DQ15_A FBA_D56 M13 DQ11_B FBA_CMD19 M4 CA1_B
VSS_22 VDDQ_4 BYTE4 FBA_D37 DQ13_A
NC
FBA_D57 DQ15_B FBA_CMD20 CA2_B
G14 C14 F13 NC BYTE7 N13 L12
G3 VSS_23 VDDQ_5 C4 FBA_D39 E12 DQ14_A FBA_D61 U12 DQ14_B FBA_CMD22 L5 CA3_B
NC
H11 VSS_24 VDDQ_6 E1 FBA_D32 B12 DQ12_A FBA_D59 P12 DQ10_B FBA_CMD21 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBA_D33 B13 DQ10_A FBA_D62 V12 DQ12_B FBA_CMD24 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D35 A12 DQ11_A FBA_D63 U11 DQ9_B FBA_CMD23 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBA_CMD26 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBA_EDC4 C13 FBA_EDC7 T13 FBA_CMD17 K3 CA8_B
GND
M12 VSS_29 VDDQ_11 H14 27 FBA_EDC4 FBA_DBI4# D13 EDC1_A 27 FBA_EDC7 FBA_DBI7# R13 EDC1_B FBA_CMD30 K5 CA9_B J14FBA_ZQ_2_A RV1177 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 27 FBA_DBI4# DBI1_n_A NC 27 FBA_DBI7# DBI1_n_B FBA_CMD33 CABI_n_B ZQ_A
M14 J13 M10
M3 VSS_31 VDDQ_13 J2 FBA_WCK45 D11 FBA_WCKB67 R11 CKE_n_B K14FBA_ZQ_2_B RV1178 1 OPT@ 2 121_0402_1%
NC
VSS_32 VDDQ_14 27 FBA_WCK45 FBA_WCK45_N NC1 27 FBA_WCKB67 FBA_WCKB67_N R10 WCK_t_B ZQ_B
N1 K13 D10 NC
VSS_33 VDDQ_15 27 FBA_WCK45_N NC2 27 FBA_WCKB67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBA_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
VSS_40 VDDQ_22

follow CRB bit swap

R14 T1 FBA_CLK1# K10
VSS_41 VDDQ_23 27 FBA_CLK1# CK_c
R3 T11 FBA_CLK1 J10
VSS_42 VDDQ_24 27 FBA_CLK1 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10 @
VPP_1
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
A5
VPP_2
4.7U_0603_6.3V6K

V10 1 1 1 1 1 1 1 1
VPP_3 V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV596

CV597

CV598

CV599

CV600

CV1526

CV1527

CV1528
MT61K256M32JE-14-A_FBGA180 2 2 2 2 2 2 2 2
@

FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

@
CD@
CV636

CV623

CV624

CV625

CV628

CV627

CV626

CV629

CV632

CV630

CV631

CV635
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 B
@

@
@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@

OPT@
CV617

CV620

CV616

CV619

CV618

CV621

CV633

CV634

CV611

CV610

CV609

CV608

FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV622

CV601

CV602

CV603

CV607

CV604

CV605

CV606

CV614

CV612

CV613

CV615

CV595

CV638

CV637

CV639

CV642

CV641

CV640

CV643

CV593

CV645

CV644

CV594

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_GDDR6_A_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 32 of 68

5 4 3 2 1
 5 4 3 2 1

UV6D
?
? UV6C
COMMON ?
?
FBVDDQ COMMON

27,34 FBB_CMD[0..33]
A11 A1 UV6B FBB_CMD13 H3 K1 +FBB_VREFC
A13 VSS_1 VDD_1 A14 UV6A FBB_CMD15 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 FBB_CMD0 G4 CA1_A
NORMAL
A4 VSS_3 VDD_3 E5 FBB_CMD9 H12 CA2_A
VSS_4 VDD_4 27 FBB_D[0..15] NORMAL 27 FBB_D[16..31] CA3_A
B1 H13 x16 x8 FBB_CMD11 H5
B14 VSS_5 VDD_5 H2 FBB_D7 G2 FBB_D28 N2 FBB_CMD12 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBB_D1 B3 DQ7_A FBB_D30 P3 DQ6_B FBB_CMD3 J12 CA5_A
D
C12 VSS_7 VDD_7 L2 FBB_D5 F2 DQ2_A FBB_D29 M2 DQ4_B FBB_CMD4 J11 CA6_A D
VSS_8 VDD_8 FBB_D6 DQ6_A BYTE3 FBB_D31 DQ7_B FBB_CMD6 CA7_A
C3 P10 BYTE0 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBB_D2 B4 DQ4_A FBB_D24 U3 DQ5_B FBB_CMD5 J3 CA8_A
D1 VSS_10 VDD_10 V1 FBB_D0 B2 DQ0_A FBB_D25 V3 DQ2_B FBB_CMD8 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_D4 E2 DQ3_A FBB_D26 U4 DQ1_B FBB_CMD7 G10 CABI_n_A
D14 VSS_12 VDD_12 FBB_D3 A3 DQ5_A FBB_D27 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBB_EDC0 C2 FBB_EDC3 T2 TCK
E4 VSS_15 FBVDDQ 27 FBB_EDC0 FBB_DBI0# D2 EDC0_A 27 FBB_EDC3 FBB_DBI3# R2 EDC0_B F10
VSS_16 27 FBB_DBI0# DBI0_n_A 27 FBB_DBI3# DBI0_n_B TDI
F1 N10
F12 VSS_17 FBB_WCK01 D4 FBB_WCKB23 R4 TDO
F14 VSS_18 B10 27 FBB_WCK01 FBB_WCK01_N D5 WCK_t_A 27 FBB_WCKB23 FBB_WCKB23_N R5 NC3 F5
VSS_19 VDDQ_1 27 FBB_WCK01_N WCK_c_A 27 FBB_WCKB23_N NC4 FBB_CMD10 TMS
F3 B5 L3
G1 VSS_20 VDDQ_2 C1 FBB_D20 P13 FBB_CMD1 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBB_D17 U13 DQ13_B FBB_CMD32 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBB_D10 B11 FBB_D22 M13 DQ11_B FBB_CMD14 L12 CA2_B
VSS_23 VDDQ_5 FBB_D15 DQ8_A
NC BYTE2 FBB_D21 DQ15_B FBB_CMD11 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBB_D8 E13 DQ15_A FBB_D19 U12 DQ14_B FBB_CMD12 L10 CA4_B
VSS_25 VDDQ_7 BYTE1 FBB_D13 DQ13_A
NC
FBB_D23 DQ10_B FBB_CMD3 CA5_B
H4 E14 F13 NC P12 K12
L11 VSS_26 VDDQ_8 F11 FBB_D12 E12 DQ14_A FBB_D16 V12 DQ12_B FBB_CMD4 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBB_D9 B12 DQ12_A FBB_D18 U11 DQ9_B FBB_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBB_D14 B13 DQ10_A DQ8_B FBB_CMD5 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBB_D11 A12 DQ11_A FBB_EDC2 T13 FBB_CMD8 K5 CA9_B J14FBB_ZQ_1_A RV1179 1 OPT@ 2 121_0402_1%
NC
M14 VSS_30 VDDQ_12 J13 DQ9_A 27 FBB_EDC2 FBB_DBI2# R13 EDC1_B FBB_CMD7 M10 CABI_n_B ZQ_A
VSS_31 VDDQ_13 FBB_EDC1 27 FBB_DBI2# DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBB_ZQ_1_B RV1180 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 27 FBB_EDC1 FBB_DBI1# EDC1_A FBB_WCK23 ZQ_B
N1 K13 D13 R11
N12 VSS_33 VDDQ_15 K2 27 FBB_DBI1# DBI1_n_A NC 27 FBB_WCK23 FBB_WCK23_N R10 WCK_t_B
VSS_34 VDDQ_16 FBB_WCKB01 27 FBB_WCK23_N WCK_c_B
N14 L1 D11 NC
N3 VSS_35 VDDQ_17 L14 27 FBB_WCKB01 FBB_WCKB01_N D10 NC1
NC
VSS_36 VDDQ_18 27 FBB_WCKB01_N NC2 FBB_CMD2
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBB_CLK0# K10
VSS_41 VDDQ_23 27 FBB_CLK0# CK_c
R3 T11 FBB_CLK0 J10
VSS_42 VDDQ_24 27 FBB_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
C C
T5 VSS_45 VDDQ_27 U5 NC6
VSS_46 VDDQ_28

follow CRB bit swap

U1
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10 @
VPP_1
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
A5
VPP_2
4.7U_0603_6.3V6K

V10 1 1 1 1 1 1 1 1
VPP_3 V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV649

CV650

CV652

CV651

CV653

CV1529

CV1530

CV1531
MT61K256M32JE-14-A_FBGA180 2 2 2 2 2 2 2 2
@

FBVDDQ

1
RV1181
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 2 +FBB_VREFC
RV1182 +FBB_VREFC 34
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM 16 mil

1
931_0402_1% 1
@ RV1183 CV675
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2
1

2
B B
2
@

QV33
@

@
CD@

CD@
CV690

CV678

CV677

CV679

CV683

CV680

CV681

CV682

CV687

CV685

CV684

CV689
28 MEM_VREF
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

LSI1012XT1G_SC-89-3
@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@

OPT@
CV669

CV672

CV670

CV673

CV671

CV674

@
CV688

CV686

CV663

CV664

CV661

CV662

3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
FBVDDQ FBVDDQ
1K OHM PULL-DOWN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLACE OF THE 1.33K
FOR RV1183
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV676

CV654

CV655

CV656

CV660

CV658

CV657

CV659

CV668

CV665

CV666

CV648

CV691

CV692

CV693

CV697

CV694

CV695

CV696

CV646

CV698

CV699

CV647
CV1520

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_GDDR6_B_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 33 of 68

5 4 3 2 1
 5 4 3 2 1

UV7D
?
? UV7C
COMMON ?
?
FBVDDQ COMMON
UV7A
27,33 FBB_CMD[0..33]
UV7B
A11 A1 NORMAL FBB_CMD29 H3 K1 +FBB_VREFC
VSS_1 VDD_1 27 FBB_D[32..47] FBB_CMD31 CA0_A VREFC +FBB_VREFC 33
A13 A14 NORMAL G11
A2 VSS_2 VDD_2 E10 FBB_D43 G2 FBB_CMD16 G4 CA1_A
VSS_3 VDD_3 DQ7_A 27 FBB_D[48..63] CA2_A 1
A4 E5 FBB_D41 B3 x16 x8 FBB_CMD25 H12 CV743
B1 VSS_4 VDD_4 H13 FBB_D46 F2 DQ2_A FBB_D50 N2 FBB_CMD22 H5 CA3_A 820P_0402_25V7
B14 VSS_5 VDD_5 H2 FBB_D45 E3 DQ6_A FBB_D55 P3 DQ6_B FBB_CMD21 H10 CA4_A @
VSS_6 VDD_6 BYTE5 FBB_D42 DQ4_A FBB_D54 DQ4_B FBB_CMD24 CA5_A 2
C10 L13 B4 M2 J12
D
C12 VSS_7 VDD_7 L2 FBB_D47 B2 DQ0_A FBB_D53 P2 DQ7_B FBB_CMD23 J11 CA6_A D
VSS_8 VDD_8 FBB_D44 DQ3_A BYTE6 FBB_D51 DQ5_B FBB_CMD26 CA7_A
C3 P10 E2 U3 J4
C5 VSS_9 VDD_9 P5 FBB_D40 A3 DQ5_A FBB_D49 V3 DQ2_B FBB_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBB_D52 U4 DQ1_B FBB_CMD30 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_EDC5 C2 FBB_D48 U2 DQ0_B FBB_CMD33 G10 CABI_n_A
VSS_12 VDD_12 27 FBB_EDC5 FBB_DBI5# EDC0_A DQ3_B CKE_n_A
D14 D2
D3 VSS_13 27 FBB_DBI5# DBI0_n_A FBB_EDC6 T2 N5
VSS_14 FBB_WCKB45 27 FBB_EDC6 FBB_DBI6# EDC0_B TCK
E11 D4 R2
E4 VSS_15 FBVDDQ 27 FBB_WCKB45 FBB_WCKB45_N D5 WCK_t_A 27 FBB_DBI6# DBI0_n_B F10
VSS_16 27 FBB_WCKB45_N WCK_c_A FBB_WCK67 TDI
F1 R4 N10
VSS_17 27 FBB_WCK67 FBB_WCK67_N NC3 TDO
F12 R5
F14 VSS_18 B10 27 FBB_WCK67_N NC4 F5
x16 x8
F3 VSS_19 VDDQ_1 B5 FBB_D34 B11 FBB_D60 P13 FBB_CMD27 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBB_D38 G13 DQ8_A FBB_D57 U13 DQ13_B FBB_CMD28 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBB_D35 E13 DQ15_A FBB_D61 M13 DQ11_B FBB_CMD19 M4 CA1_B
NC
G14 VSS_22 VDDQ_4 C14 FBB_D33 F13 DQ13_A FBB_D58 N13 DQ15_B FBB_CMD20 L12 CA2_B
VSS_23 VDDQ_5 BYTE4 FBB_D37 DQ14_A
NC BYTE7 FBB_D56 DQ14_B FBB_CMD22 CA3_B
G3 C4 E12 NC U12 L5
H11 VSS_24 VDDQ_6 E1 FBB_D32 B12 DQ12_A FBB_D63 P12 DQ10_B FBB_CMD21 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBB_D39 B13 DQ10_A FBB_D59 V12 DQ12_B FBB_CMD24 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBB_D36 A12 DQ11_A FBB_D62 U11 DQ9_B FBB_CMD23 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBB_CMD26 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBB_EDC4 C13 FBB_EDC7 T13 FBB_CMD17 K3 CA8_B
GND
VSS_29 VDDQ_11 27 FBB_EDC4 FBB_DBI4# EDC1_A 27 FBB_EDC7 FBB_DBI7# EDC1_B FBB_CMD30 CA9_B
M12 H14 D13 R13 K5 J14FBB_ZQ_2_A RV1184 1 OPT@ 2 121_0402_1%
M14 VSS_30 VDDQ_12 J13 27 FBB_DBI4# DBI1_n_A NC 27 FBB_DBI7# DBI1_n_B FBB_CMD33 M10 CABI_n_B ZQ_A
M3 VSS_31 VDDQ_13 J2 FBB_WCK45 D11 FBB_WCKB67 R11 CKE_n_B K14FBB_ZQ_2_B RV1185 1 OPT@ 2 121_0402_1%
NC
VSS_32 VDDQ_14 27 FBB_WCK45 FBB_WCK45_N NC1 27 FBB_WCKB67 FBB_WCKB67_N R10 WCK_t_B ZQ_B
N1 K13 D10 NC
N12 VSS_33 VDDQ_15 K2 27 FBB_WCK45_N NC2 27 FBB_WCKB67_N WCK_c_B
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBB_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
VSS_40 VDDQ_22 FBB_CLK1#

follow CRB bit swap

R14 T1 K10 CK_c
VSS_41 VDDQ_23 27 FBB_CLK1# FBB_CLK1
R3 T11 J10
VSS_42 VDDQ_24 27 FBB_CLK1 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
C C
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10 @
VPP_1
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
A5
VPP_2
4.7U_0603_6.3V6K

V10 1 1 1 1 1 1 1 1
VPP_3 V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV747

CV749

CV748

CV750

CV751

CV1532

CV1533

CV1534
MT61K256M32JE-14-A_FBGA180 2 2 2 2 2 2 2 2
@

FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

B B
@

@
CD@
CV733

CV720

CV721

CV722

CV725

CV723

CV724

CV726

CV730

CV727

CV728

CV732
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

@
@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@

OPT@
CV714

CV717

CV713

CV715

CV716

CV718

CV729

CV731

CV708

CV707

CV706

CV705

FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@
CV719

CV752

CV753

CV700

CV704

CV701

CV702

CV703

CV711

CV709

CV710

CV712

CV746

CV736

CV734

CV735

CV739

CV738

CV737

CV740

CV744

CV742

CV741

CV745

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 N18P_GDDR6_B_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 34 of 68

5 4 3 2 1
 5 4 3 2 1

+1.8V_AUDIO
DVDD DVDD_IO +5VD +5VA
Analog power for DACs, ADCs

+5VD
D Note: DVDD-IO must be equal to or smaller than DVDD

2.2U_0402_6.3V6M
0.1U_6.3V_K_X5R_0201
D

+5VA
2 2

CA2
DVDD_IO +1.8V_AUDIO

CA1
+3VALW +3VS DVDD +1.8VS
HDA_BITCLK_AUDIO 1 1
8 HDA_BITCLK_AUDIO
RA1 1 @ 2 0_0402_5% RA2 1 @ 2 0_0402_5%

20
18

46

41

40
HDA_SYNC_AUDIO RA3 1 @ 2 0_0402_5%

3
8 HDA_SYNC_AUDIO UA1

2.2U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

CPVDD/AVDD2
PVDD2

PVDD1

AVDD1
HDA_SDOUT_AUDIO

DVDD-IO
DVDD
+1.8VS

0.1U_6.3V_K_X5R_0201
8 HDA_SDOUT_AUDIO 1 2 +1.8VALW

10U 6.3V M X5R 0402

RA4 1 2 0_0402_5% 2 1

CA3
@
HDA_SDIN0

CA4

CA5
2 SPKR_MUTE#

CA6
@
8 HDA_SDIN0 RA5 1 2 0_0402_5% PDB
+1.8VALW
2 1 CD@ 14 HDA_BITCLK_AUDIO
1 2 HPOUT_L BCLK
RA6 1 @ 2 0_0402_5% 27
DMIC_CLK HPOUT-L HDA_SYNC_AUDIO
15
38 DMIC_CLK HPOUT_R SYNC
26
DMIC_DATA HPOUT-R 47
38 DMIC_DATA MIC2_VREFOL JD2
28 RA7 2 @ 1 100K_0402_1%
MIC2-VREFO-L PLUG_IN +3VS
48 JSENSE RA8 2 @ 1 0_0402_5%
EC_MUTE# MIC2_VREFOR JD1
49 EC_MUTE# Close to Pin7 29
MIC2-VREFO-R CA7 2 1 0.22U_6.3V_K_X5R_0201
EC_BEEP#
49 EC_BEEP# 1 NEW JACK@
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
PCH_BEEP DMIC_DATA_R DMIC_DATA
8 PCH_BEEP 4 0_0402_5% 2 @ 1 RA9
RING2_CONN 30 GPIO0/DMIC-DATA12
MIC2-L/RING2 5 DMIC_CLK_R 0_0402_5% 2 @ 1 RA10 DMIC_CLK
RING3_CONN 31 GPIO1/DMIC-CLK
MIC2-R/SLEEVE 6
+5VS +5VA PC_BEEP I2C-DATA
34
+5VD PCBEEP 7
+5VS I2C-CLK
RA11 1 @ 2 0_0402_5%
+5VA
LA1 1 2 8

1U_0402_6.3V6K
0.1U_6.3V_K_X5R_0201
BLM15PD600SN1D_2P EMC_NS@ RA12 1 2 10K_0402_5% VDD_STB 33 NC1
2 2 5VSTB 9

CA9

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1 2 2 LINE2-R 35 NC2

CA8

CA10

CA11

CA12

CA13
RA13 1 @ 2 0_0603_SM LINE2-R 10
LINE2-L 36 NC3
1 1@ LINE2-L
2 2 1 1 11
NC4
12
NC5

CA14 1 2 1U_0402_6.3V6K CBP 23 45 SPK_R+

CBP SPK-OUT-R+
CBN 24 44 SPK_R-
CBN SPK-OUT-R-
43 SPK_L-
SPK-OUT-L-
42 SPK_L+
C 2.2U_0402_6.3V6M 2 1 CA15 MIC2-CAP32 SPK-OUT-L+ C
MIC2-CAP 13
2.2U_0402_6.3V6M 2 1 CA16 VREF 38 DC DET/EAPD
DA1
EC_MUTE# 1 @2 SPKR_MUTE# VREF
2.2U_0402_6.3V6M 1 2 CA17 LDO3-CAP19 16 SDATA_IN RA14 2 1 33_0402_5% HDA_SDIN0
LDO3-CAP SDATA-IN

1
LRB751V-40T1G_SOD323-2
RA15 2.2U_0402_6.3V6M 1 2 CA18 LDO2-CAP21 17 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO
RA16 1 @ 2 0_0402_5% @ 10K_0402_5% LDO2-CAP SDATA-OUT
2.2U_0402_6.3V6M 1 2 CA19 LDO1-CAP39
LDO1-CAP 25 CPVEE
CPVEE

Thermal Pad
2
CA20
1U_0402_6.3V6K

AVSS1

AVSS2
1
CA21
RA17 1 @ 2 4.7K_0402_5% EC_BEEP_R 1 2
ALC3287-CG_MQFN48_6X6

37

22

49
@
@ 0.1U_6.3V_K_X5R_0201
DA2
EC_BEEP# 2 RA18 CA22
1PC_BEEP1 1 2PC_BEEP1_R1 2 PC_BEEP
PCH_BEEP 3
4.7K_0402_5% 0.1U_6.3V_K_X5R_0201
1

LBAT54CW T1G_SOT323-3
RA19
10K_0402_5%
RA20 1 @ 2 0_0402_5% @
Speaker
2

JSPK1

SPK_R+ RA23 1 @ 2 0_0603_5% SPK_R+_CONN 1

SPK_R- RA22 1 @ 2 0_0603_5% SPK_R-_CONN 2 1
RA21 1 2 0_0402_5% SPK_L+ RA24 1 @ 2 0_0603_5% SPK_L+_CONN 3 2 5
EMC_NS@ SPK_L- RA25 1 @ 2 0_0603_5% SPK_L-_CONN 4 3 GND1 6
4 GND2
RA26 1 2 0_0402_5%

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
@

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

220P_25V_K_X7R_0201
HDA_SYNC_AUDIO HIGHS_W S33041-S0191-HF

CA27

CA28

CA29

CA30
CA23

CA24

CA25

CA26
2 2 2 2 ME@
HDA_SDOUT_AUDIO DMIC_CLK RA27 1 @ 2 0_0402_5% 1 1 1 1
EMC_NS@
HDA_BITCLK_AUDIO_R 1 2 HDA_BITCLK_AUDIO DMIC_DATA
1 2 0_0402_5% For EMC Near CODEC

EMC@

EMC@

EMC@

EMC@
RA29 1 CD@
1 CD@
1 CD@
1
RA28 1/16W _27_5%_0402 2 2 2 2 CD@
HDA_SDIN0 EMC_NS@
100P 25V J NPO 0201

100P 25V J NPO 0201

EMC@
22P_0201_258J

1 1
CA31

CA32
22P_0201_258J

33P_50V_J_NPO_0201

33P_50V_J_NPO_0201

1
GND GNDA
CA34

1 1 1
CA33

CA35

CA36

2 2
B EMC_NS@ B
2
EMC_NS@
2 EMC_NS@ EMC_NS@
2 EMC_NS@
2

RING3_CONN
RING2_CONN
A_HP_OUTL_R
Audio Jack
JHP1
A_HP_OUTR_R
PLUG_IN
MIC2_VREFOL RA31 2 1 2.2K_0402_5% RING2_CONN 3
HPOUT_L RA32 1 2 56_0402_5% A_HP_OUTL_R 1 G/M
L
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

RA30 0_0402_5% CA37 470P_50V_K_X7R_0201 LINE2-L CA38 1 @ 2 1U_0402_6.3V6K PLUG_IN 5

1

1
47P_25V_J_NPO_0201

1 @ 2A_HP_OUTL_R_C 1 2 A_HP_OUTL_R 5
1 DA7 DA3 DA4 DA5 DA6 LINE2-R CA40 1 @ 2 1U_0402_6.3V6K 6
1

@
CA39

6
EMC@

HPOUT_R RA34 1 2 56_0402_5% A_HP_OUTR_R 2

RA33 1 2 100K_0402_1% R
2
MIC2_VREFOR RA36 2 1 2.2K_0402_5% RING3_CONN 4
NEW JACK@
2

EMC_NS@ CA41 M/G

7

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ RA35 0_0402_5% 470P_50V_K_X7R_0201
2

CA42

CA43

CA44

CA45
1 @ 2A_HP_OUTR_R_C 1 2 A_HP_OUTR_R MS
1 2 1 1
@ ATOB_063-RT16-0101
RA37 @ @ ME@
10K_0402_5%

EMC@

EMC@
For EMI 1 @ 2 2 1 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Codec ALC3287

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size
D Document Number Rev 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 35 of 68
5 4 3 2 Date: 1 Sheet
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Card Reader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 36 of 68
5 4 3 2 1
 5 4 3 2 1

+1.8VALW +1.8V_TPM

RM1
1 2
0.01_0603_1%
+3VALW +1.8V_TPM
TPM@ +1.8V_TPM

10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
D 2 2 2 2 D

CM2

CM1 TPM@

CM3 TPM@

CM4
1 1 1 1@

2
RM13 RM6
@ TPM@ @ RTPM28 stuff for NationZ
0_0603_5% 0_0603_5%

1
2 1 1 1
CM5 CM6 CM7 CM8
@ TPM@ 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
10U_0603_6.3V6M 4.7U_0402_6.3V6MTPM@ TPM@
1 2 2 2
1 2
CM9 CM10
+1.8V_TPM TPM@ @
1U_0402_6.3V6K 10U_0603_6.3V6M
2 1

RM93 0_0402_5%
2

1
RM92 RM20
TPM@ 10K_0402_5% @ TPM@

22
UM1

1
10K_0402_5%

VHIO2

VHIO1

VSB
1

2
RM9 2 @ 1 0_0402_5% TPM_PIRQ#_R 18 2
9 TPM_SPI_IRQ# PIRQ#/GPIO2 NC1 TPM_GP2
3 RM94 2 TPM@ 1 10K_0402_5% +1.8V_TPM
NC2 4 TPM_PIN4 RM95 2 @ 1 0_0402_5%
TPM_MOSI PP/GPIO6 +1.8V_TPM
RM90 1 TPM@ 2 1/16W_10_5%_0402 21 5
9,49 SPI_SI_C TPM_MISOI MOSI/GPIO7 NC3
RM91 1 TPM@ 2 1/16W_10_5%_0402 24 9
9,49 SPI_SO_C MISO NC5 10
NC6 11
NC7 12
RM7 2 TPM@ 1 0_0402_5% 20 NC8 13
9 SPI_CS2# SCS#/GPIO5 GPIO4 14
TPM_CLK NC9 +1.8V_TPM
RM89 1 TPM@ 2 1/16W_10_5%_0402 19 15
9,14,49 SPI_CLK_PCH_C SCLK NC10
C NPCT750LABYX_QFN32_5X5 16 C
TPM_PLT_RST# 17 GND1 25
PLTRST# NC11 26
6 NC12 27 TPM_PIN27 RM14 1 @ 2 10K_0402_5%
GPIO3 NC13 28
TPM_PP 7 NC14 31
NC4 NC15 32
NC16
29 TPM_PIN29
+1.8V_TPM +1.8VS +3VS SDA/GPIo0

1
30
SCL/GPIO1

GND2

GND3
RM11
0_0402_5%
@
1
2

RPM3 RM96 RM22

23

33
TPM@
10K_0404_4P2R_5% @ 10K_0402_5%
TPM@ 10K_0402_5% TPM@
4
3

TPM_PLT_RST#

D10
@
1 2 TPM_SPI_IRQ#
+1.8V_TPM
+1.8V_TPM
RB751V-40_SOD323-2
SCS00008K00

1
RM18
1

@
RM288
10K_0402_5%
10K_0402_5%
TPM@

2
D TPM_PIN29 RM19 2 @ 1 0_0402_5% TPM_PLT_RST#
3
2

5 QM2B
G LBSS138DW1T1G_SOT363-6
S TPM@
4

D
6

B B
TPM_PIRQ#_R 2 QM2A
G LBSS138DW1T1G_SOT363-6
S TPM@
1

DM23 1 2 RB751V-40_SOD323-2 TPM_PLT_RST#

8,28,42,45 PLT_RST#
@ SCS00008K00

+1.8V_TPM DM31 1 2 RB751V-40_SOD323-2

9,14,49 APU_LPC_RST#
TPM@ SCS00008K00 1
CM75
1

0.1U_0201_6.3V6-K
RM15 @
@ 2
10K_0402_5%
2

TPM_PLT_RST#
+5VALW
1

RM17
10K_0402_5%
@
2

D
2 QM1A
G 2N7002KDWH_SOT363-6
@
S
1
3

D
APU_LPC_RST# 5 QM1B
G 2N7002KDWH_SOT363-6
@
A S A
4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 37 of 68

5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+3VS
+LCDVDD +LCDVDD_CON CMOS Camera
UG9
5 1 W=60mils
IN OUT

RF_NS@
1 2
GND @ W=40 mils +3VS_CMOS

0.1u_0201_10V6K

33P_0402_50V8J
4.7U_0402_6.3V6M
CG22 EDP_ENVDD 4 3 +3VS +3VS_CMOS_R
EN OCB 1 1 1 FI1 W=40mils
0.1u_0201_10V6K
2 SY6288C20AAC_SOT23-5 RI146 1 @ 2 0_0603_5% 1 2
2 2 2 1A_32V_ERBRD1R00X
1 1@
U5 EN PIN VIH MIN 1.5V CI42

CG7

CG8

CG6
CI43
0.1u_0201_10V6K
10U_0603_6.3V6M
CD@
2 2

V20B+ FG3 +LEDVDD For RF

1 2
2A 80 mil
2A 80 mil

EMC@
4.7U_0805_25V6-K

0.1U_0201_25V6-K
3A_32V_0497003PKRHF 1 1
D D

CD@
2 2

CG14

CG15
EMI Request

RG81 1 @ 2 0_0402_5% EDP_ENVDD

7 PCH_EDP_ENVDD

JEDP1
1
+LEDVDD 1
2
3 2
3
1

4
RG79 INVT_PWM 5 4
100K_0402_5% DISPOFF# 6 5
eDP_HPD_CON 7 6
+3VS 8 7
8
2

9
+LCDVDD_CON 10 9
11 10
EDP_AUX# 11

2
12
RG69 RG82 EDP_AUX 13 12
100K_0402_1% @ 100K_0402_1% @ 14 13
EDP_TX0+ 15 14
EDP_TX0- 16 15
16

1
17
EDP_TX1+ 18 17
APU_EDP_TX2+ EDP_CPU@ CG26 1 2 .1U_0402_10V6-K EDP_TX2+ EDP_AUX EDP_TX1- 19 18
7 APU_EDP_TX2+ EDP_AUX# 20 19
APU_EDP_TX2- EDP_CPU@ CG27 1 2 .1U_0402_10V6-K EDP_TX2- EDP_TX2+ 21 20
7 APU_EDP_TX2- EDP_TX2- 22 21
APU_EDP_TX3+ EDP_TX3+ 22

2
EDP_CPU@ CG25 1 2 .1U_0402_10V6-K 23
7 APU_EDP_TX3+ EDP_TX3+ 24 23
RG78 RG6
APU_EDP_TX3- EDP_CPU@ CG24 1 2 .1U_0402_10V6-K EDP_TX3- 100K_0402_1%@ 100K_0402_1% @ EDP_TX3- 25 24
7 APU_EDP_TX3- 26 25
27 26
27
1

1
28
APU_EDP_TX0+ EDP_CPU@ CG19 1 2 .1U_0402_10V6-K EDP_TX0+ 29 28
7 APU_EDP_TX0+ APU_EDP_TX0- EDP_TX0- 29
EDP_CPU@ CG16 1 2 .1U_0402_10V6-K 30
7 APU_EDP_TX0- 31 30
APU_EDP_TX1+ EDP_CPU@ CG18 1 2 .1U_0402_10V6-K EDP_TX1+ 32 31
7 APU_EDP_TX1+ APU_EDP_TX1- EDP_TX1- +3VS_DMIC 32
EDP_CPU@ CG17 1 2 .1U_0402_10V6-K For DMIC
+3VS_CMOS
33
7 APU_EDP_TX1- DMIC_DATA 34 33
APU_EDP_AUX EDP_AUX 35 DMIC_DATA DMIC_CLK 34
EDP_CPU@ CG20 1 2 .1U_0402_10V6-K 35 DMIC_CLK 35
7 APU_EDP_AUX APU_EDP_AUX# EDP_AUX# 35
EDP_CPU@ CG21 1 2 .1U_0402_10V6-K 36
7 APU_EDP_AUX# 37 36
RG52 1 @ 2 0_0402_5%USB20_P2_R 38 37
10 USB20_P2 2 0_0402_5%USB20_N2_R 38
RG51 1 @ 39 41
10 USB20_N2 40 39 GND1 42
+3VS_CMOS 40 GND2
0.5A
CVILU_CF69402D0R0-05-NH
ME@
C EDP symbol: C

1.update to 40pin reserved for 144HZ panel 6/20 wei

+3VS For EMI

LI1 EMC_NS@
USB20_P2 4 3 USB20_P2_R
4 3
2

RG71
4.7K_0402_5% USB20_N2 1 2 USB20_N2_R
@ 1 2
EXC24CH900U_4P
1

ENBKL RG53 1 @ 2
0_0402_5%

RG80 1 @ 2 0_0402_5% DISPOFF#

49 BKOFF#

RG70 1 @ 2 0_0402_5% ENBKL

7 PCH_EDP_ENBKL ENBKL 49
1

RG72
100K_0402_5%
2

EMI request
+3VS
DMIC_CLK DISPOFF# INVT_PWM
2

470P_0201_50V7-K

470P_0201_50V7-K
100P_0201_25V8J
RG77
1 EMC_NS@
1 EMC_NS@
1
1K_0402_5%
EMC_NS@
@
1

2 2 2
RG54 1 @ 2 0_0402_5% INVT_PWM
7 PCH_EDP_PWM
CG42

CG43

CG41
B B
1

RG2
100K_0402_5%
2

APU_EDP_HPD RG66 1 @ 2 0_0402_5% eDP_HPD_CON

7 APU_EDP_HPD
1

RG5
100K_0402_5%
2

Touch Screen delete TS function0704SF

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 eDP/CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 38 of 68
5 4 3 2 1
 5 4 3 2 1

+1.8VS_AON

RG31 2 @ 1 0_0402_5% HDMI1_TX0-_R

EMC_NS@
HDMI1_TX0- 2 0.1u_0201_10V6K HDMI1_TX0-_C

1
CG33 1 LG3 1 2

RG60
10K_0402_5%
26 HDMI1_TX0- 1 2
HDMI D0 HDMI1_TX0+ 2 0.1u_0201_10V6K HDMI1_TX0+_C 4 3
26 HDMI1_TX0+ CG32 1
4 3

2
EXC24CH500U_4P
RG38 2 @ 1 0_0402_5% HDMI1_TX0+_R
IFPC_HPD
28 IFPC_HPD

QG4
RG32 2 @ 1 0_0402_5% HDMI1_TX1-_R MMBT3904W H_SOT323-3

1
C
EMC_NS@ 2 RG58 1 2 100K_0402_5% RG59 1 @ 2 0_0402_5% HDMI1_HPD_CON
HDMI1_TX1- CG35 1 2 0.1u_0201_10V6K HDMI1_TX1-_C LG5 1 2 B
26 HDMI1_TX1- 1 2 E

3
HDMI D1 HDMI1_TX1+ 2 0.1u_0201_10V6K HDMI1_TX1+_C
1

1
D CG34 1 4 3 CG29 D
26 HDMI1_TX1+ 4 3 RG57 220P_0402_50V7K RG62
EXC24CH500U_4P 100K_0402_5% 100K_0402_5%
RG37 2 @ 1 0_0402_5% HDMI1_TX1+_R 2

2
RG33 2 @ 1 0_0402_5% HDMI1_TX2-_R

EMC_NS@
HDMI1_TX2- HDMI1_TX2-_C +3VALW_APU
26 HDMI1_TX2- CG37 1 2 0.1u_0201_10V6K LG4 1 2
1 2
HDMI D2
HDMI1_TX2+ CG36 1 2 0.1u_0201_10V6K HDMI1_TX2+_C 4 3
26 HDMI1_TX2+ 4 3
EXC24CH500U_4P
RG36 2 @ 1 0_0402_5% HDMI1_TX2+_R

HPD

1
RG61
HDMI1_CLK-_R

2
RG34 2 @ 1 0_0402_5% 1M_0402_5%

G
EMC_NS@

2
HDMI1_TXC- 2 0.1u_0201_10V6K HDMI1_CLK-_C HDMI_HPD HDMI1_HPD_CON

3
CG39 1 LG2 1 2

1
26 HDMI1_TXC- 1 2 10 HDMI_HPD

D
HDMI1_TXC+ CG38 1 2 0.1u_0201_10V6K HDMI1_CLK+_C 4 3
HDMI CLK 26 HDMI1_TXC+ 4 3 QG6
EXC24CH500U_4P PJA138K_SOT23-3

RG50 2 @ 1 0_0402_5% HDMI1_CLK+_R

HDMI1_TX0+_C RG15 1 2 499_0402_1% HDMI1_TX0+_B RG23 1 @ 2 0_0402_5%

HDMI1_TX0-_C RG16 1 2 499_0402_1% HDMI1_TX0-_B RG24 1 @ 2 0_0402_5%

HDMI1_TX1+_C RG17 1 2 499_0402_1% HDMI1_TX1+_B RG25 1 @ 2 0_0402_5%

HDMI1_TX1-_C RG18 1 2 499_0402_1% HDMI1_TX1-_B RG26 1 @ 2 0_0402_5%

C C
HDMI1_TX2+_C RG19 1 2 499_0402_1% HDMI1_TX2+_B RG27 1 @ 2 0_0402_5%

HDMI1_TX2-_C RG20 1 2 499_0402_1% HDMI1_TX2-_B RG63 1 @ 2 0_0402_5%

HDMI1_CLK+_C RG21 1 2 499_0402_1% HDMI1_CLK+_B RG29 1 @ 2 0_0402_5%

HDMI1_CLK-_C RG22 1 2 499_0402_1% HDMI1_CLK-_B RG30 1 @ 2 0_0402_5%

1
D QG1
2
+3VS
G 2N7002KW _SOT323-3

3
RG4 1 @ 2

100K_0402_5%

+5VS +5VS_HDMI1_F +5VS_HDMI1

QG5
LP2301ALT1G_SOT23-3
FG2
1 3 1 2

S
1.1A_8V_1206L110THYR

G
2
DG3 1
CG31
DG1 DG2 HDMI1_TX2+_R 1 10 HDMI1_TX2+_R
Line-1 NC1 .1U_0402_10V6-K
HDMI1_HPD_CON 1 HDMI1_HPD_CON 51 SUSP

1
10 HDMI1_CLK+_R 1 10 HDMI1_CLK+_R

2
Line-1 NC1 Line-1 NC1 HDMI1_TX2-_R 2 9 HDMI1_TX2-_R 2

1
RG43
HDMI1_CLK_CON HDMI1_CLK_CON Line-2 NC2 @

2
2 9 HDMI1_CLK-_R 2 9 HDMI1_CLK-_R @ 0_0805_5% RG45
Line-2 NC2 Line-2 NC2 HDMI1_TX1+_R 4 7 HDMI1_TX1+_R
Line-3 NC3 @ 0_0805_5% @
HDMI1_DAT_CON 4 7 HDMI1_DAT_CON HDMI1_TX0+_R 4 7 HDMI1_TX0+_R
Line-3 NC3 HDMI1_TX1-_R 5 6 HDMI1_TX1-_R DG4

2
Line-3 NC3

1
+5VS_HDMI1 +5VS_HDMI1 Line-4 NC4 RB751V-40_SOD323-2

2
5 6 HDMI1_TX0-_R 5 6 HDMI1_TX0-_R DG5
Line-4 NC4 3

1
Line-4 NC4 RB751V-40_SOD323-2
GND1
3 3
GND1 GND1 8

1
GND2
8 8 For EMC NV suggestion
GND2 GND2 RG64

1
AZ1143-04F-R7G_DFN2510P10E10 2.2K_0402_5%
RG65
AZ1143-04F-R7G_DFN2510P10E10 AZ1143-04F-R7G_DFN2510P10E10 For EMC EMC_NS@ 2.2K_0402_5%
EMC_NS@

2
EMC_NS@

2
B B
JHDMI1
HDMI1_TX2+_R RG11 1 2 1/16W _6.8_5%_0402 HDMI1_TX2+_CON 1 2
HDMI1_TX2-_R RG12 1 2 1/16W _6.8_5%_0402 HDMI1_TX2-_CON 3 TMDS_Data2+ TMDS_Data2_Shield 4 HDMI1_TX1+_CON RG9 1 2 1/16W _6.8_5%_0402 HDMI1_TX1+_R
5 TMDS_Data2- TMDS_Data1+ 6 HDMI1_TX1-_CON RG10 1 2 1/16W _6.8_5%_0402 HDMI1_TX1-_R
HDMI1_TX0+_R RG7 1 2 1/16W _6.8_5%_0402 HDMI1_TX0+_CON 7 TMDS_Data1 shield TMDS_Data1- 8
HDMI1_TX0-_R RG8 1 2 1/16W _6.8_5%_0402 HDMI1_TX0-_CON 9 TMDS_Data0+ TMDS_Data0 shield 10 HDMI1_CLK+_CON RG13 1 2 1/16W _6.8_5%_0402 HDMI1_CLK+_R
11 TMDS_Data0- TMDS_CLOCK+ 12 HDMI1_CLK-_CON RG14 1 2 1/16W _6.8_5%_0402 HDMI1_CLK-_R
13 TMDS_CLOCK shieldTMDS_CLOCK- 14
HDMI1_CLK_CON 15 CEC RESERVED 16 HDMI1_DAT_CON
17 SCL SDA 18
HDMI1_HPD_CON 19 DDC/CEC GND +5V
20 HPD
21 GND1
22 GND2
+1.8VS_VGA +1.8VS_AON 23 GND3
GND4
ALLTO_C128W 7-K1939-L
ME@
2

RG41 RG40
@ 0_0402_5% @ 0_0402_5%
1

AUX
1

NV suggestion
RG56 RG55
10K_0402_5% 10K_0402_5%
2
G1

HDMI1_DAT_CON 6 1
D1 S1 HDMI1_DAT 26

PJT7838_SOT363-6
QG3A
5
G2

HDMI1_CLK_CON 3 4
D2 S2 HDMI1_CLK 26

Vgs(th)≤1V PJT7838_SOT363-6
QG3B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 39 of 68
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 40 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 41 of 68

5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms＜spec＜100ms
Need short +3VALW_LAN +LAN_VDDREG

JL1 1 2 @ width : 40 mils RL1 1 @ 2 0_0603_5%

1 2
JUMP_43X79

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
D D

CL1

CL2
1 1
+3VALW

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
0.01U_6.3V_K_X7R_0201
LP2301ALT1G_SOT23-3

CL4

CL5
1 1 1 1
3 1 @

8111GUL@

8111GUL@
QL2

D
2 2

CL6

CL7
0.1U_6.3V_K_X5R_0201

CL9
RL2 1 1 @ @
100K_0402_5% 2 2 2 2

G
2
CL8
@ @
@

2
2 2
RL3 1 @ 2 47K_0402_5%
49 LAN_PWR_ON#

Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

+3VALW_LAN +3VS

+3VALW_LAN

2
2

2
RL4

G
RL5 10K_0402_5%
10K_0402_5%
@
manual change the PN to RTL8111GUL-CG @ QL1
L2N7002KWT1G_SOT323-3

1
LAN_CLKREQ#_R 1 3
UL1 LAN_CLKREQ# 9
1

S
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
8,45,49 PCIE_WAKE# 1 2 0_0402_5% @
45,49 LAN_WAKE# RL6 @
C C

33 RL18 1 @ 2 0_0402_5%
+3VALW_LAN 32 GND 16 CLK_PCIE_LAN#
1 2 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN CLK_PCIE_LAN# 9
RL8 RSET
+LAN_VDD10 30 RSET REFCLK_P 14 PCIE_PTX_C_DRX_N0 CLK_PCIE_LAN 9
2.49K_0402_1%
LAN_XTALO 29 AVDD10 HSIN 13 PCIE_PTX_C_DRX_P0 PCIE_PTX_C_DRX_N0 5
LAN_XTALI 28 CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P0 5
+3VS RL12 TPL1 @ 1 Test_Point_12MIL 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# 1 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 43
0_0402_5% TPL2 @ 1 Test_Point_12MIL 25 9
LED2 MDIP3 LAN_MDI3+ 43
1

@ +LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 43
1K_0402_1% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ 43
21 5
ISOLATE# 20 LANW AKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 43
ISOLATEB MDIP1 LAN_MDI1+ 43
2

PLT_RST# 19 3 +LAN_VDD10
8,28,37,45 PLT_RST# PCIE_PRX_C_DTX_N0 PERSTB AVDD10_1 LAN_MDI0-
5 PCIE_PRX_DTX_N0 CL10 1 2 0.1U_6.3V_K_X5R_0201 18 2
2018/01/24: add AZ5815-01F.R7GR for
LAN_PWR_ON# PCIE_PRX_C_DTX_P0 HSON MDIN0 LAN_MDI0+ LAN_MDI0- 43
ISOLATE# RL10 1 @ 2 CL11 1 2 0.1U_6.3V_K_X5R_0201 17 1
5 PCIE_PRX_DTX_P0 HSOP MDIP0 LAN_MDI0+ 43 RTL8111H Lan Surge issue (Default reserve)
0_0402_5%
1

+LAN_VDD10
RL11
15K_0402_5%
@

1
2

RTL8111GUL-CG QFN 32P DL4

1
@ AZ5815-01FPR7GR_DFN1006P2E-2
EMC_8111H@
B B

2
2
For RTL8111GUL(SWR mode)
For RTL8111H (LDO mode)
+LAN_VDD10
LL1 1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
LAN_XTALI
+LAN_REGOUT RL13 1 2 8111H@
0_0805_5%
LAN_XTALO_R 1 2 LAN_XTALO 1 1

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
RL19 1K_0402_5% 1
YL1 CL3 CL15 CL16 1 1 1 1 1 1
0.1U_6.3V_K_X5R_0201 4.7U_0402_6.3V6M 0.1U_6.3V_K_X5R_0201
1 4 2 2 8111GUL@

CL17

CL18

CL19

CL20

CL21

CL22
8111H@ 8111GUL@
OSC1 GND2 2
2 3 2 2 2 2 2 2
GND1 OSC2 @ @
1 1
CL12
15P_0402_50V8J
25MHZ_10PF_7V25000014 CL13
15P_0402_50V8J
Layout Note: LL1 must be
within 200mil to Pin24,
2 2 CL15,CL16 must be within
200mil to LL1 Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
A
+LAN_REGOUT: Width =60mil A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 LAN_RTL8111H_CG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 42 of 68

5 4 3 2 1
 5 4 3 2 1

TL1
TCT 24 1 MCT
MCT1 TCT1
LAN_MDI3+ 23 2 LAN_MDO3+
42 LAN_MDI3+ MX1+ TD1+
LAN_MDI3- 22 3 LAN_MDO3-
42 LAN_MDI3- MX1- TD1-

1
21 4 MCT RL17
MCT2 TCT2 20_0603_5%

1
D LAN_MDI1+ 20 5 LAN_MDO1+ D
42 LAN_MDI1+ MX2+ TD2+ EMC_GST@
DL3
Default DL1/DL2 use

1
2
LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
42 LAN_MDI1- MX2- TD2- EMC_GST@
S DIO(BR) AZ1513-04S.R7G SOT23-6L 18 7 MCT EMC

2
MCT3 TCT3

for 8111H, L340 project

2
LAN_MDI2+ 17 8 LAN_MDO2+
42 LAN_MDI2+ MX3+ TD3+
LAN_MDI2- 16 9 LAN_MDO2-
42 LAN_MDI2- MX3- TD3-
15 10 MCT
MCT4 TCT4
DL1 1 1
LAN_MDI0+ 14 11 LAN_MDO0+ CL14 CL23
LAN_MDI1+ 4 3 LAN_MDI0- 42 LAN_MDI0+ MX4+ TD4+ 0.022U_50V_K_X7R_0603 1000P_1206_2KV7-K
LAN_MDI0- 13 12 LAN_MDO0- EMC_GST@ EMC_GST@
42 LAN_MDI0- MX4- TD4- 2 2
1 EMC
5 2 CL24
0.01U_0201_25V6-K BOTH_GST5009 LF
EMC_GST@
2
LAN_MDI1- 6 1 LAN_MDI0+
EMC
AZ1513-04S.R7G SOT23 CHASSIS1_GND
C C
EMC_8111H@

DL2
LAN_MDI2+ 4 3 LAN_MDI3- 只有 8111H可使用，8111GUL不可用

TL2
5 2 LAN_MDI3+ 23 2 LAN_MDO3+
TD1+ MX1+
LAN_MDI3- 22 3 LAN_MDO3- JRJ1 ME@
TD1- MX1-
12
LAN_MDI1+ 20 5 LAN_MDO1+ GND_4
LAN_MDI2- 6 1 LAN_MDI3+ TD2+ MX2+
11
LAN_MDI1- 19 6 LAN_MDO1- GND_3
AZ1513-04S.R7G SOT23 TD2- MX2-
10
EMC_8111H@ LAN_MDI2+ 17 8 LAN_MDO2+ LAN_MDO0+ 1 GND_2
TD3+ MX3+ TX_DA+ 9
LAN_MDI2- 16 9 LAN_MDO2- LAN_MDO0- 2 GND_1
TD3- MX3- TX_DA-
Place Close to TL1 EMC LAN_MDI0+ 14 11 LAN_MDO0+ LAN_MDO1+ 3
TD4+ MX4+ RX_DB+ CHASSIS1_GND
LAN_MDI0- 13 12 LAN_MDO0- LAN_MDO2+ 4
TD4- MX4- BI_DC+
B 24 4 LAN_MDO2- 5 B
TCT1 NC1 BI_DC-
21 7 LAN_MDO1- 6
TCT2 NC2 RX_DB-
18 10 LAN_MDO3+ 7
TCT3 NC3 BI_DD+
TCT 15 1 MCT LAN_MDO3- 8
TCT4 GND BI_DD-

AJOHO_N-8660GR ALLTO_C10235-10839-L
@
8/16 Update RJ45 P/N DC021608091 wei

Place Close to TL1 EMC

JL2
MCT 1 2
1 2
JUMP_43X79
RL14 1 @ 2 0_0603_5% @
CHASSIS1_GND
RL15 1 @ 2 0_0603_5%

RL16 1 @ 2 0_0603_5%
A A
EMC
Security Classification LC Future Center Secret Data Title
CHASSIS1_GND
Issued Date 2015/08/20 Deciphered Date 2018/09/20 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 43 of 68

5 4 3 2 1
 5 4 3 2 1

REMOTE1+_R RS1 1 @ 2 0_0402_5% REMOTE1+

Close to U1 REMOTE1-_R RS2 1 @ 2 0_0402_5% REMOTE1- REMOTE1+

Near GPU&VRAM REMOTE2+
Near CPU core
1

1
REMOTE1+_R 1 CS6 C

1
1 CS5 C 100P_0201_25V8J 2 QS16
CS1 REMOTE2+_R RS3 1 @ 2 0_0402_5% REMOTE2+ 100P_0201_25V8J 2 QS15 @ B MMBT3904WH_SOT323-3
2200P_0201_25V7-K @ B MMBT3904WH_SOT323-3 2 E

3
@ 2 E REMOTE2-

3
2 REMOTE1-_R REMOTE2-_R RS4 1 @ 2 0_0402_5% REMOTE2- REMOTE1-

REMOTE2+_R
+3VALW
D 2 REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D
CS2 Trace width/space:10/10 mil Near CPU
2200P_25V_K_X7R_0201
1 Trace length:<8"

1
REMOTE2-_R
@

1
RS19
+3VS 13.7K_0402_1% RS21
@ @ 13.7K_0402_1%
SMSC thermal sensor

2
2
NTC_V1
placed near DIMM

2
RS17 NTC_V2

1
US1 4.7K_0402_5%

1
+3VS @ RTS2
@ 100K_0402_1%_NCP15WF104F03RC RTS3
@

1
1 10 EC_SMB_CK2 100K_0402_1%_NCP15WF104F03RC
VDD SCLK EC_SMB_CK2 7,28,49

2
1 REMOTE1+_R 2 9 EC_SMB_DA2
D1+ SDA EC_SMB_DA2 7,28,49

2
CS7

2
0.1u_0201_10V6K REMOTE1-_R 3 8 RS13 1 @ 2 0_0402_5%
D1- ALERT# SMB1_ALERT# 49
@ RS20
2 REMOTE2+_R 4 7 RS18 2 @ 1 4.7K_0402_5% @ 0_0402_5%
D2+ TCRIT# +3VS
REMOTE2-_R 5 6
D2- GND

1
NCT7719W_MSOP10

Address 1001_101xb
for layout optimized, change the EC_AGND to
C GND C

+5VLP +5VLP
+5VLP

HW thermal sensor

2
1 RS29 RS36
CS12 21.5K_0402_1% 21.5K_0402_1%
0.1u_0201_10V6K @ @
@

1
2
US18 @
1 8 TMSNS1 RS88 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 49
2 7 PHYST1 RS9 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 RS10 1 @ 2 0_0402_5% NTC_V2
49,59,61 EC_ON OT1 TMSNS2 NTC_V2 49
4 5 PHYST2 RS11 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

over temperature threshold:

RSET=3*RTMH
92+/-30C
B
Hysteresis temperature threshold. B
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn
need check ME SDV CONN list
Change to SP011411114 ref ME conn list,20181017SF update
HIGHS_WS83081-S0171-HF

ME@ 10
0.5A +5VS GND2
GND1
9

R52 1 @ 2 0_0603_5% +5VS_FAN1 8

7 8
1 1 49 EC_FAN1_SPEED 7
C50 49 EC_FAN1_PWM 6
C49 .1U_0402_10V6-K 5 6
10U_0805_10V6K @ 4 5
2 2 3 4
49 EC_FAN2_PWM 3
49 EC_FAN2_SPEED 2
1 2
0.5A +5VS 1
A JFAN1 A
R75 1 @ 2 0_0603_5% +5VS_FAN2

1 1
C60
C81 .1U_0402_10V6-K
10U_0805_10V6K @ Title
2 2 Security Classification LC Future Center Secret Data
Issued Date 2016/08/16 Deciphered Date 2018/09/20 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
Document Number
Number Rev
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date:
Date: Saturday, May 09, 2020 Sheet
Sheet 44 of 68
5 4 3 2 1
 A B C D E

+3VS +3VS_WLAN +3VS_WLAN

JN9 Need short

1 2
1 2 JUMP_43X79 RN25 1 2 10K_0402_5% PCH_W LAN_OFF#
@ RN26 1 2 10K_0402_5% PCH_BT_OFF# +3VS_WLAN

for wlan same power source issue 0719SF

+3VALW

1 1 1
CN1 CN2 CN3
@ @
@ 0.01U_16V_J_X7R_0402
UN1 2 2
0.1u_0201_10V6K 2 10U 6.3V M X5R 0402
RN19
5 1 1 2
IN OUT
0.01_0603_1%
1 2 1
GND @ JW LAN1 ME@
1 1 2
3V_W LAN_EN 4 3

CN20
0.01U_0402_25V7K
49 3V_W LAN_EN 3 GND1 3.3VAUX1 4
EN OCB 10 USB20_P6 5 USB_D+ 3.3VAUX2 6 1 @ T2
10 USB20_N6 USB_D- LED1#
2@ 7 8
SY6288C20AAC_SOT23-5 9 GND2 PCM_CLK/I2S_SCK 10
@ 11 SDIO_CLK PCM_SYNC/I2S_WS 12
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T3
17 SDIO_DATA1 LED#2 18
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22
23 SDIO_WAKE# UART_RXD
SDIO_RESET#

KEY E
25 PIN24~PIN31 NC PIN 24
+3VS +3VS_WLAN
WLAN 27 26
29 28

2
31 30
@ RN13

2
QN2 10K_0402_5% 33 32

G
@ 35 GND3 UART_TXD 34
5 PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
37 36
5 PCIE_PTX_C_DRX_N1 PETN0 UART_RTS

1
39 38 EC_TX_RSVD 1 2 0_0201_5%
WLAN GND4 VENDOR_DEFINED1 EC_RX_RSVD
RN5 @
3 1 41 40 RN6 1 @ 2 0_0201_5%
5 PCIE_PRX_DTX_P1 PERP0 VENDOR_DEFINED2
43 42

D
5 PCIE_PRX_DTX_N1 45 PERN0 VENDOR_DEFINED3 44
+3VS L2N7002KWT1G_SOT323-3
47 GND5 COEX3 46
9 CLK_PCIE_W LAN 49 REFCLKP0 COEX2 48
9 CLK_PCIE_W LAN# 51 REFCLKN0 COEX1 50 SUSCLK_R
RN14 1 2 0_0402_5% W LAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST#
1 9 W LAN_CLKREQ# PCIE_WAKE#_W LAN CLKREQ0# PERST0# BT_OFF# PLT_RST# 8,28,37,42,45
RN21 1 AOAC@ 2 0_0402_5% 55 54 RN8 1 2 1K_0402_5%
8,42,49 PCIE_WAKE# PEWAKE0# W_DISABLE2# W LAN_OFF# PCH_BT_OFF# 9
change WLAN CLKREQ# PH power source 0329SF
57 56 RN9 1 @ 2 0_0402_5%
C2 GND7 W_DISABLE1# PCH_W LAN_OFF# 9
0.1U_6.3V_K_X5R_0201 U135 RN22 1 @ 2 0_0402_5%
42,49 LAN_W AKE#
2 5 1
@ Vcc OE If support AOAC, NC R61; 59 58 W LAN_SMB_DATA RN34 1 @ 2 0_0402_5%
EC_RX 46,49
RSRVD/PETP1 I2C_DATA W LAN_SMB_CLK
2 SUSCLK if not support AOAC, stuff R61. 61
RSRVD/PETN1 I2C_CLK
60 RN35 1 @ 2 0_0402_5%
EC_TX 46,49
IN_A SUSCLK 9 63 62
65 GND8 ALERT# 64
SUSCLK_R 4 3 RSRVD/PERP1 RSRVD
OUT_Y GND 67 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68

1
71 GND9 UIM_POWER_SNK/CLKREQ1# 70
M74VHC1GT125DF2G_SC70-5 RSRVD/REFCLKP1
UIM_POWER_SRC/GPIO1/PEWAKE1# RN10
73 72
@ 75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14 PLT_RST#
2 RN30 1 @ 2 0_0402_5% 2
ARGOS_NASE0-S6701-TS40 1
+3VS_WLAN CN7
8/16 Update Conn. P/N SP070013200 wei 1000P_0402_50V7K
2
@

1 1 1

1U_0402_6.3V6K
0.1u_0201_10V6K

CN5

CN6
10U 6.3V M X5R 0402

CN8
2 2 2

+3.3V_NGFF +3.3V_NGFF

1 M.2 SSD(PCIE)

1
C1
0.1U_6.3V_K_X5R_0201
2 R8117 +3VS
10K_0402_5%
@
J8 2A

5
U134 1 2
1 2 +3.3V_NGFF

2
GND VCC
PLT_RST# 1 JUMP_43X79
8,28,37,42,45 PLT_RST# IN1 1 1

22U_0603_6.3V6-M

4.7U_0402_6.3V6M
4 SSD_RST# @
OUT 1

.1U_0402_10V6-K
APU_SSD_RST# 2

CD@
CF37

CF38
8 APU_SSD_RST# IN2

M.2 SSD(SATA/PCIE)

CD@
CF39
2 2
2
MC74VHC1G08DFT2G_SC70-5 Change 0805 to Jump HLZ SDV 0616

1
CC170 1

3
PR8118
1000P_0402_50V7K 10K_0402_5%
+3VS +3.3V_NGFF
J16 2A 2
JSSD1

2
1 2
1 2 +3.3V_NGFF 1 2
3 GND_1 3.3V_1 4
JUMP_43X79 1 1 GND_2 3.3V_2 6
22U_0603_6.3V6-M

PCIE_PRX_DTX_N4
4.7U_0402_6.3V6M

@ 5 2
1 5 PCIE_PRX_DTX_N4 PERN3 N/C_2 8
.1U_0402_10V6-K

PCIE_PRX_DTX_P4 7
CD@
CF24

CF25

5 PCIE_PRX_DTX_P4 9 PERP3 N/C_3 10 CF40

CD@
CF26

2 2 PCIE_PTX_DRX_N4 CF12 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N4_C 11 GND_3 DAS/DSS# 12

3 5 PCIE_PTX_DRX_N4 PETN3 3.3V_3 14 .1U_0402_10V6-K 3
2 PCIE_PTX_DRX_P4 CF13 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P4_C 13 1
Change 0805 to Jump HLZ SDV 0616 5 PCIE_PTX_DRX_P4 15 PETP3 3.3V_4 16 +3.3V_NGFF
PCIE_PRX_DTX_N5 17 GND_4 3.3V_5 18
5 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 19 PERN2 3.3V_6 20
+3.3V_NGFF 5 PCIE_PRX_DTX_P5 PERP2 N/C_4 22
JSSD2 21
PCIE_PTX_DRX_N5 CF10 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N5_C 23 GND_5 N/C_5 24
5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P5_C PETN2 N/C_6 26

1
CF11 2 25
1 2 5 PCIE_PTX_DRX_P5 PETP2 N/C_7 28
GND_1 3.3V_1 4 27 RF10
3 PCIE_PRX_DTX_N6 GND_6 N/C_8 30
PCIE_PRX_DTX_N11 GND_2 3.3V_2 6 29 10K_0201_5%
5 2 5 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PERN1 N/C_9 32
5 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PERN3 N/C_2 8 31 @
7 5 PCIE_PRX_DTX_P6 PERP1 N/C_10 34
5 PCIE_PRX_DTX_P11 PERP3 N/C_3 10 33
9 CF23 GND_7 N/C_11 36

2
GND_3 DAS/DSS# 12 PCIE_PTX_DRX_N6 CF8 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N6_C 35
PCIE_PTX_DRX_N11 CF17 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N11_C 11 5 PCIE_PTX_DRX_N6 PETN1 N/C_12 38
5 PCIE_PTX_DRX_N11 PETN3 3.3V_3 14 .1U_0402_10V6-K PCIE_PTX_DRX_P6 CF9 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P6_C 37
PCIE_PTX_DRX_P11 CF18 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P11_C 13 1 5 PCIE_PTX_DRX_P6 PETP1 DEVSLP 40
5 PCIE_PTX_DRX_P11 PETP3 3.3V_4 16 +3.3V_NGFF 39
15 PCIE_PRX_DTX_P7 GND_8 N/C_13 42
PCIE_PRX_DTX_N10 GND_4 3.3V_5 18 41
17 5 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 PERN0/SATA-B+ N/C_14 44
5 PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PERN2 3.3V_6 20 43
19 5 PCIE_PRX_DTX_N7 PERP0/SATA-B- N/C_15 46

1
5 PCIE_PRX_DTX_P10 PERP2 N/C_4 22 45
21 PCIE_PTX_DRX_N7 GND_9 N/C_16 48
PCIE_PTX_DRX_N10 GND_5 N/C_5 24 CF1 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N7_C 47 RF12
CF19 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N10_C 23 5 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 PETN0/SATA-A- N/C_17 50
5 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 PETN2 N/C_6 26 CF7 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P7_C 49 SSD_RST# 10K_0201_5% @
1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P10_C
1

CF21 2 25 5 PCIE_PTX_DRX_P7 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ#

5 PCIE_PTX_DRX_P10 PETP2 N/C_7 28 51
27 RF2 CLK_PCIE_SSD# GND_10 CLKREQ# 54 SSD_CLKREQ# 9
PCIE_PRX_DTX_N9 GND_6 N/C_8 30 53 1 1
29 10K_0201_5% 9 CLK_PCIE_SSD# REFCLKN PEWAKE# 56

2
5 PCIE_PRX_DTX_N9 PERN1 N/C_9 32 CLK_PCIE_SSD 55 CF41
PCIE_PRX_DTX_P9 31 @ 9 CLK_PCIE_SSD REFCLKP N/C_18 58
5 PCIE_PRX_DTX_P9 PERP1 N/C_10 34 57 TP76 1000P_0402_50V7K
33 GND_11 N/C_19
GND_7 N/C_11 36 DF1 @
2

PCIE_PTX_DRX_N9 CF20 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N9_C 35 +3.3V_NGFF

5 PCIE_PTX_DRX_N9 PETN1 N/C_12 38 @ 59 NC NC 60 2
PCIE_PTX_DRX_P9 CF14 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P9_C 37 2 1 SATA_DEVSLP0

1
5 PCIE_PTX_DRX_P9 PETP1 DEVSLP 40 SATA_DEVSLP0 8 61 NC NC 62
39 SUSCLK_R
PCIE_SATA_PRX_DTX_P8 GND_8 N/C_13 42 RF6 63 NC NC 64 RF23 1 @ 2
41
5 PCIE_SATA_PRX_DTX_P8 PCIE_SATA_PRX_DTX_N8 PERN0/SATA-B+ N/C_14 44 RB521CM-30T2R_VMN2M-2 10K_0201_5% 65 NC NC 66
43 +3.3V_NGFF
5 PCIE_SATA_PRX_DTX_N8 PERP0/SATA-B- N/C_15 46 67 68 0_0201_5%
1

45 @
PCIE_SATA_PTX_DRX_N8 GND_9 N/C_16 48 PEDET 69 N/C_1 SUSCLK 70
CF15 2 1 0.22U_0201_6.3V6-K PCIE_SATA_PTX_DRX_N8_C 47 RF4 71 PEDET 3.3V_7 72

2
5 PCIE_SATA_PTX_DRX_N8 PCIE_SATA_PTX_DRX_P8 2 1 0.22U_0201_6.3V6-K PCIE_SATA_PTX_DRX_P8_C 49 PETN0/SATA-A- N/C_17 50 SSD_RST#
CF16 10K_0201_5% @ 73 GND_12 3.3V_8 74
5 PCIE_SATA_PTX_DRX_P8 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ1#
51
CLK_PCIE_SSD1# GND_10 CLKREQ# 54 SSD_CLKREQ1# 9 75 GND_13 3.3V_9
1 1
53 1 1 GND_14
9 CLK_PCIE_SSD1# REFCLKN PEWAKE# 56
2

CLK_PCIE_SSD1 55 CF29 1

22U_0603_6.3V6-M
.1U_0402_10V6-K
.1U_0402_10V6-K
1
9 CLK_PCIE_SSD1 77 76
REFCLKP N/C_18 58 Only support PCIE SSD

CF36

CF143
+3.3V_NGFF 57 TP77 1000P_0402_50V7K PEG1 PEG2
GND_11 N/C_19 RF7

CF42
@ 2 2
1

59 NC NC 60 2 10K_0201_5%
RF13 @ ARGOS_NASM0-S6701-TS40 2
61 NC NC 62 RF22 1 @ 2 SUSCLK_R
10K_0201_5% 63 NC NC 64 ME@
0_0201_5%

2
@ 65 NC NC 66
SUSCLK_SSD2 +3.3V_NGFF SUSCLK是否需要预留?
67 68 OPTANE@ OPTANE@
2

SSD2_DET 69 N/C_1 SUSCLK 70 OPTANE@

71 PEDET
GND_12
3.3V_7 72
3.3V_8 74
For optane
73
75 GND_13 3.3V_9
1

1 1 1
PEDET (PE_DTCT) GND_14
.1U_0402_10V6-K

RF14
22U_0603_6.3V6-M
.1U_0402_10V6-K

SATA Device GND 77 76

CF28

CF22

CF27

10K_0201_5% PEG1 PEG2

PCIe Device Open @ 2 2 2
4 ARGOS_NASM0-S6701-TS40 4
2

SSD_DET# ME@
0 - SATA OPTANE@
1 - PCIE For optane
OPTANE@
OPTANE@
+3VALW_APU
2

RF18
2.2K_0402_5%
1

SSD2_DET Security Classification LC Future Center Secret Data Title

RF15 1 @ 2 0_0402_5%
SSD_SATA_PCIE_DET1# 8
Issued Date 2016/12/14 Deciphered Date 2018/09/20 NGFF WLAN&SSD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 45 of 68
A B C D E
 A B C D E

+USB_VCCA

CI2 1 2

+
220U_6.3V_M

CI3 1 2
@ 47U_0805_6.3V6-M
LEFT SIDE USB3.0 PORT x2 CI4 1 2
@ 1U_0402_10V6K

+5VALW +USB_VCCA CI35 1 2

UI125 @ 1U_0402_10V6K
5 1
IN OUT JUSB1 ME@
1
CI32 2
1U_0402_6.3V6K GND USB30_TX_P1 CI10 1 2 0.22U_6.3V_K_X5R_0402 USB30_TX_C_P1 RI10 1 @ 2 0_0402_5% USB30_TX_R_P1 9
USB_OC2# 10 USB30_TX_P1 StdA_SSTX+
4 3 1
2 46,49 USB_ON# ENB OCB USB_OC2# 10 USB30_TX_N1 CI11 1 USB30_TX_C_N1 RI11 USB30_TX_R_N1 VBUS
2 0.22U_6.3V_K_X5R_0402 1 @ 2 0_0402_5% 8
10 USB30_TX_N1 USB20_P1_S 1 2 0_0402_5% USB20_P1_R 3 StdA_SSTX-
G517E2T11U_SOT23-5 1 RI2 @
1 CI31 7 D+ 1
1000P_0201_50V7-K USB20_N1_S RI3 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
USB30_RX_P1 CI75 1 2 0.33U 10V K X5R 0402 USB30_RX_C_P1 RI13 1 2 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11
USB load switch to low active 1.8A 2
EMC_NS@
10 USB30_RX_P1
@
4 StdA_SSRX+ GND_3 12
USB30_RX_N1 CI76 1 2 0.33U 10V K X5R 0402 USB30_RX_C_N1 RI12 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
10 USB30_RX_N1 StdA_SSRX- GND_5

ALLTO_C190AG-10939-L

09/05 Update USBConn. P/N DC021609011 wei

UARTA_P80_EN
LI15 EMC_NS@
USB30_RX_C_N1 1 2 USB30_RX_R_N1
1 2

USB30_RX_C_P1 USB30_RX_R_P1

1
4 3 RI27
4 3

2
USB20_P1_R

100K_0402_5%
EXC24CH900U_4P RI26
+USB_VCCA @ 0_0402_5% USB_NS@
USB20_N1_R

2
LI16 EMC_NS@

1
USB30_TX_C_N1 1 2 USB30_TX_R_N1

AZ5725-01F.R7GR_DFN1006P2X2
1 2

2
DI65
DI62

1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3
4 3 EMC@
EXC24CH900U_4P

2
EMC_NS@ DI24 EMC@

2
EXC24CH900U_4P USB30_RX_R_N110 1 USB30_RX_R_N1
USB20_P1_S 4 3 USB20_P1_R NC1 Line-1
4 3 USB30_RX_R_P1 9 2 USB30_RX_R_P1
NC2 Line-2

1
USB20_N1_S 1
1 2
2 USB20_N1_R USB30_TX_R_N1 7
NC3 Line-3
4 USB30_TX_R_N1
09/20SF Update USB debug CONN GND pin follow TINY5
LI8 EMC@
EMC USB30_TX_R_P1 6 USB30_TX_R_P1
5
NC4 Line-4
EMC 3
GND1
8
GND2

AZ1143-04F-R7G_DFN2510P10E10

2 2

RIGHT SIDE USB3.0 PORT x2 +USB_VCCB

HIGHS_FC5AF161-2931H
16 18
+5VALW +USB_VCCB 15 16 GND2 17
UI1 14 15 GND1
5 1 13 14
IN OUT 12 13
1 12
CI15 2 USB20_N5 11
GND 10,46 USB20_N5 USB20_P5 11
1U_0402_6.3V6K 10
USB_OC1# 10,46 USB20_P5 10
4 3 9
2 46,49 USB_ON# ENB OCB USB_OC1# 10 USB30_TX_P5 9
8
10,46 USB30_TX_P5 USB30_TX_N5 8
G517E2T11U_SOT23-5 1 7
10,46 USB30_TX_N5 7
CI16 6
1000P_0201_50V7-K USB30_RX_P5 5 6
10,46 USB30_RX_P5 USB30_RX_N5 5 +3VALW +3VALW_RE
Low Active 1.8A EMC_NS@ 4
2 10,46 USB30_RX_N5 4
3
+3VALW_RE 2 3
1 2 @
1 J17 1 2 JUMP_43X39
1 2
JP2
ME@ UR1
5 1
+USB_VCCB IN OUT

0.1U_6.3V_K_X5R_0201
HIGHSTAR_FC5AF241-2931H 2

10U 6.3V M X5R 0402

GND
24 1 1 1

1U_6.3V_K_X5R_0201
23 24 SYSON 4 3
23 49,60 SYSON EN OCB

CR2

CR1
22 26

CR3
21 22 GND2 25 SY6288C20AAC_SOT23-5 @ @
21 GND1 2 2 2
20 @
USB20_N5 19 20
10,46 USB20_N5 USB20_P5 19
18
10,46 USB20_P5 18
17
USB30_TX_P5 16 17
10,46 USB30_TX_P5 USB30_TX_N5 16
15
10,46 USB30_TX_N5 15
14
USB30_RX_P5 13 14
10,46 USB30_RX_P5 USB30_RX_N5 13
12
10,46 USB30_RX_N5 12
11
+3VALW_RE 10 11
9 10
+3VS CR_PW R USB20_N7 8 9
10 USB20_N7 USB20_P7 8
7
10 USB20_P7 6 7
RW 1 1 @ 2 5 6
0_0402_5% FP_LED# 4 5
+3VALW PB_PW R 49 FP_LED# 4
ON/OFFBTN# 3
50 ON/OFFBTN# PW R_LED# 3
3 2 3
49,50 PW R_LED# 2
R87 1 @ 2 1
0_0402_5% 1
JP9
ME@

For USB Debug Function 是否有必要

09/20SF add USB debug follow TINY5
change from SA00007WL0D to SA00007WL00 SF1001
SVT non-staff0322SF
2 1 USB_UART_SEL
8 USBDEBUG
RI23 1/16W _0_5%_0402
+3VALW USB_NS@
USBDEBUG Kernel debug
Set input Set input
+3VALW
Set output Low ENABLE
USB_NS@
UI129
1

USB_NS@
RI30
USB_NS@
1/16W _10K_5%_0402 RI24 2 1 1/16W _0_5%_0402 SOUTA_C 1 10
45,49 EC_TX 1D+ VCC
RI25 2 USB_NS@
1 1/16W _0_5%_0402 SINA_C 2 9 USB_UART_SEL
UARTA_P80_EN POST 80
2

USB_UART_SEL 45,49 EC_RX 1D- S

3 8 USB20_P1_S
10 USB20_P1 2D+ D+
NCY3958Y USB20_N1_S
Set input DISABLE
4 7
1

D 10 USB20_N1 2D- D-
UARTA_P80_EN Set output Low ENABLE
2
L2N7002KWT1G_SOT323-3 5 6
G GND1 OE#
QI13
11
S GND2
USB_NS@
3

4 4
NCT3958Y_DFN10_3X3 OE# S FUNCTION
H X DISABLE

L L D(+/-) to 1D(+/-)
USB20_P1 2 @ 1 USB20_P1_S
RI28 0_0402_5% L H D(+/-) to 2D(+/-)

USB20_N1 2 @ 1 USB20_N1_S
RI29 0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 46 of 68
A B C D E
 A B C D E F G H

SATA HDD Conn.

JHDD1
1
SATA_PTX_C_DRX_P0_CON 2 1
SATA_PTX_C_DRX_N0_CON 3 2
+5VS_HDD 4 3
SATA_PRX_C_DTX_N0_CON 5 4
SATA_PRX_C_DTX_P0_CON 6 5
7 6
1
8 7 12
1
1 1 1 1 1 8 GND2
CF34 CF35 CF31 CF6 CF30 9
33P_0201_50V8-J 33P_0201_50V8-J 0.1u_0201_10V6K 10U_0805_10V6K 10U_0805_10V6K 10 9 11
+5VS +5VS_HDD 10 GND1
2
RF@
2
RF@
2 2 2
@
Need short
HIGHS_FC5AF101-2931H
J3 1 2 @
1 2 ME@
JUMP_43X79
For EMC

SATA HDD Redriver(NEW ADD 20190614 ) +3VS

+3VS_SATA

R109 1 @ 2 0_0402_5%

+3VS_SATA
2 2

+3VS_SATA

2
SATA_RE@
RF20
1/20W_4.7K_5%_0201

U133
Close APU

1
7 10
EN VDD1 20
SATA_PTX_DRX_P0 1
CF147 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0 1 VDD2
5 SATA_PTX_DRX_P0 A_INP
SATA_PTX_DRX_N0 1
CF148 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0 2 6 REXT RF21 1 2 4.99K_0402_1%
5 SATA_PTX_DRX_N0 A_INN REXT 16 DEW SATA_RE@
SATA_PRX_DTX_P0 1
CF149 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0 5 DEW
5 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 1
CF150 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0 4 B_OUTP 9 A_DE
5 SATA_PRX_DTX_N0 B_OUTN A_DE 8 B_DE
A_EQ1 17 B_DE
A_EQ2 18 A_EQ1 15 SATA_PTX_U_DRX_P0 1
CF151 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0_CON
B_EQ1 19 A_EQ2 A_OUTP 14 SATA_PTX_U_DRX_N0 1
CF152 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0_CON
B_EQ2 13 B_EQ1 A_OUTN
B_EQ2 11 SATA_PRX_U_DTX_P0 1
CF153 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0_CON
3 B_INP 12 SATA_PRX_U_DTX_N0 1
CF154 SATA_RE@2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0_CON
21 GND1 B_INN
EPAD
PS8527C_TQFN20_4X4
SATA_RE@

3 +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA 3

+3VS_SATA
2

2
SATA_RE@ SATA_RE@
R41 R43 R47 R54 R57 R79 R36
1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201
1

1
A_EQ1 A_EQ2 B_EQ1 B_EQ2 A_DE B_DE DEW
1 1 1
SATA_RE@ SATA_RE@ SATA_RE@
2

2
CF144 CF145 CF146
R44 R45 R46 R60 R78 R80 R81 0.01U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201
@ @ @ @ @ @ @ 2 2 2
1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201
1

1
Close to pin 10. Close to pin 20.

Equalization level setting for Channel x(x=A/B), De-emphasis level setting for Channel x(x=A/B), De-emphasis widith adjustment,
internally tied to VDD/2 internally tied to VDD/2 internally pulled down
[x_EQ2, x_EQ1] == [x_DE] == [DEW] ==
L/M: for channel loss up to 2.4dB M: -3.5dB (default) M: for SATA3(default)
L/L: for channel loss up to 7.4dB L: 0dB L: for SATA3
L/H: for channel loss up to 14.4dB H: -6dB H: for SATA2
M/M: for channel loss up to 12.2dB (default)
M/L: for channel loss up to 9.4dB
4 M/H: for channel loss up to 13.3dB 4
H/M: for channel loss up to 6.2dB
H/L: for channel loss up to 11.2dB
H/H: for channel loss up to 5dB

Security Classification LC Future Center Secret Data Title

Follow Vendor suggest
Issued Date 2015/08/20 Deciphered Date 2018/09/20 HDD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 47 of 68
A B C D E F G H
 5 4 3 2 1

+5VALW 1.5A
1

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
+ C1333

CT1

CT9
150U_B2_6.3VM_R35M
@ VBUS_P0
2

2
U6
5 1
IN OUT
2
GND
D VBUS_EN_C 4 3 TYPE_C_OCP# D
EN OCB TYPE_C_OCP# 10
High active SY6288C20AAC_SOT23-5 1
Q4211

1
D C8791
R4712 2 @ 1 EC_VBUS_EN_R 2 1000P_0201_50V7-K
49 EC_VBUS_EN
0_0402_5% G @ EMC_NS@
2
2N7002KW_SOT323-3 S

3
VBUS_EN R4711 2 @ 1 0_0402_5%

+3VALW
+3V_MUX +5VALW +5V_MUX
R133 2 @ 1 0_0402_5% R173 2 @ 1 0_0402_5%

+3VS +5VS
R134 1 @ 2 0_0402_5% R174 1 @ 2 0_0402_5%

U26
VBUS_P0 VBUS_P0

GND6
GND5
2 2 JP1
TYPE_C_OCP# 16
VBUS_EN 15 OCP_DET CC1271 CC1272

GND9
GND10
VBUS_EN 220P_0201_25V7-K 220P_0201_25V7-K
1 1 A12 B1
VMON 17 12 CC1 A5 GND2 GND3
VMON CC1 14 CC2 B5 C_RX2_P_C A11 B2 C_TX2_P_C
C CC2 SSRXp2 SSTXp2 C
C_RX2_N_C A10 B3 C_TX2_N_C
11 MUX_TX2_N C2076 1 2 0.1U_6.3V_K_X7R_0402C_TX2_N B3 SSRXn2 SSTXn2
C_TX2_1P/2N 10 MUX_TX2_P C2075 1 2 0.1U_6.3V_K_X7R_0402C_TX2_P B2 A9 B4
C_TX2_1N/2P Vbus2 Vbus3
C2068 1 2 0.33U 10V K X5R 0402 USB30_RX_N0_M 4 24 C_RX2_N A10 A8 B5 CC2
10 TYPE-C_USB3_RX_N0 USB30_RX_P0_M SSRX_1P/2N C_RX2_1P/2N C_RX2_P SBU1 CC2
C2067 1 2 0.33U 10V K X5R 0402 5 1 A11
10 TYPE-C_USB3_RX_P0 SSRX_1N/2P C_RX2_1N/2P C_DM C_DP
C2065 1 2 0.22U_6.3V_K_X5R_0402 USB30_TX_N0_M 6
10Gbps 2:1 MUX 8 MUX_TX1_N C2073 1 2 0.1U_6.3V_K_X7R_0402C_TX1_N
A7
Dn1 Dp2
B6
10 TYPE-C_USB3_TX_N0
A3
C2066 1 2 0.22U_6.3V_K_X5R_0402 USB30_TX_P0_M 7 SSTX_1P/2N C_TX1_1P/2N 9 MUX_TX1_P C2074 1 2 0.1U_6.3V_K_X7R_0402C_TX1_P A2 C_DP A6 B7 C_DM
10 TYPE-C_USB3_TX_P0 SSTX_1N/2P C_TX1_1N/2P Dp1 Dn2
2 C_RX1_N B10 CC1 A5 B8
C_RX1_1P/2N 3 C_RX1_P B11 CC1 SBU2
C_RX1_1N/2P A4 B9
+5V_MUX Vbus1 Vbus4
13 C_TX1_N_C A3 B10 C_RX1_N_C
VCON_IN R171 1 @ 2 0_0402_5% SSTXn1 SSRXn1
23 Realtek C_TX1_P_C A2 B11 C_RX1_P_C

0.1u_0201_10V6K
M1 21 C_CONN_STAT 19 R172 1 @ 2 0_0402_5% SSTXp1 SSRXp1
RP_SEL_M1 5V_IN

10U 6.3V M X5R 0402

+3V_MUX
RTS5449E

GND5
GND6
GND7
GND8
M0 22 2 1 A1 B12
RP_SEL_M0 20 GND1 GND4

C2063

C2077
0.1U_0201_6.3V6-K
LDO_3V3
4.7U_0402_6.3V6M

ATOB_066-12A1-3211
C2064

1 2 1 2

GND1
GND2
GND3
GND4
18 25 ME@
VBUS_P0
CC1273

REXT E-PAD
2

VBUS_P0
R3150 2 1
6.2K_0402_1%

1
RTS5449E-GR_QFN24_4X4 Close Pin13
1

R3155

4.7U_0805_25V6-K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.1U_25V_K_X5R_0201
Close Pin19 200K_0402_1%

10U_0805_25V6K
1 1 1 1 1 1

C918

C919

C922

C921

C920

C1334

C8801
D38

1
VMON

SPHV24-01ETG-C_SOD882-2
@

1
2 2 2 2 2 2@

1
EMC_NS@ @

2
+3V_MUX +3V_MUX
Rp configuration
R3149
10K_0402_1%
2

2
Rp:1.5A (now) 1
R3139 R3142

2
10K_0402_5% @ 10K_0402_5%
B
M1 M0 Note B

Rp:900mA 0 1 R3144/R4674 mount

1

M1 M0 R943 1 @ 2 0_0402_5% R3135 1 @ 2 0_0402_5% CC1 C_DP

Rp:1.5A 1 0 R3139/R4674 mount CC2 C_DM
2

L23 EMC@ L31 EMC@

Rp:3.0A 1 1 R3139/R3142 mount

2
R3144 R4674 4 3 C_DP C_RX1_N 4 3 C_RX1_N_C D47 EMC_NS@ D48 EMC_NS@
10 USB20_P0 4 3 4 3
@ 10K_0402_5% 10K_0402_5%

1 2 C_DM C_RX1_P 1 2 C_RX1_P_C

10 USB20_N0 1 2 1 2
1

EXC24CH900U_4P EXC24CH900U_4P
R3137 1 @ 2 0_0402_5%
R91 1 @ 2 0_0402_5%

+3V_MUX R3136 1 @ 2 0_0402_5%

For C_VBUS
R944 2 @ 1 0_0402_5%
power switch enable pin L32 EMC@ AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3

1
2

L24 EMC@ C_TX1_P 4 3 C_TX1_P_C

R3146 C_TX2_N 3 4 C_TX2_N_C 4 3
10K_0402_5% 3 4
@ 1 2
C_TX2_P 2 1 C_TX2_P_C 1 2
Power switch enable pin Note 2 1
1

EXC24CH900U_4P
VBUS_EN EXC24CH900U_4P C_TX1_N R3138 1 @ 2 0_0402_5% C_TX1_N_C
Low Active R3146 mount
2

R3107 2 @ 1 0_0402_5%
R3141 High Active R3141 mount
10K_0402_5%
R100 2 @ 1 0_0402_5%
1

L25 EMC@
C_RX2_P 3 4 C_RX2_P_C D36 EMC_NS@ D20 EMC_NS@
3 4 C_TX2_P_C 9 10 1 C_TX2_P_C C_TX1_P_C 9 10 1 C_TX1_P_C
1 1
C_RX2_N 2 1 C_RX2_N_C C_TX2_N_C 8 9 2 2 C_TX2_N_C C_TX1_N_C 8 9 2 2 C_TX1_N_C
+3V_MUX 2 1
For C_VBUS C_RX1_N_C 7 C_RX1_N_C C_RX2_N_C 7 C_RX2_N_C
EXC24CH900U_4P 7 4 4 7 4 4
power switch OCP pin
PH at CPU side 09/06 wei
2

R101 2 @ 1 0_0402_5% C_RX1_P_C 6 6 5 5 C_RX1_P_C C_RX2_P_C 6 6 5 5 C_RX2_P_C

R3147
10K_0402_5% 3 3 3 3
@
Power switch OCP pin Note 8 8
1

A TYPE_C_OCP# A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
Low Active R3147 mount For ESD
High Active R3140 mount
2

R3140
@ 10K_0402_5%
1

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Type-C RTS5449E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 48 of 68
5 4 3 2 1
 5 4 3 2 1

For EMI For ESD +3VS

APU_LPC_RST# +3VL_EC_R
CLK_PCI_EC RE2 1 @ 2 33_0402_5% +3VL_EC
EC_FAN2_SPEED RE278 1 2 10K_0402_5%
1 RE4 1 @ 2 0_0603_5%
1 CE1
25 WRST# CE2 220P_0201_25V7-K EC_FAN1_SPEED RE10 1 2 10K_0402_5%
22P_0402_50V8-J @ RE1 1 @ 2 0_0603_5% (For PLL Power) 1 1
@ +3VL
+3VL_EC 2 CE4 CE5
2 0.1u_0201_10V6K 1000P_0201_50V7-K
EC_FAN2_PWM RE65 1 2 10K_0402_5%

@
DE1 1 2 2 2
+3VS RE3 1 2 0_0603_5%

@
+3VALW +3VL_EC EC_AGND EC_FAN1_PWM
RE6 1 @ 2 0_0603_5% RE11 1 2 10K_0402_5%

@
RB751V-40_SOD323-2

1 2 WRST#
+1.8VALW +VFSPI
+3VL_EC All capacitors close to EC LPC_FRAME# RE7 1 @ 2 10K_0201_5%

2
EC_AGND

CD@
CD@
RE8

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
0.1u_0201_10V6K
1 RE97 2 @ 1 0_0402_5% RE437 ENBKL RE9 1 2 100K_0402_5%

@
100K_0402_5% 1 1 1 1 1 1 1
CE12 0_0603_5% @ +3VL_EC_R
D
1U_0402_6.3V6K For SPI ROM Mirror D
2

1
2 2 2 2 2 2 2

CE10

CE11
+VFSPI
CE53 1 2 CD@

CE6

CE7

CE8

CE9
CE54
0.1u_0201_10V6K
For PMIC
+3VALW +3VL_EC
UE1

114
121

127
106
11
26
50
92

74
IT8227E-CX_LQFP128_16X16

1
LPC_AD0 10 87 EC_SMB_CK0 预留 RE273 RE274
9 LPC_AD0

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

VFSPI
AVCC

VSTBY(PLL)
LPC_AD1 9 EIO0/LAD0/GPM0(3) SMCLK0/GPF2 88 EC_SMB_DA0 0_0402_5% @
9 LPC_AD1 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 0_0402_5%
LPC_AD2 8 115 EC_SMB_CK1 @
9 LPC_AD2 LPC_AD3 7 EIO2/LAD2/GPM2(3) SM BUS SMCLK1/GPC1 116 EC_SMB_DA1 EC_SMB_CK1 57,58,67
EIO3/LAD3/GPM3(3) SMDAT1/GPC2 EC_SMB_DA1 57,58,67

2
9 LPC_AD3 APU_LPC_RST# 22 117 RE289 2 @ 10_0402_5%
9,14,37 APU_LPC_RST# CLK_PCI_EC 13 ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) 118 APU_THERMTRIP# 7,25
RPE4
9 CLK_PCI_EC LPC_FRAME#_EC ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) LAN_PWR_ON# 42 +3VALW EC_SMB_DA0
RE285 1 @ 2 0_0402_5% 6 1 4
9 LPC_FRAME# ECS#/LFRAME#/GPM5(3) EC_SMB_CK0 2 3

2.2K_0404_4P2R_5%
EC_RTCRST#_ON 126 EC_0.75VALW_EN RE98 1 @ 2 10K_0402_5%
12 EC_RTCRST#_ON GA20/GPB5(3)
RE283 1 @ 2 0_0402_5% 5 85 RE45 1 @ 2 0_0201_5%
9,14 SERIRQ EC_SMI#_R ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 FP_PWR_EN 50
RE438 1 @ 2 0_0402_5% 15 86
8 EC_SMI#
RE439 1 @ 2 0_0402_5% EC_SCI#_R 23 PLTRST#/ECSMI#/GPD4(3) LPC PS2DAT0/TMB1/GPF1 89 FPR_AL0 PBTN_OUT# 8 +3VL_EC +5VALW
9 EC_SCI# ECSCI#/GPD3 PS/2 PS2CLK2/GPF4 EC_0.75VALW_EN
FPR_AL0 50
USB_ON#
WRST# 14 90 RE15 1 2 100K_0402_5%
WRST# PS2DAT2/GPF5 EC_0.75VALW_EN 61

IT8227E-CX
RE56 1 @ 2 0_0402_5% 4
+3VS 9 KBRST# KBRST#/GPB6(3) +3VL_EC
RPE2
2 3 EC_SMB_DA1
RPE3 24 PWR_LED# 1 4 EC_SMB_CK1

LQFP128
EC_SMB_CK2 PWR_LED# 46,50 SUSP# RE18 1 2 100K_0402_5%

@
1 4 PWM0/GPA0 25 PWR_LED1#
2 3 EC_SMB_DA2 PWM1/GPA1 BATT_LOW_LED# PWR_LED1# 50
28 2.2K_0404_4P2R_5% EC_ON_APU
PWM2/GPA2 EC_BKL_EN BATT_LOW_LED# 50 RE14 1 @ 2 100K_0402_5%
BKOFF# 113 29
2.2K_0404_4P2R_5% 38 BKOFF# LID_SW# CRX0/GPC0 PWM3/GPA3 EC_FAN2_PWM EC_BKL_EN 50
123 CIR 30
@ 50 LID_SW# CTX0/TMA0/GPB2(3) SMCLK5/PWM4/GPA4 31 EC_FAN1_PWM EC_FAN2_PWM 44 SUSP# RE19 1 2 100K_0402_5%
SMDAT5/PWM5/GPA5 EC_FAN1_PWM 44
EC_SMB_CK1 1
SYSON RE21 1 2 100K_0402_5%
PWM PAD

@@@@@
H_PROCHOT#_EC EC_SMB_DA1 IT1
80 PAD 1 EC_VR_ON
DAC4/DCD0#/GPJ4(3) EC_FAN1_SPEED IT2 RE296 1 2 100K_0402_5%
119 47 EC_FAN1_SPEED 44 PAD 1
46,60 SYSON USB_ON# 33 DSR0#/GPG6 TACH0A/GPD6(3) 48 1 IT3
PM_SLP_S5# 8,14 PAD SYSON_VDDQ
46 USB_ON# GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) IT4 RE64 1 2 100K_0402_5%
C PAD 1 C
1 2 0_0402_5%
81 120 EC_VBUS_EN IT5 EC_0.75VALW_EN
RE291 @ RE875 1 2 100K_0402_5%
44,59,61 EC_ON DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) EC_VBUS_EN 48
124 SUSP#
EC_TX TMRI1/GPC6(3) SUSP# 51,60 +0.6V_ENABLE
17 RE876 1 @ 2 100K_0402_5%
45,46 EC_TX EC_RX 16 TXD/SOUT0/LPCPD#/GPE6 1
KSI7 PAD

@@@
45,46 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) IT6
KSI6 PAD 1
71 107 1 IT7
WRST# PAD
58 ADP_I ADC5/DCD1#/GPI5(3) GPE4 EC_ON_APU 51 IT8 PM_SLP_S5#
72 UART port 18 CE50 1 2 EMC_NS@ 1000P_0201_50V7-K
8 EC_SYS_PWRGD ADC6/DSR1#/GPI6(3) WAKE UP RI1#/GPD0(3) EC_VR_ON PM_SLP_S3# 8
RE276 2
10_0402_5%73
@ 21
58 PSYS P_APU_OCPL ADC7/CTS1#/GPI7(3) RI2#/GPD1 EC_VR_ON 62 PM_SLP_S3#
62 P_APU_OCPL
35
RTS1#/GPE5 For factory EC flash CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
62 VR_PWRGD RE440 1 @ 2 0_0402_5% VR_PWRGD_R 34
LAN_WAKE# 122 PWM7/RIG1#/GPA7 112 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
EC_SMB_DA2 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 EC_ON_5V 59
7,28,44 EC_SMB_DA2 95 110 ON/OFF ON/OFF 50
EC_SMB_CK2 94 CTX1/SOUT1/GPH2/SMDAT3/ID2 PWRSW/GPB3 111
7,28,44 EC_SMB_CK2 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4 EC_3V/5V_USM 59
109 NOVO# 50
EC_SPI_CLK 105 GPB1 108 ACIN#
EC_SPI_CS1# 101 FSCK GPB0 RE874 1 2 0_0201_5%
EC_SPI_SI 102 FSCE#
EXTERNAL SERIAL FLASH RE326 1
@
@ 2 0_0201_5%
EC_TP_EN#
SMB1_ALERT#
50
44
+3VL EMC Request
EC_SPI_SO 103 FMOSI 66 RE20 1 @ 2 0_0201_5%
FMISO ADC0/GPI0(3) NTC_V1 44
67 RE47 1 FP@ 2 0_0201_5%
FP_LED# ADC1/GPI1(3) PCIE_WAKE# FPR_DELINK_R 50
RE48 2 @ 1 0_0201_5% KSO16 56 68 PCIE_WAKE# 8,42,45
46 FP_LED# 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 BATT_I NTC_V2 44
KSO17
KSO17/SMISO/GPC5(3) ADC3/GPI3(3) BATT_I 58
35 EC_BEEP# 32 70 RE290 2 @ 10_0402_5% RE35 1 @ 2 10K_0201_5% ON/OFF
PWM6/SSCK/GPA6 ADC4/GPI4(3) ADAPTER_ID 57,58
GPG2 100 A/D D/A RE36 1 @ 2 10K_0201_5% BKOFF#
TE4 @ 1 GPG0 125 SSCE0#/GPG2
SSCE1#/GPG0 SPI ENABLE EC_FAN2_SPEED LID_SW#
76 EC_FAN2_SPEED 44 RE38 2 1 100K_0402_5%
KSO0 36 TACH2A/GPJ0 77
KSO0/PD0 TACH2B/GPJ1 EC_LID_OUT# EC_MUTE# 35
KSI[0..7] KSO1 37 78 RE40 1 2 10K_0402_5% BKOFF#
50 KSI[0..7] 38 KSO1/PD1 DAC2/TACH0B/GPJ2(3) 79 0.75VALW_PG EC_LID_OUT# 50
KSO2 0.75VALW_PG 61
KSO3 39 KSO2/PD2 DAC3/TACH1B/GPJ3(3) +3VL_EC
KSO[0..17] KSO3/PD3
50 KSO[0..17] KSO4 40
KSO5 41 KSO4/PD4
KSO6 42 KSO5/PD5
KSO6/PD6 EC_TP_EN# RE877 1 @ 2 100K_0402_5%
KSO7 43
+3VL KSO8 44 KSO7/PD7
KSO8/ACK# EC_ON RE95 1 @ 2 100K_0402_5%
KSO9 45
+3VL_EC KSO10 46 KSO9/BUSY
B
KSO11 51 KSO10/PE 2 BATT_TEMP B
KSO11/ERR# GPJ7 BATT_TEMP 57,58 EC_ON_5V RE301 1 2 100K_0402_5%
GPG2 RE43 1 @ 2 10K_0201_5% KSO12 52 CLOCK 128 AC_PRESENT 8
KSO13 53 KSO12/SLCT GPJ6 EC_1.8VALW_EN RE302 1 2 100K_0402_5%
GPG2 RE44 2 1 10K_0402_5% KSO14 54 KSO13
KSO15 55 KSO14 84 SYSON_VDDQ
KSO15 KBMX EGCLK/GPE3 SYSON_VDDQ 60 EC_ON RE299 1 2 100K_0402_5%
GPG2 RE46 1 @ 2 10K_0201_5% 83 0_0402_5% 2 @ 1 RE297
EGCS#/GPE2 82 EC_1.8VALW_EN 66
0_0402_5% 2 @ 1 RE292
EGAD/GPE1 VGA_AC_DET 28
58
when mirror, GPG2 pull high KSI0
KSI1 59 KSI0/STB# EC_ON_5V RE304 1 @ 2 100K_0402_5%

when no mirror, GPG2 pull low KSI2

KSI3
60
61
KSI1/AFD#
KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0
19
20
NUM_LED# 50
+3VL_EC
EC_1.8VALW_EN RE305 1 @ 2 100K_0402_5%
KSI3/SLIN# SMDAT4/L80LLAT/GPE7 ENBKL 38
KSI4 62 GPIO RE873 1 @ 2 0_0402_5%
KSI4 PCH_FNLK 9,50
KSI5 63 3 RE298 1 @ 2 0_0201_5% 3V_WLAN_EN 45
KSI6 64 KSI5 GPH7 99
KSI6 ID6/GPH6 BATT_CHG_LED# 50

1
KSI7 65 98 RE51 1 FP@ 2 0_0201_5% FPR_SCL 50
KSI7 ID5/GPH5 97 RE5
AGND ID4/GPH4 96 +0.6V_ENABLE 60
10K_0402_5%
VCORE

ID3/GPH3 CAPS_LED# 50
93 RE27 2 @ 1 0_0201_5%
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5

CLKRUN#/ID0/GPH0 EC_RSMRST# 8

2
LAN_WAKE#
LAN_WAKE# 42,45
104
1
27
49
91

75

12

0.1u_0201_10V6K
CE3

1 RE34 1 @ 2 0_0402_5% APU_PROCHOT# 7

58 VR_HOT# +3VL

H_PROCHOT#_EC RE325 1 @ 2 0_0402_5% 1

2

2
BATT_TEMP EMC_NS@ CE16 1 2 100P_0201_25V8J CE14
EC_AGND
1

NOVO# 47P_0201_25V8-J RE42

ACIN# EMC_NS@ CE17 1 2 100P_0201_25V8J RE267 EMC_NS@ 100K_0402_5%
100_0402_5% 2
ON/OFF CE18 1 2 1U_0402_6.3V6K @
@

1
ACIN# RE262 1 @ 2 0_0402_5%
ACIN 58
1 2

1
CE48 QE1 D
EMC_NS@ H_PROCHOT#_EC 2
A 0.01U_0201_10V6K G A
2 DE6
RE308 1 @ 2 ALW_PWRGD_R @1 2 EC_RSMRST#
2N7002KW_SOT323-3 S 59,60 ALW_PWRGD
0_0402_5%
3

@
EC_SPI_CS1# RB521CS-30GT2RA_VMN2-2
RE293 1 @ 2 0_0402_5%
EC_SPI_CS1#_R 9
EC_SPI_SI RE294 2 @ 1 0_0402_5%
SPI_SI_C 9,37
EC_SPI_SO RE295 2 @ 1 0_0402_5%
SPI_SO_C 9,37
Security Classification LC Future Center Secret Data Title
EC_SPI_CLK RE49 2 @ 1 0_0402_5%
SPI_CLK_PCH_C 9,14,37
Issued Date 2015/08/20 Deciphered Date 2018/09/20 EC IT8227LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 49 of 68

5 4 3 2 1
 5 4 3 2 1

+3VL +3VALW

ON/OFF switch ON/OFFBTN#

Novo button NOVO_BTN#
ON/OFFBTN# 46

2
R82 R83

1
100K_0402_5% 100K_0402_5%

1
@

1
R261 1 @ 2 0_0402_5% D1 SW2 D24

1
1

1
AZ5725-01F.R7GR_DFN1006P2X2 EVQP7L01K_4P AZ5123-01F.R7GR_DFN1006P2X2

T3 3
EMC@
SW5

T1
T3BL-03-Q-T-R_4P

2
NOVO# 2

2
D15
49 NOVO#

2
EMC@

2
1 NOVO_BTN#

T2

4 T4
ON/OFF R85 1 @ 2 0_0402_5% 3 @

2
BAT54CW_SOT323-3
+3VALW +3VL

8/31 Update the P/N SN100008W00 wei

2
R111 R114
D D
100K_0402_5% 100K_0402_5% 20200113 change source
@

1
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF
ON/OFF 49 LID switch
PWR_LED1#
J5 1 2 @

SHORT PADS 7/3 PWR LED function under check

1
J6 1 2 @ 1
D29 C1104

1
SHORT PADS AZ5123-01F.R7GR_DFN1006P2X2 U14 100P_0201_25V8J
EMC_NS@ 1
Power LED for L350 C1105
1
GND
3
2
R10418 1 @ 2 LID_SW#
PWR_LED1# 1 2 0.01U_0201_10V6K OUTPUT LID_SW# 49
LED4 R151 1 2 1.5K_0402_5% 0_0402_5%

2
49 PWR_LED1# +5VALW
2 +VCC_LID

2
L-C192WDT-LCFC R264 1 @ 2 2
+3VL VCC
0_0402_5%
LED6 1 2 AH9247-W-7_SC59-3
For EMC CPI fail need add R10418---1204SF
L-C192WDT-LCFC
E15P@

K/B Connector KSI[0..7]

KSI[0..7] 49 KBD symbol: KB Backlight Connector
PWR_CAPS_LED CI26 1 2 100P_0201_25V8J KSO[0..17]
KSO[0..17] 49 1.update to SP010027P00 8/8 wei
EMC_NS@
+3VALW
RI87 1 @ 2 0_0402_5%
PWR_CAPS_LED
JKB1 update BL circuit and need too be confirm conn pin define
0925SF
RI44 1 @ 2 0_0402_5% 1
+3VS CAPS_LED# CAPS_LED#_R 1 LED_KB_C
RI33 1 2 200_0402_1% 2 +5VS JKBL1
49 CAPS_LED# 3 2 0.5A
KSO15 1
KSO10 4 3
LED_KB_C 2 1
KSO11 5 4 1
3 2
KSO14 6 5 D RI37 1 @ 2 0_0603_5%
4 3
KSO13 7 6 RI150 1 @ 2 EC_BKL_EN_R 2 QI6
49 EC_BKL_EN 4
KSO12 8 7 0_0402_5% G PJA138K_SOT23-3 1
Mic_LED#R 8 CI27 5
CI29 1 2 100P_0201_25V8J KSO3 9 S BL@ GND1
9 0.1u_0201_10V6K 6

2
EMC@ KSO6 10 GND2
Mute_LED#R 1 2 100P_0201_25V8J 11 10 3 @
CI28 KSO8 RI19 2
KSO7 12 11 HIGHS_FC1AF040-1201H
EMC@ 100K_0402_5%
CAPS_LED# CI24 1 2 100P_0201_25V8J KSO4 13 12 BL@ ME@
EMC@ KSO2 14 13
14

1
C NUM_LED#_R CI25 1 2 100P_0201_25V8J KSI0 15 C
EMC@ KSO1 16 15
KSO5 17 16
18 17
8/23 PWR LED function under check KSI3
KSI2 19 18
KSO0 20 19
KSI5 21 20
CAPS_LED# NUM_LED#_R Mute_LED#R Mic_LED#R KSI4
KSO9
22
23
21
22
TP/B Connector
KSI6 24 23
24 TP_I2C3_SCL
KSI7 25 TP_I2C3_SDA
KSI1 26 25
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

26
1

KSO16 27 +3VS TP_PWR_R TP_PWR

2
DI7 DI15 DI16 DI17 KSO17 28 27
1

NUM_LED#_R 29 28 DI13
RI34 1 2 200_0402_1% RI149 1 @ 2 0_0603_5% RI22 1 @ 2 0_0603_5%
49 NUM_LED# 1 20_0402_5% 30 29
EMC@ EMC@ EMC@ EMC@ RI86 @
+3VALW 30

0.1u_0201_10V6K

EMC_NS@
RI88 1 @ 2 0_0402_5% 31 1
+3VS FnLK_LED FnLK_LED#R 31
RI54 1 2 300_0402_5% 32
Mute_LED# RI57 1 2 300_0402_5% Mute_LED#R 33 32 36
2

2 33 GND2
Mic_LED# RI58 1 2 300_0402_5% Mic_LED#R 34 35 +3VALW_APU LP2301ALT1G_SOT23-3
34 GND1 2
2

CI19

CI21
QI24 3 1 @

D
100P_0201_25V8J HIGHSTAR_FC8AF341-3201H
1
EMC_NS@ ME@

0.01U_0201_10V6K
1 @ 1
AZC199-02S.R7G_SOT23-3
For EMC CI77

1
G
For EMC

2
0.1u_0201_10V6K
@
2 2

CI78
+3VS +3VS EC_TP_EN# RI148 1 @ 2
follow OD add FnLK LED 49 EC_TP_EN#
100K_0402_5%
TP_PWR

1 1
2

CI79 CI80 1 2 TP_I2C3_SDA

RI40 2.2K_0201_5%
RI81 RI21 0.01U_0201_25V6-K 0.1u_0201_10V6K
FnLK_LED#R @ 10K_0402_5% @ 10K_0402_5% EMC_NS@ @
2 2 RI41 1 2 2.2K_0201_5% TP_I2C3_SCL

1
AZ5123-01F.R7GR_DFN1006P2X2

DI9 RI80 1 @ 2 0_0402_5% Mute_LED# RI20 1 @ 2 0_0402_5% FnLK_LED RI42

EMC@ @
1

D QI5 D
L2N7002KDW1T1G_SOT363-6

Mute _CTL 2 PCH_FNLK 2 10K_0402_5%

1 @
8 Mute _CTL 9,49 PCH_FNLK
1

CI18 G G TP_PWR

2
EC_LID_OUT#_R JTP1
1

1 2 0_0402_5%
100P_50V_J_NPO_0201

100P_0201_25V8J RI38 @
QH9A

1 1
EMC_NS@

49 EC_LID_OUT# TP_INT# 1
EMC@ RI84 S CI82 RI18 S L2N7002KWT1G_SOT323-3 RI39 1 @ 2 0_0402_5% 1
2 2
1

+3VS @ 100K_0402_5% EMC_NS@ @ 100K_0402_5% 3 2

8 PCH_TP_INT#
2

100P_50V_J_NPO_0201 3
CI81

2 2 4
5 4
2

2
2

10K_0201_5% TP_I2C3_SDA 6 5
RI83 6
RI43

TP_I2C3_SCL 7

2
For EMC 10K_0402_5% @ 7

G
8
TP_PWR 8
B Mic_LED# B
TP_PWR
9
1

GND1

2
TP_INT# 2N7002KDWH 10
3 1PCH_TP_INT1#

G
Vth= min 1V, max 2.5V GND2
1 2 0_0402_5% PCH_TP_INT1# 8
S

RI82 @ D
ESD 2KV
HIGHS_FC5AF081-2931H

100P_0201_25V8J

100P_0201_25V8J
QX36

EMC@

EMC@
1 1
3

D 6 1 TP_I2C3_SCL
Mic _CTL 5 @ L2N7002KWT1G_SOT323-3 8,14 TP_I2C3_SCL_R ME@

S
L2N7002KDW1T1G_SOT363-6

8 Mic _CTL

D
G

5
QI23A L2N7002KDW1T1G_SOT363-6
1

G
1 2 2

CI23

CI22
CI83 RI85 S
QH9B
4

EMC_NS@ @ 100K_0402_5%
100P_50V_J_NPO_0201 3 4 TP_I2C3_SDA
2 8,14 TP_I2C3_SDA_R

S
D
2

QI23B L2N7002KDW1T1G_SOT363-6

Add Finger print To be confirm Pin define

AZ5123-01F.R7GR_DFN1006P2X2

BATT_LOW_LED# LED2 1 2 RI51 1 2 470_0402_5% +3VL +3VL FP_PWR

49 BATT_LOW_LED# +3VALW FPR_DELINK_R FPR_AL0 ME@
L-C192JFCT-LCFC_SUPER_AMBER HIGHS_FC5AF081-2931H
1

1
QI7 LP2301ALT1G_SOT-23-3 10
DI5 LED7 1 2 RI63 RI77 RI72 RI73 FP_PWR 9 GND2
1

1/20W_200K_5%_0201 3 1 FP@ 1 FP@ 2 0_0603_5% 100K_0201_5% 47K_0402_5% GND1

S

L-C192JFCT-LCFC_SUPER_AMBER FP@ 1 1 FP@ 8

EMC_NS@

E15P@ CI71 0.1u_0201_10V6K 1

USB20_N3 RI31 1 FP@ 2 0_0402_5% USB20_N3_CONN 7 8
CI74 10 USB20_N3 6 7
2

2
CI73 USB20_P3 RI32 1 FP@ 2 0_0402_5% USB20_P3_CONN
G

10 USB20_P3 5 6
2

FP@ 0.047U_0402_25V_X7R_0402 @ 0.1u_0201_10V6K FPR_DELINK RI145 1 @ 2 0_0201_5%

2

2 2 RI76 9 FPR_DELINK 4 5
RI75 FP@ 49 FPR_DELINK_R
2 3 4
2

1 FP@ 2 1 @ 2 FP_PWR_EN RI46 1 FP@ 2 0_0201_5% FPR_AL0_R

49 FPR_AL0 1 FPR_RESET_R 2 3
1 RI47 FP@ 2 0_0201_5%
9 FPR_RESET 1 FPR_SCL_R 1 2
0_0201_5% @ 0_0201_5% RI74 FP@ 2 0_0201_5%
BATT_CHG_LED# 49 FPR_SCL 1
1

49 BATT_CHG_LED# LED3 1 2 RI52 1 2 1.5K_0402_5% +5VALW CI72

RI64 0.1U_6.3V_K_X5R_0201 USB20_N3_CONN JFP1
AZ5725-01F.R7GR_DFN1006P2X2

L-C192WDT-LCFC_WHITE FP@ 100K_0201_5% 2

USB20_P3_CONN
1

LED8 1 2
12

DI6 QI8
1

L-C192WDT-LCFC_WHITE
3

E15P@
EMC_NS@

49,50 FP_PWR_EN 2 DI14

FP@ DI12 FP_EMC@
FP_PWR +3VS FP_PWR FPR_DELINK_R FPR_DELINK_R
1

FP_EMC@ 10 1
2

SSM3K15AMFV_2-1L1B
NC1 Line-1
3

RI65
2

RI67 FPR_AL0_R 9 2 FPR_AL0_R

100K_0201_5% NC2 Line-2
1 2 FPR_DELINK_R
@
For EMI
AZ5725-01F.R7GR_DFN1006P2X2

A FP@ FPR_RESET_R 7 4 FPR_RESET_R A

NC3 Line-3
2

1/20W_2.2K_5%_0201 DI11
FP_PWR 2 RI70 1 FPR_RESET FPR_SCL_R 6 5 FPR_SCL_R
1

NC4 Line-4
1

@ 1/20W_4.7K_5%_0201
EMC_NS@

+3VL RI71 LI5 EMC_NS@ 3

AZC199-02S.R7G_SOT23-3
GND1
1

USB20_N3 USB20_N3_CONN
1

RI79 1/20W_4.7K_5%_0201 4 3
RI56 1 @ 2 0_0402_5% 1 2 LED5 RI49 1 2 1.5K_0402_5% 330_0402_1% @ 4 3 8
46,49 PWR_LED# +5VALW GND2
1

RI78 FP@
2
2

L-C192WDT-LCFC 100K_0201_5% USB20_P3 1 2 USB20_P3_CONN

1 2 AZ1143-04F-R7G_DFN2510P10E10
2
1

FP@
3 2

DI10 EXC24CH900U_4P
1

AZ5123-01F.R7GR_DFN1006P2X2 D
2

5 QI9B
EMC@

G
6

D
2
2

S
49,50 FP_PWR_EN
4

G Title
FP@ Security Classification LC Future Center Secret Data
2

QI9A
FP@ S L2N7002KDW1T1G_SOT363-6
Issued Date 2015/08/20 Deciphered Date 2018/09/20 KBD/PWR/IO/LED/TP Conn.
1

L2N7002KDW1T1G_SOT363-6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size Document Number
Custom Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 50 of 68
5 4 3 2 Date: 1 Sheet
 A B C D E

+1.8VALW +1.8VS_AON

+5VALW to +5VS +1.8VALW to +1.8VS_AON

+3VALW
+5VLP +5VALW QX4
AON7380_DFN8-5
5VS_CT2 +0.6VS
1
+5VALW V20B+ 1

1000P_0402_50V7K

1
CX1 +3VS 1 2
UX2

1
5 3

CX5
1U_0402_16V6K RX10 RX8

0.1U_0402_25V6
2

1
1 14 1 100K_0402_5% @ 100K_0402_5% RX9 1
IN1_1 OUT1_2

1
Change net to SUSP# for PWR sequence 2 13 CX10 47_0603_5% RX16 @ CX17
IN1_2 OUT1_1 2

1
.1U_0402_10V6-K @ 100K_0402_1% 0.01U_50V_K_X7R_0402 RX18 1

4
SUSP# RX13 1 @ 2 0_0402_5% 3 12 3VS_CT1 @ RX15 OPT@ OPT@ @ 1/10W _47_5%_0603 CX13

CX18
EN1 CT1

2
2 SUSP 47K_0402_5% 2 @ 10U_0603_6.3V6M
39 SUSP

2
4 11 OPT@ RX20 @
VBIAS GND

2
2

1
D 1 2

2
RX14 1 @ 2 0_0402_5% 5 10 5VS_CT2 +5VS 2 SUSP 1K_0402_5%
+5VALW EN2 CT2 3VS_CT1 G QX18 OPT@

3
V1.0 6 9 D

2200P_0402_25V7-K
1 2N7002KW _SOT323-3 QX25B D
IN2_1 OUT2_2

0.1U_0402_25V6
7 8 2 +1.8VS_AON_EN# 5

L2N7002KDW1T1G_SOT363-6
1 SUSP# S @ 1
IN2_2 OUT2_1 1 2 49,51,60 SUSP#

1
CX3

CX4
1 CX9 G QX6 G

1
0.01U_50V_K_X7R_0402 15 .1U_0402_10V6-K 2N7002KW _SOT323-3
2 Thermal Pad

6
CX2 @ S QX25A D OPT@ S RX21

OPT@
@

2
1U_0402_10V6K 2 1 1 2 0_0402_5% 2

L2N7002KDW1T1G_SOT363-6
RX17 @ 430K_0402_1%

CX16
2 G2898KD1U_TDFN14P_2X3 8,28 PXS_PWREN G OPT@ OPT@

1
D
DX12

2
1
RX22 S +1.8VS_AON_EN# 2 QX23

1
2
3 1 2 0_0402_5% RX19 G L2N7002KWT1G_SOT323-3
CX15 100K_0402_5% @
1 OPT@ 0.22U_0402_25V6-K @ S

3
OPT@

2
2 RX23 1 2 49.9K_0402_1%

LBAT54SW T1G_SOT323-3 OPT@

OPT@

AON6324
VDS=30V VGS=+_12V, ID=85A, APU Power control
Rds=2.8mohm @ VGS=10V +3VALW TO +3VALW_APU
+0.75VALW QX3 +0.75VS +/- 5% 2A VGS(th)=2.25V Max
+/- 2% AON6324_DFN8-5 SB00000QP0J LP2301ALT1G 1P SOT-23-3 MAX 0.25A
Load MOS N MOS Id =< -1.6A, Vgs(th) Max >= 1V
1 Vds max 20V, Vgs Max ±8V,Rds(on) >= 150mohm +3VALW 3VS Modify +3VALW 0726 +3VALW_APU
2 1 1
0.01U_6.3V_K_X7R_0201

1 5 3 CX22
CX23 CX21 1U_0402_6.3V6K +3VALW RX24 1 @ 2 0_0603_5%
10U_0603_6.3V6M 10U_0603_6.3V6M
2 2

1
@ 1 1
4

2 CX6 CX7 RX11

0.1U_0201_6.3V6-K 470_0603_5% LP2301ALT1G_SOT23-3
2 @ @ @ +3VL 2
2 2 +3VALW Modify +3VL 726 QX5 3 1 +3VALW_M RX251 @ 2 1/2W_0.01_+-1%_0603_50PPM/C

D
V20B+

1
RX26 @
RX12 RX30 Change RX14 130K to 768K For QX3 GS 0819
RX31 100K_0201_5% @

G
2
+0.75VS_GATE_R 2 @ 1 2 @ 10.75VS_GATE 1 2

0.1U_6.3V_K_X5R_0201
RX27

2
0_0402_5% 0_0402_5% 768K_0402_1% 1 @ 2 EC_ON_APU
1
1

1
1 D D
CX8 RX32 2 QX2 SUSP 2 QX32 RX28 4.7K_0402_5%

1
0.01U_0201_25V6-K 1M_0402_5% G L2N7002KWT1G_SOT323-3 G L2N7002KWT1G_SOT323-3 0_0402_5% D 1 CX19
@ EC_ON_APU 1 2 2 QX31 2
2 49 EC_ON_APU
S S G L2N7002KWT1G_SOT323-3 CX20
2

1
@ 0.1U_6.3V_K_X5R_0201
RX29 S 2
@

3
100K_0201_5%
@

2
@

+1.8VALW +1.8VS

QX33
AON7380_DFN8-5

+5VALW V20B+ 1
2
5 3
1

1
RX33 1
1

100K_0402_1% CX24
4

RX35 CX25 0.01U_0402_25V_X7R_0402

47K_0402_5% 0.1U_25V_K_X5R_0402 2
2

3 RX36 2 3
1 2
2

10K_0402_5%
3

QX34B D
5
L2N7002KDW1T1G_SOT363-6

1
G
1

CX27
6

QX34A D S RX37 0.1U_25V_K_X5R_0402

4

2 2
L2N7002KDW1T1G_SOT363-6

49,51,60 SUSP# 430K_0402_1%

G
2

S
1

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2019/07/02 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 51 of 68
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN
A2 A4 B5

V V
3 +3V_PCH
PU301 PU904

V
B+
BATT BATT V +3VALW
1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU
A3 B4

V V
PM_SLP_S5#
PM_SLP_SUS# 6
CPU_PLTRST# 16

V
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE
+1.35V

V
11 VR_REDY SYSON 7 PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)
+1.5VS_VGA

V
PU901 VR_ON Q31

V
PU601
V

+CPU_CORE

V
+5VS

B B
Q32 +1.05VSP_VGA

V
V
SUSP#,SUSP 9 +3VS PU702
VGA

V
PU602

V
+1.5VS +3VS_VGA

V
Q27
PU502

V
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 52 of 68
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 53 of 68
5 4 3 2 1
 5 4 3 2 1

GPU Thermal Holex2 Close to RJ45 DC-IN x2

CPU Thermal Holex3 WLAN Standoff

H10 H11
H1 H2
H3 HOLEA HOLEA
D HOLEA HOLEA D
HOLEA
PCB Fedical Mark PAD

1
1

1
FD1 FD2 FD3 FD4 FD5 FD6
PAD_D2P4 PAD_D3P0X2P7
PAD_D2P4 PAD_D2P4 PAD_D2P4
1

1
H4 H5 H6 H7 H8
HOLEA HOLEA HOLEA HOLEA HOLEA

1
PAD_CT7P0B6P0D3P0 PAD_CT7P0B6P0D3P0 PAD_CT7P0B6P0D3P0 PAD_D2P7 PAD_CT7P0B6P0D3P0

H16 H17 H18

H9 H12 H15 H20 H13 H19
C HOLEA HOLEA HOLEA C
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
1

1
PAD_C2P7D2P7N PAD_C7P0D2P8 PAD_C7P0D3P3 PAD_C6P0D2P4 PAD_CT7P0B6P0D3P0 PAD_CT7P0B6P0D2P8 PAD_C7P0D2P8 PAD_O9P5X7D5P3X2P8 PAD_CT7P0B6P0D3P0
20200115 add

Close to Audio jack

follow layout list update 20190819 weiwei

SH7 ME@ SH8 ME@ SH9 ME@

B 1 1 1 B
1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SH10 ME@ SH11 ME@ SH12 ME@

1 1 1
1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

USB3.0 Shielding
DDR4 Shielding
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 54 of 68

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2018/09/20 XXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. L350 A+N
Date: Saturday, May 09, 2020 Sheet 55 of 68
5 4 3 2 1
 5 4 3 2 1

V20B+ +5VLP/ 100mA

Richtek
Adaptor RT6585C +5VALW/8A
D
EC_ON_5V EN1 Switch Mode D

FOR SYS ALW_PWRGD

135W/20V PGOOD
Page 68
EC_ON EN2 +3VLP/ 100mA

+3VALW/ 8A GMT
G9661 +2.5V/600mA
SYSON EN LDO
FOR DDR PGOOD

Richtek Page 69
+1.2V/10A
RT8231
Switch Mode +0.6VS/1A
SYSON S5 FOR DDR
SUSP# S3 Page 69 PGOOD

TI Silergy
BQ24780SRUYR SY8286 +0.75VALW/ 6A
C
Battery Charger Converter Anpec C

Switch Mode EC_0.75VALW_EN EN FOR PCH PGOOD

APL5930CKAI +1.0VGS/2A
Page 61
Page 58 1V0_MAIN_EN EN LDO
FOR GPU PGOOD

AOS Page 78
AOZ2767 FBVDDQ/ 35A
Switch Mode
VRAM_VDDQ_ADJ EN PGOOD
FOR GPU
Page 68
SMBus

Silergy
SY8286 1.8VALW/ 6A
Converter
EC_1.8VALW_EN EN FOR CPU/GPU PGOOD
Page 70

RICHTEK VDDCR_VDD/58A/96A
LV3667BY
B
Switch Mode VDDCR_SOC/15A/20A B

FOR CPU Core

Page 61
CPUCORE_ON EN PGOOD
CPU_PWRGD

Battery ON
Li-ion NCP81611 NVVDD/45A/120A
3S1P/57WH Switch Mode
NVVDD_EN EN FOR GPU NVVDD
PGOOD NVVDD_PWRGD
Page 71

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 56 of 68

5 4 3 2 1
 5 4 3 2 1

PL201 EMC@
HCB2012KF-121T50_0805
1 2
VIN
JDCIN1
PL202 EMC@
D PF201 D
1 HCB2012KF-121T50_0805
GND_1 2 APDIN 1 2 APDIN_PF 1 2
POWER_1 3
DETECT(ID) 4 12A_24V_F1206HB12V024T/M
POWER_2 5
GND_2 6

0.1U_0402_25V6
ADAPTER_ID 49,58

0.1U_0402_25V6
1000P_0402_50V7K

1000P_0402_50V7K
GND_3

EMC@
7

PC201 EMC@

EMC@
GND_4

1
PC203
PC202
HIGHS_PJSSS56-B4000-1H +3VL

2
ME@

EMC@
PC204

2
PR201
0_0402_5%

1
PR203
47K_0402_1%
0_0402_5%
PR202
PD201 VCCRTC
2 1 VCCRTC_D_R 1 2 VCCRTC_D 3
RTC_VCC @
@ 1

1 2 RTC_VCC_R 2
For 15"

1
PC205
JRTC1
PR204
BAT54CW_SOT323-3 1U_0402_10V6K
1K_0603_5% @

2
1
ME@ 1 2
ALLTO_C51126-112Z9-C 2 3
JBATT1 GND1
1
VMB BATT+ GND2
4
1 2 PL204 EMC@
2 3 HCB2012KF-121T50_0805 ME@
3 4 1 2 HIGHS_WS33020-S0351-HF
4 5 EC_SMCA
5 6 EC_SMDA
C C
6 7 PL205 EMC@
7 8 HCB2012KF-121T50_0805
8 9
3

1
PC206 1 2 PC207
9 10 1000P_0402_50V7K 0.01U_0402_25V7K
10 11
11 12
EMC@ EMC@

2
12 13
GND1 14
1

100_0402_1%

GND2 15
PR205

GND3 16
1

100_0402_1%

GND4
PR206

2
2

PD203 EC_SMB_CK1 49,58,67

AZC199-02S.R7G_SOT23-3
EMC_NS@
EC_SMB_DA1 49,58,67

PR207 1 2 100K_0402_1%
+3VALW

BATT_TEMP_IN 1 2
BATT_TEMP 49,58 A/D
PR208
10K_0402_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-DCIN /BATT/ RTC charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size Document Number
L350 A+N Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 57 of 68
5 4 3 2 1
 5 4 3 2 1

PQ101 PQ102
AONS32304_DFN8-5 AONS32314_DFN8-5
P2 V20B+
VIN 1 1 P3 PR101
0.01_1206_1%
20190815 EMC
2 2 Close to PR101
5 3 3 5 1 4

2 3

1
1

EMC@

EMC@

1
0.01U_0402_25V7K

0.01U_0402_25V7K
4

4
PC141 PC140 PC142
D 4700P_0402_50V7K D

1
2200P_0402_50V7K

PC103

PC104
0.01U_0402_25V7K

2
EMC@

1
PC102 EMC@ 2 EMC@

2
PC101 0.022U_0402_25V7K

2
470P_0402_50V7K PR102
PQ103
2
4.7_0603_5%

5
AONS32314_DFN8-5

2
780s_ACDRV_R
1 2
PR127
PC105 780s_BATDRV 1 2 780s_BATDRV_R 4

1
PC106 0.1U_0402_25V6 PC107
0.1U_0402_25V6 0.1U_0402_25V6
1/16W_4.02K_1%_0402

BQ24780_ACN
BQ24780_ACP
2

3
2
1
1
PR103
499K_0402_1% PC108
VIN BATT+ 0.01U_0402_25V7K

2
2
@
PD101

3
BAT54CW_SOT323-3
V20B+

0.1U_0402_25V6

10U_0805_25V6K
10U_0805_25V6K
1

2
EMC@

PC110

PC111
VIN
1

PC109
4.02K_0603_1%

4.02K_0603_1%

1
780s_VCC_R
PR104

PR105

BQ24780S_VDD

1
1

5
PR107
2

1
PR108 PR106 PC112 10_1206_5% PQ104
6.49K_0402_1% 42.2K_0402_1% 1U_0603_25V6K

ACN
ACP
C 1 2 AON6380_DFN8-5 C

2
1 2 780s_VCC 28 24 1 2
VCC REGN

2
2.2U_0603_10V6-K PC113 4
1 2 780s_ACDET 6 PC115
PC114 ACDET 0.047U_0603_16V7K
0.01U_0402_25V7K 25 780s_BS
1 2780s_BS_R 2 1
BTST PR109 PR110 BATT+

3
2
1
2.2_0603_5% 2.2UH_PCMB063T-2R2MS_8A_20% 0.01_1206_1%
780s_CMSRC 3 26 780s_HG PL101
CMSRC HIDRV 1 2 1 4
780s_ACDRV 4
ACDRV 2 3

1
27 780s_LX

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PHASE PQ105 PR112

EMC@
1

1
1 2 0_0402_5% 780s_ACOK 5
PR111 @ 4.7_0805_5%

PC118
PC116

PC117

PC139

PC143
49 ACIN ACOK PU101 AON6380_DFN8-5 EMC@
1 2 0_0402_5% 780s_SDA 11
PR113 @ SDA

2
49,57 EC_SMB_DA1 23 780s_LG 4
LODRV 780s_SN
1 2 0_0402_5% 780s_SCL 12 22
PR114 @ SCL GND

1
49,57 EC_SMB_CK1 PC119
1000P_0402_50V9-J

3
2
1
1 2 0_0402_5% 780s_IADP 7 29
49 ADP_I
PR115 @ EMC@

0.1U_0402_25V6

0.1U_0402_25V6
IADP PAD

1
1 2 0_0402_5% 780s_IDCHG 8 18 780s_BATDRV
PR116 @

PC120

PC121
49 BATT_I IDCHG BATDRV
1 2 0_0402_5% 780s_PMON 9
49 PSYS
PR117 @ PMON

2
17 780s_BATSRC 1 2 780s_BATSRC_R
BATSRC PR118 10_0603_5%
20 780s_SRP 1 2 780s_SRP_R
10 SRP PR119 10_0603_5%
49 VR_HOT#
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

PROCHOT#
1

1
1

PR120 13 PC123
10K_0402_1% CMPIN
0.1U_0402_25V6

BATPRES#

2
14
TB_STAT#
PC122

PC124

PC125

CMPOUT
2

19 780s_SRN 1 2 780s_SRN_R
SRN
2

780s_ILIM 21 PR121 10_0603_5%

ILIM
B B
2

PR122
780s_TB# 16

15

@ 0_0402_5% BQ24780SRUYR_QFN28_4X4
1

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP 49,57
PR123 PR124
1

143K_0402_1% 32.4K_0402_1%
1

PR125
+3VALW PC126 100K_0402_1%
0.1U_0402_25V6 V20B+
2

IchargeLIM=7A
IDischargeLIM=10A
1

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K
PR126

1
750_0603_1%

PC127

PC128

PC129

PC130

PC131

PC132

PC133

PC134

PC135

PC136
2

2
ADAPTER_ID 49,57
680P_0402_50V7K

AZ5123-01F.R7GR_DFN1006P2X2

@
0.1U_0402_25V6

1
1

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC137

PC138

PD102

@
2

2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Charger-BQ24780SRUYR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Custom
Document Number
L350 A+N Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 58 of 68
5 4 3 2 1
 5 4 3 2 1

PJ2001
+5VLP 2 1
+3VLP 2 1 +3VL 1A
JUMP_43X39

62K_0402_1%

@
4.7U_0603_6.3V6K
+3VALW_VIN +3VALW_VIN

2
56K_0402_1%

0_0603_5%
D
V20B+ V20B+ D

PC2002

PR2003
+3VLP

@
PR2002
PJ2002
PJ2003

2
1 2
1 2 +3VALW Vout=5V+-5%

1
+5VALW_VIN 2 1
2 1
Vset=5.06V+-1.5%

+3V5V_CS22

+3V5V_CS12
2
PC2001

PR2001
0.1U_0402_25V7-K
JUMP_43X79

0.1U_0402_25V6

2
+5V_LDO
10U_0805_25V6K

10U_0805_25V6K
JUMP_43X118 FSW=400KHz

2
EMC_NS@

PC2004
@
PC2003

PC2005

PC2006

10U_0805_25V6K

10U_0805_25V6K
1

0.1U_0402_25V6
TDC=8A OCP=14A

@
PR2004

PC2007

PC2008
4.7U_0603_6.3V6K

PC2009
100K_0402_1%
OVP=Vout*113%

EMC_NS@
Vout=3.3V+-5%

2
UVP=Vout*52%

12

13
Vset=3.3V+-1.5%

2
5

3
PU2001 PQ2002

5
5
FSW=475KHz

AONR32340C_DFN8-5

LDO5

LDO3
CS2

CS1
VIN

D
21 AONR32340C_DFN8-5

PQ2001

D
7 GND
TDC=8A OCP=14A 49,60 ALW_PWRGD PGOOD

+3VALW OVP=Vout*113% 4 +3V_UG 10 UGATE1

16 +5V_UG 4
G
PR2006 PC2011
UVP=Vout*52% G PC2010 PR2005 UGATE2 2.2_0603_5% 0.1U_0603_25V7K
+5VALW

S3
S2
S1
0.1U_0603_25V7K 2.2_0603_5% RT6585CGQW_WQFN20_3X3 17 +5V_BST1 2 1 2 1.5UH_PCMB063T-1R5MS_10A_20%

S1
S2
S3
1.5UH_PCMB063T-1R5MS_10A_20% 1 2 1 2 +3V_BST9 BOOT1
BOOT2 PL2002 PJ2005

3
2
1
PJ2004 PL2001

1
2
3
18 +5V_LX 1 2 +5VALW_P 2 1
2 1 +3VALWP 1 2 +3V_LX 8 PHASE1 2 1
2 1 PHASE2
8A

22U_0603_6.3V6-M
15 +5V_LG JUMP_43X118

5
330P_0402_50V7K

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

AONR32340C_DFN8-5
JUMP_43X118 +3V_LG 11 LGATE1

@
680K_0402_1%

D
LGATE2

SKIPSEL
+5VALW_P

1
14 + PC2037
@

PQ2003
PR2009

PC2025

PC2026

PC2028

PC2036
BYP1

1
PR2008 4.7_0805_5%

PC2012

PR2007
220U_B2_6.3VM_R25M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
220U_6.3V_M

EN2

EN1
FB2

FB1
1 4.7_0805_5% EMC_NS@

2
2

0.1U_0402_25V6
1

4 4
PC2014

PC2015

PC2016

PC2017

PC2018

PC2021

PR2011
EMC_NS@ G G

0.1U_0402_25V6
+

@
PC2013

13K_0402_1%

PC2023 @
2

20

19

2
2

2
PC2022

S1
S2
S3

S3
S2
S1
2

2
AONR32340C_DFN8-5 @

PR2010
@ @ @
2 PQ2004
@

1
2
3

3
2
1

1
C C

1
1
PC2029 PC2030

1
1000P_0402_50V9-J
1000P_0402_50V9-J +3VLP

1
1
EMC_NS@

PC2031

30K_0402_1%
EMC_NS@

2
0.01U_0402_25V7K

2
+3V_FB

2
PR2022
+5V_FB
2
100K_0402_1% @
PR2014
1 2 EC_ON_3V_R
PR2013
44,49 EC_ON @

1
20K_0402_1% PR2020
0_0402_5% +3V5V_USM 1 2 0_0402_5%
@

0.1U_0402_10V7K
EC_3V/5V_USM 49
1

1
@ PC2032

1
Vout=2*(1+PR2010/PR2013)
=2*(1+13K/20K) PR2021
EC_3V/5V_USM--- H: DEM L: USM

2
=2*1.65=3.3V 200_0402_1% PR2018 Vout=2*(1+PR2011/PR2018)
@
power on/S0/S3/S4: L 19.6K_0402_1% =2*(1+30K/19.6K)
S5: H =2*2.53=5.06V

2
PR2015
EC_ON_5V_R 1 2
@ EC_ON_5V 49
0_0402_5%

0.1U_0402_10V7K
1

@ PC2033
2
B B
PU2001 change PN to SA0000AK100, S IC RT6585CGQW need link CIS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-3V/5V-RT6585BGQW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom L350 A+N 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 59 of 68
5 4 3 2 1
 A B C D

V20B+
@
+1.2V_VIN 2
PJ2701
2 1
1 1.5A Vout=1.2V±5%
@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
JUMP_43X79 Vset=1.212V±2%

1
PC2702

PC2703
PC2701
+1.2VP TDC=12A

2
Vout=0.6V±5% Vref=0.6V
1A

5
OCP=1.5A PR2701
PC2704
0.1U_25V_K_X7R_0402 PQ2701
OVP=(1.25~1.35)*Vref
2.2_0603_5%
VTT=1/2VDDQ PC2705 1 2 +1.2V_BST_R 1 2
AON6380_DFN8-5 UVP=(0.7~0.8)*Vref
10U_0603_6.3V6M
1
1 2 PR2702 2 1 0_0603_5% +1.2V_UG_R 4
Fsw=500K 1

@
+0.6VSP OCP=18A
+1.2V 12A
PL2701
PJ2705

3
2
1
0.68UH_PCMB063T-R68MS_16A_20%
1A 1 2 +1.2VP 2 1

+1.2V_BST
2 1

+1.2V_UG

+1.2V_LX

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

JUMP_43X118

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
@
PC2706

PR2703

PC2707

PC2708

PC2709

PC2710

PC2711

PC2714
PC2712

PC2713
5
0_0805_5%

19

18

17

16
20
2

2
PQ2702
AON6324_DFN8-5 @

UGATE

PHASE
VLDOIN

BOOT
VTT

2
21
PAD
+1.2V_LG +1.2V_SN
@ @
1
VTTGND LGATE
15 4 1A
Rcs=Iocp x Rdson x10 /5uA
2 14
VTTSNS PGND

1
PR2704
PC2715 +0.6VSP +0.6VS

3
2
1
3
PU2701
13 +1.2V_CS 1 2 +5VALW 1000P_0402_50V9-J PR440 PLACED CLOSE TO DIMM PJ2702
@
GND CS

2
RT8231AGQW_WQFN20_3X3 PR2705 2 1
1/16W_127K_1%_0402 5.1_0603_5% 2 1
VTTREFP 4 12 +1.2V_VDD 1 2
VTTREF VDD JUMP_43X79
+3VALW
1

PR2707
PC2716
+1.2VP 5 11 +1.2V_VID 1 2 @ +1.2VP
1U_0402_6.3V6K VDDQ VID

1
PC2717
PGOOD

100K_0402_1%
2

1U_0402_6.3V6K
TON

0.01U_0402_25V7K
FB

S3

S5

2
1 PR2708 2

1
PR2706 8.1 voltage console circuit for memory OC function

PC2718
100K_0402_1%
6

10

0_0402_5%

2
+1.2V_FB

+1.2V_TON

+1.2V_PG

1
2 PR2709 VDDQ_FB_R 2

100K_0402_1%
@
+1.2V_S3

+1.2V_S5

1 2 +3VALW

1
1
PC2719 PR2710
PR2711 1 2 499K_0402_1% +1.2V_VIN
470P_0402_50V7K 1K_0402_1% Vout=0.75*(1+PR2710/PR2015)
=0.75*(1+1K/1.65K)

2
=0.75*1.606=1.205V

2
PR2714
1 2 +1.2V_S3 +1.2V_FB
49 +0.6V_ENABLE
0.1U_0402_10V7K

0_0402_5% @
1

1
PC2726

49,51 SUSP# 1 @ 2 @ PR2715

1.65K_0402_1%
2

PR2716 0_0402_5%

2
PR2719
1 2 +1.2V_S5
49 SYSON_VDDQ @
0_0402_5%
1

PC2727
0.1U_0402_10V7K
@
2

+3VALW

+5VALW
3 3

PR2723
100K_0402_5%
@
1
1

PC2728
1U_0402_6.3V6K
+3VALW PU2703
2

+2.5V_POK
+2.5V
0.5A @ 10
VPP POK
5
PJ2703 @
2 1 +2.5V_VIN 7
2 1 VIN1 2 +2.5V_P 2
PJ2704
1
0.5A
4.7U_0603_6.3V6K

VO1 2 1
4.7U_0603_6.3V6K

8
JUMP_43X39 VIN2
1

3
PC2729

PC2730

VO2 JUMP_43X39
1

1
PC2731 @

22U_0603_6.3V6-M
2

22U_0603_6.3V6-M
6 PR2724 220P_0402_50V7K @
VEN

1
PR2725 @ 39K_0402_1%
@ 0_0402_5% Vout=2.5V±5%

PC2732

PC2733
2

1 2
49,59 ALW_PWRGD

2
+2.5V_FB
1
NC1 ADJ
4
Vset=2.514V±3%
PR2726 9
NC2 THERMAL_PAD
11 Imax=0.5A
1

1 2 +2.5V_EN
46,49 SYSON @
0_0402_5%
PR2727
18.2K_0402_1%
Vref=0.8V(+-1.5%)
G9661MRE1U_TDFN10_3X3
1

PC2734
Ilimit=3A
2

.1U_0402_10V6-K
2

Vout=0.8*(1+PR2724/PR2727)
=0.8*(1+39K/18.2K)
=0.8*3.143=2.514V

4
Address 0X6A 0X68 0X66 0X64 0X62 0X60 4

TOP R (Kohm) OPEN 3.9 3 2.3 1.3 10

STATE EN1 EN2 VDDQ VTT_REFP VTT
BOT R (Kohm) 10 1.3 2.3 3 3.9 OPEN
S0 Hi Hi On On On
Bus_sel Volt
Off (% of VCC) 0% 25% 40% 60% 75% 100%
S3 Lo Hi On On (Hi-Z)
Security Classification LC Future Center Secret Data Title
S4/S5 Lo Lo Off Off Off Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-1.2V/0.6VS/2.5V-RT8231A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

Note: S3 - sleep ; S5 - power off DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom L350 A+N Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 60 of 68
A B C D
 A B C D

1 1

+3VALW

1
PR2401
10K_0402_5%

2
0.75VALW_PG_R
PR2402
1 @ 2
V20B+ 0.75VALW_PG 49
0_0402_5%
PJ2401
1A
PU2401 +0.75VALW
2 1 0.75VALW_VIN 5 9
2 1 4 IN1 PG 1 0.75VALW_BS 1 2
0.1U_25V_K_X7R_0402

3 IN2 BS PC2401 PL2401 @

10U_0805_25V6K

10U_0805_25V6K
EMC_NS@

2 IN3
JUMP_43X39
1

2 0.1U_25V_K_X7R_0402 1UH_PCMB053T-1R0MS_7A_20% PJ2402 5A

PC2402

PC2403

PC2404
IN4 6 0.75VALW_LX 1 2 0.75VALW_P 2 1
@

7 LX1 19 2 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
GND1 LX2
2

1
8 20 JUMP_43X79
18 GND2 LX3 PR2403 PC2405
2
GND3 1 1 1 1 2

21 4.7_0603_5% 330P_0402_50V8J
GND4

2
PR2404 @ 14 0.75VALW_FB EMC_NS@

PC2406

PC2407

PC2408

PC2409
0.75V_FB_R3
FB

1
100K_0402_5%

2
+3VALW 1 2 0.75VLAW_ILMT 13 12 PR2405 2 2 2 2

VCCIO_SN
0.75VALW_EN 11 ILMT NC3 10 21K_0402_1%
EN NC1 16
+3VALW
NC2
1

@ 15
BYP

2
1

2
17 0.75VALW_VCC
PR2406
1M_0402_5% VCC
PC2410
1500P_0402_50V7-K
Vout=0.75V±37.5mV

4.7U_0603_6.3V6K
1

PC2411 SY8286RAC_QFN20_3X3
EMC_NS@ PR2407 Vset=0.752V±1.46%

2
1
1K_0402_1%

PC2412
2

4.7U_0603_6.3V6K Vref=0.6V
2

1
2
TDC=5A
OCP=9.5A TYP=10.5A MAX 11.5A

1
ILMT=0 OCP=6.5A PR2410 OVP=(1.15~1.25)*Vout
ILMT=floating OCP=9.5A 78.7K_0402_1%
UVP=(0.6~0.7)*Vout
ILMT=1 OCP=12.5A

2
Vout=0.6*(1+PR2405/PR2410)
Fsw=500Khz min=425K max=575K
PR2413 =0.6*(1+21K/78.7K)
49 EC_0.75VALW_EN 1 @ 2 0_0402_5%
=0.6*1.266=0.76V

3
44,49 EC_ON 1 2 0.75VALW_EN 3

PR2414
0.1U_25V_K_X7R_0402

1K_0402_1%
1M_0402_5%

2
PC2413

PR2416

1
1
@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-VCCIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Document Number
L350 A+N Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 61 of 68
A B C D
 5 4 3 2 1

+5VALW
+5VALW V20B+

0.1U_25V_K_X7R_0402

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
2.2U_10V_K_X5R_0402

2
PR3000 PC3000

EMC@
RT3667_VCC 1 1 1
1 2 1 2 PR3001

PC3004

PC3001

PC3002
10_0603_5% 2.2_0603_5%
PC3003 0.1U_25V_K_X5R_0402
2 1 2 2 2

28

1
PU3000 2.2_0603_5% 0.22U_25V_K_X5R_0402
PQ3002
PC3005

VCC
PR3004 AON6982_DFN8-7

2
2 1 PC3006
PR3003 300K_0402_1% 1U_0402_10V6K 4 VDD_BST1_R
2 1VDD_BST1
1 2 1
50 RT3667_PWM1 2 1 VDD_VCC1 8 BOOT
PR3002 change to 787K for 3 cell battery PWM1 VCC 3 VDD_UG1 PL3000
1 2 RT3667_DVD 46 51 RT3667_PWM2 RT3667_PWM1 5 UGATE
V20B+ 1/16W_787K_1%_0402 DVD PWM2 PR3005 PWM 2 VDD_PH1 7 VDD_PH1
0.15UH_PCME064T-R15MS0R665 36A_20%
1 2
VDDCR_VDD:TDC=58A EDC=96A
PR3002
PWM3
52 RT3667_PWM3 1 @ 2VDD_EN11
EN
PHASE
7 VDD_LG1 6
+VDDCR_VDD

EMC_NS@ EMC_NS@
@ @
RT3667_PWM4 LGATE

2
PR3006 1/16W_40.2_1%_0402 100K_0402_1% 1 0_0402_5% 6

0_0805_5%
1 2 VDD_TON_R 2 1 RT3667_TONSET 2 PWM4 GND1 9
V20B+ PJ3000 PJ3001

PR3008
TONSET GND2
JUMPER JUMPER

1
1 2 PR3007 PU3001

3
4
5
RT9610CGQW_WDFN8_2X2 VDD_ISEN1P_R

2
PC3007 0.1U_25V_K_X5R_0402 6 VDDCR_VDD_ISEN1P
ISEN1P VDD_SNB1

1
PR3009

1000P_0402_50V7K
D 5 VDD_ISEN1N_R
2 1 VDDCR_VDD_ISEN1N PR3010 D
PR3011 1/16W_40.2_1%_0402 100K_0402_1% ISEN1N 2.74K_0402_1%
2 SOC_TON_R 2 RT3667_TONSETA

1
1 1 40 1 2
V20B+ 1/16W_536_1%_0402

PC3009
TONSETA
PC3011

2
1 2 PR3012 PC3008 0.1U_25V_K_X5R_0402

2
1 2
PC3010 0.1U_25V_K_X5R_0402 3 VDDCR_VDD_ISEN2P
ISEN2P PR3013 0.1U_25V_K_X5R_0402
4 VDD_ISEN2N_R
2 1 VDDCR_VDD_ISEN2N
330P_0402_50V7K 56P_50V_J_NPO_0402 ISEN2N 1/16W_536_1%_0402
PC3012 PC3013 1 2
1 2 1 2 VDDCR_SOC_COMP 30 VDDCR_VDD_ISEN1P
COMPA PC3014 0.1U_25V_K_X5R_0402

PR3014 10K_0402_1% PR3016 7 VDDCR_VDD_ISEN3P

1 2 1 PR3015 2 1 2 ISEN3P PR3017
7 VDDCR_SOC_VCC_SENSE VDD_ISEN3N_R VDDCR_VDD_ISEN3N VDDCR_VDD_ISEN1N
8 2 1
1/16W_10_1%_0402 1/16W 47.5K 1% 0402 ISEN3N
VDDCR_SOC_FB 31 1/16W_536_1%_0402 1 2
FBA

@
PR3018 PC3015 0.1U_25V_K_X5R_0402
VDDCR_SOC_VCC_SENSE_R
+VDDCR_SOC 1 2 32
VSENA VDDCR_VDD_ISEN4P
PR3019 10K_0402_1%
10 2 1
100_0402_1% ISEN4P
9 VDD_ISEN4N_R
2
PR3020
1 VDDCR_VDD_ISEN4N 2 1
+5VALW
+5VALW
V20B+

0.1U_25V_K_X7R_0402

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
RT3667_VCC PR3022 2 1 10K_0402_1% ISEN4N PR3021 10K_0402_1%
1 2

@
1/16W_536_1%_0402
PR3023 1 2 10K_0402_1% VDDCR_SOC_OFS 24

EMC@
OFSA 1 1 1
PC3016 0.1U_25V_K_X5R_0402

PC3017

PC3018

PC3019
RT3667_VCC PR3024 2 1 10K_0402_1% VDDCR_VDD_OFS 23

@
OFS RT3667_PWMA1

2
42
PR3026 1 2 10K_0402_1% PWMA1 PR3025 2 2 2
41 2.2_0603_5%
PWMA2
PR3027 124K_0402_1% PR3028 1K_0402_1%
RT3667_VCC 1 VDD_SET1_R1

1
2 2 1 2.2_0603_5% 0.22U_25V_K_X5R_0402
36 VDDCR_SOC_ISEN1P PC3022 PQ3004
VDD_SET1_R2 VDD_SET1 ISENA1P PR3032 AON6982_DFN8-7

2
2 1 2 1 25 PC3020
PR3030 1/16W_1.78K_1%_0402 SET1 35 SOC_ISEN1N_R
2 1 VDDCR_SOC_ISEN1N 1U_0402_10V6K 4 VDD_BST2_R
2 1VDD_BST2
1 2 1
PR3029 49.9K_0402_1% ISENA1N PR3031 1/16W_732_1%_0402 2 1 VDD_VCC2 8 BOOT
1 2 VCC 3 VDD_UG2 PL3001
RT3667_PWM2 5 UGATE 0.15UH_PCME064T-R15MS0R665 36A_20%
PR3033 124K_0402_1% PR3034 1K_0402_1% PC3021 0.1U_25V_K_X5R_0402 PR3035 PWM 2 VDD_PH2 7 VDD_PH2 1 2
RT3667_VCC 1 2 VDD_SET2_R1
2 1 VDD_SET2 26
SET2 ISENA2P
33
PR3038
1 @ 2 VDD_EN21
EN
PHASE
7 VDD_LG2 6
+VDDCR_VDD

EMC_NS@ EMC_NS@
PR3036 @ @
2 VDD_SET2_R2 5VALW_R2 2 LGATE

2
1 1 @ 2 34 1 0_0402_5% 6

0_0805_5%
ISENA2N +5VALW GND1 9 PJ3002 PJ3003

PR3039
0_0402_5% PR3037 1/16W_470_1%_0402 GND2
10K_0402_1% JUMPER JUMPER

1
PU3002

3
4
5
PR3040 RT9610CGQW_WDFN8_2X2 VDD_ISEN2P_R
RT3667_IBIAS

2
1 2 29
IBIAS

1
56P_50V_J_NPO_0402 220P_0402_50V7K

1000P_0402_50V7K
100K_0402_1% PC3023 PC3024 VDD_SNB2 PR3041
PC3025 1U_0402_6.3V6K 13 VDDCR_VDD_COMP 1 2 1 2 2.74K_0402_1%
COMP

1
2 1

PC3026
PC3027

2
PR3042 2.2_0603_5% PR3044 PR3043
RT3667_VDDIO 18

2
1 2 1 2 1 2 1 2
+1.8VALW VDDIO
1 2 29.4K_0402_1% 10K_0402_1% 0.1U_25V_K_X5R_0402
+1.8VS 12 VDDCR_VDD_FB
FB
@
PR3045 2.2_0603_5%

VDDCR_VDD_ISEN2P
PR3046 1 2 RT3667_EN 37 PR3047 1 2 40.2_0402_1%
49 EC_VR_ON @ 0_0402_5%
EN +VDDCR_VDD
1 2 11 VDDCR_VCC_SENSE_R PR3048 1 2 1/16W_10_1%_0402
VSEN VDDCR_VCC_SENSE 7
PC3028 0.1U_10V_K_X5R_0402 VDDCR_VDD_ISEN2N
C C

2
PC3029
PR3049 1 2 RT3667_PWROK 19
7 APU_PWROK @ PWROK
1000P_0402_50V7K
VDDCR_VSS_SENSE_R

1
0_0402_5% 14 PR3050 1 2 1/16W_10_1%_0402
2 1 RT3667_PG 39 RGND VDDCR_VSS_SENSE 7
+3VS PR3051 10K_0402_1% PGOOD PR3052 1 2 40.2_0402_1%

49 VR_PWRGD
38
PGOODA +5VALW
V20B+

0.1U_25V_K_X7R_0402

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
@

PR3053 10K_0402_1% PH3000 PR3054

1 2 RT3667_OCPL 27 2 1 SOC_IMON_R1 2 1
+3VS OCP_L 6.49K_0402_1%

EMC@
1 1 1
1 2 PR3056 100K_0402_1%_NCP15WF104F03RC

PC3030

PC3031

PC3032
49 P_APU_OCPL VDDCR_SOC_IMON SOC_IMON_R2
17 2 1 2 1
IMONA

2
@

PR3055 0_0402_5% 1/16W_23.2K_1%_0402 PR3057 20K_0402_1%

20 PR3058 2 2 2
7 APU_SVC SVC PH3001 PR3060 2.2_0603_5%
21 15 VDDCR_VDD_IMON 2 1 2 VDD_IMON_R1 2
1 1
7 APU_SVD SVD IMON 13.7K_0402_1%

1
22 PR3059 100K_0402_1%_NCP15WF104F03RC 2.2_0603_5% 0.22U_25V_K_X5R_0402
7 APU_SVT SVT VDD_IMON_R2 PQ3006
4.87K_0402_1% 2 1 PC3036
PR3062 AON6982_DFN8-7

2
2 2 2 43 PC3037
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

44 NC1 PR3061 1/16W_12.7K_1%_0402 1U_0402_10V6K 4 VDD_BST3_R

2 1VDD_BST3
1 2 1
PC3034

PC3035

45 NC2 2 1 VDD_VCC3 8 BOOT

PC3033

47 NC3 16 RT3667_V064/SET3 2 1 VDD_SET3_R12 1 RT3667_VCC VCC 3 VDD_UG3 PL3002

1 1 1 48 NC4 V064/SET3 RT3667_PWM3 5 UGATE 0.15UH_PCME064T-R15MS0R665 36A_20%
@

GND

49 NC5 PR3063 PR3064 PR3065 PWM 2 VDD_PH3 7 VDD_PH3 1 2

NC6 1 2VDD_EN31 PHASE +VDDCR_VDD

EMC_NS@ EMC_NS@
LV3667BYGQW_WQFN52_6X6 330_0402_1% 26.1K_0402_1% @ EN VDD_LG3

1
7 6 @ @

0_0805_5%
19.6K_0402_1%
LGATE
53

2
0_0402_5% 6

PR3068
GND1

2
PR3067 9 PJ3004 PJ3005
GND2

PR3066
0_0402_5% JUMPER JUMPER

1
@ PU3003

3
4
5

2
RT9610CGQW_WDFN8_2X2 VDD_ISEN3P_R

1
VDD_SNB3

1000P_0402_50V7K
1
VDD_SET3_R2 RT3667_V064_RC

1
PR3070

0.022U_0402_25V7K
2

1
2.74K_0402_1%

PC3039
1/16W_340_1%_0402

2
PR3069

PC3038
PC3040

2
1
1 2

1
0.1U_25V_K_X5R_0402

VDDCR_VDD_ISEN3P

VDDCR_VDD_ISEN3N

+5VALW
V20B+

0.1U_25V_K_X7R_0402

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
EMC@
1 1 1

PC3041

PC3042

PC3043
2
PR3071 2 2 2
2.2_0603_5%

1
B 2.2_0603_5% 0.22U_25V_K_X5R_0402 B
PC3044 PQ3008
PR3072 AON6982_DFN8-7

2
PC3045
1U_0402_10V6K 4 VDD_BST4_R
2 1VDD_BST4
1 2 1
2 1 VDD_VCC4 8 BOOT
VCC 3 VDD_UG4 PL3003
RT3667_PWM4 5 UGATE 0.15UH_PCME064T-R15MS0R665 36A_20%
PR3073 PWM 2 VDD_PH4 7 VDD_PH4 1 2
1 @ 2VDD_EN41
EN
PHASE
7 VDD_LG4 6
+VDDCR_VDD

EMC_NS@ EMC_NS@
@ @
LGATE

2
0_0402_5% 6

0_0805_5%
GND1 9 PJ3006 PJ3007

PR3074
V20B+ GND2
JUMPER JUMPER

1
PU3004

3
4
5
RT9610CGQW_WDFN8_2X2 VDD_ISEN4P_R

2
VDD_SNB4

1
1000P_0402_50V7K
PR3075
2.74K_0402_1%
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

PC3052
1

1
PC3046

PC3047

PC3048

PC3049

PC3050

PC3051

PC3053

2
2
1 2
2

0.1U_25V_K_X5R_0402

VDDCR_VDD_ISEN4P
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

VDDCR_VDD_ISEN4N

V20B+

0.1U_25V_K_X7R_0402
+5VALW

0.1U_25V_K_X7R_0402

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
EMC@
1

PC3054

EMC@
1 1 1

PC3055

PC3056

PC3057
2

2
PR3076 2 2 2
2.2_0603_5%

1
2.2_0603_5% 0.22U_25V_K_X5R_0402
PC3058 PQ3010
PR3077 AON6982_DFN8-7

2
PC3059
1U_0402_10V6K 4 SOC_BST1_R
2 1SOC_BST1
1 2 1
2 1 SOC_VCC 8 BOOT
VCC 3 SOC_UG1 PL3004
RT3667_PWMA1 5 UGATE 0.36UH_PCMB063T-R36MS3R205_20A_20%
PR3078 PWM 2 SOC_PH1 7 SOC_PH1 1 2
1 @ 2SOC_EN 1
EN
PHASE
7 SOC_LG1 6
+VDDCR_SOC

EMC_NS@ EMC_NS@
@ @
LGATE VDDCR_SOC:TDC=15A EDC=20A

2
0_0402_5% 6

0_0805_5%
GND1 9 PJ3008 PJ3009

PR3079
GND2
JUMPER JUMPER

1
A PU3005 A

3
4
5
RT9610CGQW_WDFN8_2X2 SOC_ISEN1P_R

2
SOC_SNB1

1
1000P_0402_50V7K
PR3080
4.75K_0402_1%

PC3060
PC3061

2
2
1 2

0.1U_25V_K_X5R_0402

1 2

PR3081
VDDCR_SOC_ISEN1P 1/16W_1.87K_1%_0402

VDDCR_SOC_ISEN1N

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_VDD/SOC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
L350 A+N 1.0

Date: Saturday, May 09, 2020 Sheet 62 of 68

5 4 3 2 1
 A
B
C
D

5
5

2
1
2
1

+
+

PC3137 PC3100
330U_D2_2V_Y 330U_D2_2V_Y
2
1
+

2
1
+
PC3101
PC3138 330U_D2_2V_Y
+VDDCR_VDD

+VDDCR_SOC
330U_D2_2V_Y
2
1
+

PC3102

2
1
+
330U_D2_2V_Y
PC3140
330U_D2_2V_Y
2
1
+

PC3103
330U_D2_2V_Y
2
1
+

PC3104
330U_D2_2V_Y
@

2
1
2
1
+

PC3141 PC3105
22UC_6.3VC_MC_X5RC_0603 330U_D2_2V_Y
2
1

PC3142

4
4

22UC_6.3VC_MC_X5RC_0603
2
1

PC3143
22UC_6.3VC_MC_X5RC_0603
2
1

PC3144
22UC_6.3VC_MC_X5RC_0603
@
2
1

PC3145
22UC_6.3VC_MC_X5RC_0603
2
1

2
1

PC3107
PC3146 22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
2
1

2
1

PC3108
PC3147 22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603
2
1

PC3109
2
1

22UC_6.3VC_MC_X5RC_0603
PC3148
2
1

22UC_6.3VC_MC_X5RC_0603
PC3110
2
1

22UC_6.3VC_MC_X5RC_0603
PC3149
2
1

22UC_6.3VC_MC_X5RC_0603
PC3111
2
1

22UC_6.3VC_MC_X5RC_0603
PC3150
2
1

22UC_6.3VC_MC_X5RC_0603
PC3112
2
1

22UC_6.3VC_MC_X5RC_0603
PC3151
2
1

22UC_6.3VC_MC_X5RC_0603
PC3113
2
1

22UC_6.3VC_MC_X5RC_0603
PC3152
2
1

22UC_6.3VC_MC_X5RC_0603
@

PC3114
2
1

22UC_6.3VC_MC_X5RC_0603
PC3153
2
1

22UC_6.3VC_MC_X5RC_0603
Vendor suggest:330uF*1PCS+470uF*1pcs+22uF*12PCS

PC3115

3
3

2
1

22UC_6.3VC_MC_X5RC_0603
PC3154
2
1

22UC_6.3VC_MC_X5RC_0603
PC3116
22UC_6.3VC_MC_X5RC_0603
@
2
1

PC3117
22UC_6.3VC_MC_X5RC_0603
2
1

PC3118
22UC_6.3VC_MC_X5RC_0603
Vendor suggest:330uF*7PCS+22uF*30PCS

2
1

PC3119
22UC_6.3VC_MC_X5RC_0603
2
1

PC3120
22UC_6.3VC_MC_X5RC_0603
2
1

PC3121
22UC_6.3VC_MC_X5RC_0603
2
1

Issued Date
PC3122
22UC_6.3VC_MC_X5RC_0603

Security Classification
2
1

PC3123
22UC_6.3VC_MC_X5RC_0603
2
1

PC3124
22UC_6.3VC_MC_X5RC_0603
2
1

PC3125
2013/08/15 22UC_6.3VC_MC_X5RC_0603
2
1

PC3126
22UC_6.3VC_MC_X5RC_0603

2
2

2
1

PC3127
22UC_6.3VC_MC_X5RC_0603
@
2
1

PC3128
22UC_6.3VC_MC_X5RC_0603
2
1

PC3129
22UC_6.3VC_MC_X5RC_0603
@

Deciphered Date
2
1

PC3130
22UC_6.3VC_MC_X5RC_0603
2
1

LC Future Center Secret Data

PC3131
22UC_6.3VC_MC_X5RC_0603
@
2
1

PC3132
22UC_6.3VC_MC_X5RC_0603
@

2013/08/15
2
1

PC3133
22UC_6.3VC_MC_X5RC_0603
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
@
2
1

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC3134
22UC_6.3VC_MC_X5RC_0603
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2
1

A2

PC3135
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize

Date:
R&D
Title

22UC_6.3VC_MC_X5RC_0603
@
2
1

PC3136
22UC_6.3VC_MC_X5RC_0603
Document Number
PWR_VDD/SOC

1
1

Saturday, May 09, 2020

Sheet
L350 A+N
63
of
68
Rev
1.0
A
B
C
D
 A B C D

GPU_ALL_B+ PR1816 V20B+

0.005_1206_1%
PJ1810 Vout:1.2V
1 4
3A V20B+_GPU 1 2
1 2 TDC=17.2A

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
2 3
JUMP_43X79 EDP-c=17.2A

0.1U_0402_25V6
1 1
EDP-p=18.4A

EMC_NS@
1
1 1

@
PR1801

PC1801

PC1802
FBVDDQ_BST 2 1 FBVDDQ_BST_R

PC1803
2 2 current limit=30A

2
0_0603_5%

@
26
GPU_TGP_R+ 68

1
PU1801
PC1804

BST
0.1U_0603_25V7K GPU_TGP_R- 68

2
8 14
IN_1 LX_1 OVP=(1.2~1.3)*Vout
+5V_NVVDD 9 15
UVP=(0.65~0.75)*Vout
IN_2 LX_2
Fsw=500Khz
10
IN_3 LX_3
16
FB=0.6V(+-1.5%)

2
PR1802 FBVDDQ
2.2_0603_5% 17
LX_4
PC1805 PL1801 17.2A

1
2 1 27 18 FBVDDQ_LX 1 2
VCC LX_5

1
4.7U_0603_6.3V6K

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
19 PR1803 0.42UH_CMME064T-R42MS1R_24A_20% 1
LX_6

330U_D2_2V_Y
1

1
2.2_0805_5%

PC1806

PC1807

PC1808

PC1809

PC1810

PC1811

PC1812

PC1813

PC1814

PC1815

PC1816

PC1817

PC1818

PC1819
EMC_NS@ +

PC1829
PR1804 1 2 1/16W_12K_5%_0402 FBVDDQ_EN 3 20
28,30 FBVDDQ_PWR_EN EN LX_7

2
FBVDDQ_SN 2

1
PR1805 21 PR1806
0.22U_6.3V_K_X5R_0402

1 LX_8
GPU_ALL_B+ 1 2 7 100_0402_1%
TON

1
100K_0402_1% PC1821 @
PC1820

+3VS 2
1000P_0402_50V9-J

2
1 2 FBVDDQ_RF 4 EMC_NS@
PFM

2
100K_0402_1% 6
PR1807 FB
2

PC1822
PR1811 1 2 1 11
SS PGND_1
100K_0402_5%
0.01U_0402_25V7K FBVDDQ_FB 1 2
12 FBVDDQ_VCC_SENSE 29
PGND_2
1

28 FBVDDQ_PWROK 2 PR1808
PGOOD 10K_0402_1%
13 PR1810
PGND_3 1 2 FBVDDQ_FB_R2 1 2
@
22 0_0402_5% PC1823
PGND_4 1500P_0402_50V7-K
24
NC1 23
2 2
PGND_5

28 25
NC2 PGND_6
Vout=0.6*(1+PR1808/PR1813)

0.1U_0402_25V6
1

1
AGND

=0.6*(1+10K/10K)

1
PR1813

@
10K_0402_1%
=0.6*2=1.2V

PC1831
AOZ2767QI-11_QFN28_5X5
5

2
2

2
PR1812

FBVDDQ_FB_R3
1/16W_120K_1%_0402

1
PR1814
1 2 VRAM_VDDQ_ADJ_R 2
28 VRAM_VDDQ_ADJ @ PQ1801
G LBSS139WT1G_SC70-3
0_0402_5% S

3
1

@
PR1815
100K_0402_1%
CAD Note：VRAM_VDDQ_ADJ
2

L = 1.2V
H = 1.25V

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-FBVDDQ-AOZ2767QI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom L350 A+N 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 64 of 68
A B C D
 A B C D

+3VS

Vout=1.0V±3%
Vset=1.01V±1.88%

1
1 1

PR6301
1 2
0_0402_5% PR6302 Vref=0.6V
+5VALW @ 100K_0402_1%
PC6301
TDC=2A, OCP=3.5A

2
1 2 1.0VGS_PG 28

1U_0402_6.3V6K PU6301
PJ6301@
6 7
2 1 5 VCNTL POK PJ6302@
+1.2V 10U_0603_10V6K
2 1 PC6302 VIN 3 2 1
PR6303 2 1 VOUT1 4 2 1 +1.0VGS
JUMP_43X79

26.1K_0402_1%

22U_0603_6.3V6-M
1 2 8 VOUT2
28,30 1V0_MAIN_EN @ EN JUMP_43X79

2
9 2

PC6304
1

GND
0_0402_5% 2 1 EPAD FB

PR6304
PC6305 @

1
PC6303 22P_50V_F_NPO_0402

1
2
0.1U_0402_25V6 2 2

2
PD6301 @
3 PR6305 1 2 0_0402_5%

1 @

100K_0402_1%
LBAT54SWT1G_SOT323-3 2 PR6307 1 2 0_0402_5%

PR6306
APL5930CKAI-TRG_SO8
@ @ Vout=0.8*(1+PR6304/PR6306)
=0.8*(1+26.1K/100K)

2
=0.8*1.261=1.009V

3 3

Security Classification LC Future Center Secret Data Title 4

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-+1.0VGS-APL5930

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom L350 A+N 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 65 of 68
A B C D
 A B C D

+3VALW

1
PR1401
1
V20B+ 10K_0402_5% 1

PJ1401 PU1401 +1.8VALW

2
2 1
1A 1V8VALW_VIN 5 9 1V8VALW_PG @
2 1 4 IN1 PG 1 1V8VALW_BS 1 2
IN2 BS

EMC_NS@
3 PL1401

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
JUMP_43X39 IN3

1
2 PC1401 1UH_PCMB053T-1R0MS_7A_20% 5A

PC1402

PC1403

PC1404
IN4 6 1V8VALW_LX 0.1U_25V_K_X7R_0402 1 2
@

7 LX1 19

22U_0603_6.3V6-M
GND1 LX2

1
8 20

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
18 GND2 LX3 PR1403 PC1405
GND3

1
21 4.7_0805_5% 330P_0402_50V8J

PC1415

PC1416
GND4

2
PR1404 @ 14 1V8VALW_FB EMC@

PC1406

PC1407

PC1408

PC1409
100K_0402_5% FB

2
+3VALW 1 2 1V8VALW_ILMT 13 12 1V8VALW_FB_R1
1V8VALW_EN 11 ILMT NC3 10 1V8VALW_SNB
EN NC1 16
+3VALW
NC2
1

@ 15 @ @
BYP

2
PR1406 17 1V8VALW_VCC PC1410
1M_0402_5% VCC 1500P_0402_50V7-K

4.7U_0603_6.3V6K
1
EMC@ PR1407
PC1411 SY8286RAC_QFN20_3X3

2
1
1K_0402_1% PR1408

PC1412
2

4.7U_0603_6.3V6K 37.4K_0402_1%

1
1 2

1
ILMT=0 OCP=6.5A PR1410
18.7K_0402_1%
2
ILMT=floating OCP=9.5A 2

ILMT=1 OCP=12.5A

2
Vout=0.6*(1+PR1408/PR1410)
=0.6*(1+37.4K/18.7K)
=0.6*3=1.8V

PR1413
Vout=1.8V±50mV
1 2 1V8VALW_EN
49 EC_1.8VALW_EN @ Vset=0.962V±1.78%
0_0402_5% Vref=0.6V
.1U_0402_10V6-K

1M_0402_5%
1

TDC=5A
PC1413

PR1416

OCP=9.5A
2

OVP=(1.15~1.25)*Vout
@
UVP=(0.6~0.7)*Vout
Fsw=500Khz min=425K max=575K

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-VCCIO-SY8286RAC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Document Number
L350 A+N Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 66 of 68
A B C D
 5 4 3 2 1

G61:Iout=44.4A/90.7A G62: Iout=45.8A/120.5A N18P-G0:Iout=47A/109A

Fsw=400K,OCP=150A PR7535=20.5K
PR7535=22.6K PR7546 PR7549=430
PR7546 PR7549=487 PR7538=6.65K
PR7538=8.25K (G62) PR7540=20K
D PR7540=24.9K (G62) PR7542=39.2K D

PR7542=49.9K (G62) PR7553=53.6K

PR7553=66.2K (G62)
PR7501 0_0402_5%
NVDD_SDA
+5V_NVVDD
1 2
49,57 EC_SMB_DA1 NVDD_SDA 28
@

PR7503 0_0402_5%
NVVDD_B+ PR7502 GPU_ALL_B+
1 2 NVDD_SCL 0.005_1206_1%
49,57 EC_SMB_CK1 NVDD_SCL 28

2
@ +5V_NVVDD PR7513 1 4
2.2_0603_5%

1U_25V_K_X6S_0402

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
PR7508 25.5K_0402_1% 1 1 1 2 3
1 2 NVVDD_EN_R

PC7501

PC7502

PC7503
28,29,30 NVVDD_EN 2

1
PR7583 PC7507
2 2 2

1
0_0402_5% @ 2.2U_25V_K_X5R_0402
1

1
3 1 2 PC7588 PR7505
.1U_0402_10V6-K 2.2_0603_5% 2
1
NVVDD

2
PD5801 PR7585 PC7511 EMC@

2
LBAT54SWT1G_SOT323-3 2 1 2 +5V_NVVDD 2.2U_25V_K_X5R_0402

NVVDD_VCC1
+1.8VS_AON +1.8VS_AON 1 NVVDD_BOOT1 68 NVVDD_Vin_R- NVVDD_Vin_R+ 68
6.8K_0402_1%
PR7510
PC7506
2NVVDD_BOOT1_R

2
1

2
1 2 PR7504

NVVDD_VCC
1

1
0_0402_5% PR7580 1/10W_3.9_5%_0603

1
PR7514 PR7594 PR7586 N18: MID PSI PR7586 stuff Place close to 0_0402_5% PC7505

30
29
28
26
27

25
2.2U_25V_K_X5R_0402

3
10K_0402_5% 10K_0402_5% 10K_0402_5% N17: HIG PSI PR7586 un-stuff @ PU7502 0.22U_0603_50V7-K
GPU pins

1
UP9632@
NVVDD

VCC

VIN6
VIN5
VIN4
VIN2
VIN3

VIN1
PVCC
1

2
@ 33
PR7516 TC7501 BOOT
2

2
NVVDD1_NC1 1 32 NVVDD_PHASE1
1 2 0_0402_5% NVVDD_PSI_R 1 2 PAD NC1 PHASE
28 NVVDD_PSI PR7515 @ 0.22UH_CMME104T-R22MS_50A_20%
31
100_0402_1% NC2 19 NVVDD_SW1 1 2
SW10 1

330U_D2_2V_Y
1 2 0_0402_5% NVVDD_PWRGD_R NVVDD_VSN 1 2 0_0402_5% 41 18
28 NVVDD_PWRGD PR7517 @ PR7518 @ NVVDD_VSS_SENSE 30 GL2 SW9
PL7501 1

330U_D2_2V_Y
1
PR7593 6 17 +

PC7510
PR7521 @ GL1 SW8

1
1 @ 2 0_0402_5% 37 16 +

PC7509
NVVDD_PWM_VID_R NVVDD_TMON_R ZCD_EN SW7
28 NVVDD_PWM_VID PR7520 1 @ 2 0_0402_5% PC7512
1000P_0402_50V7K
1 2
NVVDD
36
FAULT SW6
15 PR7519
2
PR7523 NCP303150MNTWG SW5
14 1/8W_2.2_5%_0805
2

2
PC7513 4700P_25V_K_X7R_0402 100_0402_1% NVVDD_PWM1 34 13 EMC_NS@
1 2 NVVDD_REFIN_R2 1 2 NVDD_VID_BUFF NVVDD_VSP 1 2 0_0402_5% PWM SW4 12
PR7522 @ NVVDD_VDD_SENSE 30 SW3

1 2
NVVDD_DRON 35 11 @
DISB# SW2
1
@ 10
1/16W_6.19K_1%_0402 NVVDD_CSP1 38 SW1 PC7508
PC7520 IMON

PGND10
PR7571 PC7521 PR7527 2200P_0402_50V7K

PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9

PGND1
PR7526

2
NVVDD_COMP NVVDD_COMP_C1 NVVDD_COMP_2C NVVDD_REFIN1

AGND
C PR7525 1/16W_309_1%_0402 4.32K_0402_1% 1 2 1 2 1 2 39 EMC_NS@ C
REFIN

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
NVVDD_B+ 1 2 NVVDD_REFIN_R 1 2 PR7524
2

1
20.5K_0402_1% 330P_0402_50V7K 49.9_0402_1%

PC7514

PC7515

PC7516

PC7517

PC7518

PC7519

PC7576

PC7577

PC7578

PC7579
37

36

35

34

33

32

31
38
40

39
PU7501 33P_0402_50V8J

1
16.5K_0402_1% PC7572

7
8
9
20
21
22
23
24
40
5
2
PC7524 PR7530 PR7531 0.1U_0402_25V6

EN

SCL

SDA

VCC

VSN
PWM_VID

PGOOD

PSI

VSP
VID_BUFF
1

2
1 2 NVVDD_COMP_C2 1 2 1 2

2
2

PC7523 4700P_25V_K_X7R_0402
1K_0402_5%

1 2 1/16W_3.3K_1%_0402 1K_0402_1% NCP303150MNTWG_PQFN41_5X6

PR7529

NVVDD_REFIN 1 30 2200P_25V_K_X7R_0402
PC7522 @ @ @ @ @ @ @
REFIN COMP @ @ @
1 2 0.01U_50V_K_X7R_0402 NVVDD_VREF 2 29 NVVDD_FB
VREF FB
1

NVVDD_VRAMP 3 28 NVVDD_DIFF
VRAMP DIFF PR7532 33.2K_0402_1%
1 2 NVVDD_SS 4 27 NVVDD_FSW 1 2 PC7527 1000P_0402_50V7K
2 Soft Start; 600us SS FSW FSW:400K
PC7528 PR7572 26.1K_0402_1%
NVVDD_I2C NVVDD_TMON
PR7533 0_0402_5% 1 2 +5V_NVVDD
0.01U_50V_K_X7R_0402 I2C ADD:0X40 PR7573
1 2
100K_0402_1%
5
I2C TMON
26 1 @ 2 0_0402_5%
1
PR7507 @
2 NVVDD_TMON_R PR7535 NVVDD_B+
1
Warm Boot: 1phase 1
PR7534
2
78.7K_0402_1%
NVVDD_LPC1 6
LPC1
NCP81611MNTXG IOUT
25 NVVDD_IOUT 1 2

1 2 NVVDD_LPC2 7 24 NVVDD_ILIM 1 2
Cold Boot: 1phase PR7536 54.9K_0402_1% LPC2 ILIM OCP:250A 1/16W_22.6K_1%_0402
NVVDD_PWM4 8 23 NVVDD_CSCOMP PR7537 93.1K_0402_1%
<5A: 1 phase DCM PWM4/PHTH1 CSCOMP
NVVDD_PWM3 NVVDD_CSSUM

2
<15A: 1 phase CCM 9 22

1U_25V_K_X6S_0402
PWM3/PHTH2 CSSUM

10U_25V_K_X6S_0805_H1.25

10U_25V_K_X6S_0805_H1.25
PR7548 1 1 1
PWM1/PHTH4

NVVDD_PWM2 10 21 NVVDD_CSREF
2.2_0603_5%

PC7529

PC7530

PC7531
PWM2/PHTH3 CSREF
1

2 2 2 2

1
DRON

PR7540 PR7542 PC7534 NVVDD_VCC2

CSP4

CSP3

CSP2

CSP1
NC1

NC2

NC3

NC4

1
PR7538 24.9K_0402_1% 49.9K_0402_1% 41 PC7533
8.25K_0402_1% GND PR7543
0.01U_50V_K_X7R_0402 Total OCP 147A 2

100P_0402_50V8J
NCP81611MNTXG_QFN40_5X5 1 300K_0402_1%
Perphase OCP 64A NVVDD 2
11

12

13

14

15

16

17

18

19

20
2

2
+5V_NVVDD PC7542 EMC@
PC7537
1

2
2.2U_25V_K_X5R_0402 NVVDD_BOOT2
2.2U_25V_K_X5R_0402
NVVDD_PWM1 1
NVVDD_DRON

NVVDD_CSP4

NVVDD_CSP2

NVVDD_CSP1

2
PR7545
PR7546 NVVDD_BOOT2_R
1

PR7539 1 2

2
@ PR7553 1 2 0_0402_5% 1/10W_3.9_5%_0603
2 1 66.5K_0402_1% NVVDD_VREF PR7578 PC7535
+5VALW +5V_NVVDD

1
@ 0.22U_0603_50V7-K
0_0402_5% NVVDD

30
29
28
26
27

25
11/16W_487_1%_0402

3
PR7506 0_0603_5% 2 differential PU7503
PR7547 TC7502
2

UP9632@

VCC

VIN6
VIN5
VIN4
VIN2
VIN3

VIN1
PVCC
1

2
NVVDD_CSP1 PAD
1

PC7536 100P_0402_50V8J 1 2 33
NVVDD2_NC1 BOOT NVVDD_PHASE2

1
PC7541 @ 1 32
PR7509 2 1 0_0603_5% 2200P_0402_50V7K PR7550 NC1 PHASE
@

+5VS 100K_0402_1%
2

130_0402_1% 31 0.22UH_CMME104T-R22MS_50A_20%
NC2

1
1 2 NVVDD_REFIN1 19 NVVDD_SW2 1 2
PR7549 SW10 1

330U_D2_2V_Y
41 18 1
GL2 SW9

330U_D2_2V_Y
2
B 1 2 PR7528 10_0402_5% PR7591 6 17 PL7502 + B

PC7539
GL1 SW8

1
1 @ 2 0_0402_5% 37 16 +

PC7538
PR7552 NVVDD_TMON_R ZCD_EN SW7
+5V_NVVDD 36 15 PR7599
11/16W_487_1%_0402 NVVDD_CSP2 FAULT SW6 2
PR7557
2 1 2
NVVDD_PWM2 34
NCP303150MNTWG SW5
14
13
1/8W_2.2_5%_0805
EMC_NS@ 2
1 2 PC7543 100P_0402_50V8J PWM SW4 12
100K_0402_1% SW3

1 2
NVVDD_DRON 35 11
NVVDD_REFIN2 DISB# SW2

1
1 2 10
2K_0402_5% PR7556 NVVDD_CSP2 38 SW1 PC7599
IMON

PGND10
240_0402_1% PR7559 10_0402_5% 2200P_0402_50V7K
disable phase3/4

PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9

PGND1

2
NVVDD_REFIN2

AGND
39 EMC_NS@
REFIN

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2

1
PC7544

PC7545

PC7546

PC7547

PC7548

PC7549

PC7580

PC7581

PC7583

PC7582
1
PC7573

7
8
9
20
21
22
23
24
40
5
2
0.1U_0402_25V6

2
2
NCP303150MNTWG_PQFN41_5X6
@ @ @ @ @ @ @ @ @ @

A A

Security Classification LC Future Center Secret Data Title

PWR-N18-NVVDD-ON-NCP81611MN
Issued Date 2018/08/02 Deciphered Date 2018/08/02
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom L350 A+N 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 67 of 68

5 4 3 2 1
 5 4 3 2 1

+3VS
+3VS

2
PR7619
0_0402_5%
@

2
D D
PR7640
64 GPU_TGP_R- PR7699 1 @ 2 0_0402_5% 10K_0402_1%

1
PC7601

1U_0402_16V6K
@
PC7602

1
1000P_0402_50V7K

2
PR7601 100_0402_1% 1 2
1 2
64 GPU_TGP_R+

2
PR7603 PR7604

1
PR7641 10K_0402_1%
PR7602 PR7618 0_0402_5% 10K_0402_1% 1 2 1 2 BS_REF: 0.05V
75K_0402_1% SH_IN_Nx 1 2 1 2 OVRM_SKIP 1/16W_324K_1%_0402
@
PC7603

1
BS_OK_Threshold: 6V @ PR7645 1K_0402_1% 1000P_0402_50V7K

27
2 2
PU7601 1 2

VCC
PR7605 PC7604 25 PR7606
SH_IN_N1 1 SKIP 26 1 2 1 2
1/16W_487_+-1%_0402 1000P_0402_50V7K SH_IN_N1 MODE
PR7620 10K_0402_1% CM_REF: 0.845V

1
SH_IN_P1 2 28 OVRM_EN 1 2 BG_REF_OUT
GND_FET BS_IN1 3 SH_IN_P1 ENABLE 31 365K_0402_1% PR7607 1/16W_680K_1%_0402
BS_IN1 CUSTOM31 =1.3V

1
PR7698 1 2 0_0402_5% SH_IN_N2 4 24 BS_REF
67 NVVDD_Vin_R- @ SH_IN_P2 5 SH_IN_N2 BS_REF 23 BG_REF_OUT PC7605
1000P_0402_50V7K
BS_IN2 6 SH_IN_P2 BG_REF_OUT 22 CM_REF_IN 1 2
SH_O2 7 BS_IN2 CM_REF_IN 21
0_0402_5% 8 SH_O2 CUSTOM21 20
CUSTOM8 DIFF_OUT_P ADC_IN_P 28
PR7608 100_0402_1% PR7652 10 19 ADC_IN_N 28
1 2 1 SH_O3 DIFF_OUT_N
67 NVVDD_Vin_R+ @ 2 11
BS_IN3 CUSTOM18
18 PC7611

1
1 12 17 1 2
SH_IN_P3 SH_O4
1

PR7610 13 32 SH_O1
PR7630 1 2 14 SH_IN_N3 SH_O1 30 BS_OK
PR7609 PC7606 @ BS_IN4 BS_OK
47P_0402_50V8J

1
75K_0402_1% 0.015U_25V_K_X7R_0402 0_0402_5% 15 29 MUX_SEL @
SH_IN_P4 MUX_SEL

1_/16W_357_1%_0402
2 16 PR7611 PR7612

GND
SH_IN_N4

1
GND_FET 9
BS_OK_Threshold: 6V GND_FET 1 0_0402_5% 0_0402_5%
2 2

PR7614
2

US5650QQKI_WQFN32_4X4 PC7607

2
33
PR7613 PC7608 0.015U_25V_K_X7R_0402
+3VS @ @

1_/16W_357_1%_0402
1/16W_487_+-1%_0402 2
1000P_0402_50V7K
1

2
1
1 2
C GND_FET PR7677 PC7609 C
1

0_0402_5% PC7610
47P_0402_50V8J 47P_0402_50V8J

10K_0402_1%
2 1

2
PR7615
@ @

2
TC7601

1
PR7617
1 @ 2 0_0402_5% 1
28 ADC_MUX_SEL

PAD
@
UPI---US5650
PR7605=487
PR7613=487
PR7610=357ohm for Lower 70W 215 for 75W to 90W 165 for 100W to 110W
PR7614=357ohm for Lower 70W 215 for 75W to 90W 165 for 100W to 110W
PR7603=324K
PR7602=75K
PR7609=75K
PC7604=1nF
PC7608=1nF

B
ON---NCP45491 B
PR7605=649
PR7613=649
PR7610=475ohm for lower 70W 287 for 75W to 90W 221 for 100W to 110W
PR7614=475ohm for lower 70W 287 for 75W to 90W 221 for 100W to 110W
PR7603=243K
PR7602=75K
PR7609=75K
PC7604=1nF
PC7608=1nF

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-N18-OVRM&IIC-US5650QQKI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size Document Number
L350 A+N Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Saturday, May 09, 2020 Sheet 68 of 68
5 4 3 2 1