Testing & Verification

..(For VLSI Circuits and Systems)

Introduction

Reference : 1. Mohammad Tehranipoor, Electrical and Computer Engineering, University of Connecticut, Internet Resources
2. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
 Hello All,
Why Testing and Verification?
Have you ever heard about ‘CPU Bugs’ ?
A hardware bug is a defect in the design, manufacture, or operation of computer hardware that
causes incorrect operation.

https://wiki.osdev.org/CPU_Bugs
https://en.wikipedia.org/wiki/Pentium_FDIV_bug
The severity of the FDIV bug is debated. Though rarely encountered by most users (Byte magazine estimated
that 1 in 9 billion floating point divides with random parameters would produce inaccurate results),both the
flaw and Intel's initial handling of the matter were heavily criticized by the tech community.
In December 1994, Intel recalled the defective processors. In January 1995, Intel announced "a pre-tax charge
of $475 million against earnings, ostensibly the total cost associated with replacement of the flawed
processors

Intel attributed the error to missing entries in the lookup table used by the
floating-point division circuitry

Similarly, the F00F bug in Intel Pentium series Processors was discovered in 1997 which causes the
processor to stop operating until rebooted.
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
Ref. Aritra Hazra, Dept. of Computer Sc & Engg, IIT Kharagpur
 To understand ‘Testing’ Theme
Let’s see an Example…
Functional automatic test pattern generation (ATPG) programs generate a complete set of test-patterns
to completely exercise the circuit function. In a 64-bit ripple-carry adder, from a functional point of view,
the adder has 129 inputs and 65 outputs. Therefore, to completely exercise its function, we need 2129
=680,564,733,841,876,926,926,749,214,863,536,422,912 input patterns, producing 225
=36,893,488,147,419,103,232 output responses.

The fastest automatic test equipment (ATE), at present, operates at 1 GHz. This ATE would take 2.158 x
1022 years to apply all of these patterns to the circuit-under-test (CUT), assuming that the tester and
circuit can operate at 1 GHz. Thus, we see that an exhaustive functional test is impractical, except for
small circuits, and today most circuits tend to be huge.

Structural test, on the other hand, need at most, 1,728 test-patterns. The 1 GHz ATE would apply these
patterns in 0.000001728 s, and since this test-pattern set covers all possible structural stuck-at faults in
the adder, it achieves exactly the same fault coverage as the intractable functional test-pattern set
described above.
 Hardware Testing Theme
Testing (Need Test Pattern Set to Test a Particular Hardware)

Structural Testing Exhaustive Testing

(Functional)
2N
Single Stuck-at-fault Multiple Stuck-at-fault Sequential Testing
Model Model Sequential SCOAP
3N -1 faults in fault list (Used for
very complex systems, still accuracy D-Algo
Fault Model (2N Faults) Fault Simulation (for does not differ much)
ATPG)
PODEM
§ Scan Test
Equivalence Dominance
Sensitize, Propagate and § Boundary Scan Test
Ø Serial (More Time)
Ø Parallel (Less Time) Justify (SPJ)
(Reduced Fault Set List)
Ø Deductive (Even Lesser) (Used for “Difficult to Test” Faults)
Ø Concurrent (Event Driven based Deductive) SCOAP
Controllability and Observability Measures
(Gives an idea about difficulty and easiness for
testing a fault)
Course Plan:
Suggested Text/References :
1.Bushnell, M. and Agrawal, V.D., Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI
Circuits, Kluwer Academic (2000).
2. Abramovici, M., Breuer, M. A. and Friedman, A.D., Digital Systems Testing and Testable Design, Jaico
Publishing House (2001)
3.VLSI Test Principles and Architectures: Design for Testability. Edited by Laung-Terng Wang, Cheng-Wen Wu,
and Xiaoqing Wen (2006)
4. Kropf, T., Introduction to Formal Hardware Verification, Springer Verlag (1999)
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