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Lab Manual Exp 1

The document describes experiments performed in a VLSI lab to analyze the behavior of a CMOS inverter. 1) The VTC and current characteristics of an inverter are plotted by varying the widths of the PMOS and NMOS transistors. Increasing the PMOS width shifts the VTC to the right, while increasing the NMOS width shifts it to the left. 2) Decreasing the power supply voltage VDD causes the VTC to shrink in both dimensions and reduces the noise margin of the inverter. 3) The propagation delay of an inverter is estimated by varying the PMOS to NMOS width ratio and it is found that there is an optimal ratio that minimizes delay.

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Sumit Roy
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46 views5 pages

Lab Manual Exp 1

The document describes experiments performed in a VLSI lab to analyze the behavior of a CMOS inverter. 1) The VTC and current characteristics of an inverter are plotted by varying the widths of the PMOS and NMOS transistors. Increasing the PMOS width shifts the VTC to the right, while increasing the NMOS width shifts it to the left. 2) Decreasing the power supply voltage VDD causes the VTC to shrink in both dimensions and reduces the noise margin of the inverter. 3) The propagation delay of an inverter is estimated by varying the PMOS to NMOS width ratio and it is found that there is an optimal ratio that minimizes delay.

Uploaded by

Sumit Roy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EC39004 : VLSI LABORATORY

LAB MANUAL

Objective-1:
Design a CMOS inverter and plot its VTC using LTSpice. Investigate the effect of PMOS and NMOS widths on
the VTC and the switching threshold. What is the impact of VDD on the VTC (check even when VDD < |V Th|)?
Plot the current characteristics of a CMOS inverter.

Circuit Diagrams:
a) For Plotting the VTC

b) For Investigating the effects of PMOS and NMOS widths on the VTC and the switching threshold

c) For checking the impact of VDD on the VTC


Plots and Observations:

a) Plotting the VTC of the inverter

• The PMOS width = 2um and NMOS width = 1um


• We can see that for these widths the VTC is not symmetric, that is, the switching threshold voltage is
not at 0.9V (= 𝑉𝑑𝑑2)
• The current characteristics of the inverter are also plotted here and we observe that the Short-circuit
current is maximum at the switching threshold voltage.

b) Effect of device widths on the VTC and the switching threshold

• The NMOS width has been fixed to 1um while the PMOS width is varied
• We can clearly see that increasing the width of the PMOS is making the VTC shift to the right
• The PMOS width has been fixed to 360nm while the NMOS width is varied
• We can clearly see that increasing the width of the NMOS is making the VTC shift to the left

c) Impact of VDD on the VTC

• We can see that decreasing VDD leads to shrinking of the VTC in both dimensions.
• The inverting behaviour is retained even when VDD < |Vth| because of sub-threshold conduction
• We also observe that the gain in the transition region increases as we decrease VDD
• But below a certain point, the gain in the transition region starts falling again
• Due to the shrinking of the VTC, we can say that the noise margin of the inverter keeps decreasing as
the VDD decreases.
Objective-2:
For the CMOS inverter, estimate its propagation delay when no load is connected. Examine the effect of the
PMOS/NMOS ratio on the propagation delay. Find the PMOS/NMOS ratio for which the delay is minimum.
Now, could you connect a variable load capacitor at the output node and investigate the delay?

Circuit Diagrams:

a) Circuit for estimating and checking the impact of PMOS/NMOS ratio on propagation delay without a load
capacitor

b) Circuit for observing the impact of a load capacitor on the propagation delay

Plots and Observations:

a) Plots for estimating the propagation delay without any external cap:
• For the above experiment we have taken Wp = 2um, Wn = 1um and Lp = Ln = 180nm.
• In the above plot blue signal represents the input signal and the green signal represents the output
signal.
• We know that propagation delay is defined as the time difference between input and output when they
are Vdd/2.

b) Plots for observing the impact of external cap on tp :

• W and L values of the PMOS and NMOS are same as before. Green, blue, red and light blue represents
the output signals with external cap 0.1pF, 0.2pF, 0.3pF and 0.4pF respectively.
• Therefore, from the above plot we can say that as the external capacitance increases, time delay will
also increase because Cout increases. and, Tp = 0.69*(Reqp + Reqn)*Cout/2.

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