Von Neumann/Turing Stored Program concept Main memory storing programs and data ALU operating on binary data Control unit interpreting instructions from memory and executing Input and output equipment operated by ontrol unit Princeton Institute for Advanced Studies IAS Completed 1952 OQ IAS - details 1000 x 40 bit words Binary number 2x20 bit instructions Set of registers (storage in CPU) Memory Buffer Register Memory Address Register Instruction Register Instruction Buffer RegisterProgram Counter Accumulator Multiplier Quotient Commercial Computers 1947 - Eckert-Mauchly Computer orporation UNIVAC | (Universal Automatic omputer) US Bureau of Census 1950 calculations Became part of Sperry-Rand Corporation Late 1950s - UNIVAC IT Faster More memory oO oO IBM Punched-card processing equipment 1953 - the 701 IBM's first stored program computer Scientific calculations 1955 -the 702Business applications Lead to 700/7000 series 4o ransistors Replaced vacuum tubes Smaller Cheaper Less heat dissipation Solid State device Made from Silicon (Sand) Invented 1947 at Bell Labs William Shockley et al. o ransistor Based Computers Second generation machines NCR & RCA produced small transistor machines IBM 7000 DEC - 1957 = Produced PDP-1Microelectronics Literally - "smallelectronics' A computer is made up of gates, memory cells and interconnections These can be manufactured on a semiconductor e.g. silicon wafer Generations of Computer Vacuum tube - 1946-1957 Transistor - 1958-1964 Small scale integration - 1965 on Up to 100 devices on a chip Medium scale integration - to 1971 100-3,000 devices on a chip Large scale integration - 1971-1977 3,000 - 100,000 devices on a chip Very large scale integration - 1978 to ate = 100,000 - 100,000,000 devices on a chip Utra large scale integration Q* Over 100,000,000 devices on a chip Moore's Law Increased density of components on chip Gordon Moore - cofounder of Intel Number of transistors on a chip will double every year Since 1970's development has slowed a little = Number of transistors doubles every 18 months Cost of a chip has remained almost nchanged Higher packing density means shorter electrical paths, iving higher performance Smaller size gives increased flexibility Reduced power and cooling requirements Fewer interconnections increases Cc areliability IBM 360 series 1964 Replaced (& not compatible with) 7000 series First planned "family" of computers « Similar or identical instruction sets = Similar or identical 0/S = Increasing speed « Increasing number of 1/0 ports (i.e., more terminals) = Increased memory size « Increased cost Multiplexed switch structure DEC PDP-8 1964 First minicomputer (after miniskirt!) Did not need air conditioned room Small enough to sit on a lab bench$16,000 $100k+ for IBM 360 Embedded applications & oEM BUS STRUCTURE Semiconductor Memory 1970 Fairchild Size of a single core i.e. 1 bit of magnetic core storage Holds 256 bits Non-destructive read Much faster than core Capacity approximately doubles each year Intel 1971- 4004 »First microprocessor « All CPU components on a single chip bit=4 bit Followed in 1972 by 8008 #8 bit Both designed for specific applications 1974 -8080 « Intel's first general purpose microprocessor Speeding it up Pipelining On board cache On board L1 & L2 cache Branch prediction Data flow analysis Speculative execution U erformance Mismatch Processor speed increased Memory capacity increased Memory speed lags behind processor speedSYSTEM BUSES Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of controlsignals What is a program? A sequence of steps For each step, an arithmetic or logical peration is done For each operation, a different set of control signals is needed ° Function of Control Unit For each operation a unique code is provided e.g. ADD, MOVEA hardware segment accepts the code and issues the control signals We have a computer! Components The Control Unit and the Arithmetic and ogic Unit constitute the Central rocessing Unit Data and instructions need to get into the system and results out Input/output Temporary storage of code and results is needed » Main memory aoe lee Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC= Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions Execute Cycle Processor-memory data transfer between CPU and main memory Processor I/O Data transfer between CPU and 1/0 module Data processing Some arithmetic or logical operation on ata Control Alteration of sequence of operations e.g. jump Combination of above QInterrupts Mechanism by which other modules (e.g. 1/0) may interrupt normal sequence of processing Program e.g. overflow, division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking 1/0 from I/O controller Hardware failure "e€.a. memor_ parity error Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: = Suspend execution of current program» Save context = Set PC to start address of interrupt hander routine = Process interrupt » Restore context and continue interrupted program Multiple Interrupts Disable interrupts « Processor will ignore further interrupts whilst processing one interrupt « Interrupts remain pending and are checked after first interrupt has been processed = Interrupts handled in sequence as they occur Define priorities = Low priority interrupts can be interrupted by higher priority interrupts » When higher priority interrupt has been processed, processor returns to previousinterrupt All the units must be connected Different type of connection for diferent type of ni =» Memory = Input/Output = CPU Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals =Reade | = Write = Timing Input/Output Connection(1) Similar to memory from computer's viewpoint —Output Receive data from computer Send data to peripheral Input « Receive data from peripheral « Send data to computer Input/Output Connection(2) Receive control signals from computer Send control signals to peripherals eg. spin disk Receive addresses from computer e.g. port number to identify peripheral Send interrupt signals (control) 9 PU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interruptsBuses There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g.Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP) What is a Bus? A communication pathway connecting two or more devices Usually broadcast Often grouped » A number of channels in one bus = e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown Carries data «= Remember that there IS no differencebetween "data and "instruction" at this level Width is a key determinant of performance «8, 16, 32, 64 bit Address bus Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system «e.g. 8080 has 16 bit address bus giving 64k address space Control and timing information = Memory read/write signal = Interrupt request = Clock signals NIC- Network Interface CardBus Types Dedicated * Separate data & address lines * Multiplexed * Shared lines * Address valid or data valid control line « Advantage - fewer lines * Disadvantages = More complex control « Utimate performance Bus Arbitration More than one module controlling the bus e.g. CPU and DMA controller [DMA - irect Memory Access] Only one module may control bus at one time Arbitration may be centralised or distributed 0Centralised Arbitration Single hardware device controlling bus access « Bus Controller « Arbiter May be part of CPU or separate 0 istributed Arbitration Each module may claim the bus Control logic on all modules Timing Co-ordination of events on bus Synchronous = Events determined by clock signals = Control Bus includes clock line = A single 1-0 is a bus cycle = All devices can read clock line » Usually sync on leading edge « Usually a single cycle for an eventPCI Bus Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines U Cl Bus Lines (required) Systems lines *Incuding clock and reset Address & Data 32 time mux lines for address/data Interrupt & validate lines Interface Control Arbitration * Not shared * Direct connection to PCI bus arbiter Error lines Interrupt lines ‘Not sharedCache support 64-bit Bus Extension + Additional 32 lines * Time multiplexed + 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan * For testing procedures INTERNAL MEMORIES Characteristics Location * CPU + Internal * External Capacity * Word size ° The natural unit of organisation * Number of words° or bytes Unit of transfer + Internal ° Usualy governed by data bus width + External ° Usually a block which is much larger than a word * Addressable unit ° Smallest location which can be uniquely addressed ° Word internally ° Cluster on M$ disks Access method Performance Physical type Physical characteristics Organisation