BTEH 2223 MICROPROCESSOR SYSTEMS

CHAPTER 5: INTERRUPTS

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AN INTERRUPT REVIEW
 An interrupt request (or more commonly just an interrupt) is an
internal or external event that attracts the attention of CPU quickly
in order to make CPU to respond rapidly to the change. When it is
serviced, it makes the microcontroller interrupt the execution of the
current program and execute another program instead.
 Internal interrupts can be originated in the microcontroller’s I/O modules, timer, its
memory such as when writing in the data EEPROM, or its CPU such as a division by
zero.
 External interrupts originate in peripherals and reach the microcontroller through one of
its pins and associated ports.

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 Many interrupts can be masked, ie disabled, by setting a bit in a control register. The interrupts
are called as Maskable interrupts. In some processors however (but not PIC), some interrupts are
not maskable.

 There are also Interrupt Flags, bits in SFRs (the INTCON register), which are set whenever an
associated interrupt occurs. These record the fact that an interrupt has occurred, even if the CPU
is unable to respond to it.

 Microcontrollers also have one bit for global control (GIE bit in INTCON register) of interrupts.
This is equivalent to enabling or disabling the whole interrupt system in the microcontroller. Bit
GIE is cleared on RESET, for example, when the microcontroller is first powered up.

 In order for an maskable interrupt request to reach the CPU and be serviced,
- both the global interrupt system and
- the specific interrupt control bits associated with the interrupt source must be enabled.

 Non-maskable interrupts will always reach the CPU and will be serviced independently of the
global control bit status.

 An Interrupt that has occurred, but has not received CPU response, is called a Pending
Interrupt.
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 In the case of several interrupts, one Interrupt Service Routine (ISR) is completed before the
next interrupt is responded to.
A Generic Interrupt Structure

Other
replicated for all other maskable interrupts
maskable Global Interrupt Enable*
interrupts

Interrupt X Enable*

Interrupt X Interrupt
S Q
inputs to
(reset by CPU CPU
R Interrupt
or program) Flag*

Non-maskable
Interrupt
* bits in a Special Function Register  INTCON register

- When the CPU has responded to an interrupt, it is necessary to clear interrupt

flag (automatically or be done within the program of user).
- CPU always responds to non-maskable interrupt (normally is the important
external interrupt), so no interrupt flag is required for that.
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The PIC 16F84A Interrupt Sources Structure

4 interrupt sources
Timer Overflow

External Interrupt

Port B Change
Note that the interrupt flags are
EEPROM Write
set by the interrupt action, but
Complete must be cleared in the program,
during the ISR.
What happens if this isn’t done?
Global Interrupt Enable
Port A, Bit 2 RA2 1 18 RA1 Port A, Bit 1
Port A, Bit 3 RA3 RA0 Port A, Bit 0
*Port A, Bit 4 RA4/T0CKI OS C1/CLKIN Oscillator connections
Reset MCLR OS C2/CLKOUT
Ground VSS VDD Supply voltage
External Interrupt input **Port B, Bit 0 RB0/INT RB7 Port B, Bit 7
with edge triggered Port B, Bit 1 RB1 RB6 Port B, Bit 6
Port B, Bit 2 RB2 RB5 Port B, Bit 5
# edge it responds to is controlled by Port B, Bit 3 RB3 9 10 RB4 Port B, Bit 4
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the setting of the INTEDG bit of *also Counter/Timer clock input
OPTION register. **also external Interrupt input
The PIC 16F84A INTCON Register

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The PIC 16F84A / PIC 16F87x OPTION Register

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 The PIC 16 Series
Interrupt Detected main program is running
Interrupt Response
Complete Current Instruction
Note that this diagram
shows what the PIC
Save Program Counter on Stack
microcontroller itself does
Automatically clear to
as an interrupt occurs. The
avoid other interrupts
programmer need not Clear GIE
possibly interrupting
worry about any of these this interrupt
actions, but needs to know Reload PC with 0004H
that they’re happening.
Continue Program Execution ISR execution starts

No Instruction
is RETFIE?

Yes

Set GIE to 1 Done by retfie

instruction
Load PC from Stack

Continue Program Execution main program continues 8

ISR execution flow
chart

Set GIE bit =1

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ISR starting address
 There are two possible ways to provide the CPU with the address for the interrupt service
subroutine:

1. The interrupt service subroutine is stored in a fixed memory location that the CPU
already knows. It is known as a fixed interrupt request. In this type of interrupt, the
microcontroller always jumps to a fixed location in memory. This address has the first
instruction in the interrupt service subroutine. Depending on the type of microcontroller,
there can be a different memory address assigned to each interrupt source, or as happens
with PIC microcontrollers, there is a single address for all interrupts. In any case, these
addresses are always fixed. Because of its simplicity, this type of interrupt is widely used
in microcontrollers.

2. At the time of the interrupt being requested, the interrupt service subroutine address is
given to the CPU. This is more flexible but it is also more difficult to implement. When
the interrupt is requested, the address for the interrupt service subroutine or other
information to find it is given to the CPU. This information given to the CPU is known as
an interrupt vector, thus giving the name of this technique: vectored interrupts. When
using vectored interrupts, the interrupt service subroutine may be located at any address
in the program memory. The interrupt vector can have a different structure: the simplest
structure is the address of the subroutine. It can also be a number that acts as a pointer
to the subroutine (with the vector, the CPU looks for the subroutine address from a table
of addresses located in memory). Vectored interrupts are widely used in microprocessors
but not in microcontrollers.
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Programming with Single Interrupts

It is comparatively easy to write simple programs with just one interrupt. For success, the
essential points to watch are:

• Start the ISR at the Interrupt Vector, location 0004;

• Enable the interrupt that is to be used, by setting enable bits in the INTCON and/or PIE
registers (PIE1 and PIE2 registers).
• Set the Global Enable bit, GIE;
• Once in the ISR, clear the interrupt flag;  because the interrupt is handling already!
• End the ISR with a retfie instruction;
• Ensure that the interrupt source, for example Port B or Timer 0, is actually set up to
generate interrupts!

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 A Simple
Interrupt
Application with
Single Interrupt

This is the
external
interrupt

Because the
particular
interrupt flag is
set by CPU 13
before.
PRACTICE 5.1
The INTCON Register of a PIC 16F84A is set as shown in a) below.
a) Determine which interrupts are enabled.
b) An interrupt occurs, and the INTCON register is found to have changed to b).
Which interrupt source has called?
c) Which bit must the user change before the end of the ISR?

1 0 1 0 1 0 0 0 INTCON 1 0 1 0 1 0 0 1 INTCON

a) b)

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 PRACTICE 5.2
org 0000
An inexperienced goto start
programmer writes the
code opposite for a org 0014
16F84A to respond to an goto my_interrupt
external interrupt. He
correctly enables the ;this is the interrupt routine
interrupt, and no other my_interrupt movlw 0f
interrupts are enabled. addwf counter1,1
btfsc flags,2 ;test motor run flag
a) How should the clrf overflow
INTCON register be set? return

b) What are the errors in ;Program starts here

the program? start bsf status,5
…

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Moving to Multiple Interrupts – Identifying the Source
As we have seen, the 16F84A has four interrupt sources, but only one interrupt vector. Therefore, if
more than one interrupt is enabled, it is not obvious at the beginning of an ISR which interrupt has
occurred. In this case the programmer must write the ISR so that at its beginning it tests the flags of all
possible interrupts and determines from this which one has been called. This is done by reading
the appropriate bits in the special function registers (INTCON, PIR1, and PIR2)
associated with the interrupt system in PICs. This is shown in the example ISR below.
interrupt btfsc intcon,0 ;test RBIF
goto portb_int
btfsc intcon,1 ;test external interrupt flag
goto ext_int
btfsc intcon,2 ;test timer overflow flag
goto timer_int

portb_int
...
place portb change ISR here
...
bcf intcon,0 ;and clear the interrupt flag
retfie
ext_int
...
place external interrupt ISR here
...
bcf intcon,1 ;and clear the interrupt flag
retfie
timer_int
... 16
place timer overflow ISR goes here
...
bcf intcon,2 ;and clear the interrupt flag
retfie
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A) Context Saving
Because an interrupt can occur at any time, it has the power to be extremely destructive. The
program fragment below is written to illustrate this.
;This subroutine adds two 16-bit numbers, stored in phi-plo, and qhi-qlo,
;and stores result in rhi-rlo. 16-bit overflow in Carry flag at end.
Double_add
movf plo,0 ;move plo to the W reg
addwf qlo,0 ;add lower bytes
movwf rlo
btfsc status,0
incf phi,1 ;add in Carry
movf phi,0
addwf qhi,0 ;add upper bytes
movwf rhi
return

Int_Routine
bcf status,0 ;clear the Carry flag This ISR is
movlw 0ff ;change W reg value written to affect
bcf intcon,intf both Carry flag
retfie and W register
end
The temporary data being used in a particular activity in the CPU is called its context. In the PIC 16 Series
this includes at least the W register value and the Status register. It is clearly important to save the context
when an interrupt occurs. Some microcontrollers do this automatically, but PIC 16 Series microcontrollers
do not. Therefore, it is up to the programmer to ensure that whatever context saving that is needed is done in
the program.
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Protection  Push W register value and the Status register into a pre-designated memory location at the
beginning of ISR and restore the contex at the end of ISR (swapf and movwf instruction are normally
used).
EXAMPLE PROGRAM SEGMENT FOR CONTEXT SAVING
 This subroutine uses registers TEM_W and TEMP_ST to store the contents of the
W and STATUS registers. This operation seems easy to carry out with the
following sequence:
movwf TEMP_W
movf STATUS, W
movwf TEMP_ST

 However, this sequence is not valid because the instruction movf affects bit Z
in the STATUS register, making the value stored in the register TEMP_ST
different from the original STATUS. It is necessary to use instructions that do not
affect any bits in the STATUS register. One of these is the instruction swapf.
Using this instruction, the segment of program becomes:
movwf TEMP_W
swapf STATUS, W
movwf TEMP_ST

 The segment of program that restores the values of W and STATUS before the
subroutine finishes is:
swapf TEMP_ST, W
movwf STATUS
swapf TEMP_W, F 19
swapf TEMP_W, W
What is an interrupt occurred in a software delay
routine, does context saving method helps?
-Delay length would be increased by the duration of ISR.

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B) Critical Regions and Masking

In certain program parts we will not want to accept the intrusion of an interrupt under
any circumstances, with or without context saving. We call these critical regions. We
can disable, or mask, the interrupts for their duration, by manipulating the enable bits
(GIE bit or the particular interrupt enabled bit) in the INTCON register.

Critical regions may include:

• times when the microcontroller is simply not readied to act on the interrupt (for
example during initialization – hence only enable interrupts after initialization is
complete);
• time-sensitive activity, including timing loops and multi-instruction setting of outputs;
• any calculation made up of a series of instructions where the ISR makes use of the
result.

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 The purpose of the interrupt is to attract the attention of the CPU quickly, but
INTERRUPT actually how quickly does this happen? The time between the interrupt
occurring and the CPU responding to it is called the latency. This depends on
LATENCY certain aspects of hardware and on the characteristics of the program running.
This timing diagram shows how the mid-range PIC family responds to an
enabled external interrupt.

Two dummy cycles

are needed to save PC
to the Stack and
reload it with 0004H

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 16F873A Here the minimalist structure of the 16F84A
is seen extended to make something much
Interrupt larger. All interrupts are routed ultimately
Structure through to the single interrupt vector, seen
in the program memory map. The 16F84A
EEPROM Write Interrupt Structure

Parallel
Slave Port
External
A to D Converter Timer 0

USART Receive

USART Transmit

(Master) Synchronous
Serial Port

Capture/Compare 1

Timer 2 Port B Peripheral Global Interrupt

Change Enable Enable
Timer 1

Capture/ Compare 2

Bus Collision
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Comparator
 16F873A INTCON Register

With 15 interrupt sources,

the INTCON register can
only hold a small proportion
of all flags and enable bits.
PEIE is the Peripheral
Interrupt Enable Bit, acting
as a subsidiary Global
Enable, to all those interrupt
sources upstream of the
AND gate it drives. It must
be set to 1 if any of the
“upstream” interrupts are to
be used.

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 16F873A PIE1/PIR1 (Peripheral Interrupt
Enable/ Peripheral Interrupt Request) Registers

To augment the INTCON register, four SFRs are added - PIE1 and PIE2 for enable bits and located in
memory bank 1; and PIR1 and PIR2 in memory bank 0, holding the flag bits. PIE1 and PIR1 each
follow the same pattern, as do PIE2 and PIR2. All active bits are reset to 0 on any form of power up.

bit 7 bit 0

PIE1 PIR1
(Enable Bits) (Flag Bits)
Timer 1 Overflow TMR1IE TMR1IF*
Timer 2 Overflow TMR2IE TMR2IF*
Capture Compare 1 CCP1IE CCP1IF*
Synchronous Serial Port S S PIE S S PIF*
USART Transmit TXIE TXIF
USART Receive RCIE RCIF
Analog to Digital Converter ADIE ADIF
Parallel Slave Port Read/Write** PS PIE PS PIF*
* M ust be cleared in software
** 16F874/7 only. Reserved in 16F873/6
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16F873A PIE2/PIR2 Registers

bit 7 bit 0

PIE2 PIR2
(Enable Bits) (Flag Bits)
CCP2 CCP2IE CCP2IF
Unimplemented read as 0 read as 0
Unimplemented read as 0 read as 0
Bus Collision BCLIE BCLIF
EEPROM Write EEIE EEIF*
Unimplemented read as 0 read as 0
Comparator CMIE CMIF*
Unimplemented read as 0 read as 0
* M ust be cleared in software

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16F873A Interrupt Source and its
associated control bits

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