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ch4 Combinational Logic Circuits

This document discusses digital system design and combinational logic circuits. It covers topics like sum-of-products form, simplifying logic circuits using Boolean algebra and Karnaugh mapping, designing combinational logic circuits using truth tables and examples. It also discusses exclusive-OR and exclusive-NOR circuits, parity generators and checkers, and enable/disable circuits. Finally, it covers basic characteristics of digital ICs, Moore's law, troubleshooting digital systems, and common internal digital IC faults.
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0% found this document useful (0 votes)
31 views90 pages

ch4 Combinational Logic Circuits

This document discusses digital system design and combinational logic circuits. It covers topics like sum-of-products form, simplifying logic circuits using Boolean algebra and Karnaugh mapping, designing combinational logic circuits using truth tables and examples. It also discusses exclusive-OR and exclusive-NOR circuits, parity generators and checkers, and enable/disable circuits. Finally, it covers basic characteristics of digital ICs, Moore's law, troubleshooting digital systems, and common internal digital IC faults.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital System Design

Chapter 4
Combinational Logic Circuits
Thái Truyển Đại Chấn
Sum-of-Products (SOP) Form
• Sum-of-Products We will use

AND term

• Product-of-Sums (POS)

OR term
Simplifying Logic Circuits
• Fewer terms, fewer variables  fewer gates, fewer
connections  more reliable
• Methods:
• Boolean algebra theorems: inspiration and experience
• Karnaugh mapping: step-by-step and systematic
Algebraic Simplification
• A process of trial and error
• Which theorems to be applied
• Whether in its simplest form or can be further
• Two essential steps
• DeMorgan’s and multiplication  SOP
• Checking product terms and factoring  eliminating terms
• Example
Designing Combinational Logic Circuits
Designing Combinational Logic Circuits
Designing Combinational Logic Circuits

• Design procedure
• Truth table
• Write AND term at output = 1
• SOP
• Simplify
• Circuit
Designing Combinational Logic Circuits
• Example
• 3 inputs
• x = 1 when 2 or more inputs = 1
Designing Combinational Logic Circuits
• Example
• z = 1 when the voltage > 6V

With 4 bits we can build the circuit up to 15V

A+BCD
Designing Combinational Logic Circuits
• Example
• z = 1 when the voltage > 6V
Designing Combinational Logic Circuits
• Example: Simple copy machine
• S = 1 when either
• No paper in tray (P = 0)
• Two microswitches are activated
(Q = R = 1)
Designing Combinational Logic Circuits
• Example: Simple copy machine
Designing Combinational Logic Circuits
• Example: Simple copy machine
Using De Moren theorem
tied NAND gate = inverter

we converted NANAD gate to save money


mn
Karnaugh Map Method
Karnaugh Map Method
Karnaugh Map Method
• Graphical tool
• Theoretically, any number of inputs
• Practically, maximum 5 or 6

• Karnaugh map format


• Each case in the truth table ↔ each square
• Horizontally or vertically, adjacent square
differs only in 1 variable
• SOP = ORing the squares with 1
Karnaugh Map Method

• Looping

• Looping groups of two (pairs)


Karnaugh Map Method

• Looping groups of two (pairs)


• Looping a pair of adjacent 1s in
a K map eliminates the variable
that appears in complemented
and uncomplemented form
Karnaugh Map Method

• Looping groups of four (quads)


Karnaugh Map Method
• Looping groups of four (quads)
• Looping a quad of adjacent 1s eliminates the two variables that
appear in both complemented and uncomplemented form
Karnaugh Map Method
• Looping groups of eight (octets)
Karnaugh Map Method
• Looping groups of eight (octets)
• Looping a quad of adjacent 1s eliminates the three variables
that appear in both complemented and uncomplemented form
Karnaugh Map Method
• Complete simplification process
• Construct K map with 1s and 0s
• Loop isolated 1s
• Loop any 2 connected 1s (pair)
• Loop any octet with already-looped 1s
• Loop any quad with non-looped 1s
• Loop any pair wih non-looped 1s
• Form OR sum
Karnaugh Map Method
• Example
Karnaugh Map Method
• Example
Karnaugh Map Method
• Example
Karnaugh Map Method
• Output expression  K map
• Example
Karnaugh Map Method
• Don’t-care conditions
• Some inputs with no specified output levels
• Usually, these input conditions will never occur
• We must decide which x to change to 0 and which to 1
Karnaugh Map Method
• Example
Comparison
Algebraic method K-map
• Trial-and-error steps • Well-defined steps

• Not sure it is the simplest • Achieve the simplest form

• Not strongly limited to the • Practically, limited to 5-6


number of inputs inputs

• Help to understand Boolean • Simply a mechanical


algebra method
Exclusive-OR and Exclusive-NOR Circuits
• Exclusive-OR = XOR
Exclusive-OR and Exclusive-NOR Circuits
• Exclusive-OR
• Only two inputs
• HIGH only when the two inputs are at different levels
• ICs
• 74LS86 Quad XOR (TTL family)
• 74C86 Quad XOR (CMOS family)
• 74HC86 Quad XOR (high-speed CMOS)
Exclusive-OR and Exclusive-NOR Circuits
• Exclusive-NOR = XNOR
Exclusive-OR and Exclusive-NOR Circuits
Is an OR with inverter Is an NOR with a bubble

• Exclusive-NOR = XNOR
• Only two inputs
• HIGH only when the two inputs are at the same level
• ICs
• 74LS266 Quad XNOR (TTL family)
• 74C266 Quad XNOR (CMOS)
• 74HC266 Quad XNOR (high-speed CMOS)
Exclusive-OR and Exclusive-NOR Circuits
• Example:
• Determine the output waveform for
the input waveforms

• Design a logic circuit for a hall light


switch
• For 3 terminals
• For n terminals
Exclusive-OR and Exclusive-NOR Circuits
I

• Example:
• Build a logic circuit to determine if two 3-bit binary numbers
(x1x2x3 and y1y2y3) are equal (z = 1) or not (z = 0)

• Build the logic circuit for 𝑋 = 𝐶 𝐴𝐵 + 𝐴𝐵 + 𝐶


Parity Generator and Checker

• Example: build the odd-parity generator for a group of


3 bits (D0, D1, D2)
Parity Generator and Checker
Enable/Disable Circuits
Enable/Disable Circuits
• Example: build the following circuits
• Switching circuit: Build a logic circuit with 3 inputs (Control, Data1,
Data2) and 1 output X such that X = Data1 when Control = 1 and X =
Data2 when Control = 0
• Switching circuit for 4 data streams and 2-bit control
• A circuit to check an even parity (P) of a group of 4 bits (D1D2D3D4)
and pass D1D2D3D4 to the output (O1O2O3O4) if P is correct, otherwise
output all 0s
• A circuit to check an odd parity (P) of a group of 4 bits (D1D2D3D4)
and pass the inverse of D1D2D3D4 to the output (O1O2O3O4) if P is
correct, otherwise output all 1s
Basic Characteristics of Digital ICs
• Digital ICs
• Collection of resistors, diodes, and transistors
• Fabricated on a substrate (chip)
• Enclosed in a package
• Dual-in-line package (DIP)
Basic Characteristics of Digital ICs
• Package

• Classification by complexity.
Basic Characteristics of Digital ICs
• Moore’s law
• 1965, the number of transistors in a dense integrated
circuit doubles approximately every two years
• 2015, the rate of progress would reach saturation: “I see
Moore's law dying here in the next decade or so”

Gordon Earle Moore (1929) is an American


businessman, co-founder and chairman
emeritus of Intel Corporation
Basic Characteristics of Digital ICs
• Moore’s law
Basic Characteristics of Digital ICs
• Classification by electronic components
• Bipolar ICs
• Bipolar junction transistor (NPN and PNP)
• Transistor–transistor logic (TTL)
• Unipolar ICs
• Unipolar field-effect transistor (P-channel and N-channel
MOSFETs)
• Complementary metal-oxide semiconductor (CMOS)
• Fewer components compared to TTL
Basic Characteristics of Digital ICs
• TTL family
• Several subfamilies and series
• Differing in dissipation and switching speed
• Not differing in pin layout or logic operation
• Example: hex INVERTER
Basic Characteristics of Digital ICs
• CMOS Family
• Many with same logic functions as the TTL family
• Not always pin compatible or electrically compatible
Basic Characteristics of Digital ICs
• Power and ground
• DC power and ground
• VCC (Voltage at the Common Collector) for TTL
• VDD (Voltage Drain-to-Drain) for CMOS
• Logic-level voltage ranges
• VCC = +5V
• VDD = +3 to +18V
Basic Characteristics of Digital ICs
• Logic-level voltage ranges
Basic Characteristics of Digital ICs
• Unconnected (floating) inputs
• A floating TTL input = HIGH (logic 1)
• However, extremely susceptible to picking up noise signals
• Measures a dc level of between 1.4 and 1.8 V
• A floating CMOS input = disaster!
• Overheated and eventually destroy itself
• Measures as fluctuating randomly
Basic Characteristics of Digital ICs
• Logic-circuit connection diagrams
Basic Characteristics of Digital ICs
• Logic-circuit connection diagrams
• Logic diagram using schematic capture
• No pin numbers or chip designations
• Will be “programmed” into a PLD
Troubleshooting Digital Systems
• Three basic steps
• Fault detection
• Fault isolation
• Fault correction
• The procedure highly depends on
• The type and complexity of the circuitry
• The kinds of troubleshooting tools and documentation
• Do as much troubleshooting as possible
• Develop the analytical skills
• Describe the types of faults that are common to systems
• Present typical case studies to illustrate the analytical processes
Troubleshooting Digital Systems
• Logic probe
Internal Digital IC Faults
• Malfunction in internal circuitry
• The outputs do not respond properly TTL INVERTER circuit
to the inputs
• This failure is not common as the
following ones
Internal Digital IC Faults
• Inputs internally shorted to ground of supply
Internal Digital IC Faults
• Outputs internally shorted to ground of supply
Internal Digital IC Faults
• Example
Internal Digital IC Faults
• Open-circuited input or output
Internal Digital IC Faults
• Open-circuited input or output
• If there is an externally open circuit between Z1 pin 4 and Z2
pin 1, a TTL floating input should measure indeterminate (1.4
to 1.8 V)
• Z2 pin 1 has been probably disconnected inside the NAND
chip
Internal Digital IC Faults
• Short between two pins contention

three different levels  two output


signals may be shorted together
External Faults
• Open signal lines
• Causes
• Broken wire
• Poor solder connection; loose wire-wrap connection
• Crack or cut trace on a printed circuit board
• Bent or broken pin on an IC
• Faulty IC socket
• Not good contact between IC pin and the socket
• Checking
• Disconnecting power
• Careful visual inspection
• Checking for continuity with an ohmmeter
External Faults
• Example

• Must to an open circuit between Z1-6 and Z2-2


• Can use logic probe to trace the opening along the path
External Faults
• Shorted signal lines
• Causes • Checking
• Sloppy wiring • Careful visual inspection
• Solder bridges • Use an ohmmeter
• Incomplete etching
External Faults
• Faulty power supply
• Causes
• A fault in internal power circuitry  not provide regulated supply
voltages (lower, higher, …)
• The logic circuit draw more current than normal
• Signs
• Some ICs are not working correctly
• Some ICs are more tolerate to power supply variations
• Checking
• By an oscilloscope
• For AC ripple, regulated range, …

• Output loading (fan-out)


Troubleshooting Case Study
Troubleshooting Case Study
• Possible causes
• An internal component failure in Z1
• An external short to VCC from X
• Z1-3, Z2-5, or Z2-13 internally shorted to VCC
Troubleshooting Case Study
• Checking
• Are VCC and ground are correctly applied to Z1
• Turn off power
• Use an ohmmeter to check for a short between X and VCC
• Visual examination for solder bridges, un-etched copper slivers,
un-insulated wires touching
• Remove it and use the ohmmeter to check again
• Disconnect the 3 pins Z1-3, Z2-13, and Z2-5 from X, one
at a time
• Check for a short to VCC
Troubleshooting Case Study
• Summary of all faults
Programmable Logic Devices
• Designing combinational digital circuits
• Construct the truth table
• Write the Boolean expression
• Simplify the expression
• Build the circuit
• These steps are probably tedious, time consuming and
error-prone
Programmable Logic Devices
• Programmable logic devices
• These tedious steps can be done by a computer and PLD
development software
• Improve the efficiency
• The jobs of the circuit designer
• Identify the inputs and outputs and their relationships
• Select a PLD
• The concept behind
• Put lots of logic gates in a single IC
• Control the interconnection of these gates electronically
How do we control the interconnection of gates
in a PLD electronically?
Programmable Logic Devices
• Switching matrix
• A switch at each
intersection
• Mechanical switches,
• Fusible links,
• Electromagnetic
switches (relays),
• Transistors
Programmable Logic Devices
• Programmable array
• Programming a PLD
• Makes the actual
connection in the
array
• Determines
• Which connection to
be open
• Which connection to
be close
Programmable Logic Devices
• How to “program” a PLD IC
• Remove the PLD IC chip from its circuit board
• Place the chip in a programmer
• Connect the programmer to a computer with software
Representing Data in HDL
• Numeric data can be represented in various ways
• Hexadecimal no. is convenient for bit patterns
• Human prefers to use the decimal number
• Computers and digital syst. can operate only on binary
• So far, we use a subscript to distinguish:
• 1012, 10116, 10110, 101BCD
Representing Data in HDL

• Example
• Express the following bit pattern’s numeric value in binary,
hex, and decimal using AHDL and VHDL notation
• 10011
Representing Data in HDL
• Bit arrays/bit vectors
• When input, output, or signal consists of several bits
• A unique number to describe the bit’s position
Representing Data in HDL
• VHDL bit vector declarations
• PORT (p1 :IN BIT_VECTOR (7 DOWNTO 0);
• Intermediate signal
• SIGNAL temp :BIT_VECTOR (7 DOWNTO 0);
• BEGIN
• temp <= p1;
• END;
Representing Data in HDL
• VHDL bit vector declarations

• Libraries: standardized data types, …


• Macrofunctions: convenient functions, …
Representing Data in HDL
• VHDL bit vector declarations
• STD_LOGIC values
Truth Table Using HDL
• Truth tables using VHDL: Selected signal assignment
Truth Table Using HDL
• Example:
• Declare three signals in VHDL that are single bits named
too_hot, too_cold, and just_right. Combine (concatenate)
these three bits into a three-bit signal called temp_status,
with hot on the left and cold on the right.
• Solution
• SIGNAL too_hot, too_cold, just_right :BIT;
• SIGNAL temp_status :BIT_VECTOR (2 DOWNTO 0);
• BEGIN.
• temp_status <= too_hot & just_right & too_cold;
• END
Decision Control Structures in HDL
• The order
• Concurrent: the order does not matter
• Sequential: the order matters
• If/Then/Else using VHDL
• An integer can be compared with other numbers using
inequality operators
• A BIT_VECTOR cannot be used with inequality operators
Decision Control Structures in HDL
• If/Then/Else using VHDL
Decision Control Structures in HDL
• Elseif using VHDL
Decision Control Structures in HDL
• Case using VHDL
Decision Control Structures in HDL
• Example: Coin detector
• A coin detector in a vending machine accepts quarters,
dimes, and nickels and activates the corresponding digital
signal (Q, D, N) only when the correct coin is present.

• It is physically impossible for multiple coins to be present


at the same time.
Decision Control Structures in HDL
• Example: Coin detector
• A digital circuit must use the Q, D, and N signals as inputs
and produce a binary number representing the value of
the coin
• Write the AHDL and VHDL code.
Decision Control Structures in HDL
• Example: Coin detector

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