School of Engineering and

Physical Sciences
Advanced Analogue Electronics

Analogue Digital Conversion

Dr. Mutasim Nour

[email protected]
 Analog to Digital Converter
ADC
• An Analog to Digital converter [AD or ADC] is a circuit which
accepts an analog input signal (usually a voltage) and produces
a corresponding multi-bit number at the output.

• Once captured – time becomes irrelevant

– i.e. does not need to be processed in realtime.

• Analogue interface has to have accuracy to < +/- ½ LSB

• Conversion process takes time, therefore frequency dependent

• Nyquist criteria.
 Conversion Chain

Transducer Analogue signal ADC

processing
World

Actuator DAC DSP

Display

ADC, analogue to digital converter

DAC, digital to analogue converter
Here is an example of a 3-bit A/D converter.
Because it has 3 bits, there are 23 = 8 possible
output codes. The difference between each
output code is VREF / 23.
 Analogue to Digital Converter
ADC is a device which converts a continuous time signal into discrete
representations. The analogue input is compared with a known voltage reference
and produces a coded digital number representing that voltage. Thus the
conversion process introduces quantisation error in that changes in the
continuous time signal < the quantisation error are lost because the digital
representation only has a finite number of codes. The more bits that are used the
finer the resolution and the lower the quantisation error.

When the input reaches VREF/8, the output code

changes from 000 to 001, where the output exactly
represents the input voltage and the error reduces to
zero.
As the input voltage increases past VREF/8, the error
again increases until the input voltage reaches VREF/4,
where the error again drops to zero.

This process continues through the entire input range

and the error plot is a saw tooth.
5
The Least and Most Significant Bits (LSB and MSB) are just what their name
implies: those bits that have the least weight (LSB) and most weight (MSB) in a
digital word. For an n-bit word, the MSB has a weight of 2(n-1) = 2n / 2 where “n”
is the total number of bits in the word. The LSB has a weight of 1.
Since one LSB is equal to VREF / 2n, it stands to reason that better accuracy (lower error)
can be realized if we did either (or both) of two things:
(1) use a higher resolution converter and/or (2) use a smaller reference voltage.
The problem with higher resolution (more bits) is the cost. Also, the smaller LSB means it
is difficult to find a really small signal as it becomes lost in the noise, reducing SNR
performance of the converter.
The problem with reducing the reference voltage is a loss of input dynamic range. Again,
we also can lose a small signal in the noise, causing a loss of SNR performance.
7
If we add 1/2 LSB offset to the ADC input, the output code will change 1/2 LSB
before it otherwise would. The output changes from 000 to 001 with an input
value of 1/2 LSB rather than 1 LSB and all subsequent codes change at a point
1/2 LSB below where they would have changed without the added offset.
 Sample and Hold Devices

• Some A/D converters require the

input analog signal to be held
constant during conversion, (eg. Sampling
switch
successive approximation devices) Output
Signal
Analog Input
• In other cases, peak capture or Signal
Hold
Capacitor
sampling at a specific point in time
necessitates a sampling device.
• This function is accomplished by a
sample and hold device as shown to
the right:
• These devices are incorporated into
some A/D converters
 Sampling Frequency
• Sampling frequency > 2 * maximum signal
frequency (Nyquist criterion )

• If components exist outside the signal range they

must be attenuated by analogue filtering to <
Vpeak/2n , where n is number of bits
 ADC Uses
• Process control measuring real world (analogue
) signals e.g. pressure, flow, speed
temperature… for signal processing

• Digital audio for mixing and storage

• Measurement and sensing many other

analogue signals
 Coding
Coding schemes
Input voltage 8 bit offset binary 8-bit 2s compliment
FS 1111 1111 0111 1111
FS-1 1111 1110 0111 1110
..
..
+LSB 1000 0001 0000 0001
0 1000 0000 0000 0000
-LSB 0111 1111 1111 1111
..
..
-FS+1 0000 0001 1000 0001
-FS 000 0000 1000 0000

Please make sure you remember this

 From Analogue into
Digital
Types

• Flash
• Slope integrators
• Successive approximation
• Delta-sigma
• Voltage to frequency
 Flash Converter
• Input voltage is digitised in one cycle
• Requires 2N-1 comparators for N bits
• Cumbersome above 6 bits therefore has to be pipelined
• Extremely fast > 1G sample/s
• Power hungry
• A flash ADC is the fastest conversion time. The analogue
is compared with (2n-1) references voltages with 2n-1
comparators

• Each reference voltage is 1 discrete steep = Vref/ (2n-1)

above the reference on the lower string. The output code
generated by the comparator string is decoded into the
output data word using the decoder.

• The response time to change its input is the time it takes

for the comparators to respond and the propagation delay
of the decoder.

• Applications : Digital oscilloscopes, software radio, radar

processing
 A/D – Flash Conversion
• A multi-level voltage
divider is used to set 1V
voltage levels over the 3R Comparators
13/16 V
complete range of
+
2R
conversion.
-
11/16 V +
2R
• A comparator is used at -
9/16 V
each level to determine 2R
+

whether the voltage is 7/16 V

-

lower or higher than the

+
2R Encoder 3
-
level. 5/16 V +
2R
• The series of comparator 3/16 V
-

outputs are encoded to a 2R

+

binary number in digital

-
1/16 V +

logic (an encoder) R

-

Vin
 ADC - Dual Slope Integrating

•Independent of clock rate N bits

output
•Can integrate over period of
interference say 20ms therefore
can offer high interference
rejection
•Slow but accurate up to 20
bits available
•Usually used for display
meters. Clock input
 ADC - Dual Slope Integrating

• Initially, the capacitor is discharged and so has no voltage

across it.
• At time 0, the input to the integrator is switched to the
analogue input and the capacitor is allowed to charge for an
amount of time, T1, which is always the same.
• Its rate of charging and thus its voltage at T1 are
proportional to the input voltage.
 ADC - Dual Slope Integrating
• At time T1 the input switch flips over to the voltage reference,
which has a negative value so that the capacitor will begin to
discharge at a rate proportional to the reference.
• The counter measures how long it takes to discharge the
capacitor completely. the ratio of the discharge time to the
charge time is proportional to the ratio of the input voltage to
the voltage reference, and so the counter output represents
the analogue input voltage.

19
 Successive Approximation

1. Sample held
2. MSB of SAR (successive
approximation register) is set to
1
3. DAC converts SAR output and
compares with input
4. If comparator still high MSB
remains set to 1 and next MSB
set and compared again
5. Loop to 3 for N bits
 ADC - Successive Approximation Conversion

• Successively approximate input

voltage by using a binary search and a Test voltage
DAC (DAC output)

• SA Register holds current

approximation of result Analog
Input
• Repeat 100110

Voltage
100100
– Set next input bit for DAC to 1
100000
– Wait for DAC and comparator to
stabilize

100110
10011x
100xxx

1001xx
10xxxx
– If the input is larger than DAC output

1xxxxx
(test voltage) then set the current bit
to 1, else clear the current bit to 0

000000
T1 T2 T3 T4 T5 T6
Start of Time
Conversion 21
 SAR Process
• Process to convert Vin = Vref

0.69 to 10110 = 24 + 22 +2 =
22/31 = 0.71
• Where Vref =1 V = 31 adc 3/4 Vref

output . 0
1
0
1 1

• 5 cycles 1

•Converters – medium speed up 1- 2 MHz 1/2 Vref

•16 bits maximum

Vref = 1 Volt
• First approximation is Vin > 0.5 Vref ( generated by DAC) = 1 1/4 Vref

• Second approx. Vin < 0.75 Vref =0

• 3 approx
rd Vin > 0.625 Vref =1
• 4th approx Vin > 0.0.687 Vref =1
• 5th approx Vin < 0.718 Vref =0
0
MSB 4 3 2 1 0
 Voltage to Frequency

1. Comparator at V+
2. D1 reverse biased
3. Integrator ramps –ve
4. Rate, therefore time,
determined by Vin
5. When integrator
reaches –V+(R1/R2)
switches –ve Vin
discharging C via R3
6. R3 << R
7. Count pulses
• The simplest converter
• Always monotonic

Number of pulses over a fixed time ∝Vin

 Delta-Sigma Converters

Please see the hand written notes on ADC/DAC on

Vision
From Digital to Analogue
DAC
 Simple DAC

MSB b3 R
2R
b2
4R - V0
b1 +
8R
LSB b0

V0 = −(b3 + 0.5b2 + 0.25b1 + 0.125b0 )

V0 = −0.125 × ( 23 × b3 + 2 2 × b2 + 21 × b1 + 2 0 × b0 )
Where b3, b2, b1,and b0 are digital inputs.
MSB: Most significant bit
LSB: Least significant bit
 Problems With Simple DAC
• Requires too many different resistors for larger
number of bits.
• Very large resistance are needed for lower
significant bits, creates extremely small input
current to op amp.
• The input voltage sources have to be matched with
the same high and low values of resistors.
 Summing Digital to Analogue
Converters

• Voltage
R/2R Ladder Network
V3
R 2R
V2
R 2R
V1
R 2R
V0
2R 2R

V1=2V0, V2=4V0, V3=8V0

 DAC With R/2R Ladder

V3 2R
R
R 2R
V2
R 2R -
V1
+ Vanalog
R 2R
V0
2R
b3 b2 b1b0
Vanalog = −(b3V3 + b2V2 + b1V1 + b0V0 ) / 2
= −V0 (8b3 + 4b2 + 2b1 + b0 ) / 2
= −V0 ( 23 b3 + 2 2 b2 + 2b1 + b0 ) / 2
 Current summing DAC

• Current

0 1 0 1 1
MSB
Example b4 – b0 are set
ADC errors
• Offset
• Gain
• Non-linearity

32
Speed: needs to be faster than
Vout Offset error
signal frequency Offset
Resolutions: output step size.
Determined by num. of bits.
Accuracy: errors. See graphs.
Input Word
001 010 011
Gain error Vout Non-linear error
Vout
Gain error

Input Word Input Word

001 010 011 001 010 011
Actual Ideal
 Conversion Errors

These errors occur for ADC’s and DAC’s alike.

• Offset :Offset code offset by amount at zero

input/output (ADC/DAC) voltage.
• FSD (gain): Full scale deflection at V max not equal
to FSD as a digital number
• Non-linearity : change in code with voltage not linear
• Monotonicity : same voltage produces ambiguous
code
OFFSET ERROR
This is defined as the deviation between the first actual transition and the first ideal
transition. The first transition is when the digital output of ADC changes from 0 to
1. In an ideal case we should get a digital output of 1, when the analogue input is
between 0.5 LSB to 1.5LSB. The first transition in an ideal case will be at 0.5
LSB. Offset error is represented as EO