Module 6:

CMOS Sequential Circuit Design

 Outline

Conventional CMOS Latches and Flip Flops

Pulsed Latches
Resettable and Enabled Latches and Flip Flops
 Sequencing
Combinational logic
output depends on current inputs
Sequential logic
output depends on current and previous inputs
Requires separating previous, current, future
Called state or tokens
Ex: FSM, pipeline
clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

 Sequencing Cont.
If tokens moved through pipeline at constant speed, no sequencing
elements would be necessary
Ex: fiber-optic cable

Light pulses (tokens) are sent down cable

Next pulse sent before first reaches end of cable
No need for hardware to separate pulses

But dispersion sets min time between pulses

This is called wave pipelining in circuits

In most circuits, dispersion is high

Delay fast tokens so they don’t catch slow ones.
 Sequencing Overhead
Use flip-flops to delay fast tokens so they move through
exactly one stage each cycle.

Inevitably adds some delay to the slow tokens

Makes circuit slower than just the logic delay

Called sequencing overhead
 Sequencing Elements
Latch: Level sensitive
transparent latch, D latch
Flip-flop: edge triggered
master-slave flip-flop, D flip-flop, D register
Timing Diagrams
clk clk
Latch

Flop
D Q D Q

clk

Q (latch)

Q (flop)
Bistable Circuit
Bistable Circuit
Metastability
S-R Latch
D Latch
D Latch
 Latch Design

Pass Transistor Latch

Pros 
+ Tiny
D Q
+ Low clock load
Cons Used in 1970’s

Vt drop
dynamic
output noise sensitivity
diffusion input
 Latch Design


Transmission gate D Q
+ No Vt drop

- Requires inverted clock


Inverting buffer
X
D Q
+ Fixes

Output noise sensitivity 

D Q
Inverter at the input 
+ Fixes diffusion input (reduces
noise)
 Latch Design

Tristate feedback 
X
+ Static D Q

Static latches are now essential 



because of leakage


When the clock is 1, the input transmission gate is ON, the

feedback tristate is OFF, and the weak latch is transparent.

When the clock is 0, the input transmission gate turns OFF.

However, the feedback tristate turns ON, holding X at the
correct level.
 Latch Design

Buffered output  Q

+ No backdriving D
X




Widely used in standard cells 

+ Very robust (most important)

- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading
 Latch Design

Datapath latch  Q

+ smaller D
X
+ faster 

- unbuffered input


 Conventioanl Flip-Flop Design
Flip-flop is built as pair of back-to-back latches
 
X
D Q

 

  Q

X
D Q
 
 

 
 Pulsed Latches
A pulsed latch can be built from a conventional CMOS transparent latch driven by a brief
clock pulse.
 Enabled Latches and Flipflops
Enable: ignore clock when en = 0
Mux: increase latch D-Q delay
Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
 en

 

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

 en


 D 1
Flop

Q
0
Flop

Flop
D Q D Q
en
en
 Resettable Latches and Flipflops
Force output low when reset asserted
Asynchronous reset forces Q low immediately, while synchronous reset waits for the clock.
 
S ym bol

Latch

F lop
D Q D Q

reset reset
S ynchronous R eset

 Q   Q

reset reset
Q
D D
 

  

 


Q
Q 
A synchronous R eset

 
reset
reset
D
D 
 

 
reset
reset




Synchronous reset simply requires ANDing the input D with reset.

Asynchronous reset requires gating both the data and the feedback to force the reset
independent of the clock.
 Set / Reset
Set forces output high when enabled

Flip-flop with asynchronous set and reset



reset
set Q
D




set
reset


 Sequencing Methods
Tc

Flip-Flops
clk
Flipflops: Tokens advance from one cycle to
clk clk
the next on the rising edge. If a token arrives
too early, it waits at the flip-flop until the next

Flop

Flop
Combinational Logic

cycle.

2-Phase Transparent Latches

1
tnonoverlap tnonoverlap
2-Phase Transmission Latches: At any Tc/2
2
given time, at least one clock is low and the
corresponding latch is opaque, preventing 1 2 1

one token from catching up with another.

Latch

Latch

Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1

Pulsed Latches
Pulsed Latches: eliminate one of the p tpw

latches from each cycle and apply a brief p p

pulse to the remaining latch.

Latch

Latch
Combinational Logic
Setup and Hold Time
 Timing Diagrams
Logic Prop. Delay Contamination and Propagation Delays
tpd

Logic Cont. Delay A tpd

tcd A
Combinational
Y
Logic
Y tcd

Latch/Flop Clk->Q Prop. Delay clk tsetup

tpcq clk thold

Flop
D Q D
tpcq
Latch/Flop Clk->Q Cont. Delay Q tccq
tccq
clk tsetup thold
clk
tccq tpcq
Latch

Latch D->Q Prop. Delay D Q D tpdq

tpdq tcdq
Q

Latch D->Q Cont. Delay

tcdq
 Max-Delay: Flip-Flops
clk clk

Q1 D2
Combinational Logic
F1

F2
Tc

tsetup
clk
tpcq

Q1 tpd

D2

OR
Max Delay: 2-Phase Latches
1 2 1

D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L3
L2
Logic 1 Logic 2

1

2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

OR
 Max Delay: Pulsed Latches
p p

D1 Q1 D2 Q2
Combinational Logic

L2
L1
Tc

D1 tpdq

(a) tpw > tsetup

Q1 tpd

D2

p

tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2

OR
 Min-Delay: Flip-Flops

clk

Q1
CL
F1

clk

D2
F2

clk

Q1 tccq tcd

D2 thold
 Min-Delay: 2-Phase Latches
1

Q1
CL

L1
2

D2
L2

tnonoverlap
1

tccq
2

Q1 tcd

D2 thold

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.
But a flop is made of two latches!
 Min-Delay: Pulsed Latches
p

Q1
L1 CL

p

D2
L2

p
tpw
thold

Q1 tccq tcd

D2

Hold time increased by pulse width

 Time Borrowing

In a flop-based system:
Data launches on one rising edge
Must setup before next rising edge
If it arrives late, system fails
If it arrives early, time is wasted
Flops have hard edges
In a latch-based system
Data can pass through latch while transparent
Long cycle of logic can borrow time into next as long
as each loop completes in one cycle
 Clock Skew

We have assumed zero clock skew

Clocks really have uncertainty in arrival time
Decreases maximum propagation delay

Increases minimum contamination delay

Decreases time borrowing

 Skew: Flip-Flops
clk clk

Q1 D2
F1

F2
Combinational Logic

Tc

clk
tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1
F1

CL

clk

D2
F2

tskew

clk
thold

Q1 tccq

D2 tcd
 Skew: Latches
2-Phase Latches 1 2 1

D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
Logic 1 Logic 2

1

2

When the clocks are skewed because the data can

still arrive at the latches while they are transparent.
Therefore, we say that transparent latch-based
systems are skew-tolerant.

However, skew still effectively increases the hold

time in each half-cycle.
 Skew: Pulsed Latches
Pulsed latches can tolerate an amount of skew proportional to the pulse width.

If the pulse is wide enough, the skew will not increase the sequencing overhead because
the data can arrive while the latch is transparent.

If the pulse is narrow, skew can degrade performance.

Draw the timing diagrams of the path shown in Figure 2 and Calculate the maximum 10 and minimum delay of
the combinational logic for a clock pulse of time period 500 ps.