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Literiny, —D boatganst aed vaay be prdondi fe thet en Mok vodebly y A'S iN Coy on “yy! | Bd Bee Lomptinn DV | Pv Beads ut a foe gs rae a 4 ; fo wpm city Nn Banat peat rath = — z DF = octyl : asta LL. = Shp 4% Bisd i drrat = (oles) = taldy as) 9) Fre ty! es J Fiaad zg a £ mt (Yea etyes) ‘sap z at plencus- tu _btvrals _ oe a tpaely egy tCovfrl er Fe wy - , Mow a RA | F dud Aide f | ! J Lat +3! x) = Uy a yy! e Keyl) Cy'ry) rae” ct 4) — Batbobad ve Ue Rha te gtk— (Clea) 9 (HOB 0a)! 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Maes. me 219 (9, 2,2, 8, 6) I T —_>-- + a oo esses, Gare LEVEL =MivViMi ZATION 2 ft Maral wanton Di Be hag tase 5, Dow ofrbnral gate -Gwvel trrfotene enitalren eat Bortran dwwetions drcerbrg a obgital Xe ae > lo whites Lord Logic ig ateoen, deel ee sah & Large at gf Besbran eyratrons Yficrentey Graney: P Mevrtosleas, A is Abt Imipusank Drak fe hegre Werk duit te nndlay ag wal Be . Cb fads on owed luton f the gah 2a Wala procline. é pres, THE _map METHOD eulogy “aif. ee po a Avwple, PPadopdle nests Eisen ad tes Kara. woah ox Kamiah _ > Thy Omapplified tphetrors Toke odwecl by tru wrop Whe __ alias in one he two Ataudarot — pd of —febadoncls Om Phadvect- of Ausns: ____ The re hae Dnt ind wa _aodlptacesct Agandis_ _ é hi lA le = “ yf 7 = lea fe i as — : Mt I ot ty rs of aye = ky yey) = te SAYS + . = wb s | Bite Rojacnd dy Laat rong Be torial! cof | alesis _Ayfphutrant spive petit he, _ ' A hy Be | 2 a Ades Bag apc te Logit ta ( 18Swpbdy tu __folleroreg Breobeove [vaveheeny, & wing Ke va DEC 4.) = EO 8, 499 Solute Enis 4 a + neu + y's y eceern =eA| xy ‘ “5 U tt * _ TS ie 2 i - Fy = oy aly 2 Fludiyy » = (3,46 7) Og ght oy 4,0 7 Ur,. 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SE Met Met Maat ge hank My Sie loves _—> E(w, 4 Ys) = FL, 3,8,4, 10,11, 1,18, Ws B a _ wtb —Fk hatte 2 44 Vota 7 eat dds Bat aaug thal 4 _ Ol eae Pe “i, Mahe atavits ob,”oy pakonecem find \ Gena pane J waplivonits Ord, Usuod al forma tnaph ants ) F(A,8,¢, DI £(0,2,3,5,7,8,9, 10,14 13,15) Be cD ne CP? \ cD / BAD, BD, BC, cd loot ZB, ED A _ 75 14,10, 134,15) EAL HH, WALAe HM MyM &ita = Dow! = cage CoNDITIONS _ eit ——} Bae Xs ated ——~ Depajiment 83 [A deh dare _pentitnn vt_a bse Logica Vad via rot Apecped —teahanguit tu _dlowit torn dit ts teie_tha Noles 0a a ged ta ee epee a —— Cr —__ |} rel oe] ~ ) ——— Sly the ls an Beckman feo Le ors a ee aes i 4 5 re Le it Fb 4, Yi de tz 4% q = 2 ECS ipa = 2 ee EC S6 70) ERTCEATS) tone : PE VF] —_ veal (op ext . F x p a ro FO, 45) = Hatag 25NAND AvD Nox TMPLEME VTAT LAME DP orto RUST Wh {Aeguter Aoviuebeol 9 IK. NAVD dard tok Satis thom pith AND Dvd Of. gata. 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Wap! + ge yl + ad bet pore WYyvo x oy & xy 0 "Tnwie wa's0 a filo, te tote Barsneti on Lad £0 e _ 7 Tooltips ot D|Coers! } aaa + De : tpanrelriy a footie ct aly a ol) ot abe Oia cee ocean pw | 0 satya pilaltat yt ams Bis) doe = aad a ry z Ldntty Mele f — wobovlcan P LLUass, = MYL YX) Wprewens ta a \ Z 9 Sx REP wraa, | Lubive Crpanyan) 1D (Wt oe) wt Coy) Cove Pee Le) = entire — F(A eg + oes pedya) [lo 4 - Balaet . __ | Rea na oft L__sditond, iv Cum tnae devsnat ne ol+ t=] nok gampes |= Dom Pweg] = Audie teste Pera (5) [Fina oa_faapcaill $ ty fellas Seas a A er Ww My Ty Ww YS tyvy = i 4 = wis! (x4 ow!) « wy! = Lae bt wy Comm = nn Diy A Zz 2 eats. AE eS bitobt «| = wy) a Mont ation (11> | = wy! = AN Bte Fe poe. -Lthas © oy Doge gy Dea _deral =) (4g) Cait yle y') _ | Gy) eripleent =) faery 3) (oc yt 9) 2 go Lethal: fang,’ easy’ ihe (outages 617 Coes yet g) »| oer YOM BD) (ae a) . fade dual =) (904) 4 Cys eCard 3) (opment oy + vy! A ghoe. ; Cry) (yt gi au) = oy aul, 4 3 O| Waters (rey eg) —- : (od n'a ot mayas) 7 = Oven) [wlt abyss abuns ity 24 eoe ae jrit, AND, of, pind het Yea Hy Ww Thplntn i hata npetion dnctu Fe oly pny! acy» —a re > i Ai art ao Da She Het maa O| Wile Nok dud snviti gates Farry, b, Fo Pay!) a(n'ay)! a (aay HM {ft e 9" Co at [a T “. : Ht ae Gea Olay) Homes? a ye : Daal r+ L lag!CPT Ole —_ yo Te et fi rx ede P50 Ewen a h Bur ne ¢ = Moe yng] pe AVSe ke [Sy Be fees foment 9 YA Selano= Ste ieee J c be / be be 7 eit M1 alt ty Bra DEa.b Oz ap)! BLS, é) | Ty ed a L | Fepy @ -|2) F(a, 40 = 20,4556 7) \@b ab ab ob) 2 a “4 1 feats Of I I Cl s.sg7) bc 4e See) fA s Feng § oe 654,89) |p ae” | a act] x CEOS} | Fo Hyp nye x‘LAKSHYLR, ene 102520! agsuant olazzor Few pede oe + Myst ays. py lg ey gl + tel, 4. ont Zalylye ay A aly ye 4 ay 4) Ys 4 (oo) cuoy "Conrad ora sm dt yay mtg 2 EU, 36,7) 434 ME 4 + pert x Qt 5 7 : + sty til v ” : o 7 1) F (ou, 415) = Hy she ly! + 5A SAY 4 4 Cot Walp ealteaDi z = ony fg acyl a alyl gy ty, boat yl (ire) = (roe) (999) (117 _Co1) =__WMg_koiinye tg + ty pt = 3 (0,n ee De X is poe \ 43 a ; ali {— t ato $ : Me eee Ps 44 t i Ve a Fiamal= ete ty t op g! ie = allt soy ag) flew)y g) aay, toby’ boyy say gk ale) Qu! (roy) (100) (us)._. fore) 2 gd wet Wty ty hy she, 451)” 2 nes Fo eGo age ary14, a, + flCs 4a) Pt Loe 5 ! \ L yi a a tga ~~ Boyle acyl OT or - 4 = lyin) gl tay a) _ of l44 99 or y+ \ a >) wr ON eS Hee ea ae aE i Fo ObE + 5c 4 ad Zhe 4 06d" [28) Fla, Ca) =¥(o ECA, 469,018 36° 5 Cdn ‘ a ied E LZ a ‘age ss a aC A eas = ee a KD os} iS ab{ 10 . ? wo | ab] CPD > be +abcd xadeahe Froad+ean abdFO b,c,a)= cdo LO}, 2, 446, 9,4) MMA Rae CE Cee el 4) = 01 2, 3,6, FQ.b fod) 2 E486, 7,3, 0)4)19| 6,4, BAe ta if cd ry i” aS { 1 mee ero wala h Ty as) On (45, co) = Ero 958 6,1, 4/3) a tA cheer [PE A4 Tidemc oe wABco's ade +aco'r Aged + Bled aly = Ane! + Aden tacico! (Lree) (row) (tor) tApe'ps alvletD + Anied (oot) (p00) Gon? NE (4,5, C a= E001, 218, 9,15) +Adelp + aldcid + (too) (.d001) SBS oo!) E ta td Ca ea = ab |GA_1 | 1 | D 2 E(48,4, 10} 11) Bb io a ae. co ce IK abl -\\0 At Vf oy _ ab] | As fem | FaECd 4+ brdtab eee | 2 fo : = as [A [O\l * LBD ABC osre ugly! O00G + |e wy bbboty st ayy 4 ayy 4 a) ee + thalis + Gott!) Y's 4 Pa Ro eS pee a tore. eA Jp 2 Heat's 2 ala lady) Watyg a wyad walt wily oon Pel oea) pe wong + “Hig pt ad yly! lacy wary) Uoe loo D100 rrr ee a ccm p= Bs Qo bry 1) FAA Ha By, _ : 29 A\a\eo 4 Alge 4. c'p tABcDy Agle zAlshep « Alsc> + alacal + ‘AbC'D + Ale Daals ip tAlelids aaco a Abed’ anlen! tMit4 oirs tot Yay My & My om, Gas S— 5 SoG +92 809+ — Ax Fag] = tro. | : = 2 (A+8): (6+9)+ i ’ Cane xc) Lv | Fabre 29@ a) é a. S| DAaw am _ dec ge dingane snag towb topasl a ——| Jats _th_ ae! ae F(ab, d) wis ash es | (Ce 7a Efpeot fo — [abe SAB Lee Coli sad) Teac) oy + AY nd Sinplaniaddte [p= [Cate oui)" Cela xed!) — (Pe = [cote gon) # Cod aca’) ee tim —+ pg a ee - ico! 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D! a Al acy) 4 a'gclp + al Bop pagco'4 ACD t_Agiep! + paseo 5 d 0006 & 000! 4 OO/i+ Ol!l +0000 #0100 + O1ol+oil + Mo +t Loto +10, £ (0,13, 4.5 Tall, 0, co eA a | | (1 \ " ag WON Ag [ayy as | | [Ly : cH EP cD co oF ppb | Lira =|] | a als) |[> ay] |S 4 q Na GALLI = Se Department of Computer Science and Vnginee Viton: renait better Cpr teal Hoa We BCS302 ~1 igital Desi en and Computer Organiza Module t~ Introduction (0 Digital Design HARDWARE DESCRI PTION L, ANGUAGE § (HIDES) Computerstased ¢ OOK 10 Fedtce costs nd vi he sk ot creating w Mave dein | ©All modem des ct 28 Hanes des ilomnimge de + desi, and test a | circuit in sonware betiore Wisever manutictured 2, AM hardware description famgnage (HDL) ig a hardware oF digital systems ing ‘esta fori, © Before the advent or HDL designers relied on Sehomnties oF block Present and speeity a circuit, That methodology: is cirenits, 7 ABEDL is a modeting tne rather {hin Weomputational Wngupe + ANDI tes 2 Qeabatty Com pater programming ty ne, Fs Oriented to describing hardivngg Stimelures und the behavior of hie © I can be tied to represent ngis stlograms, truth abstractions of the behavior ofa digit © MDL describes ce Pelationship be Mat are the outpuis of thesciveniy, Sy As a documentation tanyoge, an HDL, iy Used 0 re form that ean be between designers, MTEL Ing that describes the grams and lope yates to Drone 1 OR and iigifeauls are Costly to edit, especially wel as C, but is specitenlly reits, " tnbles, Roolenn expressions, anxd complex iween signals that are the inputs to a einent and the Signals Taesent anal document digital systems in y by both humans andl computers und i suitable as an es Nehnge language several major steps 1. Design entry 1 the design ow ofan inteyrated circuit simulation or verification 3. Logie synthesis 4. ‘Timing verification 3. Fault simulat @RNSIT-CsE Lakshmi R, Asst Professor, Dopt of CSE ' Dena \= Desi y create: ipti i ign entry creates an HDL-based description ofthe fanetionaity that isto be implemented in hardware * Depending on the HDL, the description can be in a variety of forms: Boolean logie ea truth tables, a net ist of interconnected gates, or an abstract behavioral model + The HDL model may also represent a partition ofa larger circuit into sma and interacting functional units uations, ler interconnected «Logic simulation displays the behavior ofa digital system through the use of 8 computer. ‘© Asimulator interprets the HDL description © Iteither produces readable output, such as a time-ordered sequence of input and output signal values, of displays waveforms of the signals. © The simulation ofa circuit shows how the hardware will behave before it is actually fabricated. «simulation detects fictional erors in a design without having to physically ereate ‘and operate the circuit © The stimulus (ie, the logic values of the inputs to design is called a test bench. ‘© Test bench is also written in the HDL. a circuit) that tests the functionality of the «Logie synthesis derives an optimized list of physical component and their interconnections (called 2 netlist from the model ofa digital system described in an HDL. «= The netlist can be used to fabricate an integrated circuit orto lay out printes the hardware counterparts of the gates in the list «Logic synthesis producesa database describing the elements and struCiNfC ofa circuit = Itspecifies how to fabricate a physical integrated circuit aaa Thesis is €Q) based on formal procedures that implement digital circuits, and (2) 1 design process, which can be automated .d circuit board with = Logic syn performs logie minimization on those parts of a digi with eomputer software. - Ti a synthesized and fabricated, integrated circuit will operate ata specified speed “s Beediase each logic gate in a circuit has a propagation delay, cient ednnot immediately cause a change in the logic value ofthe output ofa circu iming verification checks each signal path to verify that itis not compromised by propagation dey. 1 verification confirms that a signal transition at the input of a Fault simulation compares the behavior of an ideal circuit with the behavior of a cireuit that contains a process-induced Maw. ‘+ Dust and other particulates in the atmosphere of the clean room can cause a circuit to be fabricated with a fault. ‘© Fault Simulation is used to identify input stimuli that cin bé used to reveal the difference between the faulty circuit and the fault-free circuit Leta Asst Polestr, Dept of CSE QRNSIT, CSE+ To ensure that only good devices are shipped to the customer. VERILOG - DESIGN ENCAPSULATION * Design eneapsulatio ireuit i c ionalit digita or design entry, creates a mode! representing the functionality of a digital ¢ behavic ‘a circuit and, "he model isa repository for the features that determine the behaviour of a Possibly, its structure, A Verilog model is com © Keywords posed oF text using keywords predefined lowercase identi mples of keywords are -ines of text terminate with a crs that define the language constructs, ‘ule, endmodule, input, output, wire, and, or, and nots semicolon (3) {Any text between two forward slashes (/) and the end of the tine is interpreted as a comment. + Muttitine comments begin with /* and terminate with */ * Blank spaces are ignored, but they may not appear within the text ofakeyword, a user-specified ‘Wentifer, an operator, o the representation ‘anther, Verilog is case sensitive Module Creation; The term module ‘efers (othe text enelosed by the keyword pai module... endmod © A module is the fia nental deseriptive (design ‘yword module and must * Its declared by the key end mode }/ unit in the Verilog language. always be ter minated by the keyword [>- an equations D = A+ BE = Cp” ails OF the lang Alogic diagratt (schematic) for the Boole, We'll use its Verilog description to introduce key @RNSIT-csE Lakshmi R, Asst Professor, Dept. of CSE 3 ‘ Bengamodule or_and( output, input A,B,C wire D; assign D=Al|B; i! is logical “OR” operator assign E=C 88D; —_// Bis the logical “AND" operator II This is a single-line comment 1" The text here and below form a multi-line comment 7 endmodule +The Verilog description ofthe circuit begins with the Keywordlmadulle and the name of the design (or_and) «The keyword module starts the declaration of the des declaration with the keyword endmodule. + The keyword module is followed by the;name and a parenthesi © The name of a design unit is an identifier. «Identifiers are names given to modules, variables (8 language so that they can be distinguished and referenced «= Identifiers are composed of alphanumeric characters and the underscore sensitive, Identifiers must start with an alphabetic character or an underscore, start with a number. «In Verilog Boolean equations are composed as conti within the e6de space defined by the modiile ... endmodule keywords. =p continvous assignment statement, has the appearance of an equation, but it is essential 10 ‘understand that a continuous assignment does not prescribe a computation. «Instead, it defines a relationship between signals in a circuit. cription; the last line completes the is enclosed list of ports. Signal), and other elements of the the design. () and are case but they may not finuous assignment statements and placed ~~ «PBA + Band E=CD, comesponding to the schematic shown above, where 4, B, C, D, and E are Boolean vs «+ Inthe Verilog code, signal D is formed by the “OR” of inputs A and B; output £ is formed as the “AND” of C and D. +The continous assignment is specified by the Keyword assign, followed by @ Boolean expression; the assignment is continuous in the sense that it always (ie., for the duration of a simulation) governs the relationship between D and A and B, and between E and C and D, just ae the output of logic gate i always determined by the inputs to the gate and the function of the gate. " «Verilog uses the logie operator symbols &&, ~~, and ! to re 2 Is di, --, an resent the logical F OR, and NOT, respectively. . een open Lakshmi R Ast Professor, Dept of CSE 4 @RNSIT-CSE BengalsVerilog These keywords are not logic gates, but a synthesis tool may pee gales with them, ‘The port list of a module is the interface between the module and its environment. 4m the model or_and, the ports are the inputs (A, B, C) and the output (E) of the circuit The mode, or direction, (bidirectional) ports. ‘The logie values ofthe inputs toa circuit are determined by the environments the logic values of the outputs are determined within the cireuit and result from the action of the inputs on the cireuit, of a port distinguishes between inputs, omputs, and inours The logie value of an inout port may be determined by the environment or by the internal logic of the module. The port list is enclosed in parentheses, The statement is terminated with a ser Next, the keywords input and output Specify which of the ports are inputs and which are outputs, » and commas are used t0 separate elements of the list. :micolon (;). 'ntemal connections, such as D, are declared as wires, Example 2: This example develops a Verilog e model ofa circuit having inputs 4, B, C.D and Outputs £, F, with functionality Specified by the following Boolean expressions E=A+BC+BD F=BC+BCD module Circuit Boolean_CA (E, F A,B, C) Dy: output F; ne AB assion E = A || (B 2&6) | (IB) a& assign F endmodule ) &&.C) Il (B88 (10) 88 (1 Structural (Gate-Level) Modeling: Above constructed Verilo diagram ofa circuit Another approach is to use language constructs directly to form a structural model ofa circuit, Structural models describe how a circuit is composed of other interconnected elements, such as logic gates or functional blocks, Verilog has a family of built-in struct of combinational logic. ' models based on the Boolean equations implied by the logic tat objeets, called primitives that enable direct modeling Important keyword names of the Verilog primitives are and, nand, or, not, bufif0, bufifl, notif0, and notifl. They will be deseril nor, xor, x ibed briefly here. r, buf, RNSIT-cse Lakshmi R, Asst. Professor, Dept. of CSE s ~Verilog Example Lakshmi R, Asst. Professor, Dept. of CSE 6 Most Verilog primitives are multipk ‘more inputs. input primitives—they automatically accommodate two or Schematic for and_or_prop_delay a list of (predefined) primitive gates, each ide and_or_prop_delay, is specified by descriptive keyword (je., and, not,or). The circuit has one internal connection, “The gates are connected by w/, which is declared will “The elements of the list are referred to.as,instantiatio between gates G/ and G3. h the keyword wire. mis ofa gate, each of which is referred t0 as agate instance, or primitive instance, Each gale instaice consists of a primitive name, an optional instance name (such as GI, G2, TA ce on) followed by a list oF comma-separated gate output and inputs and enclosed within parentheses. saree of the language is thatthe output ofarprimitive gate must be listed frst followed by the Ie the OR gale of the schematic is represented by the or primitive, has ‘ad has output D.and inputs w/ and E. (Note: Although the output of a .s of'a module may be listed in any order.) tement must be terminated inputs. For exampl instance name G3, a primitive must be listed first the inputs and output “The module description ends with the Keyword endmodule, Each sta swith a semicolon, buna semicolon after endmodule is not required. “The gates within module may be listed in any order. They operate concurrently in simula ‘A signal ean affect simultancously all ofthe gates to which itis connected as an input. Fach affected gate independently determines and schedules events for its output Verilog primitives have built-in logic determining their behavior. ‘The optional user specified propagation delays (c.g, 30 ns) determine the time interval between tothe input signal ofa gate and the effect apparent atthe output of the gate. a change @RNSIT-CSE“Weneseale Vins Ht ps. i units resolution ‘module and_ce prop delay ( inputa RG ‘output 8, » wirow! and G1 490 (W1, A,B}: Trop dotay: 30-9 not G2 #10(€, ¢) Prop delay: 10s 0F G3 #20 (0,1, €) Prop delay: 20.ns ‘endmodule, ate Delay: + Tospecify the * InVerilog, the a Amount of delay from the input to the ouput ofits gates, Propagation delay of, ‘a gate Specified in terms oF tine wnits and by the symbol in Veri OF @ time unit with physical tim re dimensionless. jevissmade with the “timescale compiler (Compiler directives st + Such a diretive is values oftime art with the () back quote, or grave accent ‘ecified bots the in the code that follows. symbol.) eclaration ofa module and applies to An example ofatiinescate directive is scale | ns/100 ps The first number specifies the unit oF measurement for time dh * The second number specifies lelay {he precision for which the delays are round O.1 ns. 1enoti Ic is Specified, 9 sin certain time unit, usually Ting 10° s), Above cist has propagation delay®specitied foreach gate, Output of Gates after Deiiy all numerical led off, in this case to. vensionless values of default to a Outpu Time Units, PUL _ Output os) ABC E wi b Initial - 000 1 oo 4 Change ~ toro 4 10 tooo 4 20 tO Romer 20 moo 1 oe 40. er) 30 mtooas Se * Theand, or, and not gates have a time delay of 30, 2 mulated and the inputs change from + inabove table (calculated by 0, and 10 ns, respectively. Ifthe eireu BC= 0,104.8, hand or generated by a simulator), 1 the outputs change as shown ORNSIT-Cge Lakshmi R, Asst. Professor, Dept. of CSE 7 s+ The output of the inverter at E changes from 1 to O after a 10 ns delay. The output of the AND gate at w/ changes from 0 to | after a 30 ns delay. The output of the OR gate at D changes from V to Oat ¢= 30 ns and then changes back to | at ¢= 50 ns. Test Bench: An HDL description that provides the stimulus to a design is called a test bench. 1 Test bench for and_or_prop_delay module t_and_or_prop_delay; wire DE reg ABC; & ‘and_or_prop_delay M_UUT (A,B,C, D,E); _/! Instance name (M_UUT) is required initial begin 10; B = 10; C = 1'b0; #100 A= 1b1; B= Tb1; C= tt; end initial #200 Sfinish; ‘endmodule ‘+ A test bench module contains a signal generator and an instantiation of the model that is to be verified. Note that the test bench ({_arie_or_prop)ilelay) has no input or output ports, because it does not interact with its environment. + Inputs to the circuit are deelared wit the keyword wire. The module and_of prop.delay is Misiantiated with the user-chosen instance name M_UUT a —___§(naieigtatn Siena + Exéry instantiation of a module miist include a unique instance name. + “The initial keyword isjaccompanied by a set of statements that begin executing when the simulation is initialized; the signal activity associated with initial terminates execution when the last statement has finished executing, ‘+ The initial stotements are commonly used to describe waveforms in a test bench, o'The set of statements to be executed is called a block statement and consists of several statements enclosed by the keywords begin and end, + They are executed sequentially, in the order in which they are listed. * The action specified by an initia block begins when the simulation is launehed, and the Statements are executed in sequence, subject to time delays (c. bottom, by a simulator in order to provide the input to the circuit, keyword reg and outputs of the circuit are declared with #100), left 10 right, from top to Lakshmi RASS tester Dept of se : @RNSIT-cseStimulusevents_ Respanse events \ fame 018 1160ns 174.0 ns Simulation waveforms of and_or_ prop. delay Initially, 4, B, C= value of 0.) + After 100 ns, the in (A,B, and C are each set to 'b0, which signifies one binary digit with a fa statement is preceded by Statement, and any following + The timing dia, shown here. + The total = Th ; the simulator postpones executing the Statements, untibthe specified time delay has lapsed, ‘Sram oF waveforms that result from the simulation of and_or_ prop delay is ulation generates waveforms, OVer_an interval of 200 ns, puts A; Bs and © change from 0 to 1 t= 100 ne 2 delay®; output E is unknown for the first 10 ns and output Dis unknown for the first 30 ns, Ou from 1 to Oat 130 ns and back to | at 150 ne (denoted by shading), Dut E goes from 1 100 a 110 ns. Output D goes TRUTH TABLES IN VERILOG The user ean create additional primitives by defining them in tabutar form, 5 Diese types of circuits are refereed to as userdefined Primitives (UDP), © “One way of specifying a digital circuit in tabular forme by means of a truth table. UDP descriptions are declared with the keyword pair primitive endprimitive + lH proceeds according to the following general rules + A UDP is declared with the keyword pri €, followed by a name and port list. * There can be only one output, and it must be listed frst in the port list and declared with keyword output. * There can be any number of inputs. The order in which they are listed in the input declaration ilust conform to the order in whick they are given vales in the table Unt follows, * The truth table is enclosed within the keywords table and endtable, @RNSIT-CSE ‘engin Lakshmi R, Asst. Professor, Dept. of CSE 9Lakshmi R, Asst Professor, Dept of CSE © The values of the inputs are ‘ending n().T1 Iways the last alues inputs are listed in order it a nl ; ending with a colon (:). The output is a ; a ae (2). The output is always the I The declaration of a UDP ends with the keyword endprimitive. a— B upper /--———— F . l a Schematic for Cireult with_UDP_02467 INerilog model: User-defined Primitive primitive UDP_02467 (D, A, 8, C): output D; input A,B,C; Intruth table for D=f (A, B, C) = 3(0, 2.4, 6.7): table uA 11 Column header comment Iinstantiate primitive I Nerilog model: ‘cuit instantiation of Circuit_UDP_02467 module Circuit_with_UDP_02467 (e, fa, b, 4); output input a,b,c, d; upp_02467 (e,a,b,¢): (2,4); If Optional gate instance name omitted and endmodule @RNSIT-CSE BenesDESIGN OF ADDER ANDSUBTRACTOR Aim: Design and implement Half adder, Sates. And implement the same in HDL. Full Adder, Half Subtractor, Full Subtractor using basic Components Required 3input AND Gate 1C-7411, 2input And Gate IC-7408, 2inputOR Gate IC- 7432, NOT Gate IC-7404, Patch Chords. THEORY; HALF ADDER added and two oulputs one from. the sum The ne, higher adder positon. The, half adder can be like And, OR and Notogate of, ited also be de igned Sates. The ciruit diagram and truth table oF hall adver & SUM=A’B+ABY CARRY=AB FULL ADDER: A full adder is a combinational circuit that forms the ofthree inputs and two outputs. A full adder is usefial adder cannot do so. Cireuit diagram and truth table of f arithmetic sum of input; it consists to add three bits ata time but a half full adder is shown below, Circuit Diagram of Full AdderSUM = Em (1,244 DA ABC + ABE Amc’ + ABC Fader rain Tab on cary ° son 2 Sm (3. 5,6,7) = AB + BC+ AC cAdBec ADB) sanBoc HALF SUBTRACTOR: “The half subtraétor is Constructed Use sore difference and borrow. The circuit d and two outputs. The output: ‘shown as below. lf Subtractor has two input X-OR and AND Gate. The bs Jiagram and truth table are outputK-Map for Half Sub BORROW wA'B DIEFERENC! ee oo —— 1 00 1 - —— | o FULL SUBTRACTOR: The full Subtrnetor is a combination ofAND. ‘oR, NOT hal Ina full Subtractor the logic circuit should have three inputs and (wo outputs, Thetwo hal ill be Cand A “The first half Sublractor wil ‘The exp AB assembles" is the inverted difference Subiractor put together gives a full Subtracto B. The output will be difference output of the borrow output of the half Subiracior andthe seeond te output of first subtractor. Circuit Diagram of Full Sub wor Fullgupyyaeoy Truth Table aj [own Sorrow ABC Borrow = Ditfrence= Fm (24,7) =AWEP WUC + AW" LBS Da AWN = C(A DB) FC (AT B) pen mewerne EA nac PROCEDURE: (@ Connections are give 's per circuit diagram, Gi) Logical inputs are given as per circuit diagr Gi) Observe the output and verify the truth table,REALIZATION OF LOGIC EXPRESSION USING 8:1 MULTIPLEXER AIM: Given a 4-variable logic ex} ic i AIM: aria expression, simplify it using appro} simplified logic expression using 8:1 multiplexer iC. And in emer COMPONENTS REQUIRED: Digital IC trainer kit, 8:1 Mux ac riate technique and realize the the same in HDL- ars 7404) 7408, 7432+ patch chords. THEORY: are the most widely used MSI components Br ata processing i” Fialtal systems. It is a circuit wi many inpaks but only one ousput. Byvsine control input to convey the data of to the output fine, hence & gn jnput lines, ™ (Gelect) lines, we can select ay multiplexer is also called as data selector. ind 1 output line control/select lines au Pin Diagram of 8:1 Mux (IC 74151) para SELECT MSE ‘A general) MUX. as ee a g EVM technique simplify the given function usin} Simpy 254 SHIA 13.19)PROCEDURE: (Check each ofthe IC and fix k @)Rig up the circuit as chown ji G) Apply various input date to @) Note jit