Design and Verification Flow of Multi-stage Sigma-

delta ADC Digital Core

2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus) | 978-1-6654-0476-1/20/$31.00 ©2021 IEEE | DOI: 10.1109/ElConRus51938.2021.9396481

Maksim N. Skripnichenko Ivan A. Lipatov Andrey A. Belyaev

Department of design and construction Department of design and construction Department of design and construction
of integrated circuits of integrated circuits of integrated circuits
National Research University of National Research University of National Research University of
Electronic Technology Electronic Technology Electronic Technology
Moscow, Russia Moscow, Russia Moscow, Russia
[email protected] [email protected] [email protected]

Abstract—There is a need for analog-to-digital converters noise power out of signal band possible. Also multi-stage
with high signal-to-noise ratio and large signal bandwidth to architecture, as shown in Fig. 2, where each next stage is
solve a number of radiolocation problems. Developing such ADC digitizing the quantization error of previous stage, reducing
is a challenge in analog core, digital core and verification. The noise level in signal band, can be used.
design flow of the digital core must take into account possibility
of changing the analog core specification at any design stage,
provide ability to quickly obtain synthesizable RTL code of the
device and conduct its functional verification. Automation tools
were used to reduce the time spent on development and
verification. This article describes the developed software
package that generates synthesizable RTL code and verification
environment configurations for each stage of development of the
analog core of the multi-stage sigma-delta ADC. Results after Fig. 2. Third order sigma-delta ADC with 6 stages.
functional verification are presented.
II. ADC DIGITAL PART DEVELOPMENT
Keywords—sigma-delta ADC; DSP; SoC; hardware IP;
functional verification Analog part of sigma-delta converter consists of analog
filter with certain frequency response. To restore signal passed
I. INTRODUCTION through this filter, it is necessary to calculate the inverse filter
and convolution of the signal with this filter [1].
There is a classical one-stage first-order sigma-delta ADC
design with subtractor, integrator, comparator and one-bit Digital core of typical first-order sigma-delta ADC
feedback DAC. Signal from comparator goes through low-pass converter consists of a digital low-pass filter with a finite
digital-down converter and becomes multibit. impulse response. As the order of the sigma-delta ADC and the
number of stages increase, the corresponding number of filters
increases too, in general case, one for each output.
The main problem is that all these filters are quite sensitive
to manufactory mismatch, and it is necessary to be able to
adjust the amplitude-phase frequency response of these filters
directly on chips. This problem was solved by obtaining a set
of fixed filters for each of the outputs of the analog-to-digital
converter. The block diagram of the filters is shown in Fig. 3.
The problem of calculating such fixed filters and writing
Fig. 1. Classical one-stage sigma-delta ADC design. synthesized RTL code is very difficult. Moreover, there is a
clear dependence on the stage of analog design - as the ideal
There are two principles sigma-delta ADC are based on -- components of the analog part are replaced by transistors,
oversampling and noise shaping. Cause of noise shaping amplitude-frequency response of the inverse filters constantly
quantization noise power lies out of pass band, and cause of changes, and the final result after topology extraction is quite
oversampling it’s possible to operate with single-bit signals in seriously different from all intermediate ones. At the same
analog core that will be transformed into multibit signal in time, it is necessary to check at each stage of analog design
digital core. If necessary, usage of second or third order sigma- whether it is really possible to find such a set of filters that
delta ADC can increase signal bandwidth without decreasing describes all the available amplitude-frequency responses of
effective number of bits. This structure makes transferring inverse filters, whether the coefficients before the filters are
adequate, write the RTL code and verify it.
The reported study was funded by RFBR, project number 19-37-90081.

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 frequency of 2000 MHz and shifts one sample for each clock
cycle. The second register consists of five triggers, operates at a
frequency of 400 MHz and copies data of the first register for
each clock cycle.
With this scheme it is possible to work with samples with
sampling frequency of 2 GHz in the domain zone of 400 MHz.
These samples are single-bit, which simplifies the design of
filters. Instead of classic scheme with multipliers and adders, it
is possible to use Look Up Tables. With pre-calculated values
for all variants of input, there is a solid gain in delays, area and
power consumption. The most efficient version of LUT has six
inputs.
Fig. 3. Filtering comparator outputs.
The task of calculating inverse filters with such frequency
The process of writing an RTL code containing filter response is very non-trivial, and classical methods of
coefficients and its verification are nontrivial, and rewriting constructing filters with a predetermined frequency response
them takes a lot of time. cannot demonstrate satisfactory results. So the task of
Therefore, at stage of building ADC digital part model, it constructing inverse filters was divided into two subtasks:
was proposed to make automatic generation of the RTL code of constructing a decimator that satisfies the requirements listed
the digital part. above, and constructing inverse filters that implement the
amplitude-frequency responses in the band up to 300 MHz.
Benefits:
Final set of filters, calculated by convolution of decimator
• Easy to remake; with inverse filters, can both restore original signal and
decimate it by 2.5 times. The part of the software complex that
• Low probability of error;
is generating the magnitude-frequency response works with a
• Preliminary estimation of area, timing and .mat file containing a structure with the following fields:
consumption.
• Filter coefficients;
So, at initial stage of ADC digital part development the
main emphasis was not on writing RTL code, but on creating a • Filter delay;
software package that allows generating the required RTL • Filter order.
code.
All filters get convolved with the previously calculated
Globally, all code can be divided into two parts - permanent decimator. Then, based on the filter coefficients, a code is
and custom. Permanent code refers to the part of the register generated in the Verilog hardware description language, which
file, the control automata of the memory and the procurement is a module consisting of LUT sets, two modules for each filter.
of blocks of custom code. The custom code includes digital
filters and part of the register file. The next step is Verilog HDL code generating. There are
two Look-Up Tables generated for each filter from it’s
III. BLOCK DIAGRAM OF DIGITAL PART coefficients. According to the selected oversampling method,
the first subfilter has only even filter coefficients, and the
second has only odd. In addition, samples come to the second
filter with a delay of two clock cycles to coordinate output
samples - during decimation only one of each five samples
comes out.
Table I shows the principle of decimation - every fifth
sample is highlighted in gray. In addition, this table shows why
it is necessary to delay the samples for the second filter.

TABLE I. PRINCIPLE OF DECIMATION

Fig. 4. Block diagram of ADC digital core.
Input samples
First filter output 14 12 10 8 6 4 2 0
Figure 4 shows the block diagram of the digital part of the Second filter output 15 13 11 9 7 5 3 1
ADC, consisting of a block of transition between two a.
Decimation of samples
frequency domains, a block of shift registers, directly filters,
and a register file with filter weights. The LUT module generator is written in C++ and requires
filter coefficients as the input data, the number of inputs in one
Initially, the analog block has 24 outputs with a sampling LUT and the number of bits allocated to represent the filter
frequency of 2000 MHz. To transfer data to 400 MHz coefficients. This data is generated as C++ source code, then it
frequency domain, a scheme of two parallel shift registers is is compiled and the resulting file is executed.
used. The first register consists of five triggers, operates at a

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 If the filter order is not exactly divided by the number of In addition to the register file itself, a part of the test
inputs in one LUT, the filter coefficients are supplemented with environment is generated - header files with the name of the
zeros up to the number when this condition is met. registers, addresses, masks and initial values. These files are
used to test the ADC registers and to record weight coefficients
At the same time the generation of RTL code in the during signal recovery.
SystemVerilog language, which contains the implementation of
filter modules, is performed. IV. FUNCTIONAL VERIFICATION METHODOLOGY
Each filter is calculated with its unique filter delay and During our work, we built the process of functional
number of coefficients, so each filter has its own delay that verification of designed ADC digital part, that was based on the
needs to be compensated. The first filter has a zero delay due to principles of Constrained-Random Verification. We also used
a unit coefficient and zero filter delay. Directed Verification Methodology principles in our
verification strategy to cover important cases and check the
It is necessary to have a shift register that exceeds length of
correctness of target functional implementation. The main
filter order to compensate total delay. There are several filters
problem in the verification process was the trade-off between
for each output, and all of them have its own order and its own
these two approaches. Directional testing is a computationally
delay.
expensive process [3], but if we focus on completely random
The final formula for calculating the length of of the i-th generation of configurations and input actions, this can
output shift register: ultimately lead to the waste of many modeling cycles without
increasing the functional coverage.
sh_len = max(flts_ordi + 2 + max(flts_dly – flts_dlyi) (1) To check the correctness of access to the address space of
the digital part of the ADC, a test scenario based on the above-
where mentioned Constrained-Random methodology was developed.
• flts_ordi - the set of filter orders for the i-th output, To write a register of the address space, a random bit vector of
the required bit width was formed, writing was performed, and
• flts_dly - set of filter delays for all outputs, then reading, after which the original bit vector was masked
with the specified value and checked against the read one. If
• flts_dlyi - a set of filter delay for the i-th output. any divergence was found, then the verification environment
The required register length for each filter can be found as indicated an error in accessing a specific element of the address
order of the filter and the difference between the largest delay space of the digital part.
and the delay of filter itself. The final value of shift register for The construction of a test scenario for verifying the specific
each output is the maximum value.
functionality of the developed device depends on the chosen
The next step after implementation of shift register is verification strategy. To analyze the correctness of signal
generating code for filters. This process includes generation of recovery by the digital part of the ADC, one can use its
wrapper modules around LUTs, delay of two clock cycles for mathematical model and, supplying the same input data to the
second filter output, and implementation of all these modules. model and device, compare the output data taking into account
The output of each filter is multiplied by the corresponding imperfections of the real device. An alternative strategy implies
weight coefficient, shifted by several digits and added to the the analysis of key characteristics of the output data taken from
weighted outputs of the other filters. As the number of filters the output of the digital core block. The following are the
increases, the process of logical and physical synthesis definitions of the output signal parameters of the ADC digital
becomes more complicated, and there is an option to use part, selected as the most important during developing a test
pipeline multipliers. At one moment slack on the multipliers scenario for checking signal recovery RTL-implementation.
became more than acceptable, and the generation of alternative Signal-to-Noise Ratio (SNR):
code with pipeline multipliers fixed this problem [2].
SNRdB = 10log10  Psignal  = 20log10 
RMSsignal  , (1)
Register file is also an important part of the generated code. 
Part of the register file is predefined rigidly and does not  Pnoise   RMSnoise 
change. The other part, for example, registers with filter
weights, is regenerated each time. where RMSsignal is the root mean square (RMS) amplitude of
signal; and RMSnoise is the RMS amplitude of the noise [4].

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 Signal-to-Noise and Distortion Ratio (SINAD). SINAD is a
parameter that characterizes the degradation of the wanted
signal due to the presence of extraneous signals, in particular
noise and distortion. SINAD can be defined as the ratio of the
total signal power level (Signal + Noise + Distortion) to the
unwanted signal power (Noise + Distortion):
 Psignal + Pnoise + Pdistortion  (2)
SINADdB = 10log10  
 Pnoise + Pdistortion 
Spurious free dynamic range (SFDR) is the ratio of the
RMS value of the signal to the RMS value of the worst
spurious signal RMSmax _ spur regardless of where it falls in the
frequency spectrum.

SFDRdBc = 20log10 
RMSsignal  (3)
.
 RMSmax _ spur 
The worst spur may or may not be a harmonic of the original
signal. SFDR is an important specification in communications
systems because it represents the smallest value of signal that
can be distinguished from a large interfering signal [5].
In case of a verification strategy based on the analysis of
selected key parameters, the structure of the verification
environment is significantly simplified while maintaining the
quality characteristics of verification: if the digital part does not
work properly, introduces distortions to the output signal, loses
samples, this will certainly affect the characteristics of the
output signal and will be detected on verification stage. Fig. 6. The spectrum of the ADC digital core output signal for different
configurations of modeling the digital part: a - the filter weights for the
V. VERIFICATION ENVIRONMENT COMPONENTS nominal frequency response were used as the filter weights, and the samples
corresponding to the samples of channel I of the quadrature ADC with
The verification environment is a hierarchical structure that heterodyning were used as input data; b - weights and samples from
provides high-level interfaces for controlling the process of simulation of the technical process parameters using the Monte Carlo method
interaction with the device under verification. The basis for for separate ADC were used.
such environment is a class library that simplifies writing
adaptable and reusable code. The author of the test scenario To interact with the Design Under Test (DUT), a
only needs to describe the desired effects in terms of the verification environment, consisting of interface drivers,
corresponding API methods calls that are processed by the configuration generators, configuration loading blocks, output
verification environment. The independence of the monitors, as well as auxiliary control agents, was assembled. A
environment components from each other allows code reuse. simplified connection diagram of the verification environment
Thus, using a class library, you can build a new environment components is shown on Fig. 5.
from old blocks for a new project [3]. Interface drivers transmit control switchings in accordance
with a specific interface standard. ADC analog core emulator
was used to supply an input signal to the ports of the ADC
digital part. The output samples of the digital part were
receiving using output monitors for further analysis. After
receiving a sample of sufficient size, the key signal
characteristics were calculated: SNR, SFDR and SINAD. If the
values of these calculated parameters doesn’t match specified
range, then the verification environment signals an error.
Figure 6 shows the spectrum and parameters of the ADC
output signal for different digital core simulation
configurations.
Output monitors with comparators were used to verify the
integration of the digital part with a DSP unit, which was
configured to bypass samples. Comparators were comparing
Fig. 5. Verification environment components. samples from the direct output of the digital core and from the
signal processing unit output and in case of any mismatch or
absence of samples, an error was signaled. Necessary
configuration of weight coefficients formed at the stage of

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generating the RTL code had been loading into the device • II - Full transistor-based analog core;
under verification using the address space agent. This kind of
integration of the RTL code generation stage and the • III - Full transistor-based analog core + topology
verification stage provides the necessary level of adaptability to extraction results.
the variability of the device specifications and, as a result, the The difference between the predicted area and the resulting
ability to reorganize the environment components in a short is less than 5%, which is a very good result.
time.
VII. CONCLUSIONS
To automate the launch of test scenarios, a software
package was developed and implemented that automatically The article describes the development and verification flow
launches simulation and generates reports on the passage of test for digital core of a multi-stage sigma-delta ADC. Software
scenarios in accordance with the principles of regression package which generates synthesizable SystemVerilog code for
testing. The generated report includes information about the set of sigma-delta ADCs and elements of verification
control actions were applied to the device, as well as the environment was developed. The developed software package
conditions for reproducing this simulation. provides adaptability to changes in the device specifications
and the ability to quickly rebuild the verification process. The
VI. RESULTS OF RESEARCH testing of this route was carried out during the development
As result, there was developed a mathematical model of and verification of two ADCs in the AESA 1288TK015 IC.
six-stage sigma-delta third-order ADC that can generate ACKNOWLEDGMENT
synthesizable SystemVerilog code for digital core and
verification environment corresponding to this code. M.N.Skripnichenko and I.A.Lipatov thank Mikhail
Maksimovsky, Alexey Zaytsev and Dmitry Skok.
This allowed us to obtain an initial estimate of the area,
timing and power consumption at the early stages of analog REFERENCES
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[3] ASIC/SoC Functional Design Verification A Comprehensive Guide to
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Design Compiler and TSMC 90 nm Standard Cell Library. 70 pp.
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Total number of Weight of one
Design Expected Real area, Don't Get Lost in the Noise Floor. Walt Kester, Analog Devices Inc.,
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I 9 840 113 - 1 119 433
II 10 944 119 1 236 672 1 296 490
III 11 520 118 1 301 760 1 361 130
b.
Expected and actual area of the synthesized filters at various stages of analog design.
In table 2, the following designations are used:
• I – Transistor-based filters + ideal elements;

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