DIGITAL LOGIC DESIGN LAB

REPORT

Lab No: 5 Lab Section: Wed

Name: Zaid Zukari Student ID: 64220046

Lab Partner: Abdulrahman Shik Alzoor Group No: 11

Introduction:
Multiplexers, also known as MUXs, are crucial electronic components in the field of digital circuit
design. To generate a single output, their main function is to combine and select from several input
signals. This is essential for effective data transfer, resource management, and signal routing in urgent
circumstances.

A binary combinational circuit tasked with selecting one input line from a range of lines and routing it to
a single output line is essentially what a multiplexer is. Selection or control lines are a set of input lines
that determine the selection process. The number of input lines is expressed as a power of two, or 2𝑛 ,
where 'n' is the number of control lines.

IC Description:

For digital applications, there is an integrated circuit called the 74151 that can multiplex eight lines to one
line. Figure 23 illustrates how this IC selects a particular input for multiplexing and routing to the output
by using selection lines S2, S1, and S0. As an enable signal, the Strobe line, denoted by S, is utilized.
Deactivating the 74151 chip keeps the output (y) at zero when the strobe signal is set to 1. The chip
becomes a multiplexer when the Strobe signal is set to 0, on the other hand. Table 10 describes the
selection line functionality of the 74151 and its multiplexing behaviors in detail.

The 74153, on the other hand, is a dual 4-line-to-1-line multiplexer IC. The main job of this function is to
multiplex and choose inputs for the output IY {1 = 1, 2}. The strobe signals IG {I = 1, 2} act as enable
signals for the corresponding multiplexers, and the selection lines S0 and S1 specify the input choice for
each multiplexer. The on-chip multiplexers in the 74153 are independent of one another, even though
they share selection lines S0 and S1.
Table10:
Strobe Select lines Output

S S2 S1 S0 Y
1 X X X 0
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5

Multiplexer 1
Strobe Select lines Output
1G S1 S0 1Y
1 X X 0
0 0 0 1D0
0 0 1 1D1
0 1 0 1D2
0 1 1 1D3

Multiplexer 2
Strobe Select lines Output
2G S1 S0 2Y
1 X X 0
0 0 0 2D0
0 0 1 2D1
0 1 0 2D2
0 1 1 2D3
Parity Generator:
We have chosen to design our Parity Generator using a 5-bit code, which consists of information bits A,
B, C, and D. The parity bit is represented by the fifth bit (x). By using odd parity, which requires that the
total number of 1s in the code (including x) be an odd number, we hope to preserve a sense of mystery.

We've added 74151 multiplexers to accomplish this, assigning select inputs B, C, and D to these parts.
Now, to get specific, we are building a truth table (Table 12) to show what our 5-bit code produces when
it satisfies the odd parity requirement. We are using 0, 1, A, or A' to finish the configuration, and each
distinct input combination corresponds to a particular output.

To put it briefly, we are using our 74151 multiplexers to perform a captivating dance that will enable the
Parity Generator and guarantee that our 5-bit code complies with the odd parity idea. Now is the moment
to complete the puzzle and see the magic happen!
 Inputs Outputs Connect data to
A B C D X
0 0 0 0 1 D0`
0 0 0 1 0 D0`
0 0 1 0 0 D1
0 0 1 1 1 D1
0 1 0 0 0 D2
0 1 0 1 1 D2
0 1 1 0 1 D3`
0 1 1 1 0 D3`
1 0 0 0 0 D4
1 0 0 1 1 D4
1 0 1 0 1 D5`
1 0 1 1 0 D5`
1 1 0 0 1 D6`
1 1 0 1 0 D6`
1 1 1 0 0 D7
1 1 1 1 1 D7

Vote Counter:
Digital tools like individual switches (C, S, M) for committee members, multiplexing units (74153), and a
7446 BCD-to-Seven-Segment decoder are used in the construction of the Vote Counter circuit. The goal
is to present the total number of votes on a seven-segment screen. Making the committee's decision clear
and visible while applying digital components' capabilities is the main goal. Let's make sure that every
vote counts.

Description of the Circuit:

It is possible to vote "yes" (closed) or "no" (open) for each committee member (C, S, and M). Three
weighted votes go to the senior member (S), two to the member (M), and five to the chairman (C). Two
74153 units are used to make it easier to multiplex input switches and produce Binary-Coded Decimal
(BCD) output. Next, a 7446 BCD-to-Seven-Segment decoder receives the BCD output and uses it to
control the seven-segment display.

Should every member vote "yes," the display reads "0," and should every member vote "no," it reads
"blank." If not, the decimal value corresponding to the total number of "yes" votes is displayed.

Ground represents Logic 0 and +5V represents Logic 1 in the software simulation. We use one 7446
decoder and two 74153 chips to test the functionality of the switches for C, S, and M. Pin numbers and
all, the circuit is sent to the lab for hardware implementation after the simulation is optimized. By taking
great care, connections are made exactly as planned, resulting in a smooth transition to hardware mode.
Come with me as we implement this voting system!
Results:
Conclusion:

Three members of the committee, C, S, and M will vote in this system that we are currently building.
Every participant has switches for "yes" or "no" answers. To translate these switch choices into Binary-
Coded Decimal (BCD) digits, we need to build a circuit using two 74153 units, each with four
multiplexers. The final objective is to display the total number of "yes" votes on a seven-segment display.

The system works on the following logic: if every committee member votes "no," the display stays blank;
if every vote is "yes," it displays '0." In all other cases, it shows the exact number of votes cast in favour.
We are using +5V for "yes" and ground for "no" in our software testing phase, with switches specifically
for C, S, and M. In this experiment, one 7446 decoder and two 74153 chips are used.

Our goal is to move the complete circuit design—including pin numbers—to the lab after the software
testing is successful. This careful planning guarantees a seamless transfer to the hardware implementation
stage. Our goal is to develop a novel voting system that faithfully represents the committee's decisions.