World Applied Sciences Journal 34 (12): 1902-1908, 2016

ISSN 1818-4952
© IDOSI Publications, 2016
DOI: 10.5829/idosi.wasj.2016.1902.1908

Optimising a D Flip Flop Through Delay and Power

Estimation Using an RC Model and Transistor Sizing
1
Manan Joshi, 2D.S. Chauhan and 3B.K. Kaushik

1
Uttarakhand Technical University, Dehradun, India
2
GLA University, Mathura, India
3
Indian Institute of Technology, Roorkee, India

Abstract: This paper deals with the designing of explicit pulsed dual edge triggered D Flip Flop. The flip flop
is designed with the help of CMOS inverter and CMOS transmission gates using 180nm technology. Delay and
power consumption are estimated using theoretical means and then compared with simulation results. It is
found that the theoretical results of delay are within 1% of the simulation results. Theoretical calculations show
that there is an alternative method of circuit optimisation when simulation based hit and trial method becomes
too complicated in large digital circuits.

Key words: Dynamic power consumption Lumped RC network Delay model, power estimation model
Critical path Circuit optimisation Model file

INTRODUCTION waveform slope effects at both the input and output of a

gate and an innovative approach for handling
Flip Flops and latches consume a large portion of transmission gate circuits. The highly efficient delay
system power due to redundant transitions in the internal characterization is accomplished through a fast
nodes [1]. Power budget of portable digital circuit is timing simulation technique, a theorem that reduces a
severely limited and thus requires lowering of power two-dimensional delay table into a scaled one-dimensional
consumption. Due to tight timing budgets at high table and an incremental characterization process.
frequency operations latency of the flip flops has to be A systematic method [5] to reduce standard cell library
reduced [2]. Transistor sizing thus plays an important role characterization time significantly is to use a simple and
in the optimisation of power and delay of a digital circuit. physically reasonable logic gate delay model in which
Methods of calculating delay time easily are delay varies linearly with Cl and trin. Determine its region
categorized into two groups. One is the look-up table of validity in the (Cl, trin) space and express the delay
method and the other is the delay time calculation model coefficients and its region of validity as a function
method. A look-up table method has a trade-off between of inverter (or logic gate) size. As device
the cost of establishing the table and the accuracy [3-4]. current/capacitance models are not used, the method is
Hence there is very little flexibility for various factors general enough to be used with scaling.
affecting delay time, such as input transition time, fan-out, The methods that rely on calculation construct a
output capacitance, sizes of MOSFETs, etc. The macro- special delay model and are divided into two groups
modeling method [3] is well suited for delay calculations i.e. the group that includes the properties of the circuits
of regular structure VLSI circuits, as well as circuits or MOSFETs [6] in the delay model and the other group
designed from standard cell libraries. Timing models for that does not include [7] the properties of the circuits or
both logic gate and transmission gate circuit forms are MOSFETs in the delay model. The latter methods
developed. A more accurate and efficient Gate Level consider many factors affecting the delay time. The
Delay calculation [4] uses a delay model that includes an factors are not enough for more general cases where the
accurate representation of the waveform, a consistent and sizes of MOSFETs, output capacitances, etc., are varied.
meaningful definition of delay, a consideration of The remodelling method [6], uses an RC model for a

Corresponding Author: Manan Joshi, Uttarakhand Technical University, Dehradun, India.

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MOSFET but this method also can not model exactly the product of polynomials of the input waveform slope, the
non-linear property of MOSFET with linear resistor. Delay output loading capacitance and the device
models for inverter and other logic gates are modelled configuration ratio. This approach is extended to the case
with -power MOSFET model [6], but they considered of multiple-input transitions. A model that works at
only the case of very small input transition time, resulting gate-level [12] with the modelling process that includes
in less accuracy as the input transition time increases. the characteristics of MOSFETs handles the delay
A -power-law MOS model [8] that includes the carrier variation according to the kind of gates, input transition
velocity saturation effect, which becomes prominent in time, output load (fan-out) and transistor sizes of the gate.
short-channel MOSFETs, is introduced. Since the model A delay model for CMOS inverter is extracted first and
is simple, it is used to handle MOSFET circuits then it is extended to other gates by converting them into
analytically and predicts the circuit behaviour well in the an equivalent inverter. This model calculates the delay
sub-micrometer region. Using the model, closed-form time regardless of the input transition time, output load
expressions for the delay, short-circuit power and (fan-out), or the size of MOSFETs. A systematic method
transition voltage of CMOS inverters are derived. The [13] to reduce standard cell library characterization time
delay expression includes input waveform slope effects significantly is to use a simple and physically reasonable
and parasitic drain/source resistance effects. But the logic gate delay model in which delay varies linearly with
CMOS inverter delay becomes less sensitive to the input C l and trin. Determine its region of validity in the (Cl, t rin)
waveform slope and short-circuit dissipation increases as space and express the delay model coefficients and its
the carrier velocity saturation effect in short-channel region of validity as a function of inverter (or logic gate)
MOSFETs gets more severe. This drawback is resolved in size. As device current/capacitance models are not used,
[7] by including many pre-simulation steps. A more the method is general enough to be used with scaling.
precise model [9] that considers the velocity saturation A simple analytical model [14] that allows the estimation
effects and the gate capacitance of MOSFETs is used to of the propagation delay uses a closed-form model of an
present an expression for propagation delay. The RC circuit with a linear input to evaluate the propagation
propagation delay expression is for static CMOS logic delay of CMOS gates or wires in modern VLSI and ULSI
gates considering short-circuit current and current process.
flowing through gate capacitance and using the nth power On the basis of the level of abstraction power
law MOSFET model that considers velocity saturation estimation techniques are broadly classified into [15].
effects. The short circuit current is represented by a Low-level power estimation
piecewise linear function that enables detailed analysis of High-level power estimation
the transient behaviour of a CMOS inverter. These
expressions are applied to logic gates made up of series- Low-level Power Estimation Techniques Are Those That
parallel connected MOSFETs by replacing the series- Operate at the Gate Level: High-level power estimation
connected MOSFETs by an equivalent MOSFET. The techniques [16] estimate power dissipation from a design
influence of short-circuit power on delay, is modelled in description at a high level of abstraction. The power
the expression. estimation techniques at the gate level and lower levels of
The output load is modelled with an RC model and abstraction are broadly classified into [17]:
differential equations are solved in [10]. The resistive-
capacitive behaviour of long interconnects which are Simulation based techniques
driven by CMOS gates are analysed. The analysis is Probabilistic techniques and
based on the ð-model of an RC load and is developed for Statistical techniques
submicron devices. Accurate and analytical expressions
for the output voltage waveform, the propagation delay Simulation based techniques are the earliest
and the short circuit power dissipation are derived by proposed techniques where the average power is
solving the system of differential equations which calculated by monitoring both the supply voltage and
describe the behaviour of the circuit. The effect of the current waveforms. These are too slow to handle very
coupling capacitance between input and output and large circuits. In probabilistic techniques, user-supplied
that of short circuit current are also incorporated in the input signal probabilities are propagated into the circuit.
model. Statistical techniques do not require any specialized
A delay model for multiple delay simulation [11] for models for the components. The circuit is simulated with
NMOS and CMOS logic circuits is given. For the simple randomly generated input vectors until power converges
inverter the rise or fall delay time is approximated by a to the average power.

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Power estimation techniques are also classified as An approximate expression for Req in transmission
either static or dynamic. An approach is called static when gate using an average value of current equal to the
it is based on propagating a probability or activity saturation current of the PMOS (NMOS) transistor is
measure directly through the logic, in order to estimate the given by [18].
average switching frequency and uses non simulation
based methods. Dynamic techniques use traditional
simulation models and simulate the circuit, using existing
simulation capabilities, for a limited number of randomly Load capacitance is given by the expression below
selected input vectors (or vector blocks) while monitoring [19].
the power.
This paper describes optimisation of a digital CL = Cgd,n + Cgd,p + Cdb,n + Cdb,p + Cg,n + Cg,p + Cload (1)
CMOS VLSI circuit with respect to power and delay.
The transistor level optimisation algorithm uses RC Here Cgd,n and Cgd,p are gate to drain capacitances of
model that deviates from SPICE simulations by 4-5%. the NMOS and PMOS, Cdb,n and Cdb,p are the drain to base
The general idea of transistor modelling is to characterize capacitances of the NMOS and PMOS and Cg is the thin
the delay and power contribution of a critical path so as oxide capacitance over the gate area.
to optimise PDP. To calculate data path delays, the model The table below is used to calculate each of the
has used generalized input step voltage and then above capacitance values [20].
transformed the results for realistic input signal
waveforms. Capacitance Value
This paper is summarised as follows: Section II gives Cgd,n 2CGDOn Wn
a brief introduction of the computation methodology. Cgd,p 2CGDOp Wp
Section III consists of the proposed work and section IV Cdb,n Keq,nADnCj + KeqswnPDn CJSW
compares the theoretical and simulation results. Finally Cdb,p Keq,pADpCj + KeqswpPDn CJSW
conclusions are drawn in section V. Cg,n (CGDOn + CGSOn)Wn + CoxWnLn
Cg,p (CGDOp + CGSOp)Wp + CoxWpLp
Computation Methodology: A fast methodology to CL
calculate the approximate value of the delay and average
dynamic power consumption for combinational logic The parameters taken from model file are Vt,n, | Vt,p |,
circuits is used. The critical path that is defined as the CGDO,n, CGSO,n, CGBO,n, CGDO,p, CGSO,p, CGBO,p, XJ,
path between an input and an output that has maximal tox, µo,n, µo,p, CJ, CJSW, NCH and NSUB.
delay [17]. Optimisation of the critical path helps in the
performance improvement of the overall digital circuit. In Keq is calculated using the expression
large digital circuits a method that focuses on the critical
path only requires less computational effort compared to
the exhaustive simulation approaches. For calculating the
propagation delay of D Flip Flop, delay model for a CMOS
inverter and CMOS transmission gate is considered as the where
first step.
The D Flip Flop is modelled as an RC network and the Likewise and
propagation delay for a lumped RC network is given by

PLH = 0.69ReqCL
The Low to High delay of an inverter is given by
In the expression for propagation delay 'Req' is the
average "ON" resistance of the MOS transistor and CL is
the capacitive load.
An approximate expression for Req using an average
value of current equal to the saturation current of the and the High to Low delay of an inverter is given by
PMOS (NMOS) transistor is given by [18].

and

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The rise time or fall time of signal through inverter is

given by

Total power consumption is the power consumed in

the explicit pulse generator (and the drivers), the D Flip
Flop (and the drivers).
The dynamic power consumed is proportional to the Fig. 1: Explicit pulse generator
capacitance hence the same has been calculated for each
MOSFET.
The average dynamic power required to charge and
discharge a capacitance 'Cload' at a switching frequency 'f
' and activity factor ' ' is given by [20].

Average Dynamic Power Consumption = CloadVdd2f.

For CMOS gates other than inverter, MOSFETs serial
or parallel connected are combined into one equivalent Fig. 2: The D Flip Flop
MOSFET [21].

Optimisation Through Delay and Power Calculations in

D-Flip flop: Delay and Power calculation of the D Flip
Flop [22] is given below. It is an explicit pulsed dual edge
triggered D Flip Flop. The Fig. 1 below gives the explicit
pulse generator of the D Flip Flop.
Fig. 3: Simulation Setup
The D Flip Flop shown in Fig. 2 consists of an input
and output stage that is an inverter, whereas the middle
Transistor Capacitance Values
stage is a transmission gate, that allows the input to pass
Cgd,n 3.4 × 10 16
through only at the clock edge. The two inverters invert
Cgd,p 8.01 × 10 16
the signal twice and hence the output is the same as
Cdb,n 2.46 × 10 16
input. Two clock pulses that are generated from pulse
Cdb,p 5.88 × 10 16
generator are applied to the MOSFETs (M5 & M6).
Cg,n + Cg,p 11.4 × 10 16
The circuits are simulated using two buffers
CL 31.15 × 10 16
(inverters) that drive the flip flop inputs (data and clock)
and the output drives a capacitive load of 21fF. An
Given the value of CL = 31.15 × 10 16
F the value of
additional capacitance of 3fF is placed after the clock
PHL = 11.37 × 10 12 sec.
driver. An input data with an activity factor of 25% to
Initial rise or fall time was 10ps.
reflect the average power consumption is applied at the
Hence actual delay time is 12.42ps.
input. Power consumed in the data and clock drivers is
included in our measurements. Clock frequency used is
125MHz. In the above circuit an inverter drives another
inverter or a transmission gate which is its load.
The load capacitance at each stage is calculated
using expression (1) and there after delay PHL and PLH are Rp = 3.65 × 103 ohms
calculated using expressions (2) and (3).
For Inverter 2 (buffer 2) the value of CL = 31.15 ×
Calculation of Delay 10 16 F and Rp = 3.65 × 103 ohms the value of PHL is 11.37
For Inverter 1 (buffer 1) the capacitances calculated × 10 12 sec and initial rise or fall time was 27.32ps. Hence
are as under actual delay time is 17.77ps.

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Fig. 4: Delay model of inverter driving a transmission gate

New rise or fall time is .

For Inverter 3 and Transmission gate the value of C1
= 47.4 × 10 16 F and C2 = 66.7 × 10 16 and R1 is 3650 ohm
and R2 of transmission gate is calculated as 678 ohm.
The delay of inverter and transmission gate
combination is given by

Propagation delay PHL = 66.7 × 10 12 sec and initial

rise or fall time was 39.1ps. Hence actual delay time is
69.5ps and tr/f = 152.9 × 10 12 sec.
For Inverter 4 the value of CL = 289.0 × 10 16 F and
Rp = 3.65 × 103 ohms the value of PHL is 105.5 × 10 12 sec
and initial rise or fall time was 152.9ps. Hence actual delay
time is 130.4ps and .
Total Delay is the sum of the two delays and is equal
to 199.9ps.

Calculation of Power Consumption: Total power

consumption is the power consumed in the explicit pulse
generator (and the drivers) and the D Flip Flop (and the
drivers).
Power Consumption in a digital circuit is given by [1] Fig. 5: Flow chart of the optimisation technique

Dynamic Power Consumption = CloadVdd2f.

The power dissipation of a CMOS circuit is instead Here f = 125MHz and Vdd = 1.8V and = 0.25. Hence Vdd2f
dominated by the dynamic power dissipation resulting = (1.8)2 × 125 × 10 6 = 4.05 × 10 8.
from the charging and discharging of capacitances.
The dynamic power consumed is proportional to the Total capacitance in explicit pulse generator and
capacitance hence it has been calculated for each drivers is 426.01 × 10 16 F.
MOSFET. = 37.52 + 87.45 + 54.56 + 60.44 + 40.55 + 60.44 +
To minimise the power consumption of a CMOS 37.96 + 47.09
circuit the dynamic power consumption has to be = 418.05 + 37.96
reduced. It depends on the capacitances in the MOSFET
and the load capacitances. The MOSFET capacitance Capacitance in Flip Flop and drivers is 570.35 × 10 16 F.
depends on the W and L of the transistor. The average Thus power consumed in D Flip Flop is
dynamic power required to charge and discharge a = [405 ×106 × (418.05 + 2 × 37.96) + 0.25 × 405 ×106 ×
capacitance 'Cload' at a switching frequency 'f ' and activity 570.35] × 10 16 W.
factor ' ' is given by = 20.00 × 10-6 + 5.78 × 10-6 = 25.78µW.

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Table 1: Iterations leading to optimisation of D Flip Flop

Iterations Power (µW) Power (µW) Delay (ps) Delay (ps) PDP (×10 15J) PDP (×10 15J)
Performed (Theoretical) (Simulated) (Theoretical) (Simulated) (Theoretical) (Simulated)
1st 72.01 83.05 283.53 285.8 20.4 23.6
2nd 48.9 56.4 240.7 242.6 11.8 13.7
3rd 36.34 41.91 219.4 221.22 7.97 9.3
4rth 28.31 32.65 207.8 209.5 5.9 6.9
Final 25.78 29.73 199.9 201.5 5.2 5.99

The output fall time is kept slightly larger than the to validate the design. In a large digital VLSI circuit
input rise time where ever possible to reduce short circuit theoretical model that can give approximate results, can
current. Difference between simulation values and help reduce design time by optimisation of the critical
computed values occurs due to leakage power and short path.
circuit power.
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