San Jose State University

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Master's Theses Master's Theses and Graduate Research

Spring 2015

30 GHz Adaptive Receiver Equalization Design Using 28 nm

CMOS Technology
Gustavo Tostado Villanueva
San Jose State University

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Villanueva, Gustavo Tostado, "30 GHz Adaptive Receiver Equalization Design Using 28 nm CMOS
Technology" (2015). Master's Theses. 4564.
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30 GHZ ADAPTIVE RECEIVER EQUALIZATION DESIGN

USING 28 NM CMOS TECHNOLOGY

A Thesis

Presented to

The Faculty of the Department of Electrical Engineering

San José State University

In Partial Fulfillment

of the Requirements for the Degree of

Master of Science

by

Gustavo T. Villanueva

May 2015
 © 2015

Gustavo T. Villanueva

ALL RIGHTS RESERVED

ii
 The Designated Thesis Committee Approves the Thesis Titled

30 GHZ ADAPTIVE RECEIVER EQUALIZATION DESIGN

USING 28 NM CMOS TECHNOLOGY

by

Gustavo T. Villanueva

APPROVED FOR THE DEPARTMENT OF ELECTRICAL ENGINEERING

SAN JOSÉ STATE UNIVERSITY

May 2015

Dr. Shahab Ardalan Department of Electrical Engineering

Dr. Sotoudeh Hamedi-Hagh Department of Electrical Engineering

Dr. Robert Morelos-Zaragoza Department of Electrical Engineering

Dr. Thuy T. Le Department of Electrical Engineering

iii
 ABSTRACT

30 GHZ ADAPTIVE RECEIVER EQUALIZATION DESIGN

USING 28 NM CMOS TECHNOLOGY

by Gustavo T. Villanueva

This thesis consists of a 28 nm submicron circuit design for high speed

transceiver circuits used in high-speed wireline communications that operate in the 60

Gb/s range. This thesis is based on research done on high speed equalizer standards for

the USB 3.1 SuperSpeed Differential Channel Loss Receiver Equalizer or Peripheral

Component Interconnect (PCI) Express® Base Specification Revision 3.0. As of 2015,

USB 3.1 and PCI Express® 3.0 are technologies with possibilities to be implemented in

emerging technology targeted to consumer applications that demand improvements in

signal integrity for high speed serial data communication of baud rates above 20 Gb/s.

This thesis proposes a circuit design for an adaptive equalizer capable of adjusting its

voltage gain, bandwidth, and boost for high speed data communications. The proposed

design is implemented with a novel variable gain amplifier (VGA), a digitally controlled

continuous time linear equalizer (CTLE), and a digitally controlled decision feedback

equalizer (DFE), which is believed to provide circuit power and signal integrity

improvements in the differential receiver and equalization subsystem that operate at 60

Gb/s .

iv
 ACKNOWLEDGEMENTS

This work was founded in part by Lockheed Martin Space Systems Company

(LMSSC) under the company’s employee educational program and in part by the United

States Navy through the Montgomery GI Bill.

I specially thank my friends and colleagues who provided me with the technical

advised and the guidance needed for the creation of this thesis. Albeit, I specially

appreciate the help and guidance from the faculty and staff of the department of electrical

engineering at San José State University who helped me understand and appreciate

complex circuitry design. I specially thank Professor Robert Morelos Zaragoza for his

guidance in explaining the fundamental theory behind channel modeling, Professor

Sotoudeh Hamedi-Hagh for teaching me simple techniques to analyze and understand

CMOS analog design, and most importantly Professor Shahab Ardalan for his persistent

guidance and mentorship that lead to the creation of this work. There is not enough space

in this document to individually thank those who became an integral part to my success

which consisted of all my professors, my professional colleges, my friends and my

family.

This thesis is especially dedicated to my mother, Refugio Tostado Alejandre, a

smart woman who inspired me with her exemplary knowledge, education,

professionalism, and perseverance and who instilled in me the courage to write this

thesis. I also dedicate this thesis to my two nephews, Román and Iñaki Villanueva in the

v
hope that one day they find the desire and inspiration to obtain any type of higher

education so that they can also become a beacon of inspiration to others.

vi
 TABLE OF CONTENTS

1 Introduction ............................................................................................................1

1.1 Historical Background ................................................................................ 1

1.2 Fundamental Transmission Frequency (Nyquist Frequency) and the Unit

Interval (UI) ................................................................................................ 3

1.3 Transmission Reliability, 8b/10b Data Symbols Coding, and Transfers per

Second (T/s) Measurement ......................................................................... 7

1.4 USB 3.1 Architecture Impact on Future Electronic Equipment ............... 11

1.4.1 USB Technology Transfer Rates 14

1.4.2 The SuperSpeed USB 3.0 Standard 17

1.4.3 The SuperSpeed+ USB 3.1 Standard 17

1.4.4 USB 3.0 and USB 3.1 Specification Standard Documentation 18

1.4.5 USB 3.0 and 3.1 Physical Interface Architecture 19

1.4.6 Standard Definition of the USB 3.0 Transmission Channel, the Full

Link Channel Model 20

1.5 2014 State of the Art Circuits in Analog Front-End Design for Gb/s

Wireline Receivers .................................................................................... 23

1.5.1 Technology Challenges 23

1.5.2 State of the Art Equalizer Circuits 24

vii
2 Channel Model .....................................................................................................33

2.1 Types of Printed Transmission Lines ....................................................... 33

2.2 The FR4 Microstrip Wire Line ................................................................. 36

2.3 Channel Capacity ...................................................................................... 39

2.4 Modeled FR4 PCB Traces of 1-oz Microstrip Lines ................................ 41

2.5 Simplified Circuit Model for FR4 Microstrip Channel ............................ 43

3 Equalizer Design ..................................................................................................53

3.1 Equalizer Bandwidth Limitations ............................................................. 55

3.2 Transit Frequency (𝒇𝑻) and Transit Time (𝝉𝑻) ........................................ 56

3.3 Transit Frequency Using the NMOS Diode Setup Model ........................ 75

3.4 Important NMOS Parameters Needed to Design an Amplifier ................ 86

3.5 Current Sources ......................................................................................... 90

3.6 Basic Amplifier ......................................................................................... 93

3.7 Amplification Chain Biasing .................................................................. 107

3.8 Differential Amplifier Configuration. ..................................................... 110

3.9 Pulse Shaping .......................................................................................... 111

3.10 30 GHz Equalizer Circuit Elements ........................................................ 117

4 Results .................................................................................................................119

4.1 High Pass Filter ....................................................................................... 119

viii
 4.2 Low Pass Filter ....................................................................................... 120

4.3 Pulse Shape Filter ................................................................................... 121

4.4 30 GHz Equalizer, 28 nm Technology ................................................... 122

5 Conclusion ..........................................................................................................124

6 References ...........................................................................................................127

ix
 LIST OF FIGURES

Figure 1-1 NRZ Differential Data Transmission ...........................................................4

Figure 1-2 Serial Transmission of a 10 Gb/s Signal with Repeating Code “0110” ......5

Figure 1-3 Transmission Examples of Serial Data at a Baud Rate of 10 Gb/s. (a)
Transmission of All-zeroes in 11 UIs, (b) Transmission of All-ones in 11
UIs, (c) Transmission of “01100011100” Bit Data, and (d) Transmission
of the Nyquist or Fundamental Frequency “010101010101010…) ............6

Figure 1-4 Example of Received Data if the Data Signal is Shifted by One UI. (a)
Transmitted Data Example; (b) Decimal and Hexadecimal Values of
Transmitted Data (a); (c) Example of Received Data Wrongly Shifted by
One UI; and (d) Decimal and Hexadecimal Value of Buffered Data (c) .....8

Figure 1-5 Overall Block Diagram for the USB 3.0 Physical Layer Design ..............20

Figure 1-6 USB 3.0 and USB 3.1 Short Channel Application Range .........................21

Figure 1-7 Full Link Model for Short Channel Application Range on USB 3.0 and
USB 3.1 ......................................................................................................22

Figure 1-8 Full Link Model for Long Channel Application Range on USB 3.0 and
USB 3.1 ......................................................................................................22

Figure 1-9 Analog Front End (AFE) Design of a Receiver CTLE Equalizer. Figure
Adapted by Author from [6] ......................................................................25

Figure 1-10 Transimpedance Gain. Frequency Response for the AFE. Figure Created
by Author from Data in [6] ........................................................................26

Figure 1-11 Transimpedance Gain. Frequency Response for the AFE. Figure Adapted
by Author from [7] .....................................................................................27

Figure 1-12 Charge-Based Sample-and-Hold (S/H) with Clocked Adaptive Loads.

Figure Adapted by Author from [7] ...........................................................28

Figure 1-13 Trans-Impedance Equalizer. Figure Adapted by Author from [9] ...........29

x
Figure 1-14 Pseudo-Differential CMOS Push-Pull Trans-Impedance Equalizer. Figure
Adapted by Author from [10] ....................................................................31

Figure 1-15 TAS-TIA CTLE. Figure Adapted by Author from [11] ...........................32

Figure 2-1 Typical Microstrip Line Configuration for Differential Transmission

Lines ...........................................................................................................34

Figure 2-2 Microstrip Lines Interelement Capacitance ...............................................35

Figure 2-3 FR4 Channel Interconnection ....................................................................36

Figure 2-4 FR4 Channel Loss for 9” (22.86 cm-long) and 26” (66.04 cm-long)
Wirelines. (a) Cross Section of an FR4 Microstrip Wireline; (b) Cross
Section of a Stripline Wireline. Frequency is Displayed in Linear Form .38

Figure 2-5 PCB Layout of an FR4 Microstrip and Stripline Wirelines Connected
Using Vias. Via Stubs Create Additional Interelement Capacitances ......39

Figure 2-6 Channel Capacity System Model ...............................................................40

Figure 2-7 Channel Capacity for Various Lengths of 1-oz Microstrip Wirelines with
Noiseless Environment. Data Adapted by Author from [12] ...................42

Figure 2-8 Channel Capacity for Various Lengths of 1-oz Microstrip Wirelines with
Noise Environment Caused by Signal Crosstalk and Ambient
Electromagnetic Noise. Data Adapted by Author from [12] ....................43

Figure 2-9 Modeled Channel Transfer Function Response (𝐻(𝑓)) of a 56Ω

Impedance Noiseless FR4 Microstrip or Stripline. Data Adapted by
Author from [12] ........................................................................................44

Figure 2-10 Modeled Channel Transfer Function Response (𝑯(𝒇)) of a 66.04 cm-long
Copper Microstrip that has a -50 dB Response at 10 GHz ........................47

Figure 2-11 Simplified Pi-Model for Channel Transfer Function Response (𝑯(𝒇)) of a
66.04 cm-long Copper Microstrip that Has a -50 dB Response at 10
GHz ............................................................................................................48

xi
Figure 2-12 Simplified Pi-Model for Channel Transfer Function Response (𝑯(𝒇)) of 1
cm-long Copper Microstrip Segments. (a) Simplified 1 cm-long Channel
Segment; (b) Combination of Two Simple Segments to Increase the
Length of the Channel; (c) Model of a 3 cm-long Channel Using the
Simple Channel Model ..............................................................................51

Figure 2-13 Channel Attenuation Results for Proposed Simple Model. (a) Channel
Attenuation for One Segment Pi-model; (b) 10 cm-long Channel; (c) 20
cm-long Channel; (d) 30 cm-long Channel; (e) 40 cm-long Channel; (f) 50
cm-long Channel; (g) 60 cm-long Channel; and (h) 66 cm-long Channel 52

Figure 3-1 Channel Attenuation Results for Proposed Simple Model. The Graph on
the Left X-axis Has a Linear Display while the Graph on the Right has a
Logarithmic Display. (b) 10 cm-long Channel; (c) 20 cm-long Channel;
(d) 30 cm-long Channel; (e) 40 cm-long Channel; (f) 50 cm-long Channel;
(g) 60 cm-long Channel; and (h) 66 cm-long Channel ..............................53

Figure 3-2 System Model for an Ideal Equalizer.........................................................54

Figure 3-3 Ideal Equalizer Response ...........................................................................55

Figure 3-4 Circuit Model Setup to Measure the Transistor’s Transit Frequency ........57

Figure 3-5 Small Signal π-Model for Circuit Model to Measure Transit Frequency.
(a) All Intrinsic Transistor Components Shown, and (b) Intrinsic
Transistor Elements Affected by the Circuit Test Model (Simplified)......60

Figure 3-6 Bode Plot for Equation (3-18)....................................................................62

Figure 3-7 Current Gain for a 28 nm NMOS. Voltage Gate bias Creates Different
Current Gain Profiles .................................................................................71

Figure 3-8 Drain Current for a 28 nm NMOS. Voltage Gate Bias Creates Different
Current Gain Profiles .................................................................................72

Figure 3-9 Transit Frequency. Current Gain for a 28 nm NMOS. Transit Frequency
is the Frequency that Intersect the Gain of 1 A/A .....................................73

Figure 3-10 Current Gain for a 28 nm NMOS. Common Mode Voltage (𝑽𝑮𝑮) set at
0.7 V. Transit Frequency at Current Gain of 1 A/A is 234.27 GHz.

xii
 Desired Current Gain at 30 GHz is Around 7 A/A. Drain Current at
Desired Design Frequency of 30 GHz is 74.48 µA ...................................74

Figure 3-11 NMOS Diode Configuration to Extract Transistor Technology

Parameters ..................................................................................................76

Figure 3-12 NMOS Diode Configuration. (a) Small Signal Model for Figure 3-11
Circuit. (b) π-Model for NMOS Diode Configuration ..............................77

Figure 3-13 Difference Between Classic Transit Frequency—Shown with Negative

Frequencies—and Transit Frequency Proposed in this Paper—Shown with
Positive Frequencies ..................................................................................81

Figure 3-14 28 nm NMOS Technology. (a) Gate Capacitance; (b) Drain

Capacitance ................................................................................................84

Figure 3-15 28 nm NMOS Technology. Transconductance Gain (𝒈𝒎) for NMOS

Connected in the Diode Configuration. .....................................................85

Figure 3-16 28 nm NMOS Technology. Different Derivations Comparison for Transit

Frequency when the NMOS is Connected in the Diode Configuration.....86

Figure 3-17 Gate Capacitance for 28 nm NMOS Technology. Small Signal

Parameter ...................................................................................................87

Figure 3-18 Maximum Drain Current for 28 nm NMOS Technology. Large Signal
Parameter. NMOS Intrinsic Transistor Sized to 30 nm Width and 80 nm
Length ........................................................................................................88

Figure 3-19 Hysteresis Gate Impedance for 28 nm NMOS Technology. Large Signal
Parameter ...................................................................................................88

Figure 3-20 Hysteresis Gate Impedance for 28 nm NMOS Technology. Small Signal
Parameter ...................................................................................................89

Figure 3-21 28 nm NMOS Technology. Different Derivations Comparison for Transit

Frequency when the NMOS is Connected in the Diode Configuration.....89

Figure 3-22 Programmable Current Mirror to Provide a Source Current (𝑰𝑺) ..............91

xiii
Figure 3-23 Current Mirror Measurements. Current Source (𝑰𝑺) is Adjusted by
Increasing the Number of Gate Fingers Parameter in the N2 Transistor ...92

Figure 3-24 Common Source NMOS Differential Amplifier........................................93

Figure 3-25 Simplified Common-source NMOS Circuit Leg for a Differential

Amplifier ....................................................................................................94

Figure 3-26 Common Source NMOS Differential Amplifier........................................95

Figure 3-27 Amplifier’s Source Current. Solid Line Represents Desired Finger Size 96

Figure 3-28 Amplifier Circuit Current Source ..............................................................97

Figure 3-29 High-bandwidth Common Source Amplifier with Programmable Load and
Current Source Control. Common Mode Voltage is Setup at 0.7 V.........98

Figure 3-30 High-bandwidth Amplifier Design with Various Voltage Gain Outputs ..98

Figure 3-31 Small Signal Model for Simplified NMOS Amplifier. (b) Simplified
Small Signal Model for NMOS Amplifier.................................................99

Figure 3-32 Connection of Two Identical Amplifiers Coupled without the Need of a
Coupling Capacitor. Quiescent Point of First Amplifier Bias the Gate
Input to the Second Amplifier..................................................................107

Figure 3-33 Evaluation of Amplifier Quiescent Point Voltage (Q). The Quiescent
Point of the First Amplifier Stage Affects the Input Gate Bias of the
Second Stage ............................................................................................108

Figure 3-34 Two Stage Amplifier with No Coupling Capacitance between the Stages is
Necessary .................................................................................................110

Figure 3-35 Two Stage Differential Amplifier with No Coupling Capacitance between
the Stages is Necessary. Active Load and Output Power Control ..........111

Figure 3-36 Hi Pass Filter ............................................................................................112

Figure 3-37 Equalizer Model Using a High Pass Filter in Series with an Amplifier ..113

xiv
Figure 3-38 Bode Plot Representation of a Pulse Shape Signal using a Low Pass and a
High Pass Filter Connected in Series .......................................................114

Figure 3-39 Passive Pulse Shape Filter .......................................................................115

Figure 3-40 Variable Passive Pulse Shape Filter. HPF Resistor is Programmed or
Varied to Add Attenuation to the Lower Frequency Range ....................116

Figure 3-41 Programmable Differential Pulse Shape Filter ........................................117

Figure 4-1 Frequency Response for High Pass Filter (HPF) Design.........................120

Figure 4-2 Frequency Response for Low Pass Filter (LPF) Design ..........................121

Figure 4-3 Frequency Response for Pulse Shape Filter (PSF) Design ......................122

Figure 4-4 This Thesis Equalizer Voltage Gain Response—Logarithmic

Frequency.................................................................................................122

Figure 4-5 This Thesis Equalizer Voltage Gain Response—Linear Frequency........123

xv
 LIST OF TABLES

Table 1-1 An 8b/10b Data Symbol Coding for Serial Data Transmitted over USB
3.X and PCIe® 3.0. This Table only Shows Eight Data Byte Names out
of More than 256 Allowable Coded Symbols............................................10

Table 3-1 Transfer Function Results for a 28 nm NMOS Capacitor using Cadence®
Virtuoso® Tools. .......................................................................................83

Table 3-2 Measured DC Parameters for Amplifier in Figure 3-21 Using Cadence®
Virtuoso® Analog Design Environment—Transient Analysis ...............109

Table 4-1 High Pass Filter Calculated Values for Passive Filter Elements .............119

Table 4-2 Low Pass Filter Calculated Values for Passive Filter Elements ..............121

xvi
1 Introduction

1.1 Historical Background

Since the advent of high speed serial digital communications, consumers have

been able to transfer data from computers to a variety of electronic devices such as

printers, fax machines, portable communication devices, and storage devices without the

use of bulky cables. To date, the most recognized portable device interface among

consumers worldwide is the Universal Serial Bus (USB) device interface. However,

there are other types of similar serial communications. Perhaps the most recognized

serial communication used between microcircuit devices is the PCI Express®. This

thesis uses the fundamental theory used behind two well-known high speed serial

communication standards.

Millions of USB consumer interface devices have been designed worldwide to

communicate with portable computers, smart phones, portable music or data devices and

most recently to communicate with luxury vehicle entertainment systems. In recent

years, there has been an increasing demand to build electronic systems that contain

microcircuit components that use the USB serial communication standard to transmit

data, voice or video signals at an increasing transmission rate. The USB standard is

commonly used to transmit information between two open system architectures—

between two products used by a consumer. However, a common standard that is

intended to enhance data communication between electronic components made by

different vendors is the PCI Express® (a.k.a. PCIe®) because it provides high speed

communications that are higher than what the USB standard offers. The PCIe®

1
communication standard allows point-to-point communication between microcircuit

chips to minimize timing issues caused by multiple signal wires. Unlike the USB

standard that is intended to have a maximum of three meters in length for link

connections1 between two USB devices, the PCIe® is designed to facilitate short length

communication between two or more microcircuit devices within a printed circuit board

which result in making a physical connection with a much shorter length.

Recently, the technological trend and challenge have been to design circuits that

reduce the amount of power, jitter, and design area while increasing the single data

signal2 transmission speeds, data and signal reliability, and bandwidth. However, serial

data transmission between USB or PCIe® devices is susceptible to the transmission line

loss (hereon referred as “channel loss”) which directly affects the signal integrity. To

compensate for the channel loss, a USB or PCIe® receiver design rely on a receiver front

end electronic circuit design called the differential deceiver and equalization subsystem—

which is the focus of this thesis.

1
In standard network communication theory, a link connection is a point-to-point connection between two
and independent physical ports. Each port belongs to a communication element in a network system.
2
The term single data signal is also referred to as serial data which is information or data that travel in a
single transmission line. When testing or probing data information on a single transmission line, data are
displayed across a time or frequency domain—each datum becomes a bit or frequency depending on how
the data signal is displayed. However, every bit, frequency, datum, or piece of information is stitched and
displayed into a single signal which forms the data signal. Therefore, many authors, this thesis—and the
industry in general—use the term data as if it were a singular term—instead of a plural term—because it
refers to a singular concept which is the data signal—a singular term—traveling in a single line. The
single term for a piece of information is a datum. Therefore, the term “data” is correctly applied as a
singular term when the context refers to probing electronic data from a single line. A datum is a bit of data
while data is just the voltage or frequency signal in a single metallic line that changes with time.

2
1.2 Fundamental Transmission Frequency (Nyquist Frequency) and the Unit

Interval (UI)

Serial binary data communication between two devices can be accomplished

electronically in many ways. The USB and PCIe® standards rely on communicating data

using the non-return-to-zero (NRZ) line code. In binary serial communication, a data

signal is sent through a wire by changing the voltage of the wire with respect to time.

When a logical data signal is asserted or is true, the voltage in the wire is driven to the

transmitter driver’s highest possible voltage—the datum or bit of data is a logical one.

Conversely, when the logical data is de-asserted or not true, the voltage in the wire is

driven to the transmitter’s lowest possible voltage—the datum or bit is a logical zero. As

a result, the transmission line requires either a high voltage to represent a logical one or a

low voltage to represent a logical zero. When using a differential transmission line (two-

wire communication), a change in voltage in the transmission line always indicates a data

bit transition and a data bit is always asserted or de-asserted for a predetermined period of

time called the unit interval (UI) (Figure 1-1).

3
 Time

D+
Differential
Voltage
D-
Logic 0 or
Logic 1 0 1 1 0 0 0 1 0 1 0
True or False F T T F F F T F T F
Asserted or
De-asserted D A A D D D A D A D
Bit Number bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9

UI 3 UIs
Figure 1-1 NRZ Differential Data Transmission

Baud rate refers to the speed at which logical ones and logical zeroes can be

transmitted and detected over the line per a specified UI time interval. Baud rate is also

known as the data signaling rate or simply bit rate. In the telecommunication industry,

when describing a receiver’s bit rate (baud rate), the bit rate is measured using the bit-

per-second (b/s) standard.

Let us consider a scenario where four bits are transmitted over a data line in 400

ps. Therefore, each bit would require a time of 100 ps to be transmitted. In this scenario

there are 24 or 16 combinations of ones and zeroes of possible combinations that are

serially transmitting four bits in 400 ps. In other words, every 400 ps there are four serial

bits that are transmitted. The receiver may receive the “0000” combination or a low

voltage for a period of 400 ps, or the transmitter may send a combination of “0110”

4
which in this case it means that for the first 100 ps, the receiver sees a low voltage

followed by a transition of a high voltage for 200 ps and ends with a transition of a low

voltage for the last 100 ps (Figure 1-2).

100
4 UIs [ps] 200 [ps]

0 1 1 0 0 1 1 0 0 1 1
D+

Figure 1-2 Serial Transmission of a 10 Gb/s Signal with Repeating Code “0110”

The unit interval for a 10 Gb/s is calculated by simply dividing one second by the

number of bits in that second. Therefore, the unit interval for a 10 Gb/s receiver is 100

ps. The time interval for each bit in this example is 100 ps. The time interval for one bit

in the data transmission is also known as the unit interval (UI). For example, in a

differential transmission line where each bit is transmitted using NRZ line code at a baud

rate of 10 Gb/s, the unit interval (UI) is calculated as follows:

1[𝑏] 1
𝑈𝐼 𝐺𝑏 = = [𝑠] = 0.1 × 10−9 [𝑠] = 0.1[𝑛𝑠]
10
𝑠 𝐺𝑏 (10)(109 ) (1-1)
10 [ 𝑠 ]

= 100[𝑝𝑠]

This means that in every 100 ps, the voltage signal could be a logic one or a logic

zero. This also means that the receiver may see a series of logical zeroes

(“0000…0000”), a series of logical ones (“1111111…11111”), a combination of zeroes

and ones (“0110001110…00011100”), or simply a combination of ones and zeroes

(“01010101…01010101”) (Figure 1-3).

5
 11 UIs = 1.1 [ns]
0 0 0 0 0 0 0 0 0 0 0
(a) D+

1 1 1 1 1 1 1 1 1 1 1
(b) D+

0 1 1 0 0 0 1 1 1 0 0
(c) D+

0 1 0 1 0 1 0 1 0 1 0
D+
(d)
200 [ps]

Figure 1-3 Transmission Examples of Serial Data at a Baud Rate of 10 Gb/s. (a) Transmission of

All-zeroes in 11 UIs, (b) Transmission of All-ones in 11 UIs, (c) Transmission of

“01100011100” Bit Data, and (d) Transmission of the Nyquist or Fundamental Frequency

“010101010101010…)

If the UI for a 10 Gb/s is 100 ps, and the data signal transmitted is a combination

of ones and zeroes (“01010101…0101010”), then the cyclic change or time period of the

data pattern “01” occurs every 200 ps (Figure 1-3d). This means that the highest data

frequency in terms of cyclic voltage change is 5 GHz which is known as the Nyquist

frequency or fundamental frequency. In other words, the Nyquist frequency in a NRZ

communication circuit is calculated by dividing the baud rate by two but the measure is

in Hertz instead of bits-per-second.

6
 Equalizer circuits are designs that take under consideration the Nyquist frequency.

For USB 3.0 devices that transmit at a baud rate of 5 Gb/s, the Nyquist frequency is 2.5

GHz. For USB 3.1 devices that transmit at a baud rate of 10 Gb/s, the Nyquist frequency

is 5 GHz. For the PCIe® 3.0 devices that transmit at a baud rate of 10 Gb/s, the Nyquist

frequency is 5 GHz. This thesis proposes a design that works at a Nyquist frequency of

30 GHz. Therefore, the maximum transmission data rate of this thesis circuit is 60 Gb/s.

An important observation made is that if data is sent over a line with a baud rate

of 60 Gb/s, the random data may take a form of any frequency of frequencies below 30

GHz.

1.3 Transmission Reliability, 8b/10b Data Symbols Coding, and Transfers per

Second (T/s) Measurement

In PCIe® 3.0 or USB 3.0, for every 8 bits (1 Byte) transferred, an additional 2 bits

are added to increase the reliability of the read data. This is done in an effort to increase

the reliability of the transmitted data by encoding bytes in the following manner. A

combination of 8 serial bits (one serial Byte) is known as a data symbol. The total

number of combinations of data symbols in one transmitted Byte is 28 or 256 symbols.

The symbols range from decimal values 0 to 255. However, there are symbols that may

look similar to the receiver. For example, symbol “01010101” may be seen by the

receiver as “10101010” or symbol “00100101” may be confused by the receiver as

“01001010” or “10010010” if the receiver is reading the data signal at the wrong time. In

7
other words, if a receiver buffers serial data every nibble3 is received, and if the serial

data is a series of nibbles with the bit value of 5b or hexadecimal value of 5h, then by just

shifting the data by one UI the receiver will buffer the data with the wrong bit value of

10b or hexadecimal value of Ah (Figure 1-4).

11 UIs = 1.1 [ns]

0 1 0 1 0 1 0 1 0 1 0
(a) Tx
D+

(b) 5 = 5h 5 = 5h 5 = 5h

1 0 1 0 1 0 1 0 1 0 1
(c) Rx
D+

(d) 10 = Ah 10 = Ah 10 = Ah

400 [ps]
One Nibble

Figure 1-4 Example of Received Data if the Data Signal is Shifted by One UI. (a) Transmitted Data

Example; (b) Decimal and Hexadecimal Values of Transmitted Data (a); (c) Example of

Received Data Wrongly Shifted by One UI; and (d) Decimal and Hexadecimal Value of

Buffered Data (c)

One way to minimize the error in the data received, or to increase the reliability of

the data received, is by adding a couple of bits to the serial symbol to create a larger

number of combinations which creates a total of 210 or 1024 combinations instead of the

3
A nibble is four bits or half a Byte. Data with nibble bits [0101b] has a bit value of 5 or a hexadecimal
value of Ah. The letter “b” (bit power number) and letter “h”(hexadecimal power number) abbreviates the
power number. No letter after the number indicates the number is the decimal power form.

8
256 valid data combinations. The probability of error is reduced by decreasing the

possible valid outcomes from a universe of 1024 combinations.

The PCIe® 3.0 and USB 3.0 (Gen 1) architecture uses the 8b/10b data symbol

coding per ANSI X3.230-1994 (also refereed as ANSI INCITS 230-1194) specification

(see Table 1-1). As mentioned above, for every Byte of serial information, a couple of

bits are added hence creating 1024 possible combinations whereby only 256

combinations are valid. Every Byte valid data combination is given a data Byte name.

Every bit in the valid Byte is given a letter designation from letter “A” to letter “H.” The

encoder inserts a bit “L” between the letters “E” and “F” and inserts a bit “J” after the

letter “H” to create the 10 bit.

For example, eight bits or one byte is represented by “𝑏7 𝑏6 𝑏5 𝑏4 𝑏3 𝑏2 𝑏1 𝑏0 ” where

𝑏7 is the most significant bit (MSB) and 𝑏0 is the least significant bit (LSB). Each bit is

assigned a capital letter: [𝑏7 𝑏6 𝑏5 𝑏4 𝑏3 𝑏2 𝑏1 𝑏0 ] = [H G F E D C B A]. If most of the bits

are zeroes, then the Running Disparity (RD) of the symbol sequence on a per-lane basis is

considered negative; else, most of the bits are ones and the RD is positive; otherwise

there are an equal amount of ones and zeroes which means that the RD is zero. Data are

scrambled every two bytes using the linear feedback shift register (LFSR) algorithm with

the 16th degree polynomial 𝑥16 + 𝑥 5 + 𝑥 4 + 𝑥 3 + 𝑥 0 . This means that bits 0, 3, 4, 5, and

16 are inverted and shifted.

After LFSR is applied, a couple of bits are inserted between𝑏4 and 𝑏5 and after 𝑏7

to form: [𝑏9 𝑏8 𝑏7 𝑏6 𝑏5 𝑏4 𝑏3 𝑏2 𝑏1 𝑏0 ] = [j h g f l e d c b a]—the inserted bits are represented

9
in red by lower case letters “j” and “l”. Here is an example of several data symbols

transmitted using the 8b/10b data symbol coding (see Table 1-1).

Table 1-1 An 8b/10b Data Symbol Coding for Serial Data Transmitted over USB 3.X and PCIe®

3.0. This Table only Shows Eight Data Byte Names out of More than 256 Allowable

Coded Symbols

Data
Data Bits Current RD- Current RD+
Byte
Byte HGF EDCBA abcdeifghj abcdei fghj
Value
Name [binary] [binary] [binary]
[hex]
D0.0 00 000 00000 100111 0100 011000 1011
D1.0 01 000 00001 011101 0100 100010 1011
D2.0 02 000 00010 101101 0100 010010 1011
D3.0 03 000 00011 110001 1011 110001 0100
D4.0 04 000 00100 110101 0100 001010 1011
D5.0 05 000 00101 101001 1011 101001 0100
D6.0 06 000 00110 011001 1011 011001 0100
D7.0 07 000 00111 111000 1011 000111 0100

The transfers per second (T/s) measure relates to the effective transfer rate of

valid bits per second. In the 8b/10b data symbol coding, for every 10 bits transmitted,

only 8 bits are valid. Therefore, the effective transmission rate is 8-bits in a time

allocated for 10-bits. If the transmitter transmits at a rate of 5 Gb/s, the Transfers per

second is calculated as follow:

𝐺𝑏 8 [𝑇] 𝐺𝑇 (1-2)
(5 [ ]) ( ) = 4[ ]
𝑠 10 [𝑏] 𝑠

Perhaps the most important data Byte name in the 8b/10b data symbol coding is

“D10.2.” Although its 8-bit input is “01001010b,” the 10-bit output is “0101010101b”

10
which is the Nyquist frequency. There is no other 8-bit symbol that can create the pattern

“0101010101.” In the event that the pattern is seen shifted as “1010101010,” the receiver

will shift the data by one UI and assume that the correct data was symbol “D10.2.”

Although the 8b/10b data symbol coding is effective to increase the reliability of

the received signal, the system slows down the rate at which useful data is transmitted. In

the event that the 8b/10b data symbol coding is used in a 20 Gb/s transmission line, the

actual transfer rate is 16 GT/s. Every second, 4 Gb are discarded. This represents 20%

of the transmission time is used to pass invalid data.

The 8b/10b coding is normally used for data transfer rates of less than 5 Gb/s.

USB 3.1 (Gen 2) uses a 128b/132b line encoding to transmit serial frames at a rate of 10

Gb/s which means that its Nyquist or fundamental frequency is 5 GHz. Each frame

contains data and control information. Each frame is made of a 4-bit header and 12-bit

payload. The 4-bit header identifies whether the frame is for data (“0011b”)4 or control

(“1100b”). As frames are received, data is aligned into 128 block; each block is made of

132 bits. Description of the transmission frame is beyond the scope of this thesis.

However, it can be said that the effective data transfer to an application after the serial

data has been decoded can be as high as 9.6 GT/s.

1.4 USB 3.1 Architecture Impact on Future Electronic Equipment

To understand the impact that USB and PCIe® have over the present electronic

technology, a historical background is needed. Beginning with USB architecture, the

USB serial interfaces replaced slow speed parallel interfaces used by printers and other

4
The letter “b” at the end of the bit sequence indicates that this is a binary number.

11
parallel interfaced devices that connected to desktops or laptop computers. Since 1996,

USB version 1.0 technology has allowed consumer electronics devices to become more

portable because USB technology replaced the bulky parallel interfaces or ports. The 25

pin printer ports were quickly replaced by 4 pin USB ports. The USB version 1.0

technology only supported data transfer rates (also known as “baud rates”) from 10 kb/s

to 10 Mb/s.5 As a result, the USB 1.0 technology could only be used by a limited array of

consumer devices such as keyboards, game peripherals, e.g. joysticks, and audio devices.

In other words, a 4 MB song or picture can be transferred between two USB 1.1 devices

in 5.3 seconds but in contrast a 25 GB high definition (HD) movie would take about 9.3

hours to be transferred.

One of the most important attributes of the USB interface technology is its ease-

of-use among portable device users because it allows the end user the capability of using

plug-and-play devices capable of self-configuring when connecting to a computer. Older

technology such as parallel interfaces required a more complex hardware and software

implementation. The second most important attribute is its port physical size, cost, and

device adaptation. The USB port expansion attribute allowed manufacturers to design

and adapt devices that were considered low-speed devices such as a keyboard to use the

same port interface of a mid-speed devices for instance a storage devices.

Nevertheless, innovations in technology, for example the invention of submicron

technology,6 enabled the possibility to design faster serial interfaces because such

5
For purposes of this thesis, all data rates or baud rates are measured in bits per second (b/s). A small letter
“b” represents bits while an upper letter “B” represents bytes.
6
A submicron technology is a technology whereby the smallest transistor length is below 1 µm.

12
technology can operate with a higher frequency bandwidth. A USB version 3.0 interface

allows devices to transfer a 4 MB song or picture in just 10 milliseconds or a 25 GB HD

movie in just 70 seconds because under this standard revision the transmission bout rate

can reach 5 Gb/s or 4 GT/s. As of 2014, USB version 3.0 gave the possibility to vide

stream high definition video between two USB 3.0 devices. As a result, the higher speed

serial communication that resulted from the USB 3.0 specification expanded its market

opportunity to a variety of consumer devices such as digital cameras and camcorders,

flash-based digital media and video players, smart phones, etcetera.

Because consumers are now constantly relying on portable devices such as smart

phones, portable storage devices, and other portable devices, consumers have to recharge

or power these devices. Under the USB 3.0 standard there is an added functionality to

power devices that require power management. Power management is the ability to

provide power to a device only when the device requires it, thus conserving energy.

Consumers value the importance of buying electronic devices that have the USB

3.0 interface with hardware applications that include having external mass storage

devices used to stream high definition video.7 As of 2014, the USB standard organization

has projected a shipment of more than 4,250,000,000 USB devices worldwide.

According to a Global Industry Analysts Inc. (GIA)8 detailed market report, the USB 3.0

7
Western Digital, a portable media drive manufacturer, markets a line of USB 3.0 portable hard drives of
the size of a travel passport and capable to store up to 150 hours of high definition digital movies in 2TB
capacity.
8
According to MarketResearch.com, “Global Industry Analysts, Inc., (GIA) is a leading publisher of off-
the-shelf market research. Founded in 1987, the company currently publishes more than 1300 full-scale
research reports and analyzes 40,000+ market and technology trends while monitoring more than 126,000
Companies worldwide. GIA is recognized today as one of the world's largest and reputed market research
firms serving over 9500 clients in 27 countries.”

13
market is yet to render its full potential since its technology is predicted a global increase

of sales of as many of 3 Billion USB 3.0 enabled devices by 2018 which will result in

revenues in the tenths of trillions of dollars [1] Global Industry Analyst, Inc. USB

3.0 – A Global Strategic Business Report. March 2013.

The Universal Serial Bus 3.1 Specification was released by the USB

Implementers Forum, Inc., on July 26, 2013. The SuperSpeed USB 3.1 delivers baud

rates of 10 Gb/s. As of March 2014—when this thesis was written—no published or

manufactured microcircuit components that would satisfy this standard were found. This

specific standard offers a solution to users to exchange large files between devices in

minutes while maintaining power management efficiency.

The USB 3.1 technology is still considered a deployed emerging technology with

possibilities of implementation in new USB Flash Drives by 2015, USB Hub devices, on-

the-fly Encryption for External USB devices, medical devices, automotive industry, etc.

The fact that these implementations have yet to be created by 2014 suggests that there are

still challenges in implementing the USB 3.1 that near the 10 Gb/s transfer rates.

1.4.1 USB Technology Transfer Rates

The USB standard is maintained and regulated by the nonprofit corporation called

USB Implementers Forum, Inc. (www.usb.org). The corporation was formed by

companies that developed the USB standard whose main goal is to promote the benefits

of using USB peripherals in high speed serial communication. These companies are

Hewlett-Packard (DBA HP), Intel Corporation, LSI Corporation, Microsoft Corporation,

14
Renesas Electronics, and STMicroelectronics. USB Implementers Forum, Inc., created

and supports the following standards:

(a) SuperSpeed+ USB 3.1

(b) SuperSpeed USB 3.0

(c) Wireless USB (WUSB)

(d) On-The-Go Hi-Speed USB

(e) On-The-Go Basic-Speed USB

(f) Hi-Speed USB

(g) Basic-USB

(h) ExpressCard®9

USB version 1.0 was released providing two data speeds: 1.5 Mb/s and 12 Mb/s.

USB 1.0 was limited to interface with keyboard, printers, and similar interface devices.

As personal computers (PCs) became smaller and more portable, users demanded a wider

range of interface connectivity which included portable storage media—commonly

known as memory sticks or thumb drives. To address this demand, the USB

Implementers Forum, Inc. released the USB 2.0 specification in the year 2000 that

allowed not only backward-compatibility but also increased the serial transfer rate to 480

Mb/s. Five years later, in 2005, demand for free-of-all-wires wireless technology

inspired the release of Wireless USB making the USB peripheral the most used and

versatile PC peripheral in the world.

9
The ExpressCard® standard was created by PCMCIA Association member companies formed by Dell,
Hewlett Packard (DBA HP), IBM, Intel, Lexar Media, Microsoft, SCM Microsystems and Texas
Instruments (DBA TI) with a collaboration and assistance of the USB Implementers Forum, Inc., and the
collaboration of the Peripheral Component Interconnect-Special Interest Group (a.k.a. PCI-SIG).

15
 The year of 2006 became the year where the world was entered the age of smart

mobile technology. Products such as smart phones, the iPad, the notebooks, and book

readers became an everyday household item. The word “USB” became a popular word

and advances in network routing and communication were necessary to provide

connectivity service to what was then 2 billion USB devices. USB 2.0 adopted network

routing technology similar to what is used in Ethernet network communications to allow

USB devices negotiate with one another for the purpose of self-setup and speed up

communication in shared USB architectures. The On-the-Go USB communication relies

on USB hosts, USB servers, and USB hubs that follow the 4 layer USB transmission

protocol rules. By using a USB protocol, the communication capability extended the

consumer market of the USB serial port to industrial applications and security systems.

By the year 2011, consumers were hungry for shared content products capable to

video stream on demand, or store large amounts of information. High definition

photography, HD camcorders, and similar devices required storage spaces that were in

the tenths of Giga Bytes. Transmission rates of large amount of data required a faster

than the available 480 Mb/s transfer rates. This was resolved by introducing SuperSpeed

USB 3.0 to free users from the consuming process of transferring large amounts of

information. The transmission rates of a SuperSpeed USB 3.0 connection can provide

transfer rates of up to 5 Gb/s.

Currently, the State-of-the-Art communications demand faster transfer data rates

for the USB interface. In August 2013, the USB Implementers Forum, Inc. completed

the SuperSpeed+ USB 3.1 standard to enable transmission data rates of up to 10 Gb/s.

16
However, by the first quarter of 2014, the author was not able to find any manufacturer

that had implemented a SuperSpeed+ USB 3.1 solution.

It is argued that if a SuperSpeed USB 3.0 architecture design has an adaptive

receiver front-end implementation, then it is possible that the receiver may improve the

common inter-symbol interference (ISI) created by the transmission line between the

transmitter and the receiver.

1.4.2 The SuperSpeed USB 3.0 Standard

The SuperSpeed USB 3.0 standard [2] is compatible to earlier revisions of the

USB standard. However, to support higher transmission rates, an additional 5 wires were

added to the USB 3.0 transmission line. A USB 2.0 plug has 4 terminals while a USB 3.0

has 9 terminals.

The SuperSpeed (SS) USB 3.0 standard supports data rates of up to 5Gb/s. As of

the first quarter of 2014, the SS USB3.0 standard is a deployed technology that has both

software and hardware support for consumers. However, the USB Implementers Forum,

Inc., recently introduced the new SuperSpeed+ USB 3.1 standard that supports up to

10GB/s transfer rates.

1.4.3 The SuperSpeed+ USB 3.1 Standard

The SuperSpeed+ USB 3. Standard [3] is a backward compatible standard that

supports data rates of up to 10 Gb/s and enhanced data encoding efficiency. The standard

allows data rated commonly found in Solid State Drives (SSDs) and High Definition

(HD) displays. This standard introduces the term “Gen 1,” which is used to reference the

receiver front end architecture and data requirements for the USB 3.0 standard to receive

17
a 5 Gb/s signal. The term “Gen 2” describes the receiver front end design for the

SuperSpeed+ USB 3.1 that allows baud rates of 10 Gb/s or effective data rate of as high

as 9.6 GT/s. The term “Gen X” refers to either Gen 1 or Gen 2 architectures.

1.4.4 USB 3.0 and USB 3.1 Specification Standard Documentation

This thesis project and proposal were inspired in part by the Universal Serial Bus

3.0 Specification which included errata and Engineering Change Notices (ECNs) through

May 1, 2011, Revision 1.0, June 6, 2011 [2]. Detailed specifications for the equalizer

design are described by the USB 3.0 SuperSpeed Equalizer Design Guidelines

documentation and by the Universal Serial Bus 3.1 Specification provided by the USB

Implementers Forum, Inc.

The authors of the USB 3.0 specification include the following companies:

Hewlett-Packard Company, Intel Corporation, Microsoft Corporation, NEC Corporation,

ST-Ericsson, and Texas Instruments. The authors for the USB 3.1 specification include

the following companies: Hewlett-Packard Company, Intel Corporation, Microsoft

Corporation, Renesas Corporation, ST-Ericsson, and Texas Instruments.

The USB 3.0 standard augments the basic architectural design of the USB 2.0

standard in functionality and data transmission rate. The USB 3.0 physical connection is

backwards and forward compatible. The USB 3.1 equalizer specification is different for

Gen 1 and Gen 2. The USB 3.0 and USB 3.1 standard defines a composite cable

whereby four of the lines are dedicated to support backwards compatibility to USB 2.0

and an additional five lines are used to provide the extended functionality of the USB 3.0

interface.

18
1.4.5 USB 3.0 and 3.1 Physical Interface Architecture

The USB 3.0 and USB 3.1 has adopted standard network communication

terminology and similar design organization as used in more mature and stable

technology such as Ethernet Communication Networks. The USB 3.0 communication is

arranged with a star topology. This means that point-to-point communications between

USB ports require that one port act as a host port while the other port act as a peripheral

device port.10 USB hubs may be used to drive and route communications between a USB

host and a USB peripheral device (Figure 1-5).

10
The terms “star topology,” “host,” and “point-to-point” are common technical terms used in the network
communication industry and definition and description of these terms are outside the scope of this thesis.
To have a better technical understanding of these terms, the reader is advised to read recommended training
material from the Computing Technology Industry Association (CompTIA) at www.comptia.org. The
term “peripheral device port” is a term compatible to the term “user port” as commonly used between
network communication designs that is based on layered protocol architecture.

19
 USB STAR COMMUNICATION TOPOLOGY

USB
PERIPHERAL
DEVICE

USB
USB HOST USB HUB PERIPHERAL
DEVICE

USB
PERIPHERAL
DEVICE

COMMUNICATION ROUTING
MECHANISM END USER
ADMINISTRATION

Figure 1-5 Overall Block Diagram for the USB 3.0 Physical Layer Design

1.4.6 Standard Definition of the USB 3.0 Transmission Channel, the Full Link

Channel Model

When two electronic devices use a USB wire interface, they must be

interconnected directly through USB connectors (hereon referred as a “short channel”)—

without a cable—or via USB connectors and a differential cable that is no longer than 3

meters long (hereon referred as “long channel”). The front end design must be able to

either meet the short channel design specifications or meet both the short and long

channel specifications.

A short channel interface consists of the wires from the USB transmitter to the die

pads, the connection from the die pad to the mother board—these connections pertain to

20
the component package—followed by the Printed Circuit Board (PCB) connections to the

USB connector, the connector and its mate, the PCB wire connection from the mate

connector to the receiver component package, the component package connections to the

receiver die pads, and the connection between the die pad to the USB receiver (Figure

1-6).

USB USB Peripheral

USB Host USB Host USB Host USB Peripheral USB Peripheral
Mated Device
Transceiver Package PCB Device PCB Device Package
Connector Transceiver

25 mm 10 mm

-4bB
Short Transmission Loss at 2.5 GHz

Figure 1-6 USB 3.0 and USB 3.1 Short Channel Application Range

The USB 3.0 standard specifies a maximum attenuation of -4dB between the USB

Host Transceiver to the USB Peripheral Device Transceiver at the fundamental

transmission frequency of 2.5 GHz.

A detailed representation of the USB transmission for a short channel is defined

as the full link short channel model (Figure 1-7).

21
 USB USB USB
USB
USB Host USB Host Stripline USB Host USB Host USB Host USB Host Peripheral Peripheral Peripheral USB Peripheral
Mated
Package PCB Via PCB PCB Via µtrip PCB AC Caps µtrip PCB Device Device Device Device Package
Connector
µtrip PCB Caps µtrip PCB

15.24 mm 2.54 mm 2.54 mm 2.54 mm 7.62 mm

13 mm 25 mm >10 mm 23 mm
USB Host Package USB Host PCB USB Peripheral Device PCB USB Host Package

Figure 1-7 Full Link Model for Short Channel Application Range on USB 3.0 and USB 3.1

As mentioned above, a long channel model includes a three meter connector and a

device connector the host connector and the device. The long channel full link model

PCB striplines11 are longer than the striplines used in the short channel (Figure 1-8).

USB USB USB

USB USB
USB Host USB Host Stripline USB Host USB Host USB Host USB Host Peripheral Peripheral Peripheral USB Peripheral
Mated Mated
Package PCB Via PCB PCB Via µtrip PCB AC Caps µtrip PCB Device Device Device Device Package
Connector Connector
µtrip PCB Caps µtrip PCB

241.3 mm 2.54 mm 2.54 mm 12.7 mm 38.10 mm

13 mm 251 mm 3m >50 mm 23 mm
USB Host Package USB Host PCB Cable USB Peripheral Device PCB USB Host Package

Figure 1-8 Full Link Model for Long Channel Application Range on USB 3.0 and USB 3.1

11
The term stripline refers to a type of transmission line used in PCB designs whereby the transmission line
is contained within the PCB substrate and sandwiched between two ground planes to minimize
electromagnetic interference (EMI) or white noise.

22
1.5 2014 State of the Art Circuits in Analog Front-End Design for Gb/s Wireline

Receivers

Front-end design refers to the transmitter or receiver end of the microcircuit

design. This thesis concentrates on the receiver front-end microcircuit design.

According to the International Solid-State Circuits Conference (ISSCC), a group of the

Institute of Electrical and Electronics Engineers (IEEE), the highest Nyquist frequency in

fast speed communication between devices is 30 GHz [4]. However, stable designs in the

industry achieve Nyquist frequencies of no more than 2.5 GHz. For example, the Texas

Instruments (TI) DS125BR820 is a low-power 12 Gbps 8-channel liner repeater with

equalization, the TI TLK2711-SP is a 1.6 Gbps to 2.5 Gbps Class V Transceiver, the TI

DS100BR111A is an ultra-low power 10.3 Gbps 2-channel repeater with input

equalization. Fujitsu reported at the annual ISSCC conference to have achieve the

world’s fastest transceiver of 32 Gbps for inter-processor data communication on

February 18, 2013 [5].

1.5.1 Technology Challenges

Signal degradation increases as the transmission rate increases because the

channel attenuation increases due to an increase in channel impedance. As a result,

equalizer circuits are needed to compensate for the loss in the signal.

Semiconductor technology has limitations as to the highest frequency it can

amplify. Equalizers must be able to match the loss of the signal by amplifying its signal.

This thesis will describe how to determine the highest frequency for the 28 nm

complementary metal-oxide semiconductor (CMOS) technology. Amplifiers have a

23
limited frequency bandwidth for amplification which is limited by the smallest intrinsic

length property of the CMOS transistor.

Power consumption increases as the Nyquist frequency increases. Power

dissipation and minimum power limitations may dictate the maximum baud rate.

The loss of the signal is increased as the transmission line length is increased

because the overall resistivity of the signal is increased. Signal crosstalk and reflections

are minimized by shielding the line and terminating the line with the correct impedance

matching respectively. However, for USB technologies, the length of the transmission

wire is variable while the impedance matching at the receiver end is fixed.

1.5.2 State of the Art Equalizer Circuits

This section illustrates the latest advances in equalizer circuitry. Most of the

circuits described here were demonstrated at the 2014 International Solid-State Circuits

Conference held every year in San Francisco, California.

1.5.2.1 28 Gbps 560 mW Multistandard Equalizer in 28 nm CMOS

This is a high-speed Continuous Time Linear Equalization-only (CTLE) equalizer

[6] that operates at transmission baud rate of 28 Gbps or at a maximum Nyquist

frequency of 56 Ghz in a 28 nm CMOS technology.

The analog front end (AFE) design is a comprised of a CTLE and a second stage

amplifier with inductive bust. It is not clear from the paper how the resistance and the

capacitance is varied in the CTLE circuit bit this type of circuit creates a boost at the

Nyquist frequency (Figure 1-9).

24
 Figure 1-10 shows the transimpedance gain12 of a little bit less than 15 dB for the

AFE design at a Nyquist frequency of 10 Ghz. However, it is not clear from the white

paper as to what is the effective amplification of a Nyquist signal at 56 GHz.

CTLE

CMFB

CMFB: common-mode feedback

Figure 1-9 Analog Front End (AFE) Design of a Receiver CTLE Equalizer. Figure Adapted by

Author from [6]

It is important to note that this design relies on the fact that 28 nm CMOS

technology allows for the amplification of frequencies as high as 60 GHz. This thesis

will show how this frequency is measured.

12
The transimpedance gain is the relationship between the system output voltage with respect to the system
input current. This is also known as the Y-parameter.

25
 It is assumed that the insertion loss of the channel is 36 dB at Nyquist frequency

of 56 GHz. The insertion loss is typically given as a voltage loss. The equalizer is

assumed to amplify the signal loss created by the channel. Ideally, the amplification of

the AFE should have been given in terms of voltage amplification terms rather than a

transimpedance gain to see if the equalizer is compensating for the loss.

20
Voltage Gain [dB]

10

0
0.1 1 10 100

Frequency [GHz]

Figure 1-10 Transimpedance Gain. Frequency Response for the AFE. Figure Created by Author

from Data in [6]

1.5.2.2 25 Gbps 5.8 mW CMOS Equalizer in 45 nm CMOS

This design was made in part by Professor Behzad Razavi, a worldwide well-

recognized CMOS design instructor at the University of California. Won Jung and

Razavi’s approach was to create an AFE design [7] powered by a 1 V power supply. The

AFE consists of a CTLE that feeds to a linear de-multiplexer (DMUX) that has sufficient

26
bandwidth to operate at the Nyquist frequency of 50 GHz. The CTLE equalizer is

clamed to boost 8 dB at high frequency though inductive peaking.

DMUX

ODD
CLK DATA
CTLE
DMUX

EVEN
CLK_L DATA

Offset Cancellation DMUX

DATA DATA
IN OUT

CLOCK

Figure 1-11 Transimpedance Gain. Frequency Response for the AFE. Figure Adapted by Author

from [7]

1.5.2.3 16 Gbps 4 mW CMOS Desition Feedback Equalizer in 65 nm CMOS

This circuit claims to “improve the energy efficiency of power-constrained

systems” [7] Won Jung and Razavi, A 25 Gb/s 5.8 mW CMOS Equalizer. (Reference

[4] Session 2.4) [8] by incorporating a low voltage charge-based latch and a charge-based

sample-and-hold (S/H) (Figure 1-12). This particular circuit depends on a switching

27
clock (CK) to sample the transmitted signal UI. The implications are that the clock must

be aligned to the input signal. The switching clock must be detected using a clock

recovery circuit which is not represented by this system.

VDD VDD

𝑣𝑖+
𝑣𝑜+
𝑣𝑜−
𝑣𝑖−

CLK

CLK

CLK

Figure 1-12 Charge-Based Sample-and-Hold (S/H) with Clocked Adaptive Loads. Figure Adapted by

Author from [7]

1.5.2.4 25 Gbps 90 mW Power-Scalable with Tunable Active Delay Line Equalizer in

28 nm CMOS

This section describes a cost effective adaptive equalizer circuit design to

compensate for the channel loss variations found commonly in multi-mode fiber (MMF)

channels. Figure 1-13 illustrates a common source transimpedance amplifier or active

circuit with peaking inductors [9]. This circuit is capable to program its bandwidth and

28
gain dissipation. The CMOS gain (𝑔𝑚 /𝑔𝑑𝑠 ) for the common source transistors (𝑀𝑛1 and

𝑀𝑛2 ) is approximately 5.

Negative resistance is applied to the output by circuits with transistors 𝑀𝑛3 , 𝑀𝑛4 ,

𝑀𝑛5 , and 𝑀𝑛6 to cancel the output inductance. As a result, it allows the circuit to have a

2.5 times trans-resistance result with half times the input noise.

BIAS
VDD VDD

𝑀𝑛5 𝑀𝑛6
𝑣𝑜𝑢𝑡

VDD VDD

𝑣𝑖𝑛 BIAS

𝑀𝑛3 𝑀𝑛4
𝑀𝑛1 𝑀𝑛2

Figure 1-13 Trans-Impedance Equalizer. Figure Adapted by Author from [9]

29
1.5.2.5 28 Gbps 28.8 mW Trans-Inductance Amplifier (TIA) Equalizer in 28 nm

CMOS

A CMOS TIA equalizer circuit [10] allows for high signal gain with a low power

supply. However, this circuit is sensitive to supply noise due to its high gain (Figure

1-14). The circuit shows a push-pull TIA with series-peaking inductors (𝐿𝐼𝑁 ). The

source current tail (𝐼𝐵 ) makes the transconductance gain (𝑔𝑚 ) of transistors 𝑀1 , 𝑀2 , 𝑀3 ,

and 𝑀4 refer to the bias current as a substitute of the supply voltage which allows for a

better noise reduction. Transistor 𝑀7 and 𝑀8 act as a common-source amplifier that

provides negative voltage gain through the feedback resistor (𝑅𝐹 ). Transistors 𝑀5 and

𝑀6 act as an active variable capacitor and controlled by the feedback voltage (𝑉𝐹 ).

30
 Feedback
Voltage

𝑀5

𝑀1 , 𝑀2 , 𝑀3 , and 𝑀4

TIA

𝑀6

Feedback
Voltage

𝑀7 𝑀8

Figure 1-14 Pseudo-Differential CMOS Push-Pull Trans-Impedance Equalizer. Figure Adapted by

Author from [10]

31
1.5.2.6 20 Gbps 0.9 mW Trans-Admittance Stage (TAS) Trans-Inductance (TIA)

CTLE in 28 nm CMOS

The TAS-TIA single stage CTLE circuit (Figure 1-15) [11] allows low

impedance at the TIA input and output. The circuit gain is approximately the TAS

transconductance gain (𝑔𝑚,𝑇𝐴𝑆 ) multiplied by the CTLE resistance feedback (R). The

reported gain peaking at 8.5 GHz is 8 dB. The TAS acts as a first stage source-

degenerated PMOS circuit that provides the main boosting at Nyquist frequency. The

receiver CTLE is programmable by controlling the input voltage to the TIA (𝑉𝑋 ). The

CTLE boosts high frequency signals to compensate for the channel loss. Low output

impedance to the TAS is achieved by an active-shunt load controlled by a CMOS inverter

feedback (CMFB).

TAS TIA

𝑣𝑖𝑛 CTLE INVERTER 𝑣𝑜𝑢𝑡

𝑣𝑜𝑢𝑡

VCM

Figure 1-15 TAS-TIA CTLE. Figure Adapted by Author from [11]

32
2 Channel Model

The communication link between a transmitter and a receiver is called the

transmission line or communication channel. In the case of the USB 3.1 or PCIe®

standards, the connection between the transmitter and the receiver is called the

transmission channel or simply “the channel”. The channel is composed of many parts

as described in section 1.4.6 herein, but a more simplistic model can be modeled to test

the design as proposed in this thesis.

2.1 Types of Printed Transmission Lines

There are six commonly used basic types of printed transmission lines used in the

industry and each basic type has respective modifications:

(a) Microstrip lines

(1) Suspended microstrip line

(2) Inverted microstrip line

(3) Shielded microstrip line

(b) Striplines

(1) Double-conductor stripline

(c) Suspended striplines

(1) Shielded suspended stripline

(2) Shielded suspended double-substrate stripline

(d) Slotlines

(1) Antipodal slotline

(2) Bilateral finline

33
 (e) Coplanar waveguides

(1) Shielded coplanar waveguide

(f) Finlines

(1) Bilateral slotline

(2) Antipodal finline

(3) Antipodal overlapping finline

Each type of transmission line differs from one another based on their

dimensional parameters and electrical properties. For purposes of modeling a

transmission line, this thesis will focus on the microstrip lines which have a single

transmission line geometry made of a single conductor trace separated from a ground

plane by a dielectric substrate (Figure 2-1).

Microstrip lines

Dielectric layers
Ground layer

Figure 2-1 Typical Microstrip Line Configuration for Differential Transmission Lines

Assuming the connection between the transmitter and the receiver is a single

straight microstrip line with 10 mm length, and the microstrip material is cupper, then it

can be assumed that the microstrip line has a resistance associated with the resistivity of

Ω
the material. The resistivity coefficient of copper is 168 × 10−18 𝑚. Therefore, every

millimeter of microstrip line has a resistance of 16.8 × 10−12 Ω (Equation (2-1).

34
 Ω (1)[𝑚] (2-1)
(1)[𝑚𝑚](168)(10−18 ) [ ] = 16.8 × 10−12 [Ω]
𝑚 (1000)[𝑚𝑚]

However, the microstrip line has an interelement capacitance between the

stripline and the ground plane and an interelement capacitance between the microstrip

lines (Figure 2-2). As a result, the interelement capacitance creates a system whereby its

impedance is affected by the signal frequency. At low frequencies or d.c. voltage, the

interelement capacitance is negligible. However, at data rates where signals approach the

10 GHz or above, the interelement capacitance increases the impedance of the

transmission line to such extent that the signal is greatly attenuated.

Microstrip lines

Dielectric layer
Ground layer

Figure 2-2 Microstrip Lines Interelement Capacitance

The interelement capacitance and resistivity of the microstrip material have an

impedance that varies with the voltage frequency of the signal. The capacitance depends

on the geometrical factors of the microstrip line and the dielectric permittivity between

metals. As a result, creating a precise model for the microstrip line in a computer aided

design (CAD) tool is outside the scope of this thesis. However, a simple model can be

created by comparing the measured results of microstrip lines.

35
2.2 The FR4 Microstrip Wire Line

One of the most popular printed circuit board (PCB) microstrip wirelines

available is the FR4 dielectric-material wireline. This section describes the transmission

line loss as measured in this type of wirelines and the effect that the FR4 wireline has on

the transmitted signal due to its inherent design. The FR4 wireline is simply a wire strip

that connects two microcircuit devices. On one end, there is a transmitter, while on the

other end is the receiver. The FR4 strip line can have different lengths depending on how

far are the microcircuit devices. The length of the stripline introduces a higher resistivity

in the wireline between the end points due to the FR4 stripline conductivity electrical

parameters. As a result, a longer stripline will add loss or higher attenuation on the

transmitted signal.

To minimize the effects of signal noise, the transmitter is design to deliver as

much power as possible. The receiver on the other hand must be able to amplify the

signal that was lost by the transmission channel. However, the loss of the signal is not

uniform as the frequency of the signal increases due to the wireline interelement

capacitance properties. Figure 2-3 shows how data is connected from one microcircuit

device to another via an FR4 microstrip channel.

D Q Tx Rx D Q
FR4
CHANNEL
CLK CLK

Figure 2-3 FR4 Channel Interconnection

36
 The FR4 channel is not only susceptible to the signal frequency but also to

external signal noise from adjacent wires or radio frequency electromagnetic waves from

far away. As a result, the signal response at the receiver is deteriorates at such extent that

it needs to be equalized to its original magnitude—the magnitude of the transmitter—

Figure 2-4.

The transmission line loss profile depends on the trace length and how the

connection is made. What this means is whether the transmission line is point to point, or

whether the transmission line in a PCB is done using vias or circuit board striplines that

are located between dielectric layers (Figure 2-5). Depending on the complexity of a

PCB design, transmission lines may be as simple as a point to point connection, or a

transmission line may contain multiple vias that may or may not have a via stub

component. Therefore, every transmission line transfer function is unique and difficult to

model.

37
 0
9" FR4
Channel Attenuation [dB] -10 9 FR4, Via Stub
26 FR4
-20 26" FR4, Via Stub

-30
-40
-50
-60
(a) (b)
-70
0 2 4 6 8 10
Frequency [GHz]

Figure 2-4 FR4 Channel Loss for 9” (22.86 cm-long) and 26” (66.04 cm-long) Wirelines. (a) Cross

Section of an FR4 Microstrip Wireline; (b) Cross Section of a Stripline Wireline.

Frequency is Displayed in Linear Form13

To compensate for the varying channel loss attenuation, the receiver front end

designs employ a variety of systems that shape the received signal by controlling the

receiver’s slew-rate. However, these systems are difficult to design and have limitations

as to how much the signal can be shaped. A combination of analog and digital

equalization is normally employed on high frequency transmission. For USB

transmission lines were changing flexible cable dimensions, the equalizer must be able to

check if the received signal is valid. This is called “signal training” because the receiver

13
The source of this graph was obtained from the IEEE, ISSCC tutorial lecture by Instructor Elad Alan.
Tutorial held on February 2014 in San Francisco, California. Course title “Analog Front-End Design for
Gb/s Wireline Receivers.” Data adapted by Author.

38
compares the received signal with a series of known and expected digital values. If the

signal does not match, an error signal is generated and used to digitally adjust the receiver

front-end equalizer.

Tx Rx
FR4 Trace
Via

Via Stub
Via
Stub

Figure 2-5 PCB Layout of an FR4 Microstrip and Stripline Wirelines Connected Using Vias. Via

Stubs Create Additional Interelement Capacitances

Some authors have determined that a 25 cm-long FR4 strip lines is capable to

transmit a 100 mV signal with frequencies as high as 100 GHz [12]. This means that it is

possible to use FR4 wirelines to reach transmission rates as high as 200 Gb/s. This is

significant because the highest proven transmission rate between two devices is no more

than 60 Gb/s based on state-of-the-art designs published in 2014.

2.3 Channel Capacity

Channel capacity is defined as the highest possible frequency that can be

transmitted reliably [12]. The channel capacity is primarily a function of three system

parameters: (a) the channel transfer function (𝐻(𝑓)); (b) the spectral power density (SPD)

of a source noise (𝑆𝑛 (𝑓)); and (c) the SPD of the transmitted signal (𝑆𝑇𝑥 (𝑓)).

39
 Tx Rx

CHANNEL

Figure 2-6 Channel Capacity System Model

The average transmit power (𝑃𝑠 ) is calculated as follow:

∞
2 (2-2)
𝑃𝑠 = 𝐸𝑇𝑥 [𝑥𝑇𝑥 (𝑡)] = ∫ 𝑆𝑇𝑥 (𝑓) 𝑑𝑓 [𝑊]
0

Considering that for a specific fixed channel with a specific noise source, it can be

predicted that there are an infinite number of possible input power spectral densities with

a corresponding capacity. The waterpouring method [13] is used to calculate the

maximum channel capacity (C) for a given fixed total input power as follow:

𝑆𝑇𝑥 (𝑓)|𝐻(𝑓)|2 (2-3)

𝐶=∫ 𝑙𝑜𝑔2 [1 + ] 𝑑𝑓 [𝑏𝑖𝑡𝑠/𝑠]
𝑓∈𝐹𝐿 𝑆𝑛 (𝑓)

Whereby the frequency band (𝐹𝐿 ) depends on the solution of the “L” constant,

𝑆𝑛 (𝑓) (2-4)
𝑃𝑠 = ∫ [𝐿 − ] 𝑑𝑓 [𝑊]
𝑓∈𝐹𝐿 |𝐻(𝑓)|2

𝑆𝑛 (𝑓) (2-5)
𝐿≥
|𝐻(𝑓)|2

40
 𝑆𝑛 (𝑓)
𝐿− ; 𝑓 ∈ 𝐹𝐿
|𝐻(𝑓)|2 (2-6)
𝑆𝑇𝑥 =

{ 0 ; 𝑓 ∉ 𝐹𝐿

Note that in order to obtain the channel capacity (C), Equation (2-5) must be

solved first.

2.4 Modeled FR4 PCB Traces of 1-oz Microstrip Lines

Modeling, calculating, or measuring the channel capacity of a transmission line is

important because it gives the circuit designer the ability to know the transmission limits

of the system described in Figure 2-6. Figure 2-7 shows that channel capacity is

inversely proportional to the length of the channel [12]. Disregarding the effects of

external channel noise, a 1-oz microstrip wireline approximately doubles the channel

capacity if the length of the wireline is cut by half. Therefore, an ideal design that

requires point-to-point communication between two microcircuit devices benefits if the

distance between the devices is as short as possible.

41
 150
25 cm-long, 1-oz Microstrip
50 cm-long, 1-oz Microstrip
100 cm-long, 1-oz Microstrip

100
Capacity [Gb/s]

50

Transmitter RMS Voltage [V]

Figure 2-7 Channel Capacity for Various Lengths of 1-oz Microstrip Wirelines with Noiseless

Environment. Data Adapted by Author from [12]

However, when noise is inserted into the system, the channel capacity is

substantially degraded as shown in Figure 2-8. This demonstrated the importance that

needs to be given to the trace layout of a PCB. For high frequency channels, it is critical

to make sure that the line is shielded from external ambient electromagnetic noise that

may be induced through adjacent signal channels or through unwanted radio frequency

(RF) noise.

42
 30
25 cm-long, 1-oz Microstrip
25 50 cm-long, 1-oz Microstrip
100 cm-long, 1-oz Microstrip
Capacity [Gb/s]

20

15

10

0.1 1.0 10 100

Channel Bandwidth [GHz]
Figure 2-8 Channel Capacity for Various Lengths of 1-oz Microstrip Wirelines with Noise

Environment Caused by Signal Crosstalk and Ambient Electromagnetic Noise. Data

Adapted by Author from [12]

2.5 Simplified Circuit Model for FR4 Microstrip Channel

Based on the arguments presented in previous sections, it can be argued that is it

not possible to predict with absolute certainty as to how the microstrip channel wireline

will behaves unless it is measured with instrumentation. However, it is possible to model

a simple circuit that would help simulate a channel of a specific length. Some author

have measured the frequency response of FR4 channels commonly used in PCB designs.

This section takes under consideration already published measurements and

simulations performed on FR4 microstrip channels. Based on mathematical calculations

43
of the FR4 microstrip line, the channel loss is approximately -25 dB loss for a 100 cm-

long, 1-oz microstrip (Figure 2-9). It was also shown that measured 26” (66.04 cm-long)

microstrip wireline attenuate signals as much as -50 dB (Figure 2-4). Although there is a

difference between what is calculated versus what is measured, the measurement and

simulations show that wirelines act as a simple low pass filter. Wirelines also show that

attenuation of a signal is predictable with the length of the wire.

-10
Channel Loss [dB]

-20

-30
25 cm-long, 1-oz Microstrip
-40 50 cm-long, 1-oz Microstrip
100 cm-long, 1-oz Microstrip
-50
0.1 1.0 10
Frequency [GHz]

Figure 2-9 Modeled Channel Transfer Function Response (|𝐻(𝑓)|) of a 56Ω Impedance Noiseless

FR4 Microstrip or Stripline. Data Adapted by Author from [12]

This thesis proposes a simple approach regarding the simulation of a wireline

based on Figure 2-4 and Figure 2-9. The proposed circuit makes simple assumptions

44
such as assuming that a microstrip channel or wireline is made of copper. Copper has a

linear resistivity (𝜌𝐶𝑢 ) at a temperature of 300 K is of 17.1 nΩ-m. Assuming the worst

case scenario, a 66.04 cm-long microstrip has a measure loss of -50 dB. Therefore, the

resistance of a wire made of copper with this length can be calculated as follow:

𝜌𝐶𝑢 (2-7)
𝑅𝐶𝑢,66.04 𝑐𝑚 =
66.04 [𝑐𝑚]

17.1 [nΩ][m] 100 [𝑐𝑚] (2-8)

𝑅𝐶𝑢,66.04 𝑐𝑚 =
66.04 [𝑐𝑚] [𝑚]

(2-9)
𝑅𝐶𝑢,66.04 𝑐𝑚 = 25.89 [nΩ]

The next step is to assume that the microstrip loss curve can be simulated with a

low pass filter (Figure 2-10). The transfer function for the circuit can be found as follow:

𝑣𝑅𝑥,𝑖𝑛 (2-10)
𝐻(𝑠) =
𝑣𝑇𝑥,𝑜𝑢𝑡

1
𝑠𝐶 (2-11)
=
1
𝑠𝐶 + 𝑅

1 (2-12)
=
1 + 𝑠𝑅𝐶

45
 1 (2-13)
𝐻(𝑠)|𝑠=𝑗𝜔 =
1 + 𝑗𝜔𝑅𝐶

1 (2-14)
𝐻(𝑗𝜔)|𝜔=2𝜋𝑓 =
1 + 𝑗2𝜋𝑓𝑅𝐶

1 (2-15)
|𝐻(𝑓)| =
√12 + (2𝜋𝑓𝑅𝐶)2

1 (2-16)
|𝐻(𝑓)|𝑑𝐵 = 20 𝑙𝑜𝑔10 ( ) = −50 [𝑑𝐵]
√1+(2𝜋𝑓𝑅𝐶)2

50 1 (2-17)
− = 𝑙𝑜𝑔10 ( )
20 √1 + (2𝜋𝑓𝑅𝐶)2

5 1 (2-18)
10− 2 =
√1 + (2𝜋𝑓𝑅𝐶)2

1 (2-19)
√1 + (2𝜋𝑓𝑅𝐶)2 = 5
10− 2

2
1 (2-20)
1 + (2𝜋𝑓𝑅𝐶)2 = ( 5)
10− 2

1 (2-21)
(2𝜋𝑓𝑅𝐶)2 = −1
10−5

46
 1 (2-22)
2𝜋𝑓𝑅𝐶 = ±√ −5 − 1
10

1
±√ −1
10−5
𝐶=| | ;𝑅=
2𝜋𝑓𝑅
(2-23)

25.89 𝑛Ω

; 𝑓 = 10 𝐺𝐻𝑧

1
±√ −1
10−5
𝐶=| | = 194.395 mF (2-24)
2𝜋(10)(109 )(25.89)(10−9 )

66.04 cm-long

R = 25.89 n
Tx Rx

C = 194.395 mF

Figure 2-10 Modeled Channel Transfer Function Response (|𝑯(𝒇)|) of a 66.04 cm-long Copper

Microstrip that has a -50 dB Response at 10 GHz

47
 Assuming that the capacitance of the circuit is uniform across the line, a delta-

model or pi-model can be created by dividing the capacitance in half and place the

capacitor on each end (Figure 2-11)

66.04 cm-long

R = 25.89 n
Tx Rx

= 97.1975 mF

Figure 2-11 Simplified Pi-Model for Channel Transfer Function Response (|𝑯(𝒇)|) of a 66.04 cm-

long Copper Microstrip that Has a -50 dB Response at 10 GHz

In order to model a centimeter of microstrip line, the pi-model is subdivide into

equal parts whereby the resistance (R) represents the resistance of one centimeter. The

centimeter resistance can be mathematically calculated as follow:

𝑅1 𝑐𝑚,𝐶𝑢 25.89 [𝑛Ω] (2-25)

∝ 66.04 [𝑐𝑚]
1 [𝑐𝑚]

25.89 [𝑛Ω][𝑐𝑚] (2-26)

∴ 𝑅1 𝑐𝑚,𝐶𝑢 = 66.04 [𝑐𝑚]
= 392.035 [𝑝Ω]

48
 However, to calculate the capacitance of a circuit with n segments become

difficult because the total transfer function results in a polynomial of n-segments. For

example, if the channel has only two segments, the transfer function becomes:

2
𝑠𝐶
(2-27)
𝐻𝑛=2 (𝑓) = 1 2
𝑅+(𝑅‖ )+
𝑠𝐶 𝑠𝐶

2
𝑠𝐶
(2-28)
𝐻𝑛=2 (𝑓) = 𝑅 2
𝑅+ +
1+𝑠𝑅𝐶 𝑠𝐶

𝑠2𝐶 3 𝑅+2𝐶 2 (2-29)

𝐻𝑛=2 (𝑓) = 𝐶 2 𝑅2 +4𝑠𝐶𝑅+2

On the other hand, the transfer function for a three segment results in,

2
𝑠𝐶 (2-30)
𝐻𝑛=3 (𝑓) = 1 1 2
‖(𝑅+(𝑅‖ ))+
𝑆𝐶 𝑠𝐶 𝑠𝐶

2(𝑠 2 𝐶 2 𝑅 2 + 3𝑠𝐶𝑅 + 1) (2-31)

𝐻𝑛=3 (𝑓) =
3𝑠 2 𝐶 2 𝑅 2 + 8𝑠𝐶𝑅 + 2

Therefore, calculating the value for the capacitor for a large number of segments

would result in an arduous mathematical evolution. Instead, the value of the capacitor is

derived by using a computer model whereby the capacitance is varied until the -50 dB at

10 GHz curve is obtained. The obtained value for the capacitance for 66 segments was

around 680 µF.

49
 Then each pi-model for each centimeter results by dividing each capacitor by half

as shown in the example for Figure 2-11. A true channel exhibits a linear decay in gain

as frequency is increased—the frequency axis is displayed in linear mode. Note that by

adding several segments to the model, the proposed model closer resembles the measured

value (Figure 2-13).

To improve the channel, the resistance of each segment should be as low as

possible. It was observed that this simple channel model approximates measured results

when the resistance for each segment is in the pico-ohm range. However, when

comparing the model results in Figure 2-13 to the measured results in Figure 2-4, it can

be said that this model is valid for simulation purposes.

50
 1 cm-long
R = 392.035 p
(a)

= 340 µF

R = 392.035 p R = 392.035 p

(b)

C = 680 µF
2 cm-long

R = 392.035 p R R

(c) C C

3 cm-long

Figure 2-12 Simplified Pi-Model for Channel Transfer Function Response (|𝑯(𝒇)|) of 1 cm-long

Copper Microstrip Segments. (a) Simplified 1 cm-long Channel Segment; (b)

Combination of Two Simple Segments to Increase the Length of the Channel; (c) Model

of a 3 cm-long Channel Using the Simple Channel Model

51
 0

Channel Attenuation [dB] -10

-20 (a)
(b)
(c)
-30
(d)
(e)

-40 (f)
(g)
(h)
-50

-60
0 2 4 6 8 10
Frequency [GHz]

Figure 2-13 Channel Attenuation Results for Proposed Simple Model. (a) Channel Attenuation for

One Segment Pi-model; (b) 10 cm-long Channel; (c) 20 cm-long Channel; (d) 30 cm-

long Channel; (e) 40 cm-long Channel; (f) 50 cm-long Channel; (g) 60 cm-long Channel;

and (h) 66 cm-long Channel

52
3 Equalizer Design

An equalizer is a device that amplifies the signal loss due to the effects of the

transmission channel. Since a channel has a linear loss, an amplifier should also behave

an inverse linearity. Designers tend to display the channel loss in a linear way, while

displaying the equalizer response in a logarithmic way. Figure 3-1 shows two ways to

display the channel loss. Equalizers that are able to regenerate the loss occurred by the

channel are commonly called linear equalizers.

0 0

Channel Attenuation [dB]

Channel Attenuation [dB]

-10 -10
(b)
-20 -20 (c)
-30 -30 (d)

-40 -40 (e)

(f)
-50 -50
(g)
-60 -60
0 5 10 0.1 1 10 (h)
Frequency [GHz] Frequency [GHz]

Figure 3-1 Channel Attenuation Results for Proposed Simple Model. The Graph on the Left X-axis

Has a Linear Display while the Graph on the Right has a Logarithmic Display. (b) 10

cm-long Channel; (c) 20 cm-long Channel; (d) 30 cm-long Channel; (e) 40 cm-long

Channel; (f) 50 cm-long Channel; (g) 60 cm-long Channel; and (h) 66 cm-long Channel

The idea behind a linear equalizer is to regenerate or boost the signal that was lost

due to the transmission line electrical characteristics. If the channel is assumed to be

ideal—meaning that it has no induced noise, signal cross talk, or other interelement

capacitances that may disturb the signal—then an equalizer is designed to simply amplify

the signal attenuation that was loss by the channel . However, amplifiers are inherently a

53
low pass filter that have a flat frequency response from low frequencies to the cut-off

frequency. The amplifier must be modified in such a way that it would ramp up the gain

as frequency increases.

The system model of an ideal equalizer is nothing more that the inverse of the

channel transfer function (Figure 3-2).

Tx Rx
CHANNEL

CHANNEL IDEAL
EQUALIZER
Figure 3-2 System Model for an Ideal Equalizer

An ideal equalizer must be able to inverse the transfer function of the channel to

obtain the following results:

1 1 (3-1)
𝑣𝑜 = 𝑣𝑅𝑥,𝑖𝑛 = 𝑣𝑇𝑥,𝑜𝑢𝑡 𝐻(𝑠) = 𝑣𝑇𝑥,𝑜𝑢𝑡
𝐻(𝑠) 𝐻(𝑠)

This can be illustrated graphically as follow:

54
 Ideal
Equalizer
Response

Various
Channels
Loss

Figure 3-3 Ideal Equalizer Response

Equalizers must be able to adapt its amplification properties if the channel is

changed. For example, if a signal is transmitted at 30 GHz, a 20 cm-long channel may

attenuate the transmitted signal by -28 dB while a 60 cm-long channel may attenuate the

same signal by -83 dB. In other words, the amplifier must be have variable gain.

3.1 Equalizer Bandwidth Limitations

Equalizers have a bandwidth limitation based on its inherent CMOS technology.

CMOS transistors behave as a low pass filter when its input is connected to its gate and

the output is connected to its drain. For high speed communications, it is imperative to

know precisely the limits of the technology used. This thesis is focused on the 28 nm

CMOS technology. One way to determine the bandwidth of a NMOS transistor is by

55
measuring its transit frequency which is defined as the frequency where the transistor is

capable to start amplifying. The following sections establish the basis to calculate and

know the bandwidth limits of a CMOS transistor.

3.2 Transit Frequency (𝒇𝑻 ) and Transit Time (𝝉𝑻 )

The transit or cut-off frequency of an NMOS transistor helps measure the ultimate

intrinsic speed of the transistor without any external limitations and is defined as the

frequency which absolute small signal current gain results in unity [14]. The transit

frequency delimits the maximum frequency that the MOS transistor functions as a small

signal current amplifier. To minimize any external limitations, the transistor must be in

saturation mode and the drain of the transistor is short circuited to the supply voltage.

𝐼 𝐴 (3-2)
|𝐼𝑑 | =1 [𝐴]
𝑔
𝑓=𝑓𝑇

There are two popular circuit models that help extract the transit frequency and

both models are described herein. This section describes in detail the circuit model test

that will be used for the extraction of the transit time and transit frequency [14][15].

However, the mathematical calculations of this circuit model have been purposely

modified to employ the new and proposed design method. The second circuit model

setup to extract the transit frequency will be described in subsequent sections.

56
Figure 3-4 Circuit Model Setup to Measure the Transistor’s Transit Frequency

The original circuit model requires a small signal input controlled by a sinusoidal

current source. The new method changes the sinusoidal current source for a sinusoidal

voltage source. This section demonstrates that this change does not affect the results of

the model but is critical to the new mathematical model proposed in this paper because

the voltage source acts as the desired input voltage of the targeted design.

It can be observed that the current to the gate is only affected by the small signal

input while the drain current is a function of the gate voltage bias (𝑉𝐺𝐺 ), the source

voltage (𝑉𝐷𝐷 ), and the small change in input voltage (𝑣𝑖 ).

(3-3)
𝐼𝐺𝐺 = 𝐼𝑔,𝑑.𝑐. + 𝑖𝑔 (𝜔)

57
 (3-4)
= 0 + 𝑖𝑔 (𝜔)

𝑣 (3-5)
= 𝑍𝑖
𝑔

(3-6)
𝐼𝐷𝐷 = 𝐼𝐷𝑆 + 𝑖𝑑 (𝜔)

Under this setup, the drain d.c. current (𝐼𝐷𝑆 ) is the short circuit current—this

represents the maximum drain current if a load is considered infinitesimally small or

negligible. The small change in d.c. drain current can only be present if there is a small

change in the gate voltage. Moreover, the small input current at the gate is present

because the input impedance seen at the gate depends in the small input current (𝑖𝑔 (𝜔))

which is a function of frequency.

Under this setup, the drain d.c. current (𝐼𝐷𝑆 ) is the short circuit current—this

represents the maximum drain current if a load is considered infinitesimally small or

negligible. The small change in d.c. drain current can only be present if there is a small

change in the gate voltage. Moreover, the small input current at the gate is present

because the input impedance seen at the gate depends in the small input current (𝑖𝑔 (𝜔))

which is a function of frequency.

In the event that the NMOS is used as a common source amplifier, a small current

input (𝑣𝑖 (𝜔)) change causes a small input current (𝑖𝑔 (𝜔)) change at the gate of the

58
transistor. Moreover, the small input voltage change results in a change in small drain

current (𝑖𝑑 (𝜔)) which is the output of the circuit test model.

The equivalent input impedance is a function of the gate equivalent capacitance

(𝐶𝑔𝑔 ). As the input frequency increases, the input impedance decreases which results in

the small input current to increase.

(3-7)
𝑖𝑔 = 𝑣𝑖 𝑠𝐶𝑔𝑔

(3-8)
= 𝑗𝑣𝑖 𝜔𝐶𝑔𝑔

(3-9)
= 𝑗𝑣𝑖 2𝜋𝑓𝐶𝑔𝑔

As a result, the small signal output current gain (|ℎ21 |) decreases when the

frequency increases.

𝑖𝑑 (3-10)
|ℎ21 | = | |
𝑖𝑔

59
 (a)

(b)

Figure 3-5 Small Signal π-Model for Circuit Model to Measure Transit Frequency. (a) All Intrinsic

Transistor Components Shown, and (b) Intrinsic Transistor Elements Affected by the

Circuit Test Model (Simplified)

(3-11)
𝑖𝑔 = 𝑣𝑖 𝑠(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) = 𝑣𝑖 𝑠𝐶𝑔𝑔

60
 (3-12)
𝑖𝑑 = 𝑣𝑖 (𝑔𝑚 − 𝑠𝐶𝑔𝑑 )

𝑖𝑑 𝑔𝑚 − 𝑠𝐶𝑔𝑑 (3-13)
|ℎ21 | = | | = | |
𝑖𝑔 𝑠(𝐶𝑔𝑠 + 𝐶𝑔𝑑 )

𝑠
(1+ 𝑔𝑚 )
(3-14)
= ||𝐶 |
𝑔𝑚 𝐶𝑔𝑑

𝑔𝑠 +𝐶𝑔𝑑 𝑠 |

𝑠=𝑗𝜔

𝜔
(1+𝑗 𝑔𝑚 )
(3-15)
= ||𝐶 |
𝑔𝑚 𝐶𝑔𝑑

𝑔𝑠 +𝐶𝑔𝑑 𝑗𝜔 |

𝜔=2𝜋𝑓

2𝜋𝑓
(1+𝑗 𝑔 )
2𝜋 𝑚 (3-16)
=𝐶
𝑔𝑚 | 𝐶𝑔𝑑 |
𝑔𝑠 +𝐶𝑔𝑑 | 𝑗2𝜋𝑓 |

2
𝑓
√1 + ( 𝑔 ) (3-17)
𝑚
𝑔𝑚 𝐶𝑔𝑑
=
(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) 2𝜋𝑓

Equation (3-17) takes the form of the following current gain formula,

𝑓
1+𝑗 (3-18)
𝑓0 𝐴
|ℎ21 | = |𝐴𝑜 |[ ]
𝑗𝑓 𝐴

61
Figure 3-6 Bode Plot for Equation (3-18)

The Bode plot of equation (3-18) as seen in Figure 3-6 shows that the NMOS

transistor acts as an amplifier if the current gain (|ℎ21 |) is more than one. Therefore, the

intrinsic amplification only occurs when the frequency is less than the transit frequency

(𝑓𝑇 ) which is much smaller than the frequency (𝑓0 ) at which the transistor small current

gain becomes constant. When working with Bode plots, it is important to note that the

gain of the frequencies represent the -3dB points of such frequency. For example, the
1
current gain of the transit frequency is not unity but rather . The gain of a frequency
√2

2
that points at a Bode plot with a current gain of 2 is actually . The current gain from
√2

equation (3-17) relates to the transistor’s intrinsic properties if transistor is setup as

shown in Figure 3-4.

62
 𝑔𝑚 (3-19)
𝐴𝑜 =
2𝜋(𝐶𝑔𝑠 + 𝐶𝑔𝑑 )

𝑔𝑚 (3-20)
𝑓0 =
2𝜋𝐶𝑔𝑑

(3-21)
𝑓𝑇,−3𝑑𝐵 (|ℎ ≪ 𝑓𝑜
21 |=1)

At unity gain,

𝑔𝑚 − 𝑗2𝜋𝑓𝑇 𝐶𝑔𝑑 (3-22)

|ℎ21 | = 1 = | |
𝑗2𝜋𝑓𝑇 (𝐶𝑔𝑠 + 𝐶𝑔𝑑 )

2
√(𝑔𝑚 )2 + (2𝜋𝑓𝑇 𝐶𝑔𝑑 )
(3-23)
=
2
√(2𝜋𝑓𝑇 (𝐶𝑔𝑠 + 𝐶𝑔𝑑 ))

2 2 (3-24)
(2𝜋𝑓𝑇 (𝐶𝑔𝑠 + 𝐶𝑔𝑑 )) = 𝑔𝑚 2 + 4𝜋 2 𝑓𝑇 2 𝐶𝑔𝑑

2 2 (3-25)
4𝜋 2 𝑓𝑇 2 (𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) − 4𝜋 2 𝑓𝑇 2 𝐶𝑔𝑑 = 𝑔𝑚 2

2 (3-26)
𝑓𝑇 2 4𝜋 2 [(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) − 𝐶𝑔𝑑 2 ] = 𝑔𝑚 2

63
 𝑔𝑚
𝑓𝑇 = (3-27)
2 2
2𝜋√(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) − 𝐶𝑔𝑑

𝑔𝑚
𝑓𝑇 = (3-28)
2
2𝜋√𝐶𝑔𝑠 + 2𝐶𝑔𝑠 𝐶𝑔𝑑

In this example, it is assumed that the CMOS is in the saturation region and the

drain resistance (𝑟𝑑𝑠 ) is negligible. Therefore, the transconductance gain,

𝜕𝑖 (3-29)
𝑔𝑚 = 𝜕𝑣𝑑
𝑖

𝜕 1 𝑊 (3-30)
= 𝜕𝑣 {2 𝜇𝑛 𝐶𝑜𝑥 (𝑣𝑖 − 𝑣𝑡ℎ )2 }
𝑖 𝐿

𝑊 (3-31)
= 𝜇𝑛 𝐶𝑜𝑥 (𝑣𝑖 − 𝑣𝑡ℎ )
𝐿

Where,

(3-32)
𝜇𝑛 ∶ N-Channel Carrier Mobility (fixed)

(3-33)
𝐶𝑜𝑥 ∶ Channel Oxide Capacitance (fixed)

64
 (3-34)
𝑊∶ Intrinsic Width (variable)

(3-35)
𝐿∶ Intrinsic Length (variable)

(3-36)
𝑣𝑡ℎ ∶ Threshold Voltage (variable)

That results in the following transit frequency equation proposed in this thesis,

𝑊
𝜇𝑛 𝐶𝑜𝑥 (𝑣𝑖 −𝑣𝑡ℎ )
𝐿 (3-37)
𝑓𝑇 =
2𝜋√𝐶𝑔𝑠 2 +2𝐶𝑔𝑠 𝐶𝑔𝑑

Moreover, when the transistor is in the saturation region,

2 (3-38)
𝐶𝑔𝑠 = 3 𝑊𝐿 ≫ 𝐶𝑔𝑑

This results in the following approximation for the transit frequency when

transistor is in high inversion or saturation region,

3𝜇𝑛 𝐶𝑜𝑥 (𝑣𝑖 −𝑣𝑡ℎ ) (3-39)

𝑓𝑇 ≅ 4𝜋𝐿2

Equation (3-39) suggests that increasing the width (W) of the intrinsic transistor

has little effect in the behavior of the transit frequency; an increase in the length (L) of

65
the intrinsic transistor results in a decrease of the transit frequency which results in a

smaller bandwidth. Equation (3-39) also suggests that decreasing the threshold voltage

(𝑣𝑡ℎ ) results in an increase of the transit frequency—the threshold voltage is a negative

voltage and should be compared with the small voltage input signal (𝑣𝑖 ). If the input

signal is much larger than the threshold voltage, the threshold voltage becomes

negligible.

Since the intention of this circuit is to find out the possible design limits of the

intrinsic transistor, the length of the transistor in a 28 nm technology is set to its

minimum intrinsic length to maximize the transit frequency. However, the width of the

transistor is set to it most minimum value of 30 nm to maintain the lowest possible

power—the intention of this circuit is to find out the intrinsic limitations of a transistor

targeted towards specific design specifications. It was assumed that the power of the

target circuit should be kept to its minimum. Power is directly proportional to the drain

current which is in turn directly proportional to the transistor’s intrinsic width.

The Bode plot of the circuit above shows that if the small current gain (|ℎ21 |) is

increased, the intrinsic bandwidth properties of the transistor decrease. It also shows that

there is a direct relationship between the gain (𝐴𝑜 ) of the transistor at 1Hz, the transit

frequency (𝑓𝑇 ) at unity gain, and any given frequency (𝑓𝑜 ) along the graph with a slope of

negative one.
𝐴 −1
𝐴𝑜 = − 𝑓 𝑜 −1 (1) + 𝑘
𝑇
(3-40)
𝐴𝑜 − 1
𝐴𝑜 = − (1) + 𝑘
𝑓𝑇 − 1

66
 𝐴𝑜 − 1 (3-41)
1 =− (𝑓 ) + 𝑘
𝑓𝑇 − 1 𝑇

𝐴𝑜 𝑓𝑇 − 1 (3-42)
∴𝑘 =
𝑓𝑇 − 1

𝐴𝑜 − 1 𝐴𝑜 𝑓𝑇 − 1 (3-43)
|ℎ21 | = − 𝑓+
𝑓𝑇 − 1 𝑓𝑇 − 1

𝐴𝑜 𝑓𝑇 − 𝐴𝑜 𝑓 + 𝑓 − 1 (3-44)
=
𝑓𝑇 − 1

(3-45)
𝑓𝑇,−3𝑑𝐵 ≫ 𝑓 ≫ 1 𝑎𝑛𝑑 𝐴0 ≫ 1

𝑓 𝑓 (3-46)
⇒ |ℎ21 | ≅ 𝐴𝑜 (1 − 𝑓 ) + 𝑓
𝑇 𝑇

𝑔𝑚 𝑓 𝑓 (3-47)
≅ (1 − )+
2𝜋(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) 𝑓𝑇 𝑓𝑇

(3-48)
𝑖𝑖 ∝ 𝑣𝑖 𝑎𝑛𝑑 𝑖𝑜 ∝ 𝑣𝑜

𝑖𝑜 𝑣𝑜 (3-49)
⇒ |ℎ21 | = | | = | |
𝑖𝑖 𝑣𝑖

67
 In the event that a bandwidth is desired with a cutoff frequency which experience

no attenuation, equation (3-46) can be modified as follow:

𝐴𝑜 𝑓0𝑑𝐵 𝑓0𝑑𝐵 (3-50)

≅ 𝐴𝑜 (1 − )+
√2 𝑓𝐺 𝑓𝐺

𝐴𝑜 𝑓0𝑑𝐵 𝑓0𝑑𝐵 (3-51)

− 𝐴𝑜 (1 − )≅
√2 𝑓𝐺 𝑓𝐺

1 𝑓0𝑑𝐵 𝑓0𝑑𝐵 (3-52)

𝐴𝑜 ( − (1 − )) ≅
√2 𝑓𝐺 𝑓𝐺

𝑓0𝑑𝐵 √2 𝑓0𝑑𝐵 (3-53)

𝐴𝑜 ( + − 1) ≅
𝑓𝐺 2 𝑓𝐺

2𝑓0𝑑𝐵 (3-54)
𝐴𝑜 ≅
2𝑓0𝑑𝐵 + 𝑓𝐺 (√2 − 2)

𝑓0𝑑𝐵 (𝐴𝑜 − 1)(√2 + 2) (3-55)

𝑓𝐺 ≅
𝐴𝑜

The method proposed in this thesis is intended to find the frequency (𝑓𝐺 ) for a

desired low frequency gain (𝐴𝑜 ) and a bandwidth that experiences no attenuation at that

gain (𝑓0𝑑𝐵 ). For example, this thesis will show the that the bandwidth of an amplifier

using the 28 nm CMOS technology can be set higher than 30 GHz with a voltage gain

that would be able to boost high frequency signals. An IC designer can use Equation

68
(3-55) to find the needed cutoff frequency of an amplifier while maintaining a voltage

gain higher than 1 V/V. It will be shown in the proceeding sections the results obtained

using the 28 nm CMOS technology using the Cadence Design Systems (CDS) simulation

tools.

The minimum intrinsic transit time (𝜏 𝑇 ) of the transistor measures the maximum

intrinsic speed of the transistor which is the inverse of the transit frequency. In this

example, it was observed that the transistor operates faster in the amplification region if

the length of the transistor is kept as short as possible. However, this creates an increase

in the drain current and therefore an increase in the power consumption of the circuit.

1 4𝜋𝐿2 (3-56)
𝜏𝑇 = ≅
𝑓𝑇 3𝜇𝑛 𝐶𝑜𝑥 (𝑣𝑖 − 𝑣𝑡ℎ )

Since the width of the transistor has little effect in changing the speed of the

transistor or adjust the transit frequency, this parameter should be used to adjust the drain

current which affects the transconductance gain (𝑔𝑚 ) of the transistor.

It is important to point out that the transit frequency is a function of the small

input current which in turn is a function of frequency. The small input current (𝑖𝑖 ) that

depends on the input voltage (𝑣𝑖 ) must have a magnitude which is dependent not on the

transistor’s intrinsic properties, but rather in the specifications set by the designer. A

small input current of zero magnitude has no meaning because it would result in no

change in drain current which will result in the analysis of a transit frequency that would

also have no meaning.

69
 The small current input is directly proportional to the small input voltage (𝑖𝑖 ∝

𝑣𝑖 ). Therefore, to test the limitations of a targeted design, the requirements of the input

voltage will make an affect in the transit frequency of the transistor because the limiting

gate voltage bias is defined by Equation (3-57). This d.c. voltage is commonly referred

as the common mode (CM) gate voltage.

𝑣𝑖 (3-57)
VGG,max = Vdd −
2

Reducing the gate voltage bias (𝑉𝐺𝐺 ) results in reducing the transit frequency.

Figure 5 shows a family of curves that demonstrates how a change in the gate voltage

bias results in a shift of transit frequency. The transistor size is unchanged as well as the

magnitude of the input voltage which is a design dependent variable.

As mentioned above, the transit frequency of a CMOS device is dependent on the

device dimensional parameters such as the transistor’s length and the common mode

voltage if the transistor acts as an amplifier and such amplifier is connected as a common

source amplifier. The most ideal situation is when the transistor is set up to have its most

minimum value. For the 28 nm CMOS technology, the smallest intrinsic length is not 28

nm but rather 30 nm while the smallest intrinsic transistor’s width is 80 nm.

Figure 3-7 shows the profiles for different current gains. Note that the current

gain response depends on how the gate voltage is set. Note that the current gain is not

necessarily directly proportional to the increase of the drain current. Note that at low

frequencies, the highest current gain possible is when the device’s common mode voltage

(gate voltage) is around 0.7 V d.c. However, this observation I not the same at high

70
frequencies. The drain current measured at 30 GHz is 74.48 µA while the current gain is

6.99 A/A for a gate voltage of 0.7 V. On the other hand, the drain current measured at 30

Ghz is 110.48 µA while the current gain is 9.69 A/A for a gate voltage of 0.9 V (Figure

3-8).

5.E+07

5.E+07

4.E+07

4.E+07 28 nm CMOS Technology

Regular vt-NFET
3.E+07
Current Gain [A/A]

nMOS FIN FET process

CM
W = 80 nm
3.E+07 L= 30 nm
VDC=1V
2.E+07
Current Gain, CM=0.3 V, [A/A]
2.E+07
Current Gain, CM=0.5 V, [A/A]
1.E+07 Current Gain, CM=0.7 V, [A/A]

5.E+06 Current Gain, CM=0.9 V, [A/A]

0.E+00
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
Frequency [Hz]

Figure 3-7 Current Gain for a 28 nm NMOS. Voltage Gate bias Creates Different Current Gain

Profiles

71
 Drain Current, CM=0.3 V, [µA] Drain Current, CM=0.5 V, [µA]
Drain Current, CM=0.7 V, [µA] Drain Current, CM=0.9 V, [µA]
250

200
Drain Current [µA]
150

100

50

0
0.1 1 10 100 1000
Frequency [GHz]

Figure 3-8 Drain Current for a 28 nm NMOS. Voltage Gate Bias Creates Different Current Gain

Profiles

2
Current Gain, CM=0.3 V, [A/A]
1.8
Current Gain, CM=0.5 V, [A/A]
1.6 Current Gain, CM=0.7 V, [A/A]
1.4 Current Gain, CM=0.9 V, [A/A]

1.2 75.25 324.78

Current Gain [A/A]

3.164
GHz GHz
1

0.8
234.27
0.6 GHz

0.4

0.2

0
1.E+09 1.E+10 1.E+11 1.E+12
Frequency [Hz]

72
Figure 3-9 Transit Frequency. Current Gain for a 28 nm NMOS. Transit Frequency is the

Frequency that Intersect the Gain of 1 A/A

In order to achieve maximum transistor performance, the common mode voltage

is selected in such a way that maximum bandwidth for the application is attained while

conserving power by decreasing the drain current. For example, if the design application

asks for a 3 GHz bandwidth, then the common mode voltage should me selected at 3 V

d.c. which will result in a drain current of no more than 3.11 µA. However, for

applications that demand a higher bandwidth, the drain must be increased up to over 110

µA.

Knowing the transfer function of a transistor greatly increases the ability to

predict and set the maximum and minimum gate bias voltage that is needed for the

design. The small current input is directly proportional to the small input voltage (𝑖𝑖 ∝

𝑣𝑖 ). Therefore, to test the limitations of a targeted design, the requirements of the input

voltage will make an affect in the transit frequency of the transistor because the limiting

gate voltage bias is defined by Equation (3-53).

Reducing the gate voltage bias (𝑉𝐺𝐺 or CM voltage) results in reducing the transit

frequency. Figure 3-9 shows a family of curves that demonstrates how a change in the

gate voltage bias results in a shift of transit frequency. The transistor size is unchanged

as well as the magnitude of the small input voltage which is a design dependent variable.

73
 10
9 Desired
8
Gain at
30 GHz
7
Current Gain [A/A] 6 Current Gain, CM=0.7
5 V, [A/A]

4 Transit
Frequency
3
234.27 GHz
2
1
0
1.E+09 1.E+10 1.E+11 1.E+12
Frequency [Hz]

Figure 3-10 Current Gain for a 28 nm NMOS. Common Mode Voltage (𝑽𝑮𝑮 ) set at 0.7 V. Transit

Frequency at Current Gain of 1 A/A is 234.27 GHz. Desired Current Gain at 30 GHz is

Around 7 A/A. Drain Current at Desired Design Frequency of 30 GHz is 74.48 µA

For example, Figure 3-10 shows that—for a given wanted current gain—the

transistor’s current should be high enough to achieve the desired gain—in this example

the desired gain is 7 A/A. But the drain current must be small enough to sustain the
𝑔
bandwidth of 30 GHz. Therefore, the maximum transconductnce efficiency ( 𝐼𝑚 ) for the
𝐷

example expressed herein is shown in Figure 3-10. To maintain maximum speed for the

transistor, the minimum length for the 28 nm technology is 30 nm. Varying the width

parameter would not affect much the speed of the transistor. From the figure above, it

can be observed that the amplifier should be set with a gate-to-source voltage at 0.7 V

d.c. To control the common source amplifier’s transconductance, the width of the

transistor can vary above 80 nm. However, doing so will decrease the amount of current

needed to attain the needed results. As a result, for high speed or high transmission

74
rates, the most optimum size for the active amplifier is that that has the intrinsic

transistor’s width and length.

3.3 Transit Frequency Using the NMOS Diode Setup Model

This section describes the second method used to extract the transit frequency

parameter. This section describes possible error assumptions for the extraction of the
𝑔𝑚
transit frequency which is ultimately used in the method [16]. This method is the
𝐼𝑑

most popular method for extraction of CMOS technology parameters14.

An NMOS transistor gate is shorted as illustrated in Figure 3-11 to its drain and a

variable voltage is applied to these pins. The source and bulk terminals of the transistor

are connected to ground. This configuration test model is known as the diode

configuration mode and allows for the extraction of not only the transit frequency (𝑓𝑇 )

but also the extraction of the transistor’s threshold voltage (𝑉𝑡ℎ ), the transonductance gain

(𝑔𝑚 ), and the transistor’s technology dependent parameters (μn Cox ). However, other

models are needed to extract the drain-to-source resistance (𝑟𝑑𝑠 ), and the intrinsic gain

(𝑔𝑚 𝑟𝑑𝑠 ).

14
“Aim: Design of MOS amplifier using gm/Id method.” Retrieved from http://discovery.bits-
pilani.ac.in/discipline/eee/agupta/microelectronic-circuits/spice-online/online-2/gm-id-examples.pdf on
February 22, 2013.

75
Figure 3-11 NMOS Diode Configuration to Extract Transistor Technology Parameters

Figure 3-11 shows the setup for simulation circuit where it can be observed that

the transistor is set in the diode configuration. This is done primarily to set the gate

voltage (𝑉𝐺𝑆 ) equal to the drain voltage (𝑉𝐷𝑆 ).

The simulation is set up to vary the gate voltage (𝑉𝐺𝑆 ) from -0.1V d.c. to 1V d.c.

The negative voltage is needed by Spectre®, the software simulation tool, to simulate

derivatives of drain current when the gate value is zero volts. As a result, plotting the

drain current (𝐼𝐷𝑆 ) versus the drain-to-source voltage (𝑉𝐷𝑆 ) is the same as plotting the

drain current versus the gate voltage (𝑉𝐺𝑆 ).

The gate-to-source voltage is considered the input voltage while the drain-to-

source voltage is considered the output voltage. Under these conditions, the system’s

voltage gain is at all times unity because these voltages are always the same.

𝑉𝐷𝑆 𝑉 (3-58)
= 𝐴𝑜 = 1 [ ]
𝑉𝐺𝑆 𝑉

76
 The small signal model for the circuit described in this section is shown in Figure

3-12.

(a) (b)

Figure 3-12 NMOS Diode Configuration. (a) Small Signal Model for Figure 3-11 Circuit. (b) π-

Model for NMOS Diode Configuration

It can be observed that changes in the circuit test model yields a significant

change in how the equivalent gate capacitance is calculated (𝐶𝑔𝑔 ).

(3-59)
𝑖𝑔 + 𝑖𝑑 − 𝑖𝑑 + 𝑖𝑑𝑠 = 0

(3-60)
⇒ 𝑖𝑔 = −𝑖𝑑𝑠

(3-61)
= −𝑣𝑖 [𝑔𝑚 + 𝑠(𝐶𝑔𝑠 + 𝐶𝑑𝑏 )]

77
 (3-62)
= 𝑣𝑖 𝑠𝐶𝑔𝑔

(3-63)
⇒ 𝑠𝐶𝑔𝑔 = −𝑔𝑚 − 𝑠(𝐶𝑔𝑠 + 𝐶𝑑𝑏 )

𝑊 (3-64)
= −𝜇𝑛 𝐶𝑜𝑥 𝑣𝑖 − 𝑠(𝐶𝑔𝑠 + 𝐶𝑑𝑏 )
𝐿

The transit frequency in this case is extracted by assuming the small signal

voltage gain (|𝐴𝑜 |) is directly proportional to the small signal current gain (|ℎ21 |).

𝑉𝐷𝑆 𝑖𝑑 𝑠𝐶𝑑𝑑 𝐶𝑑𝑑 (3-65)

|𝐴𝑜 | = | | = | | = |ℎ21 | | |
𝑉𝐺𝑆 𝑖𝑔 𝑠𝐶𝑔𝑔 𝐶𝑔𝑔

(3-66)
1 = |𝐴𝑜 | ∝ |ℎ21 |

As a result, the small voltage gain results in a direct proportionality of current

gain,

(3-67)
|𝐴𝑜 | ∝ |ℎ21 |

78
 𝑔
Many authors15 [16][17] implement the transconductance efficiency ( 𝐼 𝑚 ) model
𝑑𝑠

with the assumption that the transit frequency is,

1 (3-68)
𝑓𝑇 =
2𝜋𝐶𝑔𝑔

And some of these authors [17] define the gate capacitance as,

(3-69)
𝐶𝑔𝑔 ≜ 𝐶𝑔𝑠 + 𝐶𝑔𝑑 + 𝐶𝑑𝑏 ; assumed by some authors

In the event that the transistor is arbitrarily set in saturation mode [15], the input

capacitance can be approximated by,

(3-70)
𝐶𝑔𝑔 ≅ 𝐶𝑔𝑠 ; in saturation mode only

It has been demonstrated in the previous section that the gate capacitance is not

what determines the transit frequency but rather what determines the transit frequency is

a combination of:

(a) The circuit test model setup;

(b) The small input frequency to the gate of the transistor;

(c) The length parameter of the transistor;

(d) The gate bias voltage;

𝑔𝑚
15
Ardalan. Analog CMOS Design: . Lecture Notes. San Jose State University; Fall 2012. See
𝐼𝑑𝑠
also Foot note 14 herein.

79
 (e) The supply voltage; and

(f) The way the transit frequency is measured in Spectre® using the Cadence Design

Suite (CDS) software simulator.

For the circuit described in this section, the transit frequency is commonly

extracted by assuming that,

𝑔𝑚 (3-71)
𝑓𝑇 =
𝐶𝑔𝑠

1 𝜕𝐼𝐷𝑆 (3-72)
𝑓𝑇 =
𝐶𝑔𝑠 𝜕𝑉𝐷𝑆

In order to plot the transit frequency, Equation (3-72) by swiping the gate voltage

using the dc analysis in CDS Virtuoso® using the 45 nm from a standard General Process

or Cadence® Design Kit (GPDK) library. The following mathematical formula was

entered into the Virtuoso® Visualization & Analysis XL Calculator to plot the transit

frequency of the schematic model as suggested by some authors:

deriv(IS("/NM1/D"))/(2*pi*OPT("/NM1","cgs"))

Such formula yields a curve with negative frequencies which suggests that there is

something fundamentally wrong with Equation (3-71).

80
Figure 3-13 Difference Between Classic Transit Frequency—Shown with Negative Frequencies—and

Transit Frequency Proposed in this Paper—Shown with Positive Frequencies

However, this paper proposes to measure the transit frequency as calculated in

equation (3-37), which results in a transit frequency is positive which suggests that the

calculation derived in this paper is valid for the calculation of transit frequencies (Figure

3-13).

Figure 3-13 indicates that since the voltage gain is always unity no matter what

the gate voltage is, the current gain is assume to be unity also (see Equation (3-67)) and

the graph represents a transit frequency of a transistor as long as it is saturated.

Therefore, the graph is only valid for input gate voltages, and transistor sizing that is

consistent of setting the transistor in the saturation region. As a result, the transit

81
frequency graph—when extracted by the diode method—is not appropriate for transistors

that are set below the saturation region.

For example, it was found that the maximum transit frequency for the 45nm

technology is 260.5609 GHz when L=45 nm, W=120 nm, and the circuit test model is set

in the diode mode at 𝑉𝐺𝑆 =1V.

For the 28 nm CMOS technology described herein, the result for transit frequency

can be calculated in many ways. One way is by using Virtuoso® by sweeping the gate

voltage on a NMOS transistor wired in the diode configuration (Figure 3-11). Table 3-1

shows the calculated values for the transfer frequency using three different formulas. As

it can be seen, there is a significant variation between the formulas result. This may

imply that there may not be a precise consensus as to what is the best way to measure the

transit frequency of a MOS device.

82
Table 3-1 Transfer Function Results for a 28 nm NMOS Capacitor using Cadence® Virtuoso® Tools.

28 nm
Equation Reference Transit frequency Equation Transit Frequency
[THz]

(3-71) 𝑔𝑚
𝑓𝑇 = 282.6240
𝐶𝑔𝑠
Simplified from [16][17]
(3-68) 𝑔𝑚
𝑓𝑇 = 44.9810
2𝜋𝐶𝑔𝑔
[16][17]

(3-37) 𝑔𝑚
𝑓𝑇 =
25.9698
This thesis 2𝜋√𝐶𝑔𝑠 2 + 2𝐶𝑔𝑠 𝐶𝑔𝑑

It is noted that the transit values expressed above are based on the constant value

results that Virtuoso® outputs. In order to accurately measure the transit frequency, it is

necessary to find a different way to measure the transistor capacitances because

Virtuoso® outputs only one capacitance value for all the possible values of the gate

voltage.

In order to calculate the capacitance for the gate or drain given an specific voltage

across the capacitance, a transient analysis must be performed. Capacitance can be

calculated as follow:

𝑑𝑄(𝑡) (3-73)
𝐶(𝑡) =
𝑑𝑉(𝑡)

83
 𝐶(𝑡) 1 𝑑𝑄(𝑡) (3-74)
=
𝑑𝑡 𝑑𝑡 𝑑(𝑣)

𝐼(𝑡)𝑑𝑡 (3-75)
𝐶(𝑡) =
𝑑𝑉(𝑡)

𝐼(𝑡)
𝐶(𝑡) = (3-76)
𝑑𝑉(𝑡)
( )
𝑑𝑡

Equation (3-76) can be used to calculate the gate and drain capacitance for the

circuit from Figure 3-11.

(a) (b)

Figure 3-14 28 nm NMOS Technology. (a) Gate Capacitance; (b) Drain Capacitance

Based on the calculated capacitances from Figure 3-14, the transfer function can

be plotted. To do this, it was necessary to first calculate the transconductance gain (𝑔𝑚 )

can be calculated by sweeping the gate voltage as follow:

84
 𝑖 (3-77)
𝑔𝑚 = 𝑣𝐷
𝐺

𝜕𝐼𝐷 (3-78)
=
𝜕𝑉𝐺

𝜕𝐼𝐷 (𝑡)
( ) (3-79)
𝜕𝑡
𝑔𝑚 (𝑡) =
𝜕𝑉 (𝑡)
( 𝐺 )
𝜕𝑡

Figure 3-15 shows the transconductance gain as voltage is swept from 0 V to 1 V

and then from 1 V to 0V. Note that there is a hysteresis behavior on the transconductance

result.

Figure 3-15 28 nm NMOS Technology. Transconductance Gain (𝒈𝒎 ) for NMOS Connected in the

Diode Configuration.

85
Figure 3-16 28 nm NMOS Technology. Different Derivations Comparison for Transit Frequency

when the NMOS is Connected in the Diode Configuration.

Figure 3-16 shows the calculated transit frequency (𝑓𝑇 ) from two popular

formulas and this thesis proposed formula. Note that the transit frequency measurements

for the NMOS connected in the diode configuration does not correspond to the measured

and more accurate model as shown in Figure 3-4 and Figure 3-9. Therefore,

measurement results for transit frequency is highly dependent on how the circuit is

connected. In this case, a diode configuration circuit provides a sort of transconductance

gain with a bandwidth amplification that is between 3.5 GHz and 4 GHz.

3.4 Important NMOS Parameters Needed to Design an Amplifier

Based on Figure 3-4, some of the most absolute maximum values for small signal

parameters in the 28 nm NMOS device can be obtained by the following equations by

sweeping the gate voltage as a function of time (V(t)):

𝐼𝐺 (𝑡)
𝐶𝐺 (𝑡) = (3-80)
𝜕𝑉 (𝑡)
( 𝐺 )
𝜕𝑡

86
 𝑣𝐺 (𝑡) (3-81)
𝑖𝐺 (𝑡) =
𝑧𝐺 (𝑡)

𝜕𝑉 (𝑡)
( 𝐺 ) (3-82)
𝜕𝑡
=
𝜕𝑍 (𝑡)
( 𝐺 )
𝜕𝑡

𝜕𝑉 (𝑡)
( 𝐺 )
𝜕𝑡
𝑖𝐺 (𝑡) = (3-83)
𝑉
𝜕 ( 𝐼 𝐺 ) (𝑡)
𝐺
{ }
𝜕𝑡

800
700
600
Gate Capacitance (C) [fF]

500
400
300
200
100
0
-100
-200
-300
0 0.2 0.4 0.6 0.8 1
Gate-to-Source Voltage [V]

Figure 3-17 Gate Capacitance for 28 nm NMOS Technology. Small Signal Parameter

87
 45

40
Drain Current (I) [µA] 35

30

25

20

15

10

0
0 0.2 0.4 0.6 0.8 1
Gate-to-Source Voltage [V]

Figure 3-18 Maximum Drain Current for 28 nm NMOS Technology. Large Signal Parameter.

NMOS Intrinsic Transistor Sized to 30 nm Width and 80 nm Length

600

500
Gate Impedance (Z) [TΩ]

400

300

200

100 11.2 TΩ

-100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate-to-Source Voltage [V]

Figure 3-19 Hysteresis Gate Impedance for 28 nm NMOS Technology. Large Signal Parameter

88
 3

2.5
Gate Impedance (z) [pΩ]
2

1.5

0.5

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate-to-Source Voltage [V]

Figure 3-20 Hysteresis Gate Impedance for 28 nm NMOS Technology. Small Signal Parameter

2.5
Gate Current (i) [pA]

1.5

0.5

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate-to-Source Voltage [V]

Figure 3-21 28 nm NMOS Technology. Different Derivations Comparison for Transit Frequency

when the NMOS is Connected in the Diode Configuration

89
3.5 Current Sources

As indicated in the previous section, the drain current of a transistor increases as

the bandwidth and current gain requirements increase. In the case of the 28 nm NMOS

transistor, the absolute maximum current biased with a gate-to-source voltage (𝑉𝐺𝑆 ) of

0.7 V is 10 µA. Therefore, a current source (𝐼𝑆 ) needs to be designed to deliver such

current. Figure 3-22 illustrates a current mirror circuitry that will be set to provide a

maximum of 10 µA. The current source (𝐼𝑆 ) can be adjusted or programed by the PMOS

transistor (P1) by with a control bias voltage (𝑉𝐵𝐼𝐴𝑆 𝐶𝑂𝑁𝑇𝑅𝑂𝐿 ). Current output can be

adjusted by adjusting the width of transistor N2. It was found that for the 28 nm

technology, the drain current ratio between transistors N1 and N2 is around 2. To

improve the layout of the circuit, a transistor parameter called “number of gate fingers”

parameter was varied on transistor N2. The number of gate finger parameter value is

multiplied the gate width parameter to increase the overall transistor’s gate width. In

order to minimize circuit power consumption, the width parameter for transistors N1 and

N2 were set to 80 nm while their length parameter were set to 30 nm. To adjust the

desired current, the finger parameter for transistor N1 was set to unity while the transistor

N2 finger parameter was incrementally increased to measure the drain current of N2.

The control voltage (𝑉𝐵𝐼𝐴𝑆 𝐶𝑂𝑁𝑇𝑅𝑂𝐿 ) was set to zero volts to saturate PMOS transistor P1.

The width and length parameters for transistor P1 were also set to 28 nm and 80 nm

respectively with a unity finger parameter.

90
 P1

N1 N2

Figure 3-22 Programmable Current Mirror to Provide a Source Current (𝑰𝑺 )

The results for the current mirror can be seen in Figure 3-23. The voltage control

is turned off after 25 ms. The drain terminal for transistor N2 is connected to the source

voltage without d.c. filtration. As a result, there is a ringing voltage when the control

turns on the current mirror circuit.

91
Figure 3-23 Current Mirror Measurements. Current Source (𝑰𝑺 ) is Adjusted by Increasing the

Number of Gate Fingers Parameter in the N2 Transistor

92
3.6 Basic Amplifier

The basis of an equalizer is an amplifier with wide bandwidth. Figure 3-24 shows

a common source NMOS differential amplifier. To derive the transfer function for this

type of amplifier, the circuit is simplified by dividing the circuit in two.

Figure 3-24 Common Source NMOS Differential Amplifier

Note that a differential amplifier is composed of two identical mirror circuit legs

that share the same current source (𝐼𝑆𝑆 ). Figure 3-25 represents the simplified circuit leg.

The differential voltage gain and the simplified circuit voltage gain are identical. As a

result, the amplifier can be modeled and designed from a simplified version which

reduces the amount of hours spent doing circuit analysis.

93
Figure 3-25 Simplified Common-source NMOS Circuit Leg for a Differential Amplifier

To implement this circuit using a design tool, the current source (𝐼𝑆𝑆 ) is replaced

by a current mirror circuit (Figure 3-26). The current control (𝑉𝐼𝑆𝑆 ,𝐵𝐼𝐴𝑆 ) is set to zero

volts to maximize the amount of current created by the current mirror circuit. The

capacitance seen at the gate of the NMOS transistor is affected by the capacitance of the

current mirror drain capacitance. As a result, the circuit transit frequency and other

electrical parameters change. Therefore, it is important to set the source current circuitry

first before continuing making analysis and measurements.

It was already established, that if a high bandwidth circuit of 30 GHz with a

current gain above 5 A/A is desired, the common mode voltage must be set above 0.7 V.

94
It was also established that the drain current of the amplifier must be around 74.48 µA.

And it was also established that the current source analysis for one leg is of the

differential amplifier is half of what is required for the entire circuit.

Figure 3-26 Common Source NMOS Differential Amplifier

In order to increase the source current to the amount needed, the number of gate

fingers parameter must be increased to 170 fingers which generate a current of 149.1955

µA (Figure 3-27). This means that the intrinsic width parameter is increase from 80 nm

for one finger to 12 µm for 150 fingers. As a result, the capacitance seeing at the gate of

the amplifier is affected by the current source capacitance. This capacitance is critical to

attain high bandwidth in the amplifier.

95
 195

175

155

135
Source Current [µA]

Fingers=10
115
Fingers=30
95 Fingers=60
Fingers=100
75
Fingers=130
55 Fingers=170
Fingers=200
35

15

-5
0 0.1 0.2 0.3 0.4 0.5
Time [s]

Figure 3-27 Amplifier’s Source Current. Solid Line Represents Desired Finger Size

Note that the current control is not capable to bring down the current to zero

Amps. To fix this, a programmable load is added to the circuit to regulate the current

(Figure 3-28

Once the current mirror fingers has been set to provide the desired current source,

the current is half by adjusting the current mirror control voltage (𝑉𝐼𝑆𝑆 ,𝐵𝐼𝐴𝑆 ). In other

words, each differential NMOS transistor acting as the amplifier must have a bias current

leg of 74.5 µA to ensure that all quiescent points are set for maximum bandwidth.

96
 P2
Programmable Load 7W

P1
W

N1 N2
W 170W

Figure 3-28 Amplifier Circuit Current Source

The current source is active or reduced by the current mirror control

(𝑉𝐵𝐼𝐴𝑆 𝐶𝑂𝑁𝑇𝑅𝑂𝐿 ) while the programmable load is controlled by PMOS P2 gate voltage

(𝑉𝐿𝑂𝐴𝐷,𝐵𝐼𝐴𝑆 ).

Figure 3-29 shows the complete circuit for a simple high-bandwidth common

source amplifier. The voltage load (𝑉𝐿𝑂𝐴𝐷,𝐵𝐼𝐴𝑆 ) is adjusted to the most optimum output

gain. The input common voltage is the gate bias voltage for the amplifier.

Figure 3-30 shows the different voltage gain curves or frequency response for the

amplifier in Figure 3-29. This design is capable to amplify frequencies higher than 30

GHz if the load voltage bias is set to 0.42 v.

97
 P2
Programmable Load 7W

N0

Amplification

P1
W

N1 N2
W 170W

Figure 3-29 High-bandwidth Common Source Amplifier with Programmable Load and Current

Source Control. Common Mode Voltage is Setup at 0.7 V

Load Voltage = 0.5 V

Load Voltage = 0.48 V

Load Voltage = 0.46 V

Load Voltage = 0.444 V

Load Voltage = 0.42 V

Figure 3-30 High-bandwidth Amplifier Design with Various Voltage Gain Outputs

98
 Figure 3-29 shows the configuration of an open loop common source NMOS

amplifier connected to a current mirror to adjust the source current (𝐼𝑆𝑆 ) which is

controlled by the PMOS voltage gate bias (𝑉𝐵𝐼𝐴𝑆 𝐶𝑂𝑁𝑇𝑅𝑂𝐿 ).

It was observed that the current mirror impedance affects the overall bandwidth of

the circuit. By introducing the design of a current mirror to the amplifier, the IC designer

can size to an existing predefined design.

Figure 3-31shows the small signal analysis for the common source amplifier with load

𝑅𝐿 .

(a)

(b)

Figure 3-31 Small Signal Model for Simplified NMOS Amplifier. (b) Simplified Small Signal Model

for NMOS Amplifier.

99
The small signal transfer function for voltage gain is obtained as follow,

𝑉𝑜 𝑠𝐶𝑔𝑠 + 𝑔𝑚
=− (3-84)
𝑉𝑖 1
+ 𝑠𝐶𝑑𝑏
𝑟𝑑𝑠 ‖𝑅𝐿

Equation (3-84) is manipulated to find the critical frequencies. Therefore Equation

(3-84) should take the form of,

𝑠
𝑉𝑜 (1 + 𝜔 )
𝑧 (3-85)
= −𝐴𝑣
𝑉𝑖 𝑠
(1 + 𝜔 )
𝑝

As a result, Equation (3-84) results in,

𝑠
1+ 𝑔
(𝐶𝑚 )
𝑉𝑜 𝑔𝑠 (3-86)
= −𝑔𝑚 (𝑟𝑑𝑠 ‖𝑅𝐿 ) 𝑠
𝑉𝑖 1+ 1
( )
[ (𝑟𝑑𝑠 ‖𝑅𝐿 )𝐶𝑑𝑏 ]

Where,

𝑔 (3-87)
𝜔𝑧 = 𝐶 𝑚 [rad/s]
𝑔𝑠

1 (3-88)
𝜔𝑝 = (𝑟 [rad/s]
𝑑𝑠 ‖𝑅𝐿 )𝐶𝑑𝑏

(3-89)
𝐴𝑣 = 𝑔𝑚 (𝑟𝑑𝑠 ‖𝑅𝐿 ) [V/V]

100
 Equations (3-85) to (3-89) allow analysis of the common source NMOS amplifier

using the bode plot. Setting the low frequency voltage gain (𝐴𝑣 ) to be equal to an

specified voltage gain—this could vary from design to design and circuit implementation,

this example uses a gain of 2—and changing the frequency scale from radians per second

to Hz, we can plot a Bode plot with the following critical points:

𝜔 𝑔 (3-90)
𝑓𝑧,−3𝑑𝐵 = 2𝜋𝑧 = 2𝜋𝐶𝑚 [Hz]
𝑔𝑠

𝜔𝑝 1 (3-91)
𝑓𝑝,−3𝑑𝐵 = = 2𝜋(𝑟 [Hz]
2𝜋 𝑑𝑠 ‖𝑅𝐿 )𝐶𝑑𝑏

(3-92)
𝐴𝑣 = 2 = 𝑔𝑚 (𝑟𝑑𝑠 ‖𝑅𝐿 ) [V/V]

𝑠
𝑉𝑜 (1 + 𝜔 ) (3-93)
𝑧
| | = 20𝑙𝑜𝑔10 (|−𝐴𝑣 |)
𝑉𝑖 𝑑𝐵 𝑠
(1 + 𝜔 )
𝑝

(3-94)
𝑠=𝑗𝜔

𝜔
𝑉𝑜 (1 + 𝑗 𝜔 ) (3-95)
𝑧
| | = 20𝑙𝑜𝑔10 (|−𝐴𝑣 |)
𝑉𝑖 𝑑𝐵 𝜔
(1 + 𝑗 𝜔 )
𝑝

101
 𝑓
𝑉𝑜 (1 + 𝑗 )
𝑓𝑧 (3-96)
| | = 20𝑙𝑜𝑔10 (|−𝐴𝑣 |)
𝑉𝑖 𝑑𝐵 𝑓
(1 + 𝑗 )
𝑓𝑝

Seting the 3dB cut off frequency to 30GHz.

𝜔𝑝 1 (3-97)
𝑓𝑝 = = 2𝜋(𝑟 =30GHz
2𝜋 𝑑𝑠 ‖𝑅 𝐿 )𝐶𝑑𝑏

The zero-frequency (𝑓𝑧 ) was set much larger than the pole frequency (𝑓𝑝 ).

(3-98)
𝑓𝑝 ≪ 𝑓𝑧

1 𝑔𝑚 (3-99)
≪
2𝜋(𝑟𝑑𝑠 ‖𝑅𝐿 )𝐶𝑑𝑏 2𝜋𝐶𝑔𝑠

The IC designer has two options to make when deciding how to size or bias the

circuit above. The first option is to assume that the drain-to-source resistance (𝑟𝑑𝑠 ) is

much larger than the load resistance (𝑅𝐿 ) to allow him or her to control both the gain and

the bandwidth with a parameter that is linear such as the impedance of the load (𝑅𝐿 ). As

a result, the impedance of the amplifier (𝑟𝑑𝑠 ) becomes irrelevant for the designer to set

the bandwidth of the circuit. The second option is to allow the load resistance to be

larger than the drain-to-source resistance and use the new method proposed in this paper

that allows the load resistance adjust the drain current of the circuit.

102
 𝑔𝑚
The first option is what is assumed when using the 𝐼𝑑
method. Therefore, the

following sets of equations assume the first option and the reader can just replace the load

resistance for the drain-to-source resistance for the method proposed by this thesis.

(3-100)
𝑅𝐿 ≪ 𝑟𝑑𝑠

(3-101)
𝑟𝑑𝑠 ‖𝑅𝐿 ≅ 𝑅𝐿

(3-102)
𝐴𝑣 = 2 ≅ 𝑔𝑚 𝑅𝐿 [V/V]

As a result, Equation (3-99) can be arranged as follow:

1 𝑔𝑚 (3-103)
≪
𝑅𝐿 𝐶𝑑𝑏 𝐶𝑔𝑠

𝑔𝑚 𝑅𝐿 𝐶𝑑𝑏 (3-104)
⇒1≪
𝐶𝑔𝑠

From Equation (3-97), (3-89), and (3-104) become the critical points to meet the

design specifications.

1 (3-105)
=(30)(109 )
2𝜋𝑅𝐿 𝐶𝑑𝑏

103
 (3-106)
𝑔𝑚 𝑅𝐿 = 2

2 (3-107)
⇒ 𝑔𝑚 =
𝑅𝐿

𝑔𝑚 𝑅𝐿 𝐶𝑑𝑏 2𝑅𝐿 𝐶𝑑𝑏 𝐶𝑑𝑏 (3-108)

⇒1≪ = =2
𝐶𝑔𝑠 𝑅𝐿 𝐶𝑔𝑠 𝐶𝑔𝑠

1 𝐶𝑑𝑏 (3-109)
⇒ ≪
2 𝐶𝑔𝑠

The meaning of Equation (3-109) is important since it assures to choose the size
𝐶𝑑𝑏
of the NMOS transistor such that the ratio is larger than 0.5. This is difficult to
𝐶𝑔𝑠

𝑔𝑚
accomplish even when the method is used.
𝐼𝑑

Another design point of interest for a common source amplifier is the zero-

frequency. This frequency—if the design is used in analog designs—affects the stability

of the entire circuit when the loop is closed, and sets the minimum attenuation of a signal

thus becoming a factor of amplification swing. In the event that the zero-frequency needs

to be defined as the frequency where the gain is zero dB, the following equation is

derived.

𝑓
𝑉𝑜 (1 + 𝑗 )
𝑓𝑧 (3-110)
| | = 20𝑙𝑜𝑔10 (|−𝐴𝑣 |) = 0
𝑉𝑖 𝑑𝐵 𝑓
(1 + 𝑗 )
𝑓𝑝

104
 𝑓
(1 + 𝑗 )
𝑓𝑧 (3-111)
𝑙𝑜𝑔10 (|−𝐴𝑣 |) = 0
𝑓
(1 + 𝑗 )
𝑓𝑝

𝑓
(1 + 𝑗 𝑧 ) (3-112)
100 = |−𝐴𝑣 |
𝑓
(1 + 𝑗 )
𝑓𝑝

𝑓 2
1+( ) (3-113)
𝑓𝑧
1 = 𝐴𝑣 √
𝑓 2
1+( )
𝑓𝑝

𝑓 2
1 2 1 + ( )
𝑓𝑧 (3-114)
( ) =
𝐴𝑣 𝑓 2
1+( )
𝑓𝑝

(3-115)
𝑓𝑧 = 𝑓

1 2 2
( ) = (3-116)
𝐴𝑣 𝑓 2
1 + ( 𝑧)
𝑓𝑝

𝑓𝑧
2 (3-117)
1 + (𝑓 ) = 2𝐴𝑣 2
𝑝

𝑓𝑧
2 (3-118)
(𝑓 ) = 2𝐴𝑣 2 − 1
𝑝

105
 (3-119)
𝑓𝑧 |@0𝑑𝐵 = ±√2𝐴𝑣 2 𝑓𝑝 2 − 𝑓𝑝 2

Where,

(3-120)
𝑓𝑝 = 30𝐺𝐻𝑍

(3-121)
𝐴𝑣 = 2

(3-122)
⇒ 𝑓𝑧,0𝑑𝐵 = ±30 × 109 × √7

(3-123)
𝑓𝑧,0𝑑𝐵 ≅ 79.37𝐺𝐻𝑧

Therefore, from Equations (3-98) and (3-122), the following identity is derived,

(3-124)
(30 × 109 ) ≪ (30 × 109 × √7)

1 (3-125)
≪ 30 × 109 × √7
2𝜋𝑅𝐿 𝐶𝑑𝑏

106
 1 (3-126)
≅ 2 [𝑝𝑠] ≪ 𝑅𝐿 𝐶𝑑𝑏
2𝜋30 × 109 × √7

3.7 Amplification Chain Biasing

One of the most difficult thing to achieve when connecting several amplifiers in

series is two make sure that the bias of the input of the second stage is bias the same way

as the gate bias of the first stage so that the amplifier’s bandwidth is not disturbed. This

can be achieved in many ways, one way is by adding a coupling capacitor between

amplifiers and thereby creating a d.c. separation between each stage. In this method,

each stage input gate bust be biased independently. However, it was found that adding a

bias circuit for the second stage and a coupling capacitor not only reduces the gain that

was attained by a previous amplification state but also reduces the desired bandwidth.

Therefore, the output of a previous state must be preprogramed and balanced to bias the

following amplification state (Figure 3-32).

Rx Rx
Bias Point
Without
Coupling
Capacitor
Figure 3-32 Connection of Two Identical Amplifiers Coupled without the Need of a Coupling

Capacitor. Quiescent Point of First Amplifier Bias the Gate Input to the Second

Amplifier

107
 To properly bias subsequent amplification stages, the quiescent point of the

previous amplification stage must be set by adjusting the active output load voltage

(𝑉𝐿𝑂𝐴𝐷,𝐵𝐼𝐴𝑆 ). To do this, a transient analysis with an input pulse voltage to the input of

the first stage is analyzed.

It is known that reducing the gate bias voltage or common mode voltage to the

amplification stage reduces the bandwidth of the amplifier. Figure 3-33 illustrates that

for the design of this thesis, the amplifier load bias voltage (𝑉𝐿𝑂𝐴𝐷,𝐵𝐼𝐴𝑆 ) must be set

around 0.46 V.

0.42 V
0.44 V
0.46 V
Input Voltage Quescent Voltage (Q)

Desired Voltage

Output Voltage

Figure 3-33 Evaluation of Amplifier Quiescent Point Voltage (Q). The Quiescent Point of the First

Amplifier Stage Affects the Input Gate Bias of the Second Stage

The load bias voltage was set to 0.46 V because reducing the voltage will also

reduce the gain at 30 GHz (Figure 3-30).

108
Table 3-2 Measured DC Parameters for Amplifier in Figure 3-21 Using Cadence® Virtuoso®

Analog Design Environment—Transient Analysis

DC Amplifier Parameter Measured value Unit

N0 Common Mode Voltage 0.7 V
N0 Gate Capacitance 84.220778 fF
N0 Drain-to-Source Capacitance 1.121117 µF
N0 Drain Current 7.0345 µA
N0 Gate-to-Source Voltage 0.678 V
N0 Gate Resistance 4.158 TΩ
N0 Drain-to-Source Resistance 102.38587 kΩ
N2 Source Voltage 21.7103 mV
N2 Drain Capacitance 39.4 µA
N2 Drain to Source Resistance 3.08623 kΩ
Output Resistance 105.4721 kΩ
Output Capacitance 1.143 µF
Load Bias Voltage 0.46 V

Based on the measured d.c. parameters for the proposed amplifier, connecting the

amplifiers in series does not cause any impedance matching issues when the amplifiers

are connected in series. Observe that the output capacitance is much larger than the input

capacitance which makes little effect in the overall bandwidth since the output

capacitance is one of the main parameters that sets the cutoff frequency as explained in

previous sections. Also, the input resistance of the amplifier is much larger than the

output resistance. When these resistances are placed in parallel, the equivalent resistance

is basically the output resistance of the amplifier.

109
 P2 P2
7W 7W

N0 N0

P1
W

N1 N2 N2
W 170W 170W

Figure 3-34 Two Stage Amplifier with No Coupling Capacitance between the Stages is Necessary

The circuit described herein can only support no more than three stages of

amplification. The second stage voltage gain amplification at a frequency of 30GHz is

10.72 dB. The first stage voltage gain amplification at the same frequency is 2.70 dB.

This is due to the fact that in every stage, the quiescent point moves lower than the

desired 0.7 V. An impedance matching circuit should be adapted to ensure that every

stage is properly biased.

3.8 Differential Amplifier Configuration.

This section describes how to connect the designed amplifier from the previous

section. This circuit does not require a coupling capacitors between stages.

110
 P2 P2 P2 P2
7W 7W 7W 7W

N0 N0 N0 N0

P1
W

N1 N2 N2
W 170W 170W

Figure 3-35 Two Stage Differential Amplifier with No Coupling Capacitance between the Stages is

Necessary. Active Load and Output Power Control

The circuit depicted in Figure 3-35 has the same voltage gain response than the

circuit from Figure 3-34. This circuit is also designed to reduce the signal-to-noise ratio.

3.9 Pulse Shaping

In order to create a curve that slowly tapers from zero decibels upwards to a

frequency of 30 GHz, a high pass filter is connected in series with a low pass filter

amplifier, This will create a band pass filter that emulates the inverse lower frequency

response of a channel. Consider the circuit in Figure 3-36 with a transfer function

expressed in (3-127).

111
Figure 3-36 Hi Pass Filter

𝑠
(1 + 1 )
(𝑅 𝑅 𝐶 )
𝑣𝑜 𝑅𝐿 𝐿 𝑠 (3-127)
=
𝑣𝑖 𝑅𝑠 + 𝑅𝐿
𝑠
(1 + 𝑅 + 𝑅 )
( 𝑅𝑠 𝑅 𝐶𝐿 )
𝐿 𝑠

1 (3-128)
𝜔𝑧 = ( )
𝑅𝐿 𝑅𝑠 𝐶

1 (3-129)
𝜔𝑧 = ( )
𝑅𝐿 𝑅𝑠 𝐶

(3-130)
𝜔𝑧 ≪ 𝜔𝑧

Then the circuit is placed in series with the amplifier to form a band pass filter.

Note that the series resistance (𝑅𝑠 ) should be small so that there is little d.c. attenuation

created by the high pass filter.

112
 0 10

Voltage Gain [dB]

Voltage Gain [dB]

-50 5

-100 0
1 10 100 1000 1 10 100 1000

Frequency [GHz] Frequency [GHz]

10

Voltage Gain [dB]

A 5

HIGH
PASS AMPLIFIER
FILTER
0
1 10 100 1000

Frequency [GHz]

Figure 3-37 Equalizer Model Using a High Pass Filter in Series with an Amplifier

In order to better control the shape of curve for which the equalizer circuit is

designed, the a series low pass filter is connected to the circuit to create or shape the

signal needed by the equalizer.

113
 0 0

Voltage Gain [dB]

Voltage Gain [dB]

-50 -50

-100 -100

Frequency [GHz] Frequency [GHz]

0 0

Voltage Gain [dB]

Voltage Gain [dB]

-50 -50

-100 -100

Frequency [GHz] Frequency [GHz]

Figure 3-38 Bode Plot Representation of a Pulse Shape Signal using a Low Pass and a High Pass

Filter Connected in Series

Figure 3-38 represents a bode plot of a low pass filter and a high pass filter—

depicted on the left. The right bode plots represent the addition of the two frequency

responses from the low pass and the high pass filters.

114
Figure 3-39 Passive Pulse Shape Filter

A pulse shape filter is a filter that shapes the signal to have the inverse curve of a

channel wireline. This filter adds additional attenuation to the channel. The amplifier

must be able to amplify the loss signal to get an overall voltage gain of at least zero

decibels at Nyquist frequency.

Figure 3-40 shows the result of a passive pulse shape filter connected in series

with the amplifier. Note that by changing the series resistance value of the high pass

filter, the signal is attenuated at the lower frequencies but little attenuation is made at the

frequencies close to the Nyquist frequency.

115
 8
HPF Resistor = 0.7

HPF Resistor = 1.2

3
HPF Resistor = 1.7

VOLTAGE GAIN [dB] -2 HPF Resistor = 2.2

HPF Resistor = 2.7

-7

-12

-17

-22
0.001 0.01 0.1 1 10 100 1000
FREQUENCY [GHz]

Figure 3-40 Variable Passive Pulse Shape Filter. HPF Resistor is Programmed or Varied to Add

Attenuation to the Lower Frequency Range

The shape and amplification of the signal is arbitrary and depends highly on the

channel response. The ability to program the pulse shape is important. The output of the

pulse shape filter is sometimes called passive peaking.

116
Figure 3-41 Programmable Differential Pulse Shape Filter

3.10 30 GHz Equalizer Circuit Elements

As mentioned in this thesis, there are two basic elements needed to create a 30

GHz front end equalizer design: (a) a programmable differential passive pulse shape

filter, and (b) a programmable differential voltage gain amplifier (VGA).

The first element is responsible to create the shape or profile of the inverse loss

created by the channel. The pulse shape filter is programmable so that it is capable to

117
compensate or equalize the loss created by various types and lengths of channel

microwares. The pulse shape must be able to boost the signal at the Nyquist frequency.

In this case, the passive filter shapes the signal with a boost at 30 GHz.

The second electronic circuit element of an equalizer is a high bandwidth VGA.

The VGA cutoff frequency which is commonly refered as the frequency where the loss is

-3 dB from the lowest frequency, does not have to be set exactly at 30 GHZ because

when connected to the pulse shape filter, all the lower frequencies will be attenuated but

tapered so that it creates the desired amplification at the Nyquist frequency. The

amplification, must be such that it elevates the attenuated Nyquist frequency of 30 GHz

to a voltage gain above zero decibels.

118
4 Results

4.1 High Pass Filter

To calculate the right series resistance (𝑅𝑠 ), the series capacitance (𝐶𝑠 ) and the

load resistance (𝑅𝑜 ) for the high pass filter design, the following calculations were

performed,

𝑣𝑜 𝑅𝑜
= (4-1)
𝑣𝑖 𝑅 + 𝑅𝑠
𝑜 𝑠
(1 + 𝜔 )
1

𝑠
𝑣𝑜 𝑅𝑜 (1 + 𝜔 )
= 1 (4-2)
𝑣𝑖 1 + 𝑠
𝑅 +𝑅
𝜔1 ( 𝑜 𝑅 𝑠 )
𝑜

1 (4-3)
𝜔1 =
𝑅𝑠 𝐶𝑠

Table 4-1 High Pass Filter Calculated Values for Passive Filter Elements

SELECTED ZERO SELECTED DC SELECTED CALCULATED CALCULATED CALCULATED CALCULATED CALCULATED CALCULATED
FREQUENCY FOR GAIN; UPER GAIN RESISTANCE RO [Ω] POLE Rs [Ω] Cs [pF] ω1 [Grads] ωo [Grads]
UPPER LIMIT LOWER LIMIT @ THE POLE FREQUENCY
[GHz] [dB] [dB] f1 [GHz]
5 -100 -3 0.00001 4.99407E-05 100118.653 31.83098862 6.283185307 31.41592654

119
 10

-10
Voltage Gain [dB]

-20

-30

-40

-50

-60

-70

-80
0.01 0.1 1 10 100
Frequency [GHz]

Figure 4-1 Frequency Response for High Pass Filter (HPF) Design

4.2 Low Pass Filter

To calculate the right series resistance (𝑅𝑠 ), the load capacitance (𝐶𝑜 ) for the low

pass filter design, the following calculations were performed,

𝑣𝑜 1 (4-4)
=
𝑣𝑖 1 + 𝑠
𝜔 3

1 (4-5)
𝜔3 =
𝑅𝑠 𝐶𝑜

120
Table 4-2 Low Pass Filter Calculated Values for Passive Filter Elements

SELECTED LOW SELECTED SELECTED CALCULATED ω CALCULATED

PASS FREQUENCY CAPACITOR CUTOFF [Grads] R1 [Ω]
[GHz] [pF] FREQUENCY
[dB]
10 200 -3 62.83185307 0.079577472

-5

-10
Voltage Gain [dB]

-15

-20

-25

-30

-35

-40
0.1 1 10 100 1000 10000 100000
Frequency [GHz]

Figure 4-2 Frequency Response for Low Pass Filter (LPF) Design

4.3 Pulse Shape Filter

This section shows when the low pass filter and the high pass filter are connected

together to form the pulse shape filter.

121
 100

High Pass Filter

Voltage Gain [dB]

Low Pass Filter

0
Pulse Shape Filter

-100
1 10 100 1000
Frequency [GHz]

Figure 4-3 Frequency Response for Pulse Shape Filter (PSF) Design

4.4 30 GHz Equalizer, 28 nm Technology

This section shows the results of the 30 GHz programmable front end equalizer.

10
5
0
-5
Voltage Gain [dB]

-10
-15
-20
-25
-30
-35
-40
0.1 1 10 100 1000
Frequency [GHz]

GAIN CODE 000 GAIN CODE 001 GAIN CODE 010

GAIN CODE 011 GAIN CODE 100 12.5 GHz

Figure 4-4 This Thesis Equalizer Voltage Gain Response—Logarithmic Frequency

122
 5

0
Voltage Gain [dB]

-5

-10

-15

-20
1 6 11 16 21 26
Frequency [GHz]

GAIN CODE 000 GAIN CODE 001 GAIN CODE 010

GAIN CODE 011 GAIN CODE 100

Figure 4-5 This Thesis Equalizer Voltage Gain Response—Linear Frequency

123
5 Conclusion

The motivation behind using USB 3.0 technology was based on two factors: Ease-

of-use, and port expansion. Similarly, PCIe® is a technology that allows high speed

point-to-point serial communication between two microcircuit devices. Both PCIe® and

USB technologies grew from being the connection solution between PC peripherals or

microcircuit devices to being the solution of network communications between a diverse

selection of mobile and hardware products to minimize the amount of wire link

connections and increase reliability. To date, the wired and wireless USB interfaces are

the world’s most popular answer to connectivity for PC, Mobile applications, and

Consumer Electronics because of their low cost, fast implementation, and versatile data

rate transmissions while PCIe® is a common transmission bus protocol between

microcircuit devices. Both PCIe® and USB technologies are scalable and backwards

compatible. Moreover, both technologies employ the 8b/10b data symbol coding per

ANSI X3.230-1994 to increase the reliability of the transmitted signal.

Modeling an accurate transmission line in a CAD system is difficult because of

the available different types of transmission lines which have different dimensional

properties, manufacturing processes, material composition, and electrical parameters.

One of the most important parameters reviewed in this thesis was the transmission line

loss parameter. A simple CAD model approach was implemented to incorporate the

transmission line on a circuit. Attenuation of the signal in transmission lines is

dependent on the length of the transmission line, the transmission line interelement

capacitance, and the transmitted signal frequency.

124
 This thesis demonstrated a design that can be used when using the popular FR4

wireline which is predicted to support a 200 Gb/s transmission line if the transmission

line is 25 cm-long and the transmitter has an output of 100 mV. It was demonstrated that

the capacity of the channel is inversely proportional to the length of the channel. Point-

to-point communication between two microcircuit devices benefit if the devices are as

closed as possible and the transmission line or wireline is shielded from FR noise that

may be induced into the wireline from other wirelines or from the external ambient. In

addition, limiting the amount of vias between the devices decreases the effects of the

interelement capacitance introduced by the via stubs.

A simple circuit model was proposed based on observations of measured and

calculated behaviors of a microstrip wireline. The proposed simple model takes under

consideration small 1 cm-long channel segments. The model can be connected to

simulate single channel as well as differential channels.

This thesis explained the importance of deriving, measuring, and understanding

the transit frequency of the transistor to better plan for any application that requires the

use of an amplifier. This is due to the fact that the most critical device in an equalizer or

amplifier design is the component that does the active amplification. In the case of this

thesis, amplification is done using a common source NMOS amplifier. Knowing the

transit frequency and current gain at various settings of the gate-source voltage to find

the best efficient bias point.

A passive high pass filter connected to a low pass filter create a pulse shape filter

that if connected in series with can be connected in series with an amplifier, the resulting

125
circuit becomes a simple equalizer. There are three basic elements of an equalizer of the

type described in this thesis.

(1) A programmable differential pulse shaper; and

(2) A programmable differential voltage gain amplifier.

Further amplification on the signal can be made by applying an amplifier with

impedance matching at the output of the equilizer.

126
6 References

[1] Global Industry Analyst, Inc. USB 3.0 – A Global Strategic Business Report.

March 2013.

[2] USB Group. USB 3.0 SuperSpeed Equalizer Design Guidelines. June 10, 2011.

[3] USB Group, Universal Serial Bus 3.1 Specification, Rev 1.0, July 26, 2013.

[4] ISSCC, 2014 Digest of Technical Papers, VOL. 57, ISSN 0193-6530, February,

2014.

[5] ISSCC, 2013 Digest of Technical Papers, VOL. 56, ISSN 0193-6530, February,

2013.

[6] Kimura et al, 28Gb/s 560 mW Multi-Standard SerDes with Single-Stage Analog

Front-End and 14-Tap Decision-Feedback Equalizer in 28 nm CMOS.

(Reference [4] Session 2.1).

[7] Won Jung and Razavi, A 25 Gb/s 5.8 mW CMOS Equalizer. (Reference [4]

Session 2.4).

[8] Bai et al, A 0.25pJ/b 0.7V 16Gb/s 3-Tap Decision-Feedback Equalizer in 65nm

CMOS. (Reference [4] Session 2.5).

[9] Mammei et al, A Power-Scalable 7-Tap FIR Equalizer with Tunable Active Delay

Line for 10-to-25Gb/s Multi-Mode Fiber EDC in 28 nm LP-CMOS. (Reference

[4] Session 8.3).

[10] Huang et al, A 28Gb/s 1pJ/b Shared-Inductor Optical Receiver with 56% Chip-

Area Reduction in 28nm CMOS. (Reference [4] Session 8.4).

127
[11] Balan et al, A 130mW 20Gb/s Half-Duplex Serial Link in 28nm CMOS.

(Reference [4] Session 26.1).

[12] Ierssel et al, Signal Capacity of FR4 PCB for Chip-to-Chip Communication.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003.

ISCAS '03. Vol.5, Pgg. V-85 - V-88.

[13] Gallager, Information Theory & Reliable Communication. Wiley, 1968.

[14] Razavi, Fundamentals of Microelectronics. 1st Ed. New Jersey: Wiley, 2006.

[15] Howe, Microelectronics, An Integrated Approach. Upper Saddle River, NJ:

Prentice Hall, 1997. ISBN: 0135885183. As interpreted and presented by Alamo,

Microelectronics Devices and Circuits – Fall 2005, Lecture 23 – Frequency

Response of Amplifiers (I): Common-Source Amplifier. Massachusetts Institute of

Technology, December 1, 2005

[16] Jepers, The Gm/Id Methodology, a Sizing Tool for Low-Voltage Analog CMOS

Circuits. New York: Springer, 2010.

[17] Rao, Analog Front-End Design Using the Gm/Id Method for a Pulse-Based

Plasma Impedance Probe System. Thesis BSEE, Utah State University, 2010.

128