Supporting Information

for Adv. Funct. Mater., DOI 10.1002/adfm.202400008

Synergistic Engineering of Top Gate Stack for Low Hysteresis 2D MoS2 Transistors

Chuming Sheng, Xinyu Wang, Xiangqi Dong, Yan Hu, Yuxuan Zhu, Die Wang, Saifei Gou,
Qicheng Sun, Zhejia Zhang, Jinshu Zhang, Mingrui Ao, Haojie Chen, Yuchen Tian, Jieya Shang,
Yufei Song, Xinliu He, Zihan Xu, Lin Li, Peng Zhou* and Wenzhong Bao*
Supporting Information

Synergistic Engineering of Top Gate Stack for Low Hysteresis Two-Dimensional MoS2
Transistors

Chuming Sheng, Xinyu Wang, Xiangqi Dong, Yan Hu, Yuxuan Zhu, Die Wang, Saifei Gou,
Qicheng Sun, Zhejia Zhang, Jinshu Zhang, Mingrui Ao, Haojie Chen, Yuchen Tian, Jieya
Shang, Yufei Song, Xinliu He, Zihan Xu, Lin Li, Peng Zhou,* and Wenzhong Bao*

C. Sheng, X. Wang, X. Dong, Y. Hu, Y. Zhu, D. Wang, S. Gou, Q. Sun, Z. Zhang, J. Zhang,
M. Ao, H. Chen, Y. Tian, J. Shang, Y. Song, X. He, P. Zhou, W. Bao
State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan
University, Shanghai 200433, China
E-mail: [email protected]; [email protected]

P. Zhou, W. Bao
Shaoxin Laboratory, Shaoxing 312000, China

Z. Xu
Shenzhen SixCarbon Technology, Shenzhen 518055, China

L. Li
Key Laboratory for Photonic and Electronic Bandgap Materials, Ministry of Education,
School of Physics and Electronic Engineering, Harbin Normal University, Harbin 150025,
China
Figure S1. The detailed fabrication processes of monolayer MoS2 DG FETs.
Figure S2. XPS measurements of critical processes. a) XPS survey scan of the samples.
High-resolution deconvolution XPS spectra of b) Si 2p and c) O 1s in SiOx direct deposition
on Si/SiO2 substrate samples with related process, revealed that both HPA and LPA processes
could completely fill the oxygen vacancies in the 2 nm SiOx layer. d) O 1s in pristine MoS2
sample and related MoS2/SiOx samples revealed that oxygen was mainly present in the form
of Si-O or Mo-O bonds, and also demonstrated no any significant peak shift to lower binding
energy, within no tendency for the SiOx side to lose electrons. Micro images of selected area
in micro-XPS measurements of e) HPA MoS2/SiOx/HfOx and f) LPA MoS2/SiOx/HfOx
sample. Scale bars, 100 μm. The red zones indicated the selected region with a beam spot size
of 50 μm.
Figure S3. AFM images of SiOx surface before and after annealing on 280 nm SiO2 and
monolayer MoS2.
Figure S4. Transfer characteristics of selected devices. Inset shows the measurement
schematic of the device electrical performance.

The MoS2 FETs originally exhibiting BG configuration before subsequent processing

have featured an exposed channel region. The electrical characteristics of the two selected

devices were nearly identical due to these overlapping transfer characteristics.

Figure S5. Unidirectional and bidirectional voltage sweep measurements of TG
modulation. a) Initial state measurement under the BG mode. b) Unidirectional voltage
sweep of the top gate with a bias voltage from -6 V to 6 V (step = 0.06 V), resulting in a
positive VTH shift in valid TG modulation. c) Bidirectional voltage sweep of the top gate with
a bias voltage from -6 V to 6 V to -6 V (step = 0.06 V and -0.06 V), resulting in invalid TG
modulation. All measurements of hysteresis were conducted with a VBG sweep rate of 2 V s-1.
Figure S6. The VTH recovery measurements assisted by a) illumination and b) negative
top-gate bias.

Illumination-assisted VTH recovery and negative bias-assisted VTH recovery measurements

were performed sequentially on the same LPA-TG device. The tables below the

corresponding figures have showed the detailed settings and the testing environment. These

results indicated that the application of illumination and negative bias voltages can be

effective in promoting the recovery of the VTH.

Figure S7. Hysteresis and stability measurements. Output characteristics of a) HPA-TG
device and b) LPA-TG device. The drain current and corresponding top-gate leakage current
of c) HPA-TG device and d) LPA-TG device at VDS = 0.1 V with a VTG sweep rate of 0.2 V s-1.
The transfer characteristics of e) HPA-TG device and f) LPA-TG device at VDS = 1 V.

HPA-TG device exhibited a negligible hysteresis of ~14 mV (with 12 V gate voltage

sweeping) while the LPA-TG device exhibited a hysteresis of ~1.2 V (with 12 V gate voltage

sweeping). Additionally, the leakage current maintaining an average of ~ 62 fA of the

HPA-TG device has been slightly higher than its off-state current, and the device current in

the OFF-state and the leakage current have reached the measurement range limit of the

semiconductor parameter analyzer.

After continuous electrical measurements to evaluate the stability of devices, the

HPA-TG device has shown a negligible shift while the LPA-TG device exhibited slight

negative shifts.
Figure S8. Low-temperature measurements of a typical HPA-TG MoS2 FET under the
TG mode.
a) Transfer characteristics at various temperatures from 300 K to 150 K. Inset is the Arrhenius
plots. b) Extracted SB height plots.

The low temperature electrical measurements was performed in a cryostat filled with

liquid nitrogen.

Figure S8 shows that our monolayer MoS2 FETs under the TG mode exhibited a constant

on-state current over a wide temperature range (300 K to 150 K) and this behavior is similar

to that observed previously in ballistic 2D InSe FETs and carbon nanotube transistors, which

provides strong evidence for our integrated processing to achieve ohmic contacts and

excellent encapsulated configuration.[1]

Arrhenius plots were extracted by the values of ln(ID/T3/2) versus various VTG at VDS=

0.5 V. The exact SB height (SBH) was calculated from the slope of these lines in Arrhenius

plots. Figure S9b shows the effective SBH as a function of top-gate bias for the HPA-TG

device, and the accurate SBH can be extracted at the end of the linear region (at the flat-band

voltage condition, VTG = VFB). As the VTG increased (VTG > VFB), the thermally assisted

tunneling current dominated the nonlinear behavior.

Therefore, after extracting the Schottky barrier height of ∼ 29 meV, we consider that the

formed Nitrogen plasma-assisted contact could be Ohmic-like with negligible Schottky

barrier for electron injection, thereby exhibiting channel-dominated performance.

 In addition, we conducted further evaluations to understand why negligible hysteresis

can be observed, yet the SS value cannot reach the theoretical limit of 60 mV/dec at 300 K. [2]

The findings revealed that as the temperature decreased from room temperature, the SS value

continued to decrease. Previous research has shown that in the temperature range of 100–300

K, phonon scattering dominates the characteristic mechanism in MoS2 channel, which may

led to the SS degradation.[3] Several factors influencing lattice vibrations are likely associated

with intrinsic S-vacancies in MoS2,[4] grain boundaries,[5] and lattice mismatches occurring at

the interface.[6] In addition, our processes maximized interface integrity, and only a few

interface traps are active at room temperature due to differences in activation energy under

varying trapping mechanisms.[3] Therefore, our process is not the primary reason for the

limiting SS reduction. Instead, it is determined by intrinsic factors such as material

crystallinity and context of interfacial lattice matching. To further optimize the SS value of

the device, it is essential to develop damage-free interface layer deposition methods and

consider the lattice matching between materials. Additionally, the introduction of high-k

materials replacing SiOx and gate dielectric scaling can effectively reduce the equivalent

oxide thickness (EOT) of the device to improve SS value. However, new challenges in

compatibility of 2D semiconductor process integration may arise.

Figure S9. Optoelectronic measurements under dark and different illumination
wavelengths at a fixed power density of 285 μW/cm2. The transfer characteristics of a)
HPA-TG device and b) LPA-TG device.
Figure S10. Recovery measurements after illumination. The transfer characteristics of a)
HPA-TG device and b) LPA-TG device at the corresponding test conditions.

After applying illumination, the HPA-TG device can fully recover to its initial state. The

difference shown in LPA-TG device that after applying illumination, due to the presence of

PPC effect, the transfer characteristic shifts to the left compared to the original state. Then,

the device returns to the initial state as much as possible in the repeated test after few seconds

of device relaxation.
References

[1] J. Jiang, L. Xu, C. Qiu, L.-M. Peng, Nature 2023, 616, 470.
[2] K. P. Cheung, presented at Proceedings of 2010 International Symposium on VLSI
Technology, System and Application, Hsinchu, Taiwan, 26-28 April 2010, 2010.
[3] Y. Park, H. W. Baac, J. Heo, G. Yoo, Applied Physics Letters 2016, 108.
[4] A. Di Bartolomeo, L. Genovese, F. Giubileo, L. Iemmo, G. Luongo, T. Foller, M.
Schleberger, 2D Materials 2018, 5, 015014.
[5] T. Yokoi, M. Matsuura, Y. Oshima, K. Matsunaga, Physical Review Materials 2023, 7,
053803.
[6] W. Ren, J. Chen, G. Zhang, Applied Physics Letters 2022, 121.