DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 9-10: FPGA and Verilog
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang

School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture

❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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 FIELD PROGRAMMABLE GATE ARRAY
❑ FPGA:
❑ SRAM based (volatile): most popular
❑ Flash based (non-volatile)
❑ Top 10 FPGA companies (source)
1. Xilinx AMD
2. Altera Intel
3. Lattice
4. Microchip
5. Gowin Semiconductor

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FIELD PROGRAMMABLE GATE ARRAY
I/O I/O I/O I/O

SM SM SM SM
I/O

CLB CLB CLB

SM SM SM SM
I/O

CLB CLB CLB

SM SM SM SM
I/O

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 FIELD PROGRAMMABLE GATE ARRAY

Configurable 16x1 G
LUT: GQ
Logic Block CLB Bool-function
FF

contains slices of 4
G
variables

One slice example:

16x1
F
LUT: FQ
FF
Bool-function
of 4
variables F

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 FIELD PROGRAMMABLE GATE ARRAY

Zynq UltraScale+ EV

Zynq® UltraScale+
1 CLB contains 1 slice
1 slice has 8 LUT6 and 16 FFs

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 FIELD PROGRAMMABLE GATE ARRAY

Zynq UltraScale+ EV

Zynq® UltraScale+
1 CLB contains 1 slice
1 slice has 8 LUT6 and 16 FFs

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 FIELD PROGRAMMABLE GATE ARRAY

Zynq UltraScale+ EV

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 HARDWARE DESCRIPTION LANGUAGES
❑ Hardware Description Language (HDL): a language for
describing hardware
– Efficiently code large, complex designs
• Programming at a more abstract level than schematics
– CAD tools can automatically synthesize circuits
❑ Industry standards:
– Verilog: We will use it from Lab 3
– SystemVerilog: Successor to Verilog, gaining wide adoption
– VHDL (Very High Speed Integrated Circuit HDL)

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 VERILOG
❑ Developed in the early 1980s by Gateway Design
Automation (later bought by Cadence)
❑ Supports modeling, simulation, and synthesis
– We will use a (synthesizable) subset of the language features
❑ Major language features (in contrast to software
programming languages)
– Concurrency
– Bit-level behavior
❑Versions: 1995 and revised version 2001

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 VERILOG SYNTAX
❑Verilog and SystemVerilog are case-sensitive languages,
Keywords are always in all lowercase letters.
❑Comments:
▪ A single line comment starts with //
▪ A multiple-line comment starts with /* and ends with */ and
cannot be nested

//This is a single line comment

//This is also a single line comment
/* This is multiple-line
comments */

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 VERILOG SYNTAX
❑Strings: a sequence of characters enclosed in `` ``
▪ ``Hello world!``
❑Identifiers: names of variables which can be referenced
▪ Include [a-z], [A-Z], [0-9], underscore _, $
▪ Can not start with a digit or $
▪ E.g.,:
1ab: invalid
_abc5: OK
$abba: invalid

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 VALUES
❑ Verilog signals can take 4 values
▪ 0 Logical 0, or false
▪ 1 Logical 1, or true
▪ x Unknown logical value
▪ z High impedance (Hi-Z), floating/non-connected

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 BIT VECTORS
❑ Multi-bit values are represented by bit vectors
(i.e., grouping of 1-bit signals)
– Right-most bit is always least significant
– Example
• input[7:0] byte1, byte2, byte3; /* three 8-bit inputs */
• Binary Constants
❑ Constants – 8’b00000000
4’b1001 – 8’b0xx01xx1
• Decimal Constants
Base format (b,d,h,o)
– 4’d10 ; -4’d10
Decimal number representing bit width – 32’d65536
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 OPERATORS
❑ Bitwise Boolean operators
~ NOT
& AND
^ Exclusive OR
| OR

❑ Arithmetic operators
+ Addition – Subtraction
* Multiplication / Division % Modulus
<< Shift left >> Shift right
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 VERILOG PROGRAM STRUCTURE
❑ System is a collection of modules
– Module corresponds to a single piece
of hardware
❑ Declarations
– Describe names and types of inputs
and outputs
– Describe local signals, variables,
constants, etc.
❑ Statements specify what the
module does
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 VERILOG PROGRAM STRUCTURE

module M_2_1 (input x, y, sel,

output out); Declaration
wire tx, ty;

AND and0 (x, ~sel, tx);

AND and1 (y, sel, ty); Statements
OR or0 (tx, ty, out);
endmodule

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 VERILOG HIERARCHY

A module can instantiate

other modules forming a
module hierarchy

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 VERILOG PROGRAMMING STYLES
❑ Structural
– Shows how a module is built from other modules via instance
statements
– Textual equivalent of drawing a schematic
❑ Behavioral
– Specify what a module does in high-level description
– Use procedural code (e.g., in always block) and continuous
assignment (i.e., assign) constructs to indicate what actions to take
❑ We can mix the structural and behavioral styles
in Verilog design
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 STRUCTURAL STYLE
module M_2_1 (input x, y, sel,
output out);

wire tx, ty;

AND and0 (x, ~sel, tx);

AND and1 (y, sel, ty);
OR or0 (tx, ty, out);
endmodule

❑ The order of the module instantiation does not matter Essentially describing
the schematic textually

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 CAN YOU DO IT?

module Full_Adder(X1, X2, Cin, S, Cout);

input X1, X2, Cin;
output S, Cout;
wire a1, a2, a3;

xor u1(a1,X1,X2);
and u2(a2,X1,X2);
and u3(a3,a1,Cin);
or u4(Cout,a2,a3);
xor u5(S,a1,Cin);

endmodule

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 BEHAVIORAL STYLE WITH CONTINUOUS ASSIGNMENTS

❑ An assign statement represents continuously executing

combinational logic
module MUX2_1 (input x, y, sel,
output out);

assign out = (~sel & x) | (sel & y);

endmodule
❑ Multiple continuous assignments happen in parallel; the
order does not matter

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 BEHAVIORAL STYLE COMBINATIONAL LOGIC WITH
ALWAYS BLOCK

module MUX2_1 (input x, y, sel, ❑An always block is

output out); reevaluated whenever a
reg out; signal in its sensitivity list
changes
always @(x, y, sel)
begin ❑Formed by procedural
out <= (~sel & x) | (sel & y); assignment statements
end – reg needed on the LHS of a
endmodule procedural assignment

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SEQUENTIAL LOGIC IN ALWAYS BLOCKS

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BLOCKING ASSIGNMENTS

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NONBLOCKING ASSIGNMENTS

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 ASSIGNMENTS IN VERILOG
❑ Continuous assignments apply to combinational logic only

❑ Always blocks contain a set of procedural assignments

(blocking or nonblocking)
– Can be used to model either combinational or sequential logic
– Always blocks execute concurrently with other always blocks,
instance statements, and continuous assignment statements in a
module

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 NET AND VARIABLE TYPES
❑ We will mainly use two data type classes
– wire: represents a physical connection (or net) between hardware
elements
• A stateless way of connected two elements
• Can only be used to model combinational logic
• Cannot be used in the left-hand side in an always block
– reg: similar to wires, but can be used to store information (or
state) like registers
• This is used in the behavioral style only
• Can be used to model both combinational & sequential logic
• Cannot be used in the left-hand side of a continuous assignment
statement
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 (IMPROPERLY CREATED) INFERRED LATCHES
❑ To infer combinational logic, you’re recommended to ensure that
each variable within an always block gets assigned a value (under all
possible conditions)
– Otherwise, the Verilog compiler assumes that the last value should be
used, and will create a latch

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 PROCEDURAL STATEMENTS

case (case_expression)
if(condition_1)
procedural_statement_1; case_item1: procedural_expression;
case_item2: begin procedural_statements;
else if(condition_2) end
procedural_statement_2; ....
default: expression;
else
procedural_statement_3; endcase

Note: a block of multiple statements must be grouped and be within begin and end

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 PROCEDURAL STATEMENTS

[source]
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 PROCEDURAL STATEMENTS

[source]
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 PROCEDURAL STATEMENTS

[source]
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 PROCEDURAL STATEMENTS

[source]
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 MODELLING FSM IN VERILOG

[source]
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 BEFORE NEXT CLASS

• Textbook: 3.5
• Next time: Timing Analysis

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