A B C D E

1 1

Compal Confidential
2 2

MB Schematic Document
www.laptoprepairsecrets.com
FH51M
3
LA-J871P 3

Rev:1.0
2020.02.11

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Cover Sheet
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 1 of 112
A B C D E
 A B C D E

mDP - JDP1 HDMI - JHDMI1 eDP - JEDP1 Cof f eeLake H Pr ocess or Interleaved (DDR4 2400/2666)
DDI Memory BUS
- VGA Port E - VGA Port C - CPU eDP BGA1440 (42X28) - DDR4 So-DIMM 260 pin
- Channel A

1
N18P-G61/G62 (CFL-H & CML-H _ 8+2) - BANK 0,1,2,3
- Address : 0XA0/1 P.23 1
P.39 P.40 P.38
- MAX-Q
- GDDR6 4G PEG x16
- DDR4 So-DIMM 260 pin
- Channel B
8GT/s - BANK 4,5,6,7
- Address : 0XA3/4 P.24
VBIOS ROM
P.27-37 P.6-13
- SOP8
- Size : 1M
P.29 X4 DMI

LAN(GbE) JRJ45 USB3.1 - JUSB 3 USB3.1 - JUSB 2 USB3.1 - JUSB 1 Type C - JTYPEC1
- PCIE 2.0 5GT/s - GEN2 - USB3.1 GEN2
- Port 14 - On M/B - USB3.1 Port3&4 Cannonlake PCH - H SPI ROM 16M
- Port 1 SPI
- E2600 - GEN2 - GEN2 - RTS5441E FCBGA874 (25X24) - SOP8
- USB3.1 Port 2 - USB3.1 Port 5 - W/USB Charger - Size : 16M
- USB2.0 Port 2 - USB2.0 Port 3 (SLGC55544) P.16
P.71 P.42-43
CFL-H : HM370
USB3 Re-driver USB3 Re-driver
2
- PS8713 - PS8713 CML-H : HM470 2

IO_B
P.73 LPC/eSPI BUS
P.14-21
HDD - JHDD1 SSD - JSSD3 (PCIE/SATA) SSD - JSSD2 (PCIE/SATA) SSD - JSSD1 (PCIE) TPM
HD Audio I2C - NPCT750
- SATA 3.0 P.66

www.laptoprepairsecrets.com
- Port 13
(SATA 0B)
- PCIE 2.0 5GT/s - PCIE 2.0 5GT/s - PCIE 2.0 5GT/s
P.67 - PCIE Port 17-20 - PCIE Port 9-12 - PCIE Port 21-24 EMR - JEMR1 Touch Pad
- SATA @ Port 17 P.69
- SATA @ Port 12 P.68 P.68 EC KB9022
- PCH I2C0
P.64

- EC PS2 P.58
- PCH I2C1
P.63

3
I2C/PS2 3

WIFI - JNGFF1 DDC Camera Finger print Tuch Screen Fan Control*2
page 77
- Port 5 - USB2 Port 8 - USB2 Port 6
- PCH I2C2
P.38 P.66 P.38

- PCIE1.0 2.5GT/s
- USB2 Port 4
- PCIE Port 15 P.52 Extend IC Int.KBD
HDA Codec
- I2C
- ALC295 - KC3810P.59
Sub Board
P.56
IO/B (JIO1/JIO2) P.73
- KSI/KSO
HS/B (JHS1) P.66 - W/BL or 4 Zone RGB
P.63
TURBO/B (JTURBO1) P.77 Int. Speaker Int. DMIC Audio Jack

4
RTC CKT. (JRTC1) P.20 4

Power On/Of f CKT. P.63 - ON IO/B > L - On CCD Module - On IO/B

- ON M/B > R
HW Circuit DC/DC P.78 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
Block Diagrams
Power Circuit DC/DC
P.82-111
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number
Custom
R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 2 of 112
A B C D E
 A B C D E

Vcc 3.3V +/- 5% *PCB Version SIGNAL

Ra 100K +/- 1% EC Board ID Table for AD channel *Key board type STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS
S0 (Full ON) HIGH HIGH HIGH ON ON ON
Board ID Rb Vmin Vtyp Vmax EC AD Board ID PCB Revision
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF
0 0 0.000 V 0.300 V 0x00 - 0x13 0 50 Rev0.1
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E SD034120280 1 50 Rev0.2
S5 (Soft OFF) LOW LOW LOW ON OFF OFF
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 SD034150280 2 50 Rev0.3
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 SD034200280 3 50 Rev1.0 Power Plane Description S0 S3 S4 S5
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A SD034270280 4 50 Rev0.2+RGB +RTCVCC RTC Battery Power ON ON ON ON
1 5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 SD034330280 5 50 Rev0.3+RGB +19V_VIN Adapter power supply N/A N/A N/A N/A 1

6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54 SD034430280 6 50 Rev1.0+RGB +12.6V_BATT Battery power supply N/A N/A N/A N/A

7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64 SD034560280 7 60 Rev0.1 +19VB AC or battery power rail for power circuit. N/A N/A N/A N/A

8 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 SD034750280 8 60 Rev0.2 +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON
9 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 SD034100380 9 60 Rev0.3 +5VALW +5V Always power rail ON ON ON ON
10 130K +/- 1% 1.849 V 1.865 V 1.881 V 0x88 - 0x96 SD034130380 10 60 Rev1.0 +3VALW System +3VALW always on power rail ON ON ON ON*

11 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 SD034160380 11 60 Rev0.2+RGB +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON
12 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF SD034200380 12 60 Rev0.3+RGB
13 240K +/- 1% 2.316 V 2.329 V 2.343 V 0xB0 - 0xB7 SD000001B80 13 60 Rev1.0+RGB
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF SD00000G280 14 +1.05VALW +1.05V Always power rail ON ON ON ON
15 330K +/- 1% 2.521 V 2.533 V 2.544 V 0xC0 - 0xC9 SD034330380 15 +1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF

16 430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 SD00000WM80 16 +1.05V_VCCST Sustain voltage for processor in Standby modes ON ON OFF OFF

17 560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD SD034560380 17 +5VS System +5V power rail ON OFF OFF OFF

18 750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0 SD00000AL80 18 +3VS System +3V power rail ON OFF OFF OFF

19 NC 3.000 V 3.000 V 0xF1 - 0xFF 19 +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF

+0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF OFF
Address(8bit)
+VCC_CORE Core voltage for CPU ON OFF OFF OFF
BUS Device Address(7 bit) Write Read +VCC_GT Sliced graphics power rail ON OFF OFF OFF
2 I2C_0 (+3VS) XXXXXX (EMR) +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF 2

I2C_1 (+3VS) TM-P3393-003 (Touch Pad) +VCC_SA System Agent power rail ON OFF OFF OFF
DIMM1
PCH_SMBCLK +1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF
(+3VS) DIMM2 +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF

+NVVDD1 Core voltage for VGA (merge core & core_s) ON OFF OFF OFF

+1.35VSDGPU +1.35VS power rail for GPU ON OFF OFF OFF

N18P-G0/N17P-G0-K1 (VGA) 0x9E
PCH_SML1CLK +1.0VSDGPU +1.0VS power rail for GPU ON OFF OFF OFF
(+3VALW) Thermal Sensor (NCT7718W) 1001_100xb 1001_1001b 1001_1000b +1.8VALW System +1.8VALW always on power rail ON ON ON ON*
EC_SMB_CK2 Thermal Sensor (G781) 1001_101xb 1001_1011b 1001_1010b
(+3VS)
EC_SMB_CK1
(+3VLP)
PCH
BQ24780 (Charger IC)
BATTERY PACK
www.laptoprepairsecrets.com
0x90
0x12
0x16 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

LED driver 0xC0

EC_SMB_CK3
(+3VALW)

KC3810 0xC0

3
Item (X43 / X76) BOM Structure Item (X43 / X76) BOM Structure 3
43 Level Descript i on BOM Structure
Unpop @ eDP-TS USB TS_USB@
Connector CONN@ eDP-TS USB NONTS_I2C@ V PCB@/H82@/SATANRD@/CMLi5@/CMLPCH@/VGA@/N18P@/VGAG61@/TS_USB@/NONTS_I2C@/DP@/IOAC@/CNVI@/FP@/PBA@/KBLED@/LED14P@/WC18V@/TMS/@TPM@
V 431AMBBOL02 FH51M PG61QS 4G
PCB PCB@ eDP-TS I2C TS_I2C@
UMA Only(Reserved) UMA@ mDP DP@ V
H62 CPU(Reserved) H62@ For Acer IOAC IOAC@ V
H82 CPU(POP) H82@ V No Acer IOAC NIOAC@
CFL i5QS CPU CFLi5QS@ Intel CNVi CNVI@ V
CFL i5 CPU CFLi5@ FOR UART BT moduleUART_BT@
CFL QS PCH CFLPCHQS@ FOR UART debug UART@
Extend GPIO KC3810@
CML i5QS CPU CMLi5QS@
CML i7QS CPU CMLi7QS@ Finger Print FP@ V
CML i9QS CPU CMLi9QS@ FinerPrint(with PBA) PBA@ V
CML QS PCH Remove KBLED@
CML i5 CPU CMLi5@ KB LED driver LED14P@
CML i7 CPU CMLi7@ EMR 1.8V WC18V@ Item (X4E) BOM Structure Item (X76) BOM Structure
4 CML i9 CPU EMR 3.3V WC33V@ EMI requirement EMI@ V OVRM-uPI uPI_X76@ X76869BOL01 - MICRON 4

CML PCH CMLPCH@ Thermal sensor TMS@ V EMI require reserve XEMI@ OVRM-ON ON_X76@ X76869BOL02 - SAMSUNG
TPM pop TPM@ ESD requirement ESD@ V VRAM-SAMSUNG X76SAM@ X76869BOL03 - ON OVRM
TPM non-pop NTPM@ V ESD require reserve XESD@ VRAM-MICRON X76MIC@ X76869BOL04 - UPI OVRM
dGPU circuit VGA@ V SSD3 pop SSD3@ FP ESD requirement FPESD@ V
N17P GPU N17P@ Security Classification Compal Secret Data
Compal Electronics, Inc.
N18P GPU N18P@ V Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
Notes List
N18P-G61 VGAG61@ PVT PVT@ X4EAMBBOL01 PG6162 FOR EE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev

N18P-G62 MP2 VGAG62@ PVT W/RGB PVTRGB@ X4EP4MBOL01 PG6162 IO FOR EE FH51M M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 3 of 112
A B C D E
 5 4 3 2 1

DC_IN
PL101,2,3
PJP101
+19V_VIN
AC CONN. +2.5VP JDIMM1
+12.6V_BATT +12.6V_BATT+ PU2501 PJ2502
+2.5V
DDR4 Conn.
PL201,2 BATTERY +1.0VSDGPUP
JDIMM2

PJP201 PU1002 PJ1003

+1.0VSDGPU
GPU
D IMVP8 D

+19VB_CPU
PUZ2,3,4,5 +VCC_CORE
CPU +3VS
PUB1 +19VB PLZ1,2,3,4 UQ1 JPQ1
UO1
+3VS
SATA Re-driver
EN:DRVON
R19
+3VALW_TPM U5 TPM
UV45
+3VSDGPU
GPU
+19VB_CPU UM1
+3VS_WLAN JNGFF1 WLAN CARD Conn.
RM11
+3VS_WLAN JNGFF1 WLAN CARD Conn.
CHARGER +19VB PRG5 PLG1 +VCC_GT
CPU UL1
+3V_LAN UL2 LAN
EN:DRVON R20
+3VS_TPM U5 TPM
UK1
+3V_PTP JTP1 TP Conn.
UX1
+LCDVDD JEDP1 PANEL
+19VB_CPU UM2 RM54
+3VS_SSD1 JSSD1 SSD Conn. +3VS_DVDDIO
PRA3 RA2 CODEC
+19VB PLA1 +VCC_SA
CPU UM2 RM55
+3VS_SSD2 JSSD2 SSD Conn. +3VS_DVDD
EN:DRVON RA4 CODEC
RH101
+3VALW_HDA
PCH
+3VALWP
EN:3V_EN
PJ302 +3VALW RH99
+3VALW_DSW
PCH
+19VB PU301
EC,LID+3VLP UK2
+FP_VCC JFP1 FP Conn.
C C

+1.2VP CPU,Memory JPH1

+1.05VALW_PRIM
PCH
EN:SYSON +1.2V_VDDQ +1.2V_VCCPLL_OC
PJM2 RC24 CPU
+19VB RH94
+1.05VALW_PCH
PCH
PUM1 EN:SM_PG_CTRL RH102
+1.05VALW_VCCAZPLL
+0.6VSP +1.05VALW_VCCAMPHYPLL
RH103
PCH
PJM3 +0.6VS_VTT RH105
+1.05VALW_XTAL

+19VB
PU1101
EN:+1.8_PG
+1.05VALWP

PJ1101 www.laptoprepairsecrets.com
+1.05VALW UQ2

UC4
RQ5
+1.05V_VCCST

+1.05VS_VCCSTG
CPU

EN:DGPU_PWR_EN
+1.0VS_VCCIOP
+1.8VSDGPU_AON +FP_FUSE_GPU GPU
CPU UV48

+19VB PUH1 PJH1 +VCCIO

+1.8VSDGPU_MAIN GPU
EN:SUSP# UG27

B UQ2 RQ9
+1.8VS RA3
+1.8VS_VDDA CODEC B
+1.8VALWP

+19VB PU1801 PJ1801 +1.8VALW RH100 +1.8VALW _PRIM PCH

EN:SPOK_3V
+5VALW_MUX
RS127 US3 CC logic/U3 MUX
+5VALWP
PU501 JIO1
+5VALW JIO1 IO/B Conn.
+19VB PJ502 +5VALW
US11
+USB3_VCCC JTYPEC1 Type-C Conn.

US12
+USB_VCCA JUSB1 USB3.0 Conn. RF4
+VCC_FAN1 JFAN1 FAN1 Conn.

NVVDD_B+ US13
+USB_VCCB JUSB2 USB3.0 Conn. RF7
+VCC_FAN2 JFAN1 FAN2 Conn.
+19VB
GPU
PUV1 PUV2,3 PLV2,3 +NVVDD1 +5V_LEDPWR
KB BackLight Conn. +VDDA
UE5 JBL2
JPA1 UA1 CODEC
UK2
+FP_VCC JFP1 FP Conn. U4
+5VS_BL JBL1 KB BackLight Conn.
+5VS
EN:1.35VSDGPU_EN UQ1 JPQ2
RO4
+5VS_HDD JHDD1 HDD Conn.
+19VB
GPU_B+ GPU
A +1.35VSDGPU UY2
+HDMI_5V_OUT JHDMI1 HDMI Conn. A

PUW1 PLW1
+TS_PWR
RX7 JEDP1 Touch Screen

+19VB → +19VB_CPU
LX1 +INVPWR_B+
PANEL

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS
SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 4 of 112
5 4 3 2 1
 A B C D E
DH5VF_EVT Power Sequence AC mode
BIOS ver: V0.02W1
EC: ver: V002AT04

1 1

Plug in Power On S3 S3 Resume Power Off

+3VLP
+3VLP
EC_ON
→
330.8ms
EC_ON
+5VALW
+5VALW → 333.3ms
ON/OFFBTN#
ON/OFFBTN#
→ 92.03ms
+3VALW +3VALW

→ 293.7us
→ 94.88ms
+1.05VALW +1.05VALW

EC_RSMRST# → 29.19ms
EC_RSMRST#
20.1ms
2.439ms → ←→
PBTN_OUT# PBTN_OUT#

→
174.6ms 19.18ms
PM_SLP_S4# PM_SLP_S4#

→
19.22ms 100.5us
PM_SLP_S3# PM_SLP_S3#

2 SYSON → 72.1us → 152.8us

SYSON 2

→ →
275.9us 88.37us
+1.05V_VCCST +1.05V_VCCST

→ →
692.9us 367.6us
+1.2V_VDDQ +1.2V_VDDQ

+2.5VS
→ 910.1us → 2.266ms
+2.5VS

SUSP#
→ 12.7ms
→ 13.01us
→ 67.04ms
→ 13us
SUSP#

→ → → →
8.378us 55.47us 8.502us 68.53us
+1.05VS_VCCSTG +1.05VS_VCCSTG

→ → → →
877.7us 618.5us 906.0us 686.0us
+5VS +5VS

www.laptoprepairsecrets.com → → →
630.4us 8.679ms 656.1us 11.65ms
+3VS +3VS

+1.8VS → 412us → 347.6us

→ 424.9us 446.2us
+1.8VS

EC_VCCST_PG → 25.34ms → 0us

→ 25.25ms 0us
EC_VCCST_PG

SM_PG_CTRL → 25.35ms → 0us

→ 25.25ms
→ 13.97ms
SM_PG_CTRL

+0.6VS_VTT → 25.36ms
→ 3.819ms
→ 25.26ms
→ 2.034ms
+0.6VS_VTT

VR_ON → 25.19ms
→ 26.91us
→ 25.59ms
→ 27.06us VR_ON

+VCC_SA → 1.759ms
→ 51.25us
→ 1.757ms
→ 48.00us +VCC_SA

3 +VCC_CORE → 173.0ms
→ 87.75us
→ 167.1ms
→ 112.0us +VCC_CORE 3

+VCC_GT → NA
→ NA
→ NA NA
+VCC_GT

PCH_PWROK → 12.42ms
→ 47.39us
→ 12.18ms
→ 47.83us
PCH_PWROK

SYS_PWROK → 150.3ms
→ 61.95us
→ 150.6ms
→ 62.37us
SYS_PWROK

PLT_RST# → 152.3ms
→ 318.7us
→ 151.8ms
PLT_RST#

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size
Power Sequence
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 5 of 112
A B C D E
 A B C D E

Coffee Lake-H Comet Lake-H

- Re-fresh R0 stepping
UC1 UC5 UC1 UC6

CFLi5QS@ CFLi5@ CMLi5QS@ CMLi5@

S IC CL8068404121905 QRR5 U0 2.4G FCBGA S IC CL8068404121905 SRF6X U0 2.4G S IC CL8070104398806 QTJ1 R0 2.1G 1440 S S IC CL8070104399510 SRH84 R1 2.5G
SA0000COG00 SA0000COG40 SA0000D3I10 SA0000DCP40
UH1 UC1 UC8

1 CFLPCHQS@ CMLi7QS@ CMLi7@ 1

S IC FHHM370 QNYF B0 BGA 874P PCH- S IC CL8070104398908 QTJ2 R0 2.4G 1440 S S IC CL8070104399510 SRH84 R1 2.5G
SA0000BPF10 SA0000D3N10 SA0000DCP40
UC1

CMLi9QS@
S IC CL8070104399007 QTJ0 R0 2.8G S
SA0000D3G10
UH1

CMLPCH@
S IC FH82HM470 SRJAU A0 FCBGA PCH-H
SA0000DDP80

CFL-H
@ UC1D

K36 D29 EDP_TXP0

DDI1_TXP_0 EDP_TXP_0 EDP_TXN0 EDP_TXP0 <38>
K37 E29
DDI1_TXN_0 EDP_TXN_0 EDP_TXP1 EDP_TXN0 <38>
2 J35 F28 2
DDI1_TXP_1 EDP_TXP_1 EDP_TXN1 EDP_TXP1 <38>
J34 E28
H37 DDI1_TXN_1 EDP_TXN_1 A29 EDP_TXP2 EDP_TXN1 <38>
H36 DDI1_TXP_2
DDI1_TXN_2
EDP_TXP_2
EDP_TXN_2
B29 EDP_TXN2 EDP_TXP2 <38>
EDP_TXN2 <38>
eDP
J37 C28 EDP_TXP3
DDI1_TXP_3 EDP_TXP_3 EDP_TXN3 EDP_TXP3 <38>
J38 B28
DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <38>
D27 C26 EDP_AUXP
DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <38>
E27 B26
DDI1_AUXN EDP_AUXN EDP_AUXN <38>
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 +VCCIO
DDI2_TXP_1 EDP_DISP_UTIL

www.laptoprepairsecrets.com
G38
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 DP_RCOMP RC1 1 2 24.9_0402_1%
E37 DDI2_TXN_2 DISP_RCOMP
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
DDI2_TXN_3 Max Trace Length: 600 mil

F26
E26 DDI2_AUXP
DDI2_AUXN
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
3 C33 DDI3_TXN_2 3
B33 DDI3_TXP_3
DDI3_TXN_3 G27 CPU_DISPA_BCLK_R
PROC_AUDIO_CLK CPU_DISPA_SDO_R CPU_DISPA_BCLK_R <18>
A27 G25 CPU_DISPA_SDO_R <18>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI RC2 2 1 20_0402_5% CPU_DISPA_SDI_R
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 CPU_DISPA_SDI_R <18>

CFL-H_BGA1440 20191024
- SDI 20 ohm close to CPU
- BCLK/SDO 30 ohm close to PCH

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
CFL-H(1/8)DDI/eDP
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 6 of 112
A B C D E
 A B C D E

CHANNEL-A Interleaved Memory

CFL-H
@UC1A

DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <23>
BT6 AG2 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <23>
BR3 AK1
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK#1 <23>
BN5 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23>
BL2 AT2 DDR_A_CKE1 <23>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23>
BK2 AE2 DDR_A_CS#1 <23>
DDR_A_D16 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23>
BG2 AE4 DDR_A_ODT1 <23>
DDR_A_D21 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23>
BD1 AH1 DDR_A_BA1 <23>
DDR_A_D26 BC4 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AU1 DDR_A_BG0
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_WE# DDR_A_MA16_RAS# <23>
BD4 AG4 DDR_A_MA14_WE# <23>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15_CAS#
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <23>
AB2 AP4
DDR_A_D34 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 DDR_A_MA2 DDR_A_MA1 <23>
AA4 AN4 DDR_A_MA2 <23>
DDR_A_D35 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3
DDR_A_D36 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR_A_MA4 DDR_A_MA3 <23>
AB5 AP2 DDR_A_MA4 <23>
DDR_A_D37 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5
DDR_A_D38 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR_A_MA6 DDR_A_MA5 <23>
AA2 AP3
DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <23>
AA1 AN1 DDR_A_MA7 <23>
DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7

www.laptoprepairsecrets.com
DDR_A_D40 V5 AN3 DDR_A_MA8
DDR_A_D41 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA9 DDR_A_MA8 <23>
V2 AT4 DDR_A_MA9 <23>
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10
DDR_A_D43 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA11 DDR_A_MA10 <23>
U2 AN2 DDR_A_MA11 <23>
DDR_A_D44 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12
DDR_A_D45 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR_A_MA13 DDR_A_MA12 <23>
V4 AE3
DDR_A_D46 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 DDR_A_BG1 DDR_A_MA13 <23>
U5 AU2 DDR_A_BG1 <23>
DDR_A_D47 U4 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 AU3 DDR_A_ACT#
DDR_A_D48 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23>
R2
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <23>
R4 AU5
DDR_A_D51 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <23>
P4
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <23>
R1 BL3 DDR_A_DQS#1 <23>
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2
3 DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#3 DDR_A_DQS#2 <23> 3
M4 BD3 DDR_A_DQS#3 <23>
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4
DDR_A_D58 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR_A_DQS#5 DDR_A_DQS#4 <23>
L4 U3 DDR_A_DQS#5 <23>
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6
DDR_A_D60 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR_A_DQS#7 DDR_A_DQS#6 <23>
M5 L3
DDR_A_D61 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_A_DQS#7 <23>
M2
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <23>
L1 BK3
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS2 DDR_A_DQS1 <23>
BF3
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS3 DDR_A_DQS2 <23>
LP3/DDR4 BC3
DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS4 DDR_A_DQS3 <23>
BA2 AB3 DDR_A_DQS4 <23>
BA1 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_A_DQS5
NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR_A_DQS6 DDR_A_DQS5 <23>
AY4 R3
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS7 DDR_A_DQS6 <23>
AY5 M3 DDR_A_DQS7 <23>
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3
AY2 NC/DDR0_ECC_6 1 OFDDR0_DQSN_8/DDR0_DQSN_8
13 For ECC DIMM
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL CFL-H(2/8)DIMMA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 7 of 112
A B C D E
 A B C D E

CHANNEL-B Interleaved Memory

CFL-H
@ UC1B
<24> DDR_B_D[0..63] DDR CHANNEL B
1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <24>
BR11 AN9 DDR_B_CLK#0 <24>
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1
DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <24>
BR8 AM8
DDR_B_D4 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK#1 <24>
BP11 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_B_D10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <24>
BL8 AT10 DDR_B_CKE1 <24>
DDR_B_D11 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <24>
BJ7 AE7 DDR_B_CS#1 <24>
DDR_B_D16 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <24>
BF11 AE8 DDR_B_ODT1 <24>
DDR_B_D21 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14_WE# DDR_B_MA16_RAS# <24>
BC11 AH11 DDR_B_MA14_WE# <24>
DDR_B_D26 BB8 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 AF8 DDR_B_MA15_CAS#
DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <24>
2 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <24>
BB10 AH9 DDR_B_BA1 <24>
DDR_B_D30 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9 DDR_B_BG0
DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <24>
AA10 AK6
DDR_B_D34 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA2 DDR_B_MA1 <24>
AC11 AK5 DDR_B_MA2 <24>
DDR_B_D35 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_B_D36 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 DDR_B_MA4 DDR_B_MA3 <24>
AA7 AL6 DDR_B_MA4 <24>
DDR_B_D37 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_B_D38 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA6 DDR_B_MA5 <24>
AC8 AN7
DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <24>
AC7 AN10 DDR_B_MA7 <24>
DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7

www.laptoprepairsecrets.com
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
W8
W7
V10
V11
W11
W10
DDR4(IL)/LP3-DDR4(NIL)
DDR1_DQ_40/DDR1_DQ_24
DDR1_DQ_41/DDR1_DQ_25
DDR1_DQ_42/DDR1_DQ_26
DDR1_DQ_43/DDR1_DQ_27
DDR1_DQ_44/DDR1_DQ_28
DDR1_DQ_45/DDR1_DQ_29
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13
AN8
AR11
AH7
AN11
AR10
AF9
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_MA8 <24>
DDR_B_MA9 <24>
DDR_B_MA10 <24>
DDR_B_MA11 <24>
DDR_B_MA12 <24>
DDR_B_MA13 <24>
V7 AR7
DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <24>
V8 AT9 DDR_B_ACT# <24>
DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT#
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_ALERT# DDR_B_PAR <24>
P7 AR8 DDR_B_ALERT# <24>
DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT#
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#1 DDR_B_DQS#0 <24>
R7 BL9
3 DDR_B_D55 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR_B_DQS#2 DDR_B_DQS#1 <24> 3
P8 BG9 DDR_B_DQS#2 <24>
DDR_B_D56 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_B_DQS#3
DDR_B_D57 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR_B_DQS#4 DDR_B_DQS#3 <24>
M11 AC9
DDR_B_D58 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS#5 DDR_B_DQS#4 <24>
L7 W9 DDR_B_DQS#5 <24>
DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
DDR_B_D60 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS#7 DDR_B_DQS#6 <24>
L10 M9 DDR_B_DQS#7 <24>
DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS1 DDR_B_DQS0 <24>
L8 BJ9
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR_B_DQS2 DDR_B_DQS1 <24>
BF9
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS3 DDR_B_DQS2 <24>
AW11 LP3/DDR4 BB9 DDR_B_DQS3 <24>
AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS5 DDR_B_DQS4 <24>
AY8 V9 DDR_B_DQS5 <24>
AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS7 DDR_B_DQS6 <24>
AY10 L9
NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <24>
AW10
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 For ECC DIMM

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
CFL-H_BGA1440
4 Trace Width/Space: 15 mil/ 25 mil 4
Max Trace Length: 500 mil

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(3/8)DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 8 of 112
A B C D E
 A B C D E

PEG&DMI
To DGPU
1 To DGPU PEG Lane Reversed 1

PEG Lane Reversed CFL-H

UC1C
CC1 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K 2 1VGA@ CC2
<27> PEG_CRX_C_GTX_P15 PEG_CRX_GTX_N15 PEG_RXP_0 PEG_TXP_0 PEG_CTX_GRX_N15 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P15 <27>
<27> PEG_CRX_C_GTX_N15 CC3 VGA@ 1 2 0.22U_0201_6.3V6K D25 A25 2 1VGA@ CC4
PEG_RXN_0 PEG_TXN_0 PEG_CTX_C_GRX_N15 <27>
CC5 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P14 E24 B24 PEG_CTX_GRX_P14 0.22U_0201_6.3V6K 2 1VGA@ CC11
<27> PEG_CRX_C_GTX_P14 PEG_CRX_GTX_N14 PEG_RXP_1 PEG_TXP_1 PEG_CTX_GRX_N14 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P14 <27>
<27> PEG_CRX_C_GTX_N14 CC6 VGA@ 1 2 0.22U_0201_6.3V6K F24 C24 2 1VGA@ CC12
PEG_RXN_1 PEG_TXN_1 PEG_CTX_C_GRX_N14 <27>
CC7 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P13 E23 B23 PEG_CTX_GRX_P13 0.22U_0201_6.3V6K 2 1VGA@ CC13
<27> PEG_CRX_C_GTX_P13 PEG_CRX_GTX_N13 PEG_RXP_2 PEG_TXP_2 PEG_CTX_GRX_N13 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P13 <27>
<27> PEG_CRX_C_GTX_N13 CC14 VGA@ 1 2 0.22U_0201_6.3V6K D23 A23 2 1VGA@ CC15
PEG_RXN_2 PEG_TXN_2 PEG_CTX_C_GRX_N13 <27>
CC16 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P12 E22 B22 PEG_CTX_GRX_P12 0.22U_0201_6.3V6K 2 1VGA@ CC8
<27> PEG_CRX_C_GTX_P12 PEG_CRX_GTX_N12 PEG_RXP_3 PEG_TXP_3 PEG_CTX_GRX_N12 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P12 <27>
<27> PEG_CRX_C_GTX_N12 CC17 VGA@ 1 2 0.22U_0201_6.3V6K F22 C22 2 1VGA@ CC18
PEG_RXN_3 PEG_TXN_3 PEG_CTX_C_GRX_N12 <27>
CC19 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P11 E21 B21 PEG_CTX_GRX_P11 0.22U_0201_6.3V6K 2 1VGA@ CC9
<27> PEG_CRX_C_GTX_P11 PEG_CRX_GTX_N11 PEG_RXP_4 PEG_TXP_4 PEG_CTX_GRX_N11 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P11 <27>
<27> PEG_CRX_C_GTX_N11 CC20 VGA@ 1 2 0.22U_0201_6.3V6K D21 A21 2 1VGA@ CC21
PEG_RXN_4 PEG_TXN_4 PEG_CTX_C_GRX_N11 <27>
CC10 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P10 E20 B20 PEG_CTX_GRX_P10 0.22U_0201_6.3V6K 2 1VGA@ CC22
<27> PEG_CRX_C_GTX_P10 PEG_CRX_GTX_N10 PEG_RXP_5 PEG_TXP_5 PEG_CTX_GRX_N10 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P10 <27>
<27> PEG_CRX_C_GTX_N10 CC23 VGA@ 1 2 0.22U_0201_6.3V6K F20 C20 2 1VGA@ CC24
PEG_RXN_5 PEG_TXN_5 PEG_CTX_C_GRX_N10 <27>
CC25 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P9 E19 B19 PEG_CTX_GRX_P9 0.22U_0201_6.3V6K 2 1VGA@ CC26
<27> PEG_CRX_C_GTX_P9 PEG_CRX_GTX_N9 PEG_RXP_6 PEG_TXP_6 PEG_CTX_GRX_N9 PEG_CTX_C_GRX_P9 <27>
<27> PEG_CRX_C_GTX_N9 CC27 VGA@ 1 2 0.22U_0201_6.3V6K D19 A19 0.22U_0201_6.3V6K 2 1VGA@ CC28
PEG_RXN_6 PEG_TXN_6 PEG_CTX_C_GRX_N9 <27>
CC29 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P8 E18 B18 PEG_CTX_GRX_P8 0.22U_0201_6.3V6K 2 1VGA@ CC30
<27> PEG_CRX_C_GTX_P8 PEG_CRX_GTX_N8 PEG_RXP_7 PEG_TXP_7 PEG_CTX_GRX_N8 PEG_CTX_C_GRX_P8 <27>
<27> PEG_CRX_C_GTX_N8 CC31 VGA@ 1 2 0.22U_0201_6.3V6K F18 C18 0.22U_0201_6.3V6K 2 1VGA@ CC32
PEG_RXN_7 PEG_TXN_7 PEG_CTX_C_GRX_N8 <27>
CC33 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 0.22U_0201_6.3V6K 2 1VGA@ CC34
<27> PEG_CRX_C_GTX_P7 PEG_CRX_GTX_N7 PEG_RXP_8 PEG_TXP_8 PEG_CTX_GRX_N7 PEG_CTX_C_GRX_P7 <27>
2 CC35 VGA@ 1 2 0.22U_0201_6.3V6K E17 B17 0.22U_0201_6.3V6K 2 1VGA@ CC36 2
<27> PEG_CRX_C_GTX_N7 PEG_RXN_8 PEG_TXN_8 PEG_CTX_C_GRX_N7 <27>
CC37 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 0.22U_0201_6.3V6K 2 1VGA@ CC38
<27> PEG_CRX_C_GTX_P6 PEG_CRX_GTX_N6 PEG_RXP_9 PEG_TXP_9 PEG_CTX_GRX_N6 PEG_CTX_C_GRX_P6 <27>
<27> PEG_CRX_C_GTX_N6 CC39 VGA@ 1 2 0.22U_0201_6.3V6K E16 B16 0.22U_0201_6.3V6K 2 1VGA@ CC40
PEG_RXN_9 PEG_TXN_9 PEG_CTX_C_GRX_N6 <27>
CC41 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P5 D15 A15 PEG_CTX_GRX_P5 0.22U_0201_6.3V6K 2 1VGA@ CC42
<27> PEG_CRX_C_GTX_P5 PEG_CRX_GTX_N5 PEG_RXP_10 PEG_TXP_10 PEG_CTX_GRX_N5 PEG_CTX_C_GRX_P5 <27>
<27> PEG_CRX_C_GTX_N5 CC43 VGA@ 1 2 0.22U_0201_6.3V6K E15 B15 0.22U_0201_6.3V6K 2 1VGA@ CC44
PEG_RXN_10 PEG_TXN_10 PEG_CTX_C_GRX_N5 <27>
CC45 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P4 F14 C14 PEG_CTX_GRX_P4 0.22U_0201_6.3V6K 2 1VGA@ CC46
<27> PEG_CRX_C_GTX_P4 PEG_CRX_GTX_N4 PEG_RXP_11 PEG_TXP_11 PEG_CTX_GRX_N4 PEG_CTX_C_GRX_P4 <27>
<27> PEG_CRX_C_GTX_N4 CC47 VGA@ 1 2 0.22U_0201_6.3V6K E14 B14 0.22U_0201_6.3V6K 2 1VGA@ CC48
PEG_RXN_11 PEG_TXN_11 PEG_CTX_C_GRX_N4 <27>
CC49 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P3 D13 A13 PEG_CTX_GRX_P3 0.22U_0201_6.3V6K 2 1VGA@ CC50
<27> PEG_CRX_C_GTX_P3 PEG_CRX_GTX_N3 PEG_RXP_12 PEG_TXP_12 PEG_CTX_GRX_N3 PEG_CTX_C_GRX_P3 <27>
<27> PEG_CRX_C_GTX_N3 CC51 VGA@ 1 2 0.22U_0201_6.3V6K E13 B13 0.22U_0201_6.3V6K 2 1VGA@ CC52
PEG_RXN_12 PEG_TXN_12 PEG_CTX_C_GRX_N3 <27>

<27> PEG_CRX_C_GTX_P2
<27> PEG_CRX_C_GTX_N2

<27> PEG_CRX_C_GTX_P1
<27> PEG_CRX_C_GTX_N1
CC53 VGA@ 1
CC55 VGA@ 1

CC57 VGA@ 1
CC59 VGA@ 1
www.laptoprepairsecrets.com
2 0.22U_0201_6.3V6K
2 0.22U_0201_6.3V6K

2 0.22U_0201_6.3V6K
2 0.22U_0201_6.3V6K
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P0
F12
E12

D11
E11
PEG_RXP_13
PEG_RXN_13

PEG_RXP_14
PEG_RXN_14
PEG_TXP_13
PEG_TXN_13

PEG_TXP_14
PEG_TXN_14
C12
B12

A11
B11
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_P0
0.22U_0201_6.3V6K
0.22U_0201_6.3V6K

0.22U_0201_6.3V6K
0.22U_0201_6.3V6K
2
2

2
2
1VGA@ CC54
1VGA@ CC56

1VGA@ CC58
1VGA@ CC60
PEG_CTX_C_GRX_P2 <27>
PEG_CTX_C_GRX_N2 <27>

PEG_CTX_C_GRX_P1 <27>
PEG_CTX_C_GRX_N1 <27>

<27> PEG_CRX_C_GTX_P0 CC61 VGA@ 1 2 0.22U_0201_6.3V6K F10 C10 0.22U_0201_6.3V6K 2 1VGA@ CC62
PEG_CRX_GTX_N0 PEG_RXP_15 PEG_TXP_15 B10 PEG_CTX_GRX_N0 PEG_CTX_C_GRX_P0 <27>
<27> PEG_CRX_C_GTX_N0 CC63 VGA@ 1 2 0.22U_0201_6.3V6K E10 0.22U_0201_6.3V6K 2 1VGA@ CC64
PEG_RXN_15 PEG_TXN_15 PEG_CTX_C_GRX_N0 <27>
+VCCIO
RC6 1 2 24.9_0402_1% PEG_RCOMP G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<14> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <14>
<14> DMI_CRX_PTX_N0
E8 A8 DMI_CTX_PRX_N0 <14>
DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<14> DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 <14>
F6 B6
<14> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 <14>
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
To PCH
<14> DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 <14>
E5 A5
<14> DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 <14>
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<14> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <14>
<14> DMI_CRX_PTX_N3
J9 B4 DMI_CTX_PRX_N3 <14>
DMI_RXN_3 DMI_TXN_3
CFL-H_BGA1440
@

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PEG/DMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 9 of 112
A B C D E
 A B C D E

571391_CFL_H_PDG_Rev0p5 CFL-H
1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch). UC1E
2. Route the Alert signal between the Clock and the Data signals.
3. Place those resistors close CPU side.
PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%
<15> PCH_CPU_BCLK_P PCH_CPU_BCLK_N BCLKP CFG_0
A32 BN27 CFG2 RC8 1 2 1K_0402_5%
<15> PCH_CPU_BCLK_N BCLKN CFG_1 BN26 CFG2 CFG4 RC9 1 2 1K_0402_5%
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG5 RC10 1 @ 2 1K_0402_5%
<15> PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCI_BCLKP CFG_3
C36 BR20 CFG4 CFG6 RC11 1 @ 2 1K_0402_5%
<15> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG_4 BM20 CFG5 CFG7 RC12 1 @ 2 1K_0402_5%
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
<15> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLK24P CFG_6
D31 BP20 CFG7
<15> PCH_CPU_24M_CLK_N CLK24N CFG_7 BR23
CFG_8 BR22
1 CFG_9 1
BT23 The CFG signals have a default value of '1' if not terminated on the board.
CFG_10 BT22 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
CFG_11 BM19 * 1 = (Default) Normal Operation;
CFG_12 BR19 0 = Stall.
Sensitive CFG_13 BP19 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
CPU_SVID_ALERT# BH31 CFG_14 BT19 1 = Normal operation
CPU_SVID_CLK_R BH32 VIDALERT# CFG_15 * 0 = Lane numbers reversed.
<91> CPU_SVID_CLK_R CPU_SVID_DAT_R VIDSCK
BH29 BN23 CFG[4]: eDP enable:
H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 1 = Disabled.
PROCHOT# CFG_16 BP22 * 0 = Enabled.
DDR_PG_CTRL BT13 CFG_19 BN22 CFG[6:5]: PCI Express* Bifurcation:
DDR_VTT_CNTL CFG_18 00 = 1 x8, 2 x4 PCI Express*
01 = reserved
XDP_BPM#0 10 = 2 x8 PCI Express*
BR27 TC1 @ 11 = 1 x16 PCI Express*
BPM#_0 BT27 XDP_BPM#1 *
Sensitive BPM#_1 TC2 @
BM31 XDP_BPM#2 CFG[7]: PEG Training:
BPM#_2 TC3 @
EC_VCCST_PG H13 BT30 XDP_BPM#3 * 1 = (default) PEG Train immediately following RESET# de assertion.
VCCST_PWRGD BPM#_3 TC4 @ 0 = PEG Wait for BIOS for training.
H_CPUPWRGD BT31
<18> H_CPUPWRGD H_PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
BP35 BT28 *CFG Pin Use CMC debug on DDX03 R02 Schematic.
<17> H_PLTRST_CPU# H_PM_SYNC_R RESET# PROC_TDO CPU_XDP_TDI CPU_XDP_TDO <18>
<17> H_PM_SYNC_R
BM34 BL32
H_PM_DOWN PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <18>
BP31 BP28
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCK0 CPU_XDP_TMS <18>
BT34 BR28
<17,58> H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 <18>
RC17 1 @ 2 0_0402_5% J31 To be confirm
<17> PCH_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
BR33 PROC_TRST# BL30 XDP_PREQ# CPU_XDP_TRST# <21>
@ TC5 SKTOCC# TC19 @
20191024 BN1 SKTOCC# PROC_PREQ# BP27 XDP_PRDY#
PROC_SELECT# PROC_PRDY# TC20 @
PROC_SELECT#
2
> should be unconnected on CFL/CML processor @ TC6 CATERR# BM30 2
CATERR# BT25 CFG_RCOMP 1 RC18 2 49.9_0402_1% XDP_PREQ#
AT13 CFG_RCOMP XDP_PRDY# XDP_PREQ# <21>
XESD@ AW13 ZVM# Trace Width/Space: 4 mil/ 12 mil XDP_PRDY# <21>
0.1U_0201_10V6K 1 2 CC65 H_CPUPWRGD MSM# Max Trace Length: 600 mil
AU13
ESD@ AY13 RSVD1 *20191024
1000P_0402_50V7K 1 2 CC66 H_PROCHOT#_R RSVD2 - CML RCP/PDG/Check list , PROC_TDO PU 100 ohm to VCCXT
5 OF 13 *20191104
XESD@ +1.05VS_VCCSTG - CMC@ change to always pop (RC76/77/78/79)
0.1U_0201_10V6K 1 2 CC67 H_THERMTRIP# CFL-H_BGA1440
@ Place to CPU side
ESD@ RC76 2 1 51_0402_5% CPU_XDP_TMS

www.laptoprepairsecrets.com
1000P_0402_50V7K 1 2 CC68 EC_VCCST_PG
+1.2V_VDDQ CPU_XDP_TDI
RC77 2 1 51_0402_5%

RC78 2 1 51_0402_5% CPU_XDP_TDO

Near CPU side CC69 +3VS
8/21 follow 1050 Request 0.1U_0201_10V6K
2 1 Place to CPU side
CPU_XDP_TCK0

1
RC79 2 1 51_0402_5%
+1.05V_VCCST RC23
RH1 1 2 1K_0402_5% H_THERMTRIP# 330K_0402_5% RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
PCH_JTAG_TCK1 <18>
5

1
UC3
RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#

2
Vcc
DDR_PG_CTRL 2 NC 4
A Y SM_PG_CTRL <88>
8/21 PU 330K follow CRB
G

3 +1.05VS_VCCSTG 3
74AUP1G07SE-7_SOT353-5
3
1

RC21
1K_0402_5%
2

RC14 1 2 499_0402_1% H_PROCHOT#_R

<58,85> H_PROCHOT# SVID
+1.05V_VCCST
+1.05V_VCCST
1

RC22
1K_0402_5%
RC19 RC20
56_0402_1% 100_0402_1%
2

RC15 1 2 60.4_0402_1% EC_VCCST_PG

<58,78> EC_VCCST_PG_R

RC16 1 2 20_0402_5% H_PM_DOWN RC13 1 2 220_0402_5% CPU_SVID_ALERT#

<17> H_PM_DOWN_R <91> CPU_SVID_ALERT#_R

4 4
1

CPU_SVID_DAT_R
<91> CPU_SVID_DAT_R
RH2
@ 13_0402_5%
2

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(5/8)CFG,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 10 of 112
A B C D E
 A B C D E

GT
32000mA(Hexa Core GT2) +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE
+VCC_GT CFL-H +VCC_GT CFL-H UC1J
UC1K UC1I
AT14 BD35 AA13 AH13 128000mA(Hexa Core GT2) K14 W35
AT31 VCCGT1 VCCGT80 BD36 AA31 VCC1 VCC64 AH14 L13 VCC1 VCC64 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
AT37 VCCGT7 VCCGT86 BE36 AA37 VCC7 VCC70 AJ29 N32 VCC7 VCC70 Y32
AT38 VCCGT8 VCCGT87 BE37 AA38 VCC8 VCC71 AJ30 N35 VCC8 VCC71 Y33
1 VCCGT9 VCCGT88 VCC9 VCC72 VCC9 VCC72 1
AU14 BE38 AB29 AJ31 N36 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AV35 VCCGT24 VCCGT103 BG33 AC34 VCC24 VCC87 AL29 R32 VCC24
AV36 VCCGT25 VCCGT104 BG34 AC35 VCC25 VCC88 AL30 R33 VCC25
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW33 VCCGT29 VCCGT108 BH34 AD31 VCC29 VCC92 AL36 R37 VCC29
AW34 VCCGT30 VCCGT109 BH35 AD32 VCC30 VCC93 AL37 R38 VCC30
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY36 VCCGT40 VCCGT119 BJ24 AE31 VCC40 VCC103 AM35 U30 VCC40
AY37 VCCGT41 VCCGT120 BJ26 AE32 VCC41 VCC104 AM36 U31 VCC41
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA32 VCCGT48 VCCGT127 BK20 AF31 VCC48 VCC111 AN35 V14 VCC48
BA33 VCCGT49 VCCGT128 BK21 AF32 VCC49 VCC112 AN36 V31 VCC49
VCCGT50 VCCGT129 VCC50 VCC113 VCC50

www.laptoprepairsecrets.com
BA34 BK23 AF33 AN37 V32
BA35 VCCGT51 VCCGT130 BK24 AF34 VCC51 VCC114 AN38 V33 VCC51
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB34 VCCGT58 VCCGT137 BL24 AG32 VCC58 VCC121 AP37 W14 VCC58
BB35 VCCGT59 VCCGT138 BL25 AG33 VCC59 VCC122 AP38 W29 VCC59
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
3 VCCGT66 VCCGT145 VCC_SENSE_IA @ 3
BC32 BM16 AG37
VCCGT67 VCCGT146 BM17 VCC_SENSE AG38 VSS_SENSE_IA VCC_SENSE_IA <91>
BC35 9 OF 13 0926
VCCGT68 VCCGT147 VSS_SENSE VSS_SENSE_IA <91> Modify net by power
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
VCCGT71 VCCGT150 @
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
BR16 VCCGT161 VCCGT166 BT17
BR17 VCCGT162 VCCGT167 BT37
VCCGT163 VCCGT168

AH37 VSS_SENSE_GT
11 OF VSSGT_SENSE
13 AH38 VCC_SENSE_GT VSS_SENSE_GT <91>
VCCGT_SENSE VCC_SENSE_GT <91>
CFL-H_BGA1440
@ 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
CFL-H(6/8)VCC_CORE/GT
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
FH51M M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 11 of 112
A B C D E
 A B C D E

+1.2V_VDDQ
Max: 3300mA

+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

UC1L

J30 AA6

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
+VCC_SA VCCSA1 VDDQ1
K29 AE12

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
Max: 11100mA
VCCSA2 VDDQ2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 AF5
K31 VCCSA3 VDDQ3 AF6

CC70

CC71

CC72

CC73

CC74

CC75

CC76

CC77

CC78

CC79

CC80

CC81

CC82

CC83

CC84

CC85
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 VCCSA6 VDDQ6 1
K34 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13
PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12
+VCC_IO M35 VCCSA20 VDDQ20 L6 RC24 1 @ 2 0_0402_5%
Max: 6400mA M36 VCCSA21 VDDQ21 R6

1U_0201_6.3V6M

1U_0201_6.3V6M
VCCSA22 VDDQ22 T6

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
+VCCIO VDDQ23 1 1
W6 1 1 1 1
VDDQ24 Y12

CC86

CC87
AG12 VDDQ25

CC88

CC89

CC90

CC91
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11
PLACE CAP BACKSIDE
H26 G30 +1.05V_VCCSFR
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCC_SENSE_SA
VCCIO18 VCCSA_SENSE VSS_SENSE_SA VCC_SENSE_SA <91>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSS_SENSE_SA <91>
J26 150mA
J27 VCCIO20 H14 VCC_SENSE_VCCIO
VCCIO21 VCCIO_SENSE J14 VSSIO_SENSE VCC_SENSE_VCCIO <90>
1 1

1U_0201_6.3V6M

1U_0201_6.3V6M
12 OF 13 VSSIO_SENSE VSS_SENSE_VCCIO <90>

www.laptoprepairsecrets.com

CC92

CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
@
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

+1.05VS_VCCSTG
3 3

1U_0201_6.3V6M
CC94
2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
CFL-H(7/8)VCCSA/VCCIO/VDDQ
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 12 of 112
A B C D E
 A B C D E

CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 @ TC7 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 Impedance Spectrum Tool Trigger IST_TRIGE3
VSS_4 VSS_85 VSS_166 VSS_247 VSS_329 VSS_413 @ TC8 IST_TRIG
A20 AL33 B9 BJ29 BP21 F23 @ TC9 E1
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP24 VSS_330 VSS_414 F25 D1 RSVD_TP4
VSS_6 VSS_87 VSS_168 VSS_249 VSS_331 VSS_415 @ TC10 RSVD_TP3
A24 AL4 BA11 BJ31 BP25 F27
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 @ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 @ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <21> PCH_TRIGOUT_R CPU_TRIGOUT PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% J23
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT29 VSS_354 VSS_438 G8 <21> CPU_TRIGOUT_R PROC_TRIGOUT
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 @
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 @
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 @
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 @
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 @
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 @
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
VSS_50 VSS_131 VSS_212 VSS_293 VSS_375 VSS_459

www.laptoprepairsecrets.com
AG6 AU10 BG13 BM38 D16 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
CFL-H(8/8)GND/RSVD
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
FH51M M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 13 of 112
A B C D E
 A B C D E

CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<9> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <71>
<9> DMI_CTX_PRX_P0
J35 J2 USB3 MB
DMI_CRX_PTX_N0 C33 DMI0_RXP USB2P_1 N13 USB20_N2 USB20_P1 <71>
<9> DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <73>
B33 N15 USB2 (SUB/B)
<9> DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <73>
G33 K4
<9> DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <73>
<9> DMI_CTX_PRX_P1 F34 K3 USB2 (SUB/B)
DMI_CRX_PTX_N1 DMI1_RXP USB2P_3 USB20_N4 USB20_P3 <73>
C32 M10
<9> DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI1_TXN USB2N_4 USB20_P4 USB20_N4 <43>
B32 L9 TYPE C
<9> DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5 USB20_P4 <43>
K32 M1
<9> DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <38>
J32 L2 Camera
<9> DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI2_RXP USB2P_5 USB20_N6 USB20_P5 <38>
<9> DMI_CRX_PTX_N2 C31 K7
DMI_CRX_PTX_P2 DMI2_TXN USB2N_6 USB20_P6 USB20_N6 <38>
1 <9> DMI_CRX_PTX_P2
B31 K6 TS 1
DMI_CTX_PRX_N3 G30 DMI2_TXP USB2P_6 L4 USB20_P6 <38>
<9> DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI3_RXN USB2N_7
F30 L3
<9> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
<9> DMI_CRX_PTX_N3
C29 G4
DMI_CRX_PTX_P3 DMI3_TXN USB2N_8 USB20_P8 USB20_N8 <66>
<9> DMI_CRX_PTX_P3 B29 G5 FingerPrint
DMI3_TXP USB2P_8 USB20_P8 <66> +3VALW
A25 M6
B25 RSVD USB2N_9 N8
P24 RSVD USB2P_9 H3
R24 RSVD USB2N_10 H2 USB_OC0# RH200 1 2 10K_0402_5%
C26 RSVD USB2P_10 R10 USB_OC1# RH201 1 2 10K_0402_5%
B26 RSVD USB2N_11 P9
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
C27 RSVD USB2N_13 N2
L26 RSVD USB2P_13 E5 USB20_N14
M26 RSVD USB2N_14 F6 USB20_P14 USB20_N14 <52>
RSVD USB2P_14 USB20_P14 <52> BT For CNVI follow 571906_CNL_PCH_TA_WW11.pdf
D29
E28 RSVD AH36 USB_OC0#
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <43>
K29 AL40 USB_OC1# <71>
M29 RSVD GPP_E10/USB2_OC1# AJ44
RSVD GPP_E11/USB2_OC2# AL41 +3VALW
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37

1
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN USB2_RCOMP RH3
P21 F4 RH4 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUS_SENSE 10K_0402_5%
B18 F3 RH5 1 @ 2 0_0402_5%
2 C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 2

2
PCIE2_TXP/USB31_8_TXP RSVD1 GPD_7
K18 G3 USB2_ID RH6 1 @ 2 0_0402_5% STRAP
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7

1
C19 PCIE3_TXN/USB31_9_TXN GPD7
N18 PCIE3_TXP/USB31_9_TXP G45 RH7
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_P24 <68> 10K_0402_5%
R18 G46 M.2 SSD1 PCIE L3
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PTX_DRX_N24 <68> @
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 PCIE_PRX_DTX_P24 <68>

2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_PRX_DTX_N24 <68> X'tal Input:
G20 PCIE5_RXN PCIE23_TXP G49 PCIE_PTX_DRX_P23 <68>
PCIE5_RXP PCIE23_TXN PCIE_PTX_DRX_N23 <68>
M.2 SSD1 PCIE L2 High: Differential
B21 W44 Low: Single ended
A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_P23 <68>
PCIE5_TXP PCIE23_RXN PCIE_PRX_DTX_N23 <68>

www.laptoprepairsecrets.com
K21 H48
J21 PCIE6_RXN PCIE22_TXP H47 PCIE_PTX_DRX_P22 <68>
PCIE6_RXP PCIE22_TXN PCIE_PTX_DRX_N22 <68>
M.2 SSD1 PCIE L1
D21 U41
C21 PCIE6_TXN PCIE22_RXP U40 PCIE_PRX_DTX_P22 <68>
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PRX_DTX_N22 <68>
C23 PCIE7_TXP PCIE21_TXP G47 PCIE_PTX_DRX_P21 <68>
PCIE7_TXN PCIE21_TXN PCIE_PTX_DRX_N21 <68>
M.2 SSD1 PCIE L0
J24 R44
L24 PCIE7_RXP PCIE21_RXP T43 PCIE_PRX_DTX_P21 <68>
F24 PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68>
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0

@
3 3

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes
— A maximum of 16 PCIe* Ports (or devices) can be enabled
‧ When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured
2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PCI Express* (PCIe*)” chapter for the PCH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
4 4
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PCH(1/8)DMI/PCIE/USB2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 14 of 112
A B C D E
 A B C D E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H

remove TP as C5PRH UH1G
XTAL_24M_PCH_OUT 1 EMI@ 2 XTAL_24M_PCH_OUT_R BE33
RH11 33_0402_1% GPP_A16/CLKOUT_48
PCH_CPU_24M_CLK_P D7 Y3
<10> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# @ TH2
C6 Y4 @ TH3
XTAL_24M_PCH_IN 1 EMI@ 2 XTAL_24M_PCH_IN_R <10> PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
1 2
RH8 1M_0402_5% RH9 33_0402_1% PCH_CPU_BCLK_P B8 B6
<10> PCH_CPU_BCLK_P PCH_CPU_BCLK_N CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <10>
C8 A6
<10> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <10>
YH1
24MHZ_18PF_7R24000001 XTAL_24M_PCH_OUT_R U9 AJ6
XTAL_24M_PCH_IN_R XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_VGA# <27>
1 U10 AJ7 DGPU 1
3 1 XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_VGA <27>
3 1 RH10 1 2 60.4_0402_1% XCLK_BIASREF T3 AH9
33P_0402_50V8J

18P_0402_50V8J
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN# <73>
AH10 GLAN
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_LAN <73>
XCLK_BIASREF (PDG) BA49
CH5

CH6
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 AE15 CLK_PCIE_WLAN# <52>
8/24 CLKOUT_PCIE_P2 CLK_PCIE_WLAN <52> NGFF WL+BT(KEY E)
VGA_CLKREQ# BF31
BE31 GPP_B5/SRCCLKREQ0# AE6
<73> LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF1# <68>
<52> WLAN_CLKREQ# AR32 AE7 M2 SSD1
GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF1 <68>
BB30
<68> SSD2_CLKREQ# GPP_B8/SRCCLKREQ3#
<68> SSD1_CLKREQ#
BA30 AC2
PCH_RTCX1 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_NGFF3# <68>
AN29 AC3 M2 SSD3
<69> SSD3_CLKREQ# GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_NGFF3 <68>
AE47
PCH_RTCX2 20190918 SSD2&3 Change AC48 GPP_H0/SRCCLKREQ6# AB2
GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CLK_PCIE_NGFF2# <69>
AE41 AB3 M2 SSD2
1 2 20191209 AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_NGFF2 <69>
RH12 10M_0402_5% > SSD1 - GPP_B9/CLKREQ4# (PCIE only) (2018 @SSD2) AC41 GPP_H3/SRCCLKREQ9# W4
20200114 > SSD2 - GPP_B8/CLKREQ3# (PCIE/SATA) (2018 @SSD1)
AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
> SSD3 - GPP_B10/CLKREQ5# (PCIE/SATA) (2019 NEW) GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
- CH7/CH8 Change to SE173100J80 AE39
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
remove no use srcclkreq GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
AC43
GPP_H9/SRCCLKREQ15# AC14
10P_0201_50V8J

10P_0201_50V8J

1 1 CLKOUT_PCIE_N8
32.768KHZ_9PF_X1A000141000200 V2 AC15
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15 U2
CH7

CH8

2 2 T2 CLKOUT_PCIE_N9 U3
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 Trace Space: 15 mil CLKOUT_PCIE_P14 AC9 2
Max Trace Length: 1000 mil CLKOUT_PCIE_N10
use same part w C5MMH AA1
CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
AC11
Y2
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13 R6
CLKIN_XTAL REFCLK_CNV <52>
+3VS CNP-H_BGA874 Rev1.0

1
@
RH14
RH204 1 2 10K_0402_5% LAN_CLKREQ# 10K_0402_5%
RH205 1 2 10K_0402_5% VGA_CLKREQ# <27>

www.laptoprepairsecrets.com
RH206 1 2 10K_0402_5% WLAN_CLKREQ#

2
RH207 1 2 10K_0402_5% SSD2_CLKREQ#
RH220 1 2 10K_0402_5% SSD3_CLKREQ#
RH300 1 2 10K_0402_5% SSD1_CLKREQ#
CNP-H
UH1M

AW13 BD4 CLK_CNV_PRX_DTX_N

GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_P CLK_CNV_PRX_DTX_N <52>
For DDX03 R02 BE9 BE3 CLK_CNV_PRX_DTX_P <52>
BF8 GPP_G1/SD_DATA0 CNV_WR_CLKP
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
XTAL Frequency Select GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_N0 <52>
BG8 BB4 CNV_PRX_DTX_P0
+1.8VALW_PRIM GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <52>
remove SD signal from PCH BE8
GPP_G5/SD_CD# CNV_WR_D1N
BA3
CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <52>
BD8 BA2
AV13 GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <52>
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
3 CNV_BRI_PTX_DRX CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <52> 3
RH15 1 2 4.7K_0402_5% AP3 BB6 CLK_CNV_PTX_DRX_P <52>
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
STRAP AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
This signal has a weak internal pull-down 20K. GPP_I13/M2_SKT2_CFG2
3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <52>
0 = 38.4/19.2MHz XTAL frequency selected. remove CPU_C10_GATE# AM7 BD7 CNV_PTX_DRX_P0
GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P CNV_PTX_DRX_N1 CNV_PTX_DRX_P0 <52>
1 = 24MHz XTAL frequency selected. (DDX03) BG6
I2C_TS_INT# CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <52>
Notes: 20190927 <38> AV6 BF6 CNV_PTX_DRX_P1 <52>
1. The internal pull-down is disabled after RSMRST# I2C_TS_INT# AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P BA1 CNV_WT_RCOMP RH16 1 2 150_0402_1%
de-asserts.
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
2. This signal is in the primary well. GPP_J11/A4WP_PRESENT
I2C_TS_RST# AV7 B12 PCIE_RCOMPN RH17 1 2 100_0402_1%
<38> I2C_TS_RST# AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH18 1 2 200_0402_1%
+1.8VALW_PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH19 1 2 200_0402_1%
VCCPSPI Select <52> CNV_BRI_PTX_DRX GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP
CNV_BRI_PRX_DTX AY2 BD1
<52> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 BE1 GPPJ_RCOMP_1P8 RH20 1 2 200_0402_1% 20191024
<52> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX AV3 GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82 BE2 - CML Check list OK
<52> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
@ GPP_J9 AW2
RH21 1 2 4.7K_0402_5% GPP_J9 GPP_J8/CNV_MFUART2_RXD
AU9 Y35
GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
The signal has a weak internal pull-down 20K STRAP RSVD3
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin BC1
13 OF 13 RSVD1 AL35
strap must be a ‘ 1’ for the proper functionality @ TH4
of the SPI (Flash) I/Os +1.8VALW_PRIM TP
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Rev1.0 Recommend external test point
20191210C
@
+1.8VALW_PRIM - RH22 change to 20K for CNVI review RH181 1 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX
M.2 CNV Mode Select
RH182 1 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
RH22 1 2 20K_0402_1% CNV_RGI_PTX_DRX 571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
4 a weak pull up resistor to the SoC pin with a recommended value of 20K ohm. 4
RH23 2 @ 1 10K_0402_5% STRAP
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(2/8)CLK/CNVI/SD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 15 of 112
A B C D E
 A

CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8
no follow naming GPP_I6/DDPB_CTRLDATA
AT6 AN13
<27,39> DP0_HPD_PCH GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK
<27,40> HDMI_HPD_PCH AN10 AL10
AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA AL9
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
can remove if no use DP GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA
08/18 AN40
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41
AN6 GPP_F14/PS_ON#
<38> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
remove PCH DP SCLK/SDATA
M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
DDP[B..F]CTRLDATA GPP_K21 T46
This signal has a weak internal Pull-down. 5 OF 13 GPP_K20 AJ47
0 = Port B~D is not detected. GPP_H23/TIME_SYNC0
1 = Port B,C,D is detected. (Default)
Rev1.0
remove CIO_PLUG_EVENT#
Notes: CNP-H_BGA874 intel critical net recommend
1. The internal Pull-down is disabled after @
PCH_PWROK de-asserts. RH198 1 2 100K_0201_5%
2. This signal is in the primary well.
CNP-H
UH1A PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 EC_PME#_R BE36 AV29 PLT_RST#
<58,73> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <27,58,66>
RH24 0_0402_5% XESD@

R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
RSVD1 GPP_K12/GSXDOUT Y48 provided by the PCH to expand the GPIOs
CRB connect GND GPP_K13/GSXSLOAD on a platform that needs more GPIOs than the
W46 ones provided by the PCH.
RH186 1 @ 2 0_0402_5% AL37 GPP_K14/GSXDIN AA45
AN35 VSS GPP_K15/GSXSRESET#
TH6 @ TP
RH258 1 NTPM@ 2 0_0402_5% PCH_SPI_SI AU41 AL47 20191016
<66> PCH_SPI_SI_R 1 NTPM@ 2 0_0402_5% PCH_SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45 1 2 0_0402_5% BT_ON - BT_ON For Intel (GPP_B3)
RH259 RH304
<66> PCH_SPI_SO_R PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 GPP_B3 BT_ON <52,58> - TP_INT# change to GPP_B4
BF32
RH260 1 NTPM@ 2 0_0402_5% PCH_SPI_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 TP_INT# 2 1 EC_TP_INT# 20191206
<66> PCH_SPI_CLK_R SPI0_CLK GPP_B4/CPU_GP3 EC_TP_INT# <58,63> - RH304 pop
AW48 DH1
SPI0_CS1# AE44 RB751V-40_SOD323-2 +3VS
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46
PCH_SPI_IO3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43 TP_INT# RH28 2 1 100K_0402_5%
* wait confirm CG7 SPI0_IO3 GPP_H16/SML4CLK
PDG P348 quad mode support PH1K AT40 AC47 GPP_H15 GPP_B3 RH305 2 @ 1 100K_0402_5%
<66> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT#
CRB PU 20k AD48
+3VALW #571182_CFL_PCH_EDS_Rev1.0 recommend 100k BE19 GPP_H14/SML3DATA AF47
#571391_CFL_H_PDG_Rev0p71 BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 GPP_H12
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 <19> +RTCVCC
BF18 AD47
RH25 2 1 1K_0402_5% PCH_SPI_IO2 BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
RH26 2 1 1K_0402_5% PCH_SPI_IO3 BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
GPP_D21/SPI1_IO2 INTRUDER#

www.laptoprepairsecrets.com
CNP-H_BGA874 Rev1.0 RVP: 330K
RH27 2 1 1K_0402_5% PCH_SPI_SI_R A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
+3VALW
*20191024
RH29 2 1 100K_0402_5% GPP_H15 STRAP - CML RVP PU 330K

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. RH258 TPM@ RH259 TPM@ RH260 TPM@
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15
4.99_0402_1% 4.99_0402_1% 4.99_0402_1%
SD034499B80 SD034499B80 SD034499B80
PCH_SPI_CLK_R RH195 1 @ 2 100K_0201_5%

intel critical net recommend

SPI ROM ( 16MByte ) PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%

+3VALW

+3VALW +3VS
CH10 0.1U_0201_10V6K CH11
UH2 PCH_SPI_CS#0 1 2
1 2 @ 0.1U_0201_10V6K
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% 1 2
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R
/WP(IO2) CLK PCH_SPI_SI_0_R

5
4 5 UH3
GND DI(IO0) PCH_SPI_SI_0_R RH107 1 2 33_0402_1% PCH_SPI_SI_R

VCC
PCH_SPI_SO_0_R RH108 1 2 33_0402_1% PCH_SPI_SO_R PLT_RST# 1
W25Q128FVSIQ_SO8 PCH_SPI_IO3_0_R RH109 1 2 33_0402_1% PCH_SPI_IO3 IN1 4
PCH_SPI_CLK_0_R 1 2 PCH_SPI_CLK_R 2 OUT PLT_RST_BUF# <52,68,69,73>
XMC P/N: SA0000B8400 RH110 33_0402_1%

GND
PCH_SPI_IO2_0_R PCH_SPI_IO2 IN2

1
RH111 1 2 33_0402_1%
+3VALW RH199
JC1 100K_0201_5%

3
PCH_SPI_CS#0 1 8
PCH_SPI_IO2_0_R 3 CS# VCC 6 PCH_SPI_CLK_0_R XEMI@ XEMI@ MC74VHC1G08DFT2G_SC70-5 @
WP# SCLK

2
PCH_SPI_IO3_0_R 7 5 PCH_SPI_SI_0_R PCH_SPI_CLK_0_R 1 2 1 2
4 HOLD# SI/SIO0 2 PCH_SPI_SO_0_R
GND SO/SIO1 RH33 CH12
ACES_91960-0084N_MX25L3206EM2I 0_0402_5% 68P_0402_50V8J
CONN@

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(3/8)DDC/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 16 of 112
A
 A B C D E

#571391_CFL_H_PDG_Rev0p5
‧ eSPI clock and eSPI data mismatched: <500 mils.
‧ eSPI clock and eSPI chip select mismatched: <500 mils.
‧ eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
@ UH1F
F9 BB39 LPC_AD0
<71> USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <58>
F7 1.8V AW37 LPC Bus check straps
<71> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <58>
USB3 MB D11 AV37
<71> USB3_PRX_DTX_N1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <58>
C11 BA38 LPC : +3.3V
<71> USB3_PRX_DTX_P1 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <58>
C3
<73> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<73> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <58> +3VS
1 USB3 IO/B <73> USB3_PRX_DTX_N2
B9 AW35 TPM_SERIRQ <58,66> 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<73> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 RCIN#
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST# RH261 1 @ 2 0_0402_5% RCIN# 2 1 RH219
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# OVRM_EN <36,58>
C16
USB31_6_TXP CLK_LPC 10K_0402_5%
G14 BB36 RH35 2 1 22_0402_5%
F14 USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK BB34 CLK_LPC_R <58>
20191016 USB3_PTX_DRX_N5 C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
<73> USB3_PTX_DRX_N5 USB3_PTX_DRX_P5 USB31_5_TXN
B15 T48
<73> USB3_PTX_DRX_P5 USB3_PRX_DTX_N5 USB31_5_TXP GPP_K19/SMI#
USB3 IO/B <73> USB3_PRX_DTX_N5 J13 T47
USB3_PRX_DTX_P5 K13 USB31_5_RXN GPP_K18/NMI#
<73> USB3_PRX_DTX_P5 USB31_5_RXP
20191016 G12 AH40
<43> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 SSD_DEVSLP1
F11 AH35
<43> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <68>
USB3 Type C <43> USB3_PRX_DTX_P3 C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47 +3VS
<43> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37
20190924 USB3_PTX_DRX_P4 C14 GPP_F8/SATA_DEVSLP6 AN46
<43> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 USB31_4_TXP GPP_F7/SATA_DEVSLP5 SSD_DEVSLP4
B14 AR47
<43> USB3_PTX_DRX_N4 USB3_PRX_DTX_P4 USB31_4_TXN GPP_F6/SATA_DEVSLP4 SSD_DEVSLP4 <69> TPM_SERIRQ 2 1 RH37
USB3 Type C <43> USB3_PRX_DTX_P4 J15 AP48
USB3_PRX_DTX_N4 K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3 20191025
<43> USB3_PRX_DTX_N4 USB31_4_RXN - SATA Port 4 10K_0402_5%
CNP-H_BGA874 Rev1.0
LPC_PIRQA# 1 2 RH38
10K_0402_5%

CNP-H
2 @ UH1C 2
CL_CLK AR2 G36 PCIE_PRX_DTX_N9
TH10 @ CL_DATA CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <68>
For Intel CLINK TH11 @
AT5 F36
CL_RST# AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <68>
TH12 @ CL_RST# PCIE9_TXN PCIE_PTX_DRX_N9 <68>
M.2 SSD2 PCIE L3
D34 PCIE_PTX_DRX_P9
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <68>
V47 GPP_K8
V48 GPP_K9 K37 PCIE_PRX_DTX_N10
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <68>
GPP_K11 PCIE10_RXP C35 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
PCIE10_TXN PCIE_PTX_DRX_N10 <68>
M.2 SSD2 PCIE L2
L47 B35 PCIE_PTX_DRX_P10
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <68>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
GPP_K2 PCIE15_RXN/SATA2_RXN

www.laptoprepairsecrets.com
U47 E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <52> NGFF
N48 GPP_K3 PCIE15_RXP/SATA2_RXP B40 PCIE_PTX_DRX_N15 .1U_0402_16V7K 1 2 CH1 PCIE_PRX_DTX_P15 <52>
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 .1U_0402_16V7K 1 2 CH2 PCIE_PTX_C_DRX_N15 <52> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_C_DRX_P15 <52>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<68> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<68> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD2 PCIE L1 <68> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP
G38 K43 PCIE_PRX_DTX_N17
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 <69>
PCIE17_RXP/SATA4_RXP PCIE_PRX_DTX_P17 <69>
M.2 SSD3 PCIE L0
AR42 A42 PCIE_PTX_DRX_N17
AR48 GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN B42 PCIE_PTX_DRX_P17 PCIE_PTX_DRX_N17 <69>
20190918 Port4 change to Port3 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_DRX_P17 <69>
DGPU_PRSNT# AU47
AU46 GPP_F13/SATA_SDATAOUT0 P41 PCIE_PRX_DTX_N18
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40 PCIE_PRX_DTX_P18 PCIE_PRX_DTX_N18 <69>
PCIE18_RXP/SATA5_RXP PCIE_PRX_DTX_P18 <69>
M.2 SSD3 PCIE L1
3 PCIE_PTX_DRX_N14 C39 C42 PCIE_PTX_DRX_N18 3
<73> PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 D39 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN D42 PCIE_PTX_DRX_P18 PCIE_PTX_DRX_N18 <69>
<73> PCIE_PTX_DRX_P14 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_DRX_P18 <69>
20190918
GLAN PCIE_PRX_DTX_N14 D46
<73> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN
C47 AK48
<73> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
SATA_PTX_DRX_N0B B38 AH41
<67> SATA_PTX_DRX_N0B SATA_PTX_DRX_P0B C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43 SATA_GP1
<67> SATA_PTX_DRX_P0B SATA_PRX_DTX_N0B C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP2 SATA_GP1 <68>
HDD <67> SATA_PRX_DTX_N0B PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 @ TH50
20191016 SATA_PRX_DTX_P0B C46 AN47 RH187 1 PBA@ 2 10K_0402_5% +3VS
- HDD change to Port 0B <67> SATA_PRX_DTX_P0B PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 SATA_GP4 20191206
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP5 SATA_GP4 <69> - JSSD3 detect pin change to SATA_GP4
<68> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 @ TH13
D38 AM47
<68> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48 SATA_GP4 RH303 2 1 10K_0402_5%
M.2 SSD2 PCIE L0 <68> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
H42 SATA_GP1 RH39 2 1 10K_0402_5%
<68> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48 PCH_BKL_PWM
GPP_F21/EDP_BKLTCTL PCH_BKL_PWM <38> M.2 SSD PCIE/SATA select pin
PCIE_PTX_DRX_P20 B44 AV46 ENBKL
<69> PCIE_PTX_DRX_P20 PCIE_PTX_DRX_N20 A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 PCH_ENVDD ENBKL <58>
M.2 SSD3 PCIE L3 <69> PCIE_PTX_DRX_N20 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD <38>
PCIE_PRX_DTX_P20 R37
<69> PCIE_PRX_DTX_P20 PCIE20_RXP/SATA7_RXP #571391_CFL_H_PDG_Rev0p5.pdf
PCIE_PRX_DTX_N20 R35 AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
<69> PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 D43 PCIE20_RXN/SATA7_RXN THRMTRIP# AF2 PCH_PECI 2 13_0402_5% H_PECI PCH_THERMTRIP#_R <10>
RH41 1 @
<69> PCIE_PTX_DRX_P19 PCIE_PTX_DRX_N19 PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <10,58>
M.2 SSD3 PCIE L2 C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
+3VALW <69> PCIE_PTX_DRX_N19 PCIE_PRX_DTX_P19 N42 PCIE19_TXN/SATA6_TXN PM_SYNC AG5 H_PLTRST_CPU# H_PM_SYNC_R <10>
<69> PCIE_PRX_DTX_P19 PCIE_PRX_DTX_N19 M44 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOWN_R H_PLTRST_CPU# <10>
20190918 AE2
<69> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN_R <10>
1

CNP-H_BGA874 Rev1.0
RH43
10K_0402_5% UMA@ XESD@
H_PECI 0.1U_0201_10V6K 1 2 CH50
4 4
2

DGPU_PRSNT#
1

GPP_F13
RH44
10K_0402_5% VGA@ DGPU_PRSNT#
Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
DIS,Optimus 0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PCIE/SATA/USB3/eSPI
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
UMA 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FH51M M/B LA-J871P
1.0

Date: Tuesday, February 11, 2020 Sheet 17 of 112

A B C D E
 A B C D E

+1.2V_VDDQ

<58> ME_EN 1 @ 2
RH45 0_0402_5%

2
RH208 1 2 33_0402_5% HDA_RST# RH46
<56> HDA_RST#_R HDA_BIT_CLK
RH209 1 2 33_0402_5% 470_0402_1%
<56> HDA_BIT_CLK_R HDA_SDOUT
<56> HDA_SDOUT_R RH210 1 2 33_0402_5%
RH211 1 2 33_0402_5% HDA_SYNC
<56> HDA_SYNC_R

1
DRAM_RESET# 1 @ 2
DDR_DRAMRST#_R <23,24>
RH47 0_0402_5%

2 1
1 CH13 0.1U_0201_10V6K 1
100K_0201_5% 2 1RH196 HDA_BIT_CLK CNP-H @
100K_0201_5% 2 1RH197 HDA_RST# UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
intel critical net recommend <56> HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
BF12
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC @ TH14
del RF reserve cap on HDA HDA_RST# SLP_WLAN#
BE10 BD42 @ TH15
BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33 TYPEC_3A
GPP_B1/GSPI1_CS1#/TIME_SYNC1 TYPEC_3A <43>
BE29
RH48 1 2 30_0402_5% CPU_DISPA_SDO AM2 GPP_B0/GSPI0_CS1# R47 PCH_GPP_K17
<6> CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE PCH_GPP_B11 @ TH19
AN3 AP29
<6> CPU_DISPA_SDI_R CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PWROK @ TH20
RH49 1 2 30_0402_5% AM3 AU3
<6> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK SYS_PWROK <58,78>
PCM_CLK AV18 BB47 WAKE#
<52> PCM_CLK PCM_OUT AW18 GPP_D8/I2S2_SCLK WAKE# BE40 PM_SLP_A#
FOR Jefferson Peak RESET pin is glitch free,it <52> PCM_OUT GPP_D7/I2S2_RXD GPD6/SLP_A# @ TH37
CLKREQ_CNV# BA17 BF40 SLP_LAN#
is recommended that a pull-down resistor of 75K <52> CLKREQ_CNV# CNV_RF_RESET# BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28 PM_SLP_S0# @ TH21
ohm on GPP_D5(CNV_RF_RESET#) <52> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3# @ TH38
<56> PCH_DMIC_DATA0 BF15 BF42
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# BE42 PM_SLP_S4# PM_SLP_S3# <58,78>
<56> PCH_DMIC_CLK0 AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# BC42 PM_SLP_S5# PM_SLP_S4# <58,78>
+RTCVCC TH22 @ GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# @ TH23
TH24 @ AW15
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK
RH50 1 2 20K_0402_1% PCH_SRTCRST# GPD8/SUSCLK SUSCLK <52,68,69>
BF44 PM_BATLOW#
GPD0/BATLOW# BE35 SUSACK#_R
CH18 1 2 1U_0201_6.3V6M PCH_RTCRST# GPP_A15/SUSACK# @ T207
2 BE47 BC37 1 @ 2 2
<58> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSPWRDNACK <58>
CLR ME BD46 RH51 0_0402_5%
SRTCRST#
Delay 18~25 ms
PCH_PWROK AY42 BG44 LAN_WAKE#
PCH_RTCRST# <58,78> PCH_PWROK EC_RSMRST# PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R
RH52 1 2 20K_0402_1% <58> EC_RSMRST#
BA47 BG42 RH53 1 @ 2 0_0402_5% AC_PRESENT <58>
RSMRST# GPD1/ACPRESENT BD39 SLP_SUS#
SLP_SUS# BE46 PBTN_OUT#_R @T208
1 @
--No
2 0_0402_5% Support Deep Sx
PCH_DPWROK GPD3/PWRBTN# SYS_RESET# PBTN_OUT# <58>
CH19 1 2 1U_0201_6.3V6M AW41 AU2 RH54
PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
ECLR CMOS <19> PCH_SMBALERT# PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPWRGD PCH_SPKR <19,56>
JCMOS1 1 @ 2 0_0603_5% Delay 18~25 ms BE26 AE3
PCH_SMBDATA BF26 GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <10>
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE T209
<19> PCH_SML0ALERT# PCH_SML0CLK GPP_C5/SML0ALERT# ITP_PMODE CPU_XDP_TCK0 @
BF25 AH4 CPU_XDP_TCK0 <10>
GPP_C3/SML0CLK PCH_JTAGX

www.laptoprepairsecrets.com
PCH_SML0DATA BE24 AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <10>
<19> PCH_SML1ALERT# PCH_SML1CLK GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO CPU_XDP_TDI CPU_XDP_TDO <10> Connect CPU & PCH
+3VALW_DSW BF27 AH2
PCH_SML1DATA GPP_C6/SML1CLK PCH_JTAG_TDI PCH_JTAG_TCK1 CPU_XDP_TDI <10>
BE27 4 OF 13 AJ3
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <10>
CNP-H_BGA874 @ Rev1.0

RH55 2 1 1K_0402_5% WAKE#

UART BT (20191014)
RH56 2 1 8.2K_0402_5% PM_BATLOW# PM_SLP_S3# RH193 1 2 100K_0201_5%
- RH301 change to 100K PM_SLP_S4# RH194 1 2 100K_0201_5%

RH57 1 2 100K_0402_5% AC_PRESENT_R

@
+3VALW
intel critical net recommend
RH58 1 @ 2 100K_0402_5% PBTN_OUT#_R UART_BT@
RH301 1 2 100K_0402_5%
3 EC_RSMRST# 1 @ 2 PCH_DPWROK 3
UART_BT@ RH59 0_0402_5%
UART_WAKE# RH302 1 2 0_0402_5% PCH_SMBALERT#
<52> UART_WAKE#
+3VALW
+3VALW_DSW
2 1 SYS_RESET#
+3VS RH183 10K_0402_5%
LAN_WAKE# RH212 1 2 10K_0402_5%
+3VS
PCH_PWROK RH213 1 2 10K_0402_5%
EC_RSMRST# RH214 1 2 10K_0402_5%
SYS_PWROK
5

100K_0402_5% 1 @ 2 RH184
G

RH60 2 1 8.2K_0402_5% PM_CLKRUN# QH7B

2N7002KDW_SOT363-6
(DDR,G-Sensor) 100K_0402_5% 1 @ 2 RH61 PCH_DPWROK
PCH_SMBCLK 3 4 D_CK_SCLK
D_CK_SCLK <23,24>
S

RH191 2 1 2.2K_0402_5% D_CK_SCLK XESD@

D

D_CK_SDATA
2

RH192 2 1 2.2K_0402_5% 0.1U_0201_10V6K 1 2 CH20 SYS_RESET# +3VALW

G

QH7A
2N7002KDW_SOT363-6 XESD@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%
0.1U_0201_10V6K 1 2 CH21 SYS_PWROK
+3VALW PCH_SMBDATA 6 1D_CK_SDATA
D_CK_SDATA <23,24>
S

XESD@
D

0.1U_0201_10V6K 1 2 CH22 PCH_PWROK

RH251 2 1 2.2K_0402_5% PCH_SMBCLK
RH252 2 1 2.2K_0402_5% PCH_SMBDATA XESD@
RH253 2 1 2.2K_0402_5% 100P_0402_50V8J 1 2 CH51 EC_RSMRST#
PCH_SML1CLK <27,58,66>
RH254 2 1 2.2K_0402_5% (EC,VGA,Thermal Sensor)
PCH_SML1DATA <27,58,66>
4 4
From ESD Team Request
1 2 PCH_SML0CLK Near PCH side
RH63 499_0402_1%
1 2 PCH_SML0DATA
RH64 499_0402_1%
Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(5/8)PMU/HDA/SMBUS/DMIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 18 of 112
A B C D E
 A B C D E

+3VALW
CNP-H
RH215 1 2 2.2K_0402_5% I2C_1_SCL UH1K
RH216 1 2 2.2K_0402_5% I2C_1_SDA
RH217 1 2 2.2K_0402_5% I2C_0_SCL GSPI1_MOSI BA26 BA20 GPP_D9
RH218 1 2 2.2K_0402_5% I2C_0_SDA PEN_RST# BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 GPP_D10
<64> PEN_RST# EC_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK PROJECT_ID0
AU26 BB16
<58> EC_SCI# PEN_PDCT# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1
AW26 AN18
+3VS <64> PEN_PDCT# GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN3V3 RH67 1 @ 2 0_0402_5% GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
<27> GC6_FB_EN3V3 TS_EN GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN SUB_DET
BF29 BF17
<38,58> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 BE17 CPU_ID
1
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
check for remove (PCH or Both)
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD check needed? BB24
DGPU_AC_DETECT BE23 GPP_C9/UART0A_TXD
<27,58,85> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS WAKE_BT AP24
<52> WAKE_BT GPU_EVENT# GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 BA24
<27> GPU_EVENT# GPP_C10/UART0A_RTS#
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
RH72 1 VGA@ 2 10K_0402_5% DGPU_PWR_EN AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<27> DGPU_HOLD_RST# DGPU_PWR_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24 AH48
<27> DGPU_PWR_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# UART_2_PCTS_DRTS AV21
UART_2_PRTS_DCTS AW21 GPP_C23/UART2_CTS#
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34
<52> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32
+3VALW <52> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 PEN_IRQ#
<63> I2C_1_SCL I2C_1_SDA GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 PEN_IRQ# <64>
<Touch PAD> BF21 BD34
GPP_H12 <63> I2C_1_SDA I2C_0_SCL GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 PANEL_OD_EN <38>
RH74 1 @ 2 4.7K_0402_5% BC22 BF35
GPP_H12 <16> <64> I2C_0_SCL I2C_0_SDA GPP_C17/I2C0_SCL GPP_A18/ISH_GP0
<EMR> BF23 BD38
<64> I2C_0_SDA GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
This signal has a weak internal pull-down. STRAP
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
20190927 I2C_SDA_TS BE15
1 = Slave Attached Flash Sharing (SAFS) enabled. <38> I2C_SDA_TS I2C_SCL_TS GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
Notes: BE14 11 OF 13
<38> I2C_SCL_TS GPP_D23/ISH_I2C2_SCL/I2C3_SCL
1. This signal is in the primary well.
Warning: This strap must be configured to ‘ 0’ if the CNP-H_BGA874 Rev1.0
eSPI or LPC strap is configured to ‘ 0’
@
+1.8VALW_PRIM

2 CPU_ID RH255 1 H82@ 2 1K_0402_5% 2

+3VALW RH256 1 H62@ 2 10K_0402_5%

RH112 1 @ 2 4.7K_0402_5%
PCH_SMBALERT# <18> +1.8VALW_PRIM
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS) SUB_DET RH185 1 @ 2 1K_0402_5%

RH1131 @ 2 4.7K_0402_5%

SML0ALERT# / GPP_C5 has a weak internal Pull-down.

0 = LPC is selected (for EC 9022).
1 = eSPI is selected
www.laptoprepairsecrets.com
PCH_SML0ALERT# <18>

+1.8VALW_PRIM
+1.8VALW_PRIM
RH114 1 2 150K_0402_1% GPP_D9 RH84 1 @ 2 1K_0402_5%
PCH_SML1ALERT# <18> PROJECT_ID0 1 2 1K_0402_5%
RH88 @
SML1ALERT# / GPP_B23 has an internal pull-down. RH85 1 2 10K_0402_5%
0 = Disable IntelR DCI-OOB (Default) RH89 1 2 10K_0402_5%
*1 = Enable IntelR DCI-OOB
STRAP
GPP_D10 RH86 1 @ 2 1K_0402_5%
PROJECT_ID1 RH90 1 2 1K_0402_5%
+3VS RH87 1 2 10K_0402_5%
3 RH91 1 @ 2 10K_0402_5% 3

RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

The signal has a weak internal Pull-down.
0 = Disable “ No Reboot” mode. (Default)
1 = Enable “ No Reboot” mode (PCH will disable the Project_ID1 Project_ID0 20190506
TCO Timer system reboot feature). This function is Project ID - defined as Project
useful when running ITP/XDP.
Notes: GPP_D10 GPP_D9 GPP_D12 GPP_D11
1. The internal Pull-down is disabled after
PCH_PWROK is high.
2. This signal is in the primary well.
Reserved 0 0 2020 A7 0 0
Reserved 0 1 NA 0 1
Reserved 1 0 *2020 Gaming 50 1 0
@ GSPI1_MOSI
RH80 1 2 150K_0402_1% STRAP for 8 Layer 1 1 2020 Gaming 60 1 1
This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC SCI capability is available on all GPIOs
Notes: PCH GPIOs that can be routed to generate SMI# or NMI:
1. The internal Pull-down is disabled after PCH_PWROK is high. ‧ GPP_B14, GPP_B20, GPP_B23
2. This signal is in the primary well. ‧ GPP_C[23:22]
‧ GPP_D[4:0]
‧ GPP_E[8:0]
PCH_SPKR ‧ GPP_I[3:0]
RH83 2 @ 1 100K_0402_5% ‧ GPP_G[7:0] (support SMI# only).
PCH_SPKR <18,56>
Top Swap Override STRAP The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
0 = Disable “ Top Swap” mode. (Default) except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
1 = Enable “ Top Swap” mode.
4 The internal Pull-down is disabled after PCH_PWROK is high. All GPIOs have programmable internal pull-up/pull-down resistors which are off by default. 4
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(6/8)GPIO/I2C/UART/STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 19 of 112
A B C D E
 A B C D E

GPIO Group Voltage

GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW
+1.05VALW_PCH_PRIM UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
@ JPH1 AA23 VCCPRIM_1P051 VCCPRIM_3P32
1 2 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT 3.3V
1 2 HSIO for DMIU/USB3.1/PCIE=4162mA
AB22 VCCPRIM_1P053 DCPRTC1 BG47 +VCCRTCEXT +VCCRTCEXT GPPD * 1.8V

1U_0201_6.3V6M
JUMP_43X79 AB23 VCCPRIM_1P054 DCPRTC2
1 VCCPRIM_1P055
AB27 V23 0.095A +3VALW GPPE

CH23
AB28 VCCPRIM_1P056 VCCPRIM_3P35 3.3V

0.1U_0201_10V6K
AB30 VCCPRIM_1P057 AN44 0.05A GPPF

CH24
VCCPRIM_1P058 VCCSPI 1
2 AD20 +RTCVCC
AD23 VCCPRIM_1P059 BC49 GPPG 3.3V
1 VCCPRIM_1P0510 VCCRTC1 1
AD27 BD49
AD28 VCCPRIM_1P0511 VCCRTC2 2
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
+1.05VALW AF30 VCCPRIM_1P0517 VCCPRIM_3P34 GPPI 3.3V Only
6.6A VCCPRIM_1P0518 AC35 0.262A
6.6A U26 VCCPGPPHK1 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 GPPJ

22U_0603_6.3V6M

1U_0201_6.3V6M
0.174A 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
1 1 VCCPRIM_1P0525 VCCPGPPEF2
V27 +1.8VALW_PRIM

CH26
V28 VCCPRIM_1P0526 AN24 0.14A GPD 3.3V Only

CH25
V30 VCCPRIM_1P0527 VCCPGPPD AN26 +1.8VALW_PRIM
2 2 +1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA

4.7U_0402_6.3V6M

1U_0201_6.3V6M
1 1
Place Near UH1 VCCPRIM_1_0523~29 0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31 BE48

CH27

CH28
3-5MM FROM PACKAGE EDGE VCCDSW_3P31
0.42A W22 BE49 0.113A
VCCDUSB_1P051 VCCDSW_3P32 +3VALW_DSW +3VALW_HDA 2 2
W23
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 @ 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH95 1 @ 2 0_0402_5% (External VRM mode RH172 unmount)
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY 2
W20
0.1U_0201_10V6K

0.1U_0201_10V6K

1U_0201_6.3V6M

1 VCCA_SRC_1P052 Short pins AJ22,AJ23,AK22,AK23 together

AJ22
CH29

CH30

1 1 VCCDPHY_1P241 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71

0.0198A C1 AJ23 Internal LDO
CH31

C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 RH96 1 @ 2 0_0402_5%

2 0.0085A VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
V19
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
VCCMPHY_SENSE VSSMPHY_SENSE @ TH27
0.021A B1 K46 @ TH28
B2 VCCAPLL_1P051 VSSMPHY_SENSE For DDX03 R02
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053 +1.24V_PRIM_MAR
place near VCCDUSB 1-3MM FROM PACKAGE CNP-H_BGA874 Rev1.0
1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31 @

4.7U_0402_6.3V6M
1

CH32
www.laptoprepairsecrets.com
+1.05VALW_PCH
+1.05VALW_PCH 2
+1.05VALW_PCH
0.1U_0201_10V6K
1U_0201_6.3V6M

CH34

0.1U_0201_10V6K

1 1
1U_0201_6.3V6M

CH54

1 1
CH33

+3VALW
CH35

2 2 +3VALW
2 2 +3VALW +3VALW

0.1U_0201_10V6K

1U_0201_6.3V6M

0.1U_0201_10V6K
0.1U_0201_10V6K
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE 1 1 1 1
+3VALW_DSW +1.8VALW +1.8VALW_PRIM

CH39

CH37

CH38
CH36
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3
RH99 1 @ 2 0_0402_5%
1 2 0_0603_5% 2 2 2 2

0.1U_0201_10V6K
1 RH100 @

CH40

@
20200114
3 - RH100 Change to R-short 3
2

1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE

+1.05VALW_PCH +3VALW_HDA FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_VCCAZPLL RH101 2 @ 1 0_0402_5%

RH102 1 @ 2 0_0402_5%
1P_0402_50V8

1P_0402_50V8
1 1
1P_0402_50V8

CH41

CH42
1P_0402_50V8

1 1
2 2 reserved for cnvi
CH43

CH44

@ @
2 2 reserve filter follow CRB +1.8VALW_PRIM +1.8VALW_PRIM
@ @
8/21
1-3MM FROM PACKAGE EDGE

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1

CH52

CH53
+1.05VALW_VCCAMPHYPLL
2 2
1 2 0_0402_5%

@
RH103 @
22U_0603_6.3V6M

1U_0201_6.3V6M

1 1
CH46
CH45

+RTCBATTchange to 10k near AG19/AG20

2 2 DH2 +RTCVCC +RTCBATT
LC filter close to pin CONN@
RH104 2 1 1K_0402_5% 2 JRTC1
1uF 1-3MM FROM PACKAGE EDGE +CHGRTC 1 1
3 2 1
2
4 4
3
BAV70W_SOT323-3 4 GND
1U_0201_6.3V6M

0.1U_0201_10V6K

1 1 GND
+1.05VALW_XTAL
CH48
CH47

ACES_50271-0020N-001
RH105 1 @ 2 0_0402_5%
2 2 SP02000RO00
22U_0603_6.3V6M

1
Security Classification Compal Secret Data
Compal Electronics, Inc.
CH49

2 Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
PCH(7/8)Power R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FH51M M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 20 of 112
A B C D E
 A B C D E

CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 VSS VSS VSS VSS RSVD6 1
A3 AL21 BG4 M49 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <10>
AA20 AN16 D30 P46 AM5
VSS VSS VSS VSS PRDY# CPU_XDP_TRST# XDP_PRDY# <10>
AA25 AN34 D33 R12 AM4 CPU_XDP_TRST# <10>
AA27 VSS VSS AN38 D8 VSS VSS R16 CPU_TRST# AK3 PCH_TRIGOUTRH106 1 2 30_0402_5% PCH_TRIGOUT_R
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <13>
AA28 AP4 E10 R26 AK2
AA30 VSS VSS AP46 E13 VSS VSS R29 TRIGGER_IN CPU_TRIGOUT_R <13>
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC17 VSS VSS AT21 E33 VSS VSS T4
AC33 VSS VSS AT24 E35 VSS VSS T49
AC38 VSS VSS AT26 E40 VSS VSS T5
AC4 VSS VSS AT29 E42 VSS VSS T7
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AF25 VSS VSS BA14 J47 VSS VSS W28
VSS VSS VSS VSS

www.laptoprepairsecrets.com
AF28 BA44 J48 W30
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PCH(8/8)GND/RSVD
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
FH51M M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 21 of 112
A B C D E
 5 4 3 2 1

CHANNEL-A ( Interleaved Memory ) JDIMM1A

> BOT : Reverse type (4mm) <7>

<7>
<7>
<7>
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
137
139
138
140
CK0(T)
CK0#(C)
CK1(T)
REVERSE
DQ0
DQ1
DQ2
8
7
20
21
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3

> Non-ECC SO-DIMM

CK1#(C) DQ3 4 DDR_A_D4
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<7> DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D6
110 16
<7> DDR_A_CKE1 CKE1 DQ6 DDR_A_D7
17
<7> DDR_A_D[0..15] DDR_A_CS#0 149 DQ7 13 DDR_A_DQS0
<7> DDR_A_CS#0 DDR_A_CS#1 157 S0# DQS0(T) 11 DDR_A_DQS#0 DDR_A_DQS0 <7>
<7> DDR_A_D[16..31] <7> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <7>
162
D S2#/C0 DDR_A_D8 D
165 28
<7> DDR_A_D[32..47] S3#/C1 DQ8 DDR_A_D9
29
DDR_A_ODT0 155 DQ9 41 DDR_A_D10
<7> DDR_A_D[48..63] <7> DDR_A_ODT0 DDR_A_ODT1 161 ODT0 DQ10 42 DDR_A_D11
<7> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12
24
JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
<7> DDR_A_BG0 DDR_A_BG1 BG0 DQ13 DDR_A_D14
REVERSE 113 38
111 141 <7> DDR_A_BG1 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D15
+1.2V_VDDQ 112 VDD1 VDD11 142 +1.2V_VDDQ <7> DDR_A_BA0 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <7> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <7>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <7>
VDD4 VDD14 <7> DDR_A_MA0 DDR_A_MA1 A0 DDR_A_D16
123 153 133 50
VDD5 VDD15 <7> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
124 154 132 49
129 VDD6 VDD16 159 <7> DDR_A_MA2 DDR_A_MA3 131 A2 DQ17 62 DDR_A_D18
VDD7 VDD17 <7> DDR_A_MA3 DDR_A_MA4 A3 DQ18 DDR_A_D19
130 160 128 63
135 VDD8 VDD18 163 <7> DDR_A_MA4 DDR_A_MA5 126 A4 DQ19 46 DDR_A_D20
+3VS 136 VDD9 VDD19 <7> DDR_A_MA5 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21
VDD10 <7> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D22
122 58
255 258 <7> DDR_A_MA7 DDR_A_MA8 125 A7 DQ22 59 DDR_A_D23
VDDSPD VTT +0.6VS_VTT <7> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
164 257 <7> DDR_A_MA9 DDR_A_MA10 146 A9 DQS2(T) 53 DDR_A_DQS#2 DDR_A_DQS2 <7>

0.1U_0201_10V6K

2.2U_0402_6.3V6M
+0.6V_DDR_VREFCA VREFCA VPP1 259 +2.5V <7> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <7>
2 2 VPP2 <7> DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D24
119 70

CD1
<7> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D25
1 99 158 71

CD2
VSS VSS <7> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 VSS VSS <7> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D27
SPD ADDRESS FOR CHANNEL A : 5
6 VSS VSS
103
106 <7>
<7>
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_MA16_RAS#
156
152 A15_CAS# DQ27
84
66 DDR_A_D28
9 VSS VSS 107 A16_RAS# DQ28 67 DDR_A_D29
WRITE ADDRESS: 0XA0 10 VSS VSS 167 DDR_A_ACT# 114 DQ29 79 DDR_A_D30
PLACE NEAR TO PIN 14 VSS VSS 168
<7> DDR_A_ACT# ACT# DQ30 80 DDR_A_D31
READ ADDRESS: 0XA1 15 VSS
VSS
VSS
VSS
171
<7> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
PARITY
DQ31
DQS3(T)
76 DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <7>
18 172 116 74
SA0 = 0; SA1 = 0; SA2 = 0. 19 VSS
VSS
VSS
VSS
175
+1.2V_VDDQ RD7 2 <7> DDR_A_ALERT#
1 240_0402_1% DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134 ALERT#
EVENT#
DQS3#(C)
DDR_A_D32
DDR_A_DQS#3 <7>
22 176 108 174
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23 VSS
VSS
VSS
VSS
180
<18,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173 DDR_A_D33
DDR_A_D34 C
26 181 187
STRETCH GOAL IS 2133 MT/S 27
30
VSS
VSS
VSS
VSS
184
185 <18,24> D_CK_SDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D35
DDR_A_D36
VSS VSS <18,24> D_CK_SCLK SCL DQ36 169 DDR_A_D37
31 188
35 VSS VSS 189 166 DQ37 183 DDR_A_D38
36 VSS VSS 192 260 SA2 DQ38 182 DDR_A_D39
Layout Note: Layout Note: VSS VSS SA1 DQ39 DDR_A_DQS4
39 193 256 179
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <7>
VSS VSS DQS4#(C) DDR_A_DQS#4 <7>
43 197
44 VSS VSS 201 92 195 DDR_A_D40
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D41
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS_VTT 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43 DDR_A_D44
52 209 88 191
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D45
57 VSS VSS 213 For ECC DIMM 100 CB5_NC DQ45 203 DDR_A_D46
VSS VSS CB6_NC DQ46

www.laptoprepairsecrets.com
60 214 104 204 DDR_A_D47
10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M
10U_0402_6.3V6M

1 1 1 1 1 1 1 VSS VSS CB7_NC DQ47 DDR_A_DQS5

61 217 97 200
64 VSS VSS 218 95 DQS8(T) DQS5(T) 198 DDR_A_DQS#5 DDR_A_DQS5 <7>
CD3

CD4

CD5

CD6

CD7

CD8

CD9

VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <7>

65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
77 VSS VSS 231 75 DM2#/DBI2# DQ51 211 DDR_A_D52
78 VSS VSS 234 178 DM3#/DBI3# DQ52 212 DDR_A_D53
81 VSS VSS 235 199 DM4#/DBI4# DQ53 224 DDR_A_D54
82 VSS VSS 238 220 DM5#/DBI5# DQ54 225 DDR_A_D55
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <7>
86 243 96 219
89 VSS VSS 244 DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <7>
90 VSS VSS 247
Layout Note: VSS VSS 2
93 248 ESD@
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 CD10 237 DDR_A_D56
98 VSS VSS 252 DQ56 236 DDR_A_D57
VSS VSS 33P_0201_50V8J DQ57
B 1 249 DDR_A_D58 B
262 261 DQ58 250 DDR_A_D59
GND GND DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
246
0.1uF*1 CONN@
PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) 240 DDR_A_DQS#7 DDR_A_DQS7 <7>
2 2 DQS7#(C) DDR_A_DQS#7 <7>
CD11 CD12 Part Number: SP07001CY00
0.1U_0201_10V6K 2.2U_0402_6.3V6M
1 1 Part Value: S SOCKET LOTES ADDR0206-P001A 260P DDR4 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ

DIMM Side CPU Side

2
Layout Note: RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Place near JDIMM1 2 1K_0402_1%
CD13 @

1
0.1U_0201_10V6K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 1 signals
330uF*1 2
+1.2V_VDDQ
2

CD15
RD10 CD14 0.022U_0402_16V7K
2
1K_0402_1% 0.1U_0201_10V6K
1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

2
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

+
CD16

CD17

CD18

CD19

CD20

CD21

CD22

CD23

A CD32 RD11 A
330U_D2_2V_Y
CD24

CD25

CD26

CD27

CD28

CD29

CD30

CD31

24.9_0402_1%
2 2 2 2 2 2 2 @ 2 @ 2 2 2 2 2 2 2 2 2

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
DDRIV_CHA: DIMM0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 23 of 112
5 4 3 2 1
 5 4 3 2 1

CHANNEL-B ( Interleaved Memory )

> BOT : STD type (4mm) <8> DDR_B_CLK0
DDR_B_CLK0
DDR_B_CLK#0
137
139
JDIMM2A
CK0(T)
STD
DQ0
8
7
DDR_B_D0
DDR_B_D1

> Non-ECC SO-DIMM

<8> DDR_B_CLK#0 DDR_B_CLK1 CK0#(C) DQ1 DDR_B_D2
138 20
<8> DDR_B_D[0..15] <8> DDR_B_CLK1 DDR_B_CLK#1 CK1(T) DQ2 DDR_B_D3
140 21
<8> DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D4
4
<8> DDR_B_D[16..31] DDR_B_CKE0 DQ4 DDR_B_D5
109 3
<8> DDR_B_CKE0 DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D6
<8> DDR_B_D[32..47] <8> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D7
DDR_B_CS#0 149 DQ7 13 DDR_B_DQS0
D <8> DDR_B_D[48..63] <8> DDR_B_CS#0 DDR_B_CS#1 S0# DQS0(T) DDR_B_DQS#0 DDR_B_DQS0 <8> D
157 11
<8> DDR_B_CS#1 S1# DQS0#(C) DDR_B_DQS#0 <8>
JDIMM2B 162
STD 165 S2#/C0 28 DDR_B_D8
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ 112 VDD1 VDD11 142
+1.2V_VDDQ DDR_B_ODT0 155 DQ9 41 DDR_B_D11
117 VDD2 VDD12 147 <8> DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D15
VDD3 VDD13 <8> DDR_B_ODT1 ODT1 DQ11 DDR_B_D14
118 148 24
123 VDD4 VDD14 153 DDR_B_BG0 115 DQ12 25 DDR_B_D10
124 VDD5 VDD15 154 <8> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
VDD6 VDD16 <8> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
129 159 150 37
130 VDD7 VDD17 160 <8> DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1
VDD8 VDD18 <8> DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS#1 DDR_B_DQS1 <8>
135 163 32
+3VS VDD9 VDD19 DDR_B_MA0 DQS1#(C) DDR_B_DQS#1 <8>
136 144
VDD10 <8> DDR_B_MA0 DDR_B_MA1 133 A0 50 DDR_B_D16
<8> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <8> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
164 257 <8> DDR_B_MA3 DDR_B_MA4 128 A3 DQ18 63 DDR_B_D20

0.1U_0201_10V6K

2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_B_MA4 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D22
2 2 VPP2 <8> DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D18
127 45

CD33
<8> DDR_B_MA6 DDR_B_MA7 A6 DQ21 DDR_B_D23
1 99 122 58

CD34
2 VSS VSS 102 <8> DDR_B_MA7 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D21
1 1 5 VSS VSS 103 <8> DDR_B_MA8 DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS2
SPD ADDRESS FOR CHANNEL B : 6
9
VSS
VSS
VSS
VSS
106
107
<8>
<8>
DDR_B_MA9
DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120
A9
A10_AP
DQS2(T)
DQS2#(C)
53 DDR_B_DQS#2 DDR_B_DQS2
DDR_B_DQS#2
<8>
<8>
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<8>
<8>
DDR_B_MA11
DDR_B_MA12
DDR_B_MA12
DDR_B_MA13
119
158
A11
A12 DQ24
70
71
DDR_B_D30
DDR_B_D25
<8> DDR_B_MA13
READ ADDRESS: 0XA3 15
18
VSS
VSS
VSS
VSS
171
172 <8> DDR_B_MA14_WE#
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
151
156
A13
A14_WE#
DQ25
DQ26
83
84
DDR_B_D26
DDR_B_D24
VSS VSS <8> DDR_B_MA15_CAS# A15_CAS# DQ27
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS VSS
175
176
<8> DDR_B_MA16_RAS#
DDR_B_MA16_RAS# 152
A16_RAS# DQ28
66
67
DDR_B_D28
DDR_B_D27
VSS VSS DDR_B_ACT# DQ29 DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26 VSS VSS
180
181 <8> DDR_B_ACT#
114
ACT# DQ30
79
80 DDR_B_D31
VSS VSS DDR_B_PAR DQ31 DDR_B_DQS3
STRETCH GOAL IS 2133 MT/S 27
30 VSS VSS
184
185 <8> DDR_B_PAR DDR_B_ALERT#
143
116 PARITY DQS3(T)
76
74 DDR_B_DQS#3 DDR_B_DQS3 <8>
VSS VSS <8> DDR_B_ALERT# DIMM3_CHB_EVENT# ALERT# DQS3#(C) DDR_B_DQS#3 <8>
31 188 2 RD18 1 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
36 VSS VSS 192 <18,23> DDR_DRAMRST#_R RESET# DQ32 173 DDR_B_D35
Layout Note: Layout Note: VSS VSS DQ33 DDR_B_D36
39 193 187
Place near JDIMM3.257,259 Place near JDIMM3.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <18,23> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
VSS VSS <18,23> D_CK_SCLK SCL DQ36 DDR_B_D38
44 201 169
47 VSS VSS 202 +3VS 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <8>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <8>
57 VSS VSS 213 92 195 DDR_B_D40
60 VSS VSS 214 91 CB0_NC DQ40 194 DDR_B_D41
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 VSS VSS CB1_NC DQ41 DDR_B_D42

61 217 101 207
64 VSS VSS 218 105 CB2_NC DQ42 208 DDR_B_D43
CD35

CD36

CD37

CD38

CD39

CD40

CD41

65 VSS VSS 222 88 CB3_NC DQ43 191 DDR_B_D44

VSS VSS CB4_NC DQ44

www.laptoprepairsecrets.com
2 2 2 2 2 2 2 68 223 87 190 DDR_B_D45
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D46
72 VSS VSS 227 104 CB6_NC DQ46 204 DDR_B_D47
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
77 VSS VSS 231 95 DQS8(T) DQS5(T) 198 DDR_B_DQS#5 DDR_B_DQS5 <8>
VSS VSS 234 DQS8#(C) DQS5#(C) DDR_B_DQS#5 <8>
78
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D50
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D55
89 VSS VSS 244 75 DM2#/DBI2# DQ51 211 DDR_B_D51
90 VSS VSS 247 178 DM3#/DBI3# DQ52 212 DDR_B_D54
93 VSS VSS 248 199 DM4#/DBI4# DQ53 224 DDR_B_D49
94 VSS VSS 251 220 DM5#/DBI5# DQ54 225 DDR_B_D53
Layout Note: VSS VSS DM6#/DBI6# DQ55 DDR_B_DQS6
98 252 241 221
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 <8>
FROM THE JDIMM3 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <8>
262 261
GND GND

B LOTES_ADDR0205-P001A 237 DDR_B_D61 B

DQ56 236 DDR_B_D57
CONN@ DQ57 DDR_B_D60
+0.6V_DDRB_VREFCA 2.2uF*1 249
DQ58 250 DDR_B_D56
0.1uF*1 DQ59 232 DDR_B_D62
Part Number: SP07001HW00 DQ60 233 DDR_B_D59
2 2
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD 261
GND1
DQ61
DQ62
245 DDR_B_D63
CD42 CD43 262 246 DDR_B_D58
GND2 DQ63 242 DDR_B_DQS7
0.1U_0201_10V6K 2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <8>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
DQS7#(C) DDR_B_DQS#7 <8>

LOTES_ADDR0205-P001A
CONN@

Layout Note:
2
DIMM Side CPU Side

2
Place near JDIMM3 CD44 @
0.1U_0201_10V6K RD19
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ

1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2

2 1
signals
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

RD21 CD45
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD51 1K_0402_1% 0.1U_0201_10V6K CD55

1
CD46

CD47

CD48

CD49

CD50

CD52

CD53

CD54

0.1U_0201_10V6K 0.022U_0402_16V7K
1 2
CD56

CD59

CD62
CD57

CD58

CD60

CD61

CD63

A A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2
@ @ RD22
24.9_0402_1%

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIV_CHB: DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 24 of 112
5 4 3 2 1
 A B C D E

N18P-G61/G62
+1.8VSDGPU_AON
UV1
VGA_OVERT# RV327 2 VGA@ 1 10K_0201_5%
UV1A VGAG61@ VGA_ALERT# RV328 2 VGA@ 1 10K_0201_5%
FRM_LCK# RV329 2 1
S IC N18P-G61-MP2-A1 BGA 960P GPU ACIN_BUF
VGA@ 10K_0201_5%
AN12 Part 1 of 7 SA0000CZO50 RV330 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P0 AM12 PEX_RX0 P6 GPU_EVENT#_1 RV331 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N0 PEX_RX0_N GPIO0 GC6_FB_EN1V8 NVVDD_VID <96> 1.8VSDGPU_MAIN_EN
AN14 M3 VGA@ UV1 RV1 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P1 PEX_RX1 GPIO1 L6 GPU_EVENT#_1 NVVDD_PSI
AM14 DV8 2 1 RV4 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N1 AP14 PEX_RX1_N GPIO2 P5 GPU_EVENT# <19>
VGAG62@
<9> PEG_CTX_C_GRX_P2 AP15 PEX_RX2 GPIO3 P7 1.8VSDGPU_MAIN_EN SYS_PEX_RST_MON#
RB751S40T1G_SOD523-2 S IC N18P-G62-A1 BGA 960P GPU RV332 2 N17P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N2 PEX_RX2_N GPIO4 FRM_LCK# GPU_PEX_RST_HOLD#
AN15 L7 SA0000CZP30 RV82 2 N17P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P3 PEX_RX3 GPIO5
AM15 M7
<9> PEG_CTX_C_GRX_N3 PEX_RX3_N GPIO6 NVVDD_PSI <96> FBVDDQ_PSI
AN17 N8 RV335 2 N18P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P4 AM17 PEX_RX4 GPIO7 L3 GPIO22_OC_WARN# RV386 2 N18P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N4 PEX_RX4_N GPIO8 VGA_ALERT# VRAM_VDD_CTL <100>
AP17 M2
<9> PEG_CTX_C_GRX_P5 PEX_RX5 GPIO9 VRAM_VREF_CTL
AP18 L1
1 <9> PEG_CTX_C_GRX_N5 PEX_RX5_N GPIO10 VGA_I2CS_SDA 1
AN18 M5 RV2 1 VGA@ 2 1.8K_0402_1%
<9> PEG_CTX_C_GRX_P6 AM18 PEX_RX6 GPIO11 N3 ACIN_BUF VGA_I2CS_SCL
DV2 2 1 RV3 1 VGA@ 2 1.8K_0402_1%
<9> PEG_CTX_C_GRX_N6 PEX_RX6_N GPIO12 DGPU_AC_DETECT <19,58,85>

GPIO
AN20 M4 VGA@
<9> PEG_CTX_C_GRX_P7 PEX_RX7 GPIO13 VGA_I2CC_SDA
AM20 N4 RB751S40T1G_SOD523-2 RV5 1 VGA@ 2 2K_0402_5%
<9> PEG_CTX_C_GRX_N7 PEX_RX7_N GPIO14 VGA_I2CC_SCL
AP20 P2 RV6 1 VGA@ 2 2K_0402_5%
<9> PEG_CTX_C_GRX_P8 PEX_RX8 GPIO15 SYS_PEX_RST_MON#
AP21 R8
<9> PEG_CTX_C_GRX_N8 PEX_RX8_N GPIO16
AN21 M6
<9> PEG_CTX_C_GRX_P9 PEX_RX9 GPIO17 GPU_DP0_HPD#
AM21 R1
<9> PEG_CTX_C_GRX_N9 AN23 PEX_RX9_N GPIO18 P3 NVVDD_PSI
20191016 RV398 2 @ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P10 PEX_RX10 GPIO19 - DP HPD change to GPIO18 for Port E
AM23 P4
<9> PEG_CTX_C_GRX_N10 PEX_RX10_N GPIO20 VRAM_VREF_CTL
AP23 P1 RV333 2 VGA@ 1 100K_0201_5%
<9> PEG_CTX_C_GRX_P11 PEX_RX11 GPIO21 GC6_FB_EN1V8
AP24 P8 RV334 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N11 PEX_RX11_N GPIO22 GPU_PEX_RST_HOLD# GPIO22_OC_WARN# <36>
AN24 T8
<9> PEG_CTX_C_GRX_P12 AM24 PEX_RX12 GPIO23 L2 GPU_PEX_RST_HOLD# RV396 2 N18P@ 1 100K_0201_5%
<9> PEG_CTX_C_GRX_N12 AN26 PEX_RX12_N GPIO24 R4
<9> PEG_CTX_C_GRX_P13 PEX_RX13 GPIO25 FBVDDQ_PSI <100>
AM26 R5
<9> PEG_CTX_C_GRX_N13 AP26 PEX_RX13_N GPIO26 U3 HDMI_HPD_GPU# GPIO26_FP_FUSE <37>
<9> PEG_CTX_C_GRX_P14 AP27 PEX_RX14 GPIO27
<9> PEG_CTX_C_GRX_N14 AN27 PEX_RX14_N +1.8VSDGPU_MAIN +1.8VSDGPU_MAIN
<9> PEG_CTX_C_GRX_P15 PEX_RX15
AM27
<9> PEG_CTX_C_GRX_N15 PEX_RX15_N
QV13A N18P@ QV2A VGA@

5
AK14 AN9 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
<9> PEG_CRX_C_GTX_P0 PEX_TX0 ADC_IN ADC_IN_P <36>
AJ14 AM9
OVR-M ADC_IN_N

G
<9> PEG_CRX_C_GTX_N0 PEX_TX0_N ADC_IN_N <36> VGA_I2CC_SCL VGA_I2CS_SCL
AH14 4 3 4 3
<9> PEG_CRX_C_GTX_P1 PEX_TX1 +1.8VSDGPU_AON VGA_I2CC_SCL_PWR <96> PCH_SML1CLK <18,58,66>
AG14

D
<9> PEG_CRX_C_GTX_N1 PEX_TX1_N
AK15
<9> PEG_CRX_C_GTX_P2 PEX_TX2 TS_AVDD RV385 1 N18P@ 2 0_0402_5%
<9> PEG_CRX_C_GTX_N2 AJ15 AG10 QV13B N18P@ QV2B VGA@
PEX_TX2_N TS_AVDD

2
AL16 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
<9> PEG_CRX_C_GTX_P3 PEX_TX3
AK16 Thermal Sensor CV377 1 2 1U_0201_6.3V6M

G
<9> PEG_CRX_C_GTX_N3 PEX_TX3_N VGA_I2CC_SDA VGA_I2CS_SDA
<9> PEG_CRX_C_GTX_P4 AK17 1 6 VGA_I2CC_SDA_PWR <96> 1 6 PCH_SML1DATA <18,58,66>
AJ17 PEX_TX4 N18P@

D
<9> PEG_CRX_C_GTX_N4 PEX_TX4_N
AH17
<9> PEG_CRX_C_GTX_P5 PEX_TX5
AG17 AK9
<9> PEG_CRX_C_GTX_N5 PEX_TX5_N RES

RES
AK18 AL10 27MHZ_10PF_XRCGB27M000F2P18R0
<9> PEG_CRX_C_GTX_P6 PEX_TX6 RES
<9> PEG_CRX_C_GTX_N6 AJ18 AL9 RV80 VGA@ XV1
AL19 PEX_TX6_N RES AP8 470_0402_1%
<9> PEG_CRX_C_GTX_P7 PEX_TX7 RES
AK19 XTALOUT 2 1 XTALOUT_R 1 3 XTALIN
PCI EXPRESS

<9> PEG_CRX_C_GTX_N7 PEX_TX7_N 1 3

AK20
<9> PEG_CRX_C_GTX_P8 PEX_TX8 +1.8VSDGPU_AON NC NC
AJ20 AP9 1 1
<9> PEG_CRX_C_GTX_N8 PEX_TX8_N TS_VREF
<9> PEG_CRX_C_GTX_P9 AH20
AG20 PEX_TX9 unused pin PH 2K to 1V8AON CV1 VGA@ VGA@ 2 4 CV2 VGA@
2 <9> PEG_CRX_C_GTX_N9 PEX_TX9_N 2
AK21 R7 RV86 1 VGA@ 2 2K_0402_5% 18P_0402_50V8J 18P_0402_50V8J
<9> PEG_CRX_C_GTX_P10 PEX_TX10 I2CB_SCL 2 2
AJ21 R6 RV85 1 VGA@ 2 2K_0402_5%
<9> PEG_CRX_C_GTX_N10 PEX_TX10_N I2CB_SDA
<9> PEG_CRX_C_GTX_P11 AL22
AK22 PEX_TX11 R2 VGA_I2CC_SCL +1.8VSDGPU_MAIN
Crystals must have a max ESR of 80 ohm
I2C

<9> PEG_CRX_C_GTX_N11 PEX_TX11_N I2CC_SCL VGA_I2CC_SDA

AK23 R3
<9> PEG_CRX_C_GTX_P12 PEX_TX12 I2CC_SDA
AJ23 SM01000JX00
<9> PEG_CRX_C_GTX_N12 PEX_TX12_N VGA_I2CS_SCL +GPU_PLLVDD
AH23 T4 3000ma 33ohm@100mhz DCR 0.04
<9> PEG_CRX_C_GTX_P13 PEX_TX13 I2CS_SCL VGA_I2CS_SDA +1.8VSDGPU_AON +1.8VSDGPU_AON
AG23 T3
<9> PEG_CRX_C_GTX_N13 PEX_TX13_N I2CS_SDA
<9> PEG_CRX_C_GTX_P14
AK24 VGA@
AJ24 PEX_TX14 LV1 1 2
<9> PEG_CRX_C_GTX_N14 PEX_TX14_N

1
<9> PEG_CRX_C_GTX_P15 AL25 TAI-TECH HCB1608KF-330T30 VGA@ VGA@
AK25 PEX_TX15 H26

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

4.7U_0402_6.3V6M

22U_0603_6.3V6M
<9> PEG_CRX_C_GTX_N15 1 1 1 1 1 1 SM01000JX00 CG340 RG180
PEX_TX15_N GPCPLL_AVDD 2 1 +1.8VSDGPU_AON

CV195 VGA@
CV4

CV5

CV6

CV3
CV42 10K_0201_5%
AD8
AJ11 XSN_PLLVDD VGA@ VGA@ 0.1U_0201_10V6K
No support S0ix PEX_WAKE# HDMI_HPD_GPU#

2
2 2 2 2 2 2

5
AE8

VGA@

VGA@

VGA@
DP@
AL13 SP_PLLVDD CG341
<15> CLK_PEG_VGA Near

VCC
PEX_REFCLK

6
AK13 AD7 1 2 1 +1.8VSDGPU_AON
<15> CLK_PEG_VGA# VGA_CLKREQ#_R AK12 PEX_REFCLK_N VID_PLLVDD GPU <16,40> HDMI_HPD_PCH IN B 4 2
Near Near Near Near G
D
QV5B
PEX_CLKREQ_N PLTRST_VGA#_1V8 OUT Y

www.laptoprepairsecrets.com
+1.8VSDGPU_AON 2 PJT138KA 2N SOT363-6 0.1U_0201_10V6K
H26 AD7 AD8 AE8 1

GND
S
IN A

1
RV7 1 VGA@ 2 10K_0201_5% AJ26 H3 XTALIN @ VGA@ DP@
CLK

NC XTAL_IN

1
AK26 H2 XTALOUT CV201 RG2840

VCC
NC XTAL_OUT VGA@ 0.1U_0201_10V6K DP0_HPD_PCH 1 10K_0402_5%
PLTRST_VGA#_1V8 XTAL_OUTBUFF <16,39> DP0_HPD_PCH IN B

3
AJ12 J4 RV9 1 VGA@ 2 100K_0201_5% UG28 2 4 2
1 2 PEX_TREMP AP29 PEX_RST_N XTAL_OUTBUFF H1 XTAL_SSIN RV11 1 VGA@ 2 10K_0201_5% NL17SZ08DFT2G_SC70-5 PLTRST_VGA#_1V8 2 OUT Y Gate

GND
PEX_TERMP EXT_REFCLK_FL IN A GPU_DP0_HPD#

2
1
RV10 VGA@ Drain
2.49K_0402_1% 3 DP@
Source QG5

3
DP@ UG29
RV10 as close as possible to GPU N18P-G0_FCBGA960~D NL17SZ08DFT2G_SC70-5 LBSS139WT1G_SC70-3
@

+1.8VSDGPU_AON

20190906 PU at PCH side

2
- RV83 change to pop (VGA@)
- CV226 change to unpop VGA_CLKREQ# <15>
RV83 VGA@
10K_0201_5%

3
QV5A
ALL_GPWRGD 5

1
3 G
D
PJT138KA 2N SOT363-6 3
1 S VGA@
@

4
CV226
0.1U_0201_10V6K
+1.8VSDGPU_AON 2 VGA_CLKREQ#_R

RV100 1 VGA@2 10K_0201_5% PLTRST_VGA#_1V8

0.1U_0201_10V6K 2 1 CV200 +3VS

@ UV51
0.1U_0201_10V6K 2 1 CV542 VGA_OVERT# VGA@
@ 0.1U_0201_10V6K 2 1 CV541 1 20
1.8VSDGPU_MAIN_EN VDD 1V8_MAIN_EN 1.8VSDGPU_MAIN_EN3V3 <37>
0.1U_0201_10V6K 2 1 CV543
@
1.8VSDGPU_MAIN_EN 2 19 PLTRST_VGA#_1V8
1V8_MAIN_EN_GPU PEGX_RST#
<19> DGPU_PWR_EN 3 18 1VSDGPU_EN <37,102>
DGPU_PWR_EN PEX_VDD_EN
GC6_FB_EN1V8 4
GC6_FB_EN_GPU 17
FB_VDD_EN 1.35VSDGPU_EN <37,100>
5
<102> PG_1VSDGPU PEX_VDD_PG
6 16
<19> GC6_FB_EN3V3 GC6_FB_EN 3V3_SYS_EN 3VSDGPU_EN <37,39>

<100> 1.35VSDGPU_PG 7
FB_VDD_PG 15 ALL_GPWRGD
VGA_OVERT# 8 ALL_GPU_PWR_OK
<29> VGA_OVERT# OVERT#_GPU
14 GPU_OVERT# <58>
OVERT#
9 13
<19> DGPU_HOLD_RST# DGPU_HOLD_RST# 1V8_AON_EN 1V8_AON_EN <37>
12 NVVDD1_EN <37,96>
10 NVVDD_EN
<16,58,66> PLT_RST# PLT_RST#

11
GND

4 SLG4U43589VTR_STQFN20_3X2 4
VGA@
SA0000DH100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(1/11)-G61/G62 PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 27 of 112
A B C D E
 A B C D E

UV1B UV1C
<32> FBA_D[63..0] FBA_CMD[33..0] <32> <33> FBB_D[63..0] FBB_CMD[33..0] <33>
Part 2 of 7 Part 3 of 7
FBA_D0 L28 U30 FBA_CMD0 FBB_D0 G9 D13 FBB_CMD0
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_CMD1 FBB_D1 E9 FBB_D0 FBB_CMD0 E14 FBB_CMD1
FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_CMD2 FBB_D2 G8 FBB_D1 FBB_CMD1 F14 FBB_CMD2
FBA_D3 M28 FBA_D2 FBA_CMD2 R34 FBA_CMD3 FBB_D3 F9 FBB_D2 FBB_CMD2 A12 FBB_CMD3
FBA_D4 N31 FBA_D3 FBA_CMD3 R33 FBA_CMD4 FBB_D4 F11 FBB_D3 FBB_CMD3 B12 FBB_CMD4
FBA_D5 P29 FBA_D4 FBA_CMD4 U32 FBA_CMD5 FBB_D5 G11 FBB_D4 FBB_CMD4 C14 FBB_CMD5
FBA_D6 R29 FBA_D5 FBA_CMD5 U33 FBA_CMD6 FBB_D6 F12 FBB_D5 FBB_CMD5 B14 FBB_CMD6
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_CMD7 FBB_D7 G12 FBB_D6 FBB_CMD6 G15 FBB_CMD7
FBA_D8 J28 FBA_D7 FBA_CMD7 V28 FBA_CMD8 FBB_D8 G6 FBB_D7 FBB_CMD7 F15 FBB_CMD8
1 FBA_D9 FBA_D8 FBA_CMD8 FBA_CMD9 FBB_D9 FBB_D8 FBB_CMD8 FBB_CMD9 1
H29 V29 F5 E15
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_CMD10 FBB_D10 E6 FBB_D9 FBB_CMD9 D15 FBB_CMD10
FBA_D11 H28 FBA_D10 FBA_CMD10 U34 FBA_CMD11 FBB_D11 F6 FBB_D10 FBB_CMD10 A14 FBB_CMD11
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_CMD12 FBB_D12 F4 FBB_D11 FBB_CMD11 D14 FBB_CMD12
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_CMD13 FBB_D13 G4 FBB_D12 FBB_CMD12 A15 FBB_CMD13
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CMD14 FBB_D14 E2 FBB_D13 FBB_CMD13 B15 FBB_CMD14
FBA_D15 F30 FBA_D14 FBA_CMD14 Y32 FBA_CMD15 FBB_D15 F3 FBB_D14 FBB_CMD14 C17 FBB_CMD15
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CMD16 FBB_D16 C2 FBB_D15 FBB_CMD15 D18 FBB_CMD16
FBA_D17 D32 FBA_D16 FBA_CMD16 AA29 FBA_CMD17 FBB_D17 D4 FBB_D16 FBB_CMD16 E18 FBB_CMD17
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_CMD18 FBB_D18 D3 FBB_D17 FBB_CMD17 F18 FBB_CMD18
FBA_D19 C33 FBA_D18 FBA_CMD18 AC34 FBA_CMD19 FBB_D19 C1 FBB_D18 FBB_CMD18 A20 FBB_CMD19
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_CMD20 FBB_D20 B3 FBB_D19 FBB_CMD19 B20 FBB_CMD20
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_CMD21 FBB_D21 C4 FBB_D20 FBB_CMD20 C18 FBB_CMD21
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_CMD22 FBB_D22 B5 FBB_D21 FBB_CMD21 B18 FBB_CMD22
FBA_D23 H32 FBA_D22 FBA_CMD22 Y28 FBA_CMD23 FBB_D23 C5 FBB_D22 FBB_CMD22 G18 FBB_CMD23
FBA_D24 P34 FBA_D23 FBA_CMD23 Y29 FBA_CMD24 FBB_D24 A11 FBB_D23 FBB_CMD23 G17 FBB_CMD24
FBA_D25 P32 FBA_D24 FBA_CMD24 W31 FBA_CMD25 FBB_D25 C11 FBB_D24 FBB_CMD24 F17 FBB_CMD25
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_CMD26 FBB_D26 D11 FBB_D25 FBB_CMD25 D16 FBB_CMD26
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_CMD27 FBB_D27 B11 FBB_D26 FBB_CMD26 A18 FBB_CMD27
FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_CMD28 FBB_D28 D8 FBB_D27 FBB_CMD27 D17 FBB_CMD28
FBA_D29 FBA_D28 FBA_CMD28 FBA_CMD29 FBB_D29 FBB_D28 FBB_CMD28 FBB_CMD29

MEMORY INTERFACE B
L34 Y34 A8 A17
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CMD30 FBB_D30 C8 FBB_D29 FBB_CMD29 B17 FBB_CMD30
FBA_D31 L33 FBA_D30 FBA_CMD30 V31 FBA_CMD31 FBB_D31 B8 FBB_D30 FBB_CMD30 E17 FBB_CMD31
FBA_D32 FBA_D31 FBA_CMD31 FBA_CMD32 add for GDDR6 +1.35VSDGPU FBB_D32 FBB_D31 FBB_CMD31 FBB_CMD32 add for GDDR6 +1.35VSDGPU
AG28 R28 F24 G14
FBA_D33 AF29 FBA_D32 FBA_CMD32 AC28 FBA_CMD33 FBB_D33 G23 FBB_D32 FBB_CMD32 G20 FBB_CMD33
FBA_D34 AG29 FBA_D33 FBA_CMD33 R32 FBA_DEBUG0 RG2930 2 @ 1 60.4_0201_1% FBB_D34 E24 FBB_D33 FBB_CMD33 C12 FBB_DEBUG0 RG3019 2 @ 1 60.4_0201_1%
FBA_D35 AF28 FBA_D34 FBA_CMD34 AC32 FBA_DEBUG1 RG2931 2 @ 1 60.4_0201_1% FBB_D35 G24 FBB_D34 FBB_CMD34 C20 FBB_DEBUG1 RG3018 2 @ 1 60.4_0201_1%
FBA_D36 AD30 FBA_D35 FBA_CMD35 FBB_D36 D21 FBB_D35 FBB_CMD35
FBA_D37 AD29 FBA_D36 FBB_D37 E21 FBB_D36
FBA_D38 AC29 FBA_D37 FBB_D38 G21 FBB_D37
FBA_D39 AD28 FBA_D38 FBB_D39 F21 FBB_D38
FBA_D40 AJ29 FBA_D39 FBB_D40 G27 FBB_D39
FBA_D41 AK29 FBA_D40 FBB_D41 D27 FBB_D40
FBA_D42 AJ30 FBA_D41 FBB_D42 G26 FBB_D41
FBA_D43 AK28 FBA_D42 FBB_D43 E27 FBB_D42
MEMORY INTERFACE

2 FBA_D44 AM29 FBA_D43 FBB_D44 E29 FBB_D43 2

FBA_D45 AM31 FBA_D44 R30 FBB_D45 F29 FBB_D44 D12
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLKA0 <32> FBB_D46 E30 FBB_D45 FBB_CLK0 E12 FBB_CLKA0 <33>
FBA_D47 AM30 FBA_D46 FBA_CLK0_N AB31 FBA_CLKA0# <32> FBB_D47 FBB_D46 FBB_CLK0_N FBB_CLKA0# <33>
D30 E20
FBA_D48 FBA_D47 FBA_CLK1 FBA_CLKA1 <32> FBB_D48 FBB_D47 FBB_CLK1 FBB_CLKA1 <33>
AN31 AC31 A32 F20
FBA_D49 FBA_D48 FBA_CLK1_N FBA_CLKA1# <32> FBB_D49 FBB_D48 FBB_CLK1_N FBB_CLKA1# <33>
AN32 C31
FBA_D50 AP30 FBA_D49 FBB_D50 C32 FBB_D49
FBA_D51 AP32 FBA_D50 FBB_D51 B32 FBB_D50
FBA_D52 AM33 FBA_D51 K31 FBB_D52 D29 FBB_D51 F8
FBA_D53 FBA_D52 FBA_WCK01 FBA_WCK01 <32> FBB_D53 FBB_D52 FBB_WCK01 FBB_WCK01 <33>
AL31 L30 A29 E8
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK01# <32> FBB_D54 FBB_D53 FBB_WCK01_N A5 FBB_WCK01# <33>
C29
FBA_D55 FBA_D54 FBA_WCK23 FBA_WCK23 <32> FBB_D55 FBB_D54 FBB_WCK23 FBB_WCK23 <33>
AK32 J34 B29 A6
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK23# <32> FBB_D56 B21 FBB_D55 FBB_WCK23_N D24 FBB_WCK23# <33>
FBA_D57 AD32 FBA_D56 FBA_WCK45 AG31 FBA_WCK45 <32> FBB_D57 C23 FBB_D56 FBB_WCK45 D25 FBB_WCK45 <33>
FBA_D58 FBA_D57 FBA_WCK45_N FBA_WCK45# <32> FBB_D58 FBB_D57 FBB_WCK45_N FBB_WCK45# <33>
AC30 AJ34 A21 B27
FBA_D59 FBA_D58 FBA_WCK67 FBA_WCK67 <32> FBB_D59 FBB_D58 FBB_WCK67 FBB_WCK67 <33>
A

AD33 AK34 C21 C27

FBA_D59 FBA_WCK67_N FBA_WCK67# <32> FBB_D59 FBB_WCK67_N FBB_WCK67# <33>

www.laptoprepairsecrets.com
FBA_D60 AF31 FBB_D60 B24
FBA_D61 AG34 FBA_D60 FBB_D61 C24 FBB_D60
FBA_D62 AG32 FBA_D61 FBB_D62 B26 FBB_D61
FBA_D63 AG33 FBA_D62 J30 FBB_D63 C26 FBB_D62 D6
FBA_D63 FBA_WCKB01 J31 FBA_WCKB01 <32> FBB_D63 FBB_WCKB01 D7 FBB_WCKB01 <33>
<32> FBA_DBI[7..0] FBA_DBI0 P30 FBA_WCKB01_N J32 FBA_WCKB01# <32> <33> FBB_DBI[7..0] FBB_DBI0 FBB_WCKB01_N FBB_WCKB01# <33>
E11 C6
FBA_DBI1 FBA_DQM0 FBA_WCKB23 FBA_WCKB23 <32> FBB_DBI1 FBB_DQM0 FBB_WCKB23 FBB_WCKB23 <33>
F31 J33 E3 B6
FBA_DBI2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBA_WCKB23# <32> FBB_DBI2 A3 FBB_DQM1 FBB_WCKB23_N F26 FBB_WCKB23# <33>
FBA_DBI3 FBA_DQM2 FBA_WCKB45 FBA_WCKB45 <32> FBB_DBI3 FBB_DQM2 FBB_WCKB45 FBB_WCKB45 <33>
M32 AJ31 C9 E26
FBA_DBI4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 FBA_WCKB45# <32> FBB_DBI4 F23 FBB_DQM3 FBB_WCKB45_N A26 FBB_WCKB45# <33>
FBA_DBI5 AL29 FBA_DQM4 FBA_WCKB67 AJ33 FBA_WCKB67 <32> FBB_DBI5 FBB_DQM4 FBB_WCKB67 FBB_WCKB67 <33>
F27 A27
FBA_DBI6 AM32 FBA_DQM5 FBA_WCKB67_N FBA_WCKB67# <32> FBB_DBI6 FBB_DQM5 FBB_WCKB67_N FBB_WCKB67# <33>
C30
FBA_DBI7 AF34 FBA_DQM6 FBB_DBI7 A24 FBB_DQM6
FBA_DQM7 FBB_DQM7
<32> FBA_EDC[7..0] FBA_EDC0 M31 <33> FBB_EDC[7..0] FBB_EDC0 D10
FBA_EDC1 G31 FBA_DQS_WP0 +1.8VSDGPU_MAIN FBB_EDC1 D5 FBB_DQS_WP0
FBA_EDC2 E33 FBA_DQS_WP1 FBB_EDC2 C3 FBB_DQS_WP1
FBA_EDC3 M33 FBA_DQS_WP2 VGA@ FBB_EDC3 B9 FBB_DQS_WP2
FBA_EDC4 AE31 FBA_DQS_WP3 K27 +FB_PLLAVDD LV3 1 2 FBB_EDC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
3 FBA_EDC5 AK30 FBA_DQS_WP4 FB_REFPLL_AVDD TAI-TECH HCB1608KF-330T30 FBB_EDC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD 3
FBA_EDC6 AN33 FBA_DQS_WP5 FBB_EDC6 B30 FBB_DQS_WP5
1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M

4.7U_0402_6.3V6M

1U_0201_6.3V6M

4.7U_0402_6.3V6M
FBA_EDC7 FBA_DQS_WP6 1 1 1 1 SM01000JX00 FBB_EDC7 FBB_DQS_WP6 1 1
AF33 A23
CV9

CV10 VGA@

CV11 VGA@

CV379 VGA@

CV7

CV12 VGA@
FBA_DQS_WP7 U27 FBB_DQS_WP7
FBA_PLL_AVDD SM01000JX00
M30 3000ma 33ohm@100mhz DCR 0.04 D9
H30 RES 2 2 2 2 E4 RES 2 2
VGA@

VGA@
E34 RES B2 RES
M34 RES H31 FB_VREF A9 RES
AF30 RES FB_VREF D22 RES
AK31 RES D28 RES
AM34 RES Near Near RES Near
A30
AF32 RES U27 K27 B23 RES H17
RES RES

N18P-G0_FCBGA960~D N18P-G0_FCBGA960~D
@ @

change for GDDR6 +1.35VSDGPU FB_VREF +1.35VSDGPU

change for GDDR6

FBA_CMD7 FBB_CMD7
1

2 VGA@ 1 2 VGA@ 1
3.9P_0402_50V8C
CV378

49.9_0402_1%
RV393

1
RV87 10K_0402_5% CKE RV91 10K_0402_5%
FBA_CMD33 2 VGA@ 1 FBB_CMD33 2 VGA@ 1
signal
RV88 10K_0402_5% RV92 10K_0402_5%
2
N18P@

N18P@
2

FBA_CMD2 2 VGA@ 1 FBB_CMD2 2 VGA@ 1

RV89 10K_0402_5% RST RV93 10K_0402_5%
FBA_CMD18 2 VGA@ 1 FBB_CMD18 2 VGA@ 1
signal
4 RV90 10K_0402_5% RV94 10K_0402_5% 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(2/11)-G61/G62 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 28 of 112
A B C D E
 A B C D E

UV1D

Part 4 of 7
AM6
AN6 IFPA_L3 +1.8VSDGPU_AON
MULTI LEVEL
AP3 IFPA_L3_N
IFPA_L2 NC
AC6 +1.8VSDGPU_MAIN STRAPS
AN3 AJ28
AN5 IFPA_L2_N NC AJ4
AM5 IFPA_L1 NC AJ5 strap0 strap1 strap2 strap3 strap4 strap5
AL6 IFPA_L1_N NC AL11
IFPA_L0 NC

2
AK6 C15 RV26 RV27 RV78 RV31 RV32
AJ6 IFPA_L0_N NC D19 100K_0402_5% 100K_0402_5% RV28 RV29 RV30 100K_0402_5% 100K_0402_5% 100K_0402_5% RV33
AH6 IFPA_AUX_SCL NC D20 X76MIC@ @ 100K_0201_5% 100K_0201_5% 100K_0201_5% @ N17P@ N17P@ 100K_0201_5%

NC
IFPA_AUX_SDA_N NC D23 @ VGA@ @ N17P@
NC D26
NC

1
AJ9
AH9 IFPB_L3
1 IFPB_L3_N 1
AP6 V32 STRAP0
AP5 IFPB_L2 NC STRAP1 ROM_SI
AM7 IFPB_L2_N STRAP2 ROM_SO
AL7 IFPB_L1 STRAP3 ROM_SCLK
AN8 IFPB_L1_N STRAP4
AM8 IFPB_L0 STRAP5
AK8 IFPB_L0_N
IFPB_AUX_SCL

2
AL8
IFPB_AUX_SDA_N VCC_SENSE_NVVDD1

2
L4 RV34 RV35 RV79 RV39
VDD_SENSE VCC_SENSE_NVVDD1 <96> 100K_0402_5% 100K_0402_5% RV36 RV37 RV38 100K_0402_5% 100K_0402_5% RV40 RV41
AK1 X76SAM@ VGA@ 100K_0201_5% 100K_0201_5% 100K_0201_5% VGA@ N18P@ 10K_0402_5% 100K_0201_5%
<40> GPU_DP2_P0 IFPC_L0
AJ1 VGA@ @ VGA@ N18P@ N18P@
<40> GPU_DP2_N0 IFPC_L0_N VSS_SENSE_NVVDD1

1
AJ3 L5
<40> GPU_DP2_P1 VSS_SENSE_NVVDD1 <96>
HDMI
IFPC_L1 GND_SENSE

1
AJ2
<40> GPU_DP2_N1 IFPC_L1_N
AH3
<40> GPU_DP2_P2 AH4 IFPC_L2 20190921

TMDS
2.0 <40>
<40>
<40>
GPU_DP2_N2
GPU_DP2_P3
GPU_DP2_N3
AG5
AG4
IFPC_L2_N
IFPC_L3
IFPC_L3_N
X76 BOM
TEST
AM1
AM2 IFPD_L0 NVJTAG_SEL
AK11 TESTMODE RV42 1 VGA@ 2 10K_0402_5% X76 BOM
AM3 IFPD_L0_N AM10 JTAG_TCK_VGA @ TV5 UV4 UV4
AM4 IFPD_L1 JTAG_TCK AM11 JTAG_TDI @ TV6
AL3 IFPD_L1_N JTAG_TDI AP12 JTAG_TDO @ TV7 X76SAM@ X76MIC@
AL4 IFPD_L2 JTAG_TDO AP11 JTAG_TMS @ TV8
IFPD_L2_N JTAG_TMS JTAG_RST
S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V
AK4 AN11 RV43 1 VGA@ 2 10K_0402_5% SA0000C6280 SA0000BND80
AK5 IFPD_L3 JTAG_TRST_N
IFPD_L3_N UV5 UV5

<39> DP0_TXP0 AD2 X76SAM@ X76MIC@

AD3 IFPE_L0
<39> DP0_TXN0 S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V
mDP <39>
<39>
DP0_TXP1
DP0_TXN1
AD1
AC1
AC2
IFPE_L0_N
IFPE_L1
IFPE_L1_N
SERIAL
H6 ROM_CS#
SA0000C6280
UV6
SA0000BND80
UV6
2 <39> DP0_TXP2 IFPE_L2 ROM_CS_N ROM_SCLK 2
<39> DP0_TXN2 AC3 H4
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI X76SAM@ X76MIC@
<39> DP0_TXP3 IFPE_L3 ROM_SI ROM_SO
AC5 H7 S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V
<39> DP0_TXN3 IFPE_L3_N ROM_SO
1007
SA0000C6280 SA0000BND80
- DP Change to Port-E AE3 UV7 UV7
- Pin NAME no change AE4 NC
AF4 NC X76SAM@ X76MIC@
AF5 NC
AD4 NC GENERAL S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V S IC D6 256M32 K4Z80325BC-HC14 FBGA 1.2V
NC GPU_BUFRST#
SA0000C6280 SA0000BND80
AD5 E1 @ TV9
AG1 NC BUFRST_N
AF1 NC M1
NC OVERT VGA_OVERT# <27>

www.laptoprepairsecrets.com
AG3
<40> GPU_DP2_CTRL_CLK AG2 IFPC_AUX_SCL
<40> GPU_DP2_CTRL_DAT IFPC_AUX_SDA_N J2 STRAP0
STRAP0 J7 STRAP1
AK3 STRAP1 J6 STRAP2
AK2 IFPD_AUX_SCL STRAP2 J5 STRAP3
IFPD_AUX_SDA_N STRAP3 J3 STRAP4
STRAP4 J1 STRAP5
1007 AB3 STRAP5
- DP Change to Port-E <39> DP0_AUXP AB4 IFPE_AUX_SCL
- Pin NAME no change <39> DP0_AUXN IFPE_AUX_SDA_N K3
THERMDP K4
DP0_AUXN AF3 THERMDN
AF2 NC
DP0_AUXP NC
1

VGA@ VGA@
RG2839 RG2838 N18P-G0_FCBGA960~D
3 100K_0402_5% 100K_0402_5% @ 3
2

SMB_ATL_ADDR

* LOW Single GPU

High Dual GPU

DEVID_SEL

+1.8VSDGPU_AON
* LOW Orig. Device ID
High Support G-Sync GPUID
+1.8VSDGPU_AON
VGA_DEVICE
LOW 3D Device
1

High VGA Device

4 1 N18P@ * 4
RV336 N18P@ CV355
PCIE_CFG
N18P@ 10K_0402_5% 0.1U_0201_10V6K
RV337 * LOW Normal signal swing
33_0402_5% UV49 2 N18P@
2

ROM_CS# 1 2 ROM_CS_R# 1 8 RV339 High Reduce the signal amplitude

ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 33_0402_5%
3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R 1 2 ROM_SCLK
RV338 @ 4 WP#(IO2) CLK 5 ROM_SI_R 1 2 ROM_SI
GND DI(IO0)
0_0402_5%
W25Q80EWSSIG_SO8 RV340 Security Classification Compal Secret Data Compal Electronics, Inc.
N18P@ 33_0402_5% 2019/09/20 2020/09/20 Title
Issued Date Deciphered Date
SA00009QP00 N18P@ N18P(3/11)-G61/G62 STRAP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
DGPU VBIOS ROM 8Mb AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 29 of 112

A B C D E
 A B C D E

+1.35VSDGPU CHA
/6*1uF+2*10uF
Under
GPU
2*22uF+3*10uF+3*4.7uF+6*1uF

0.47U_0201_6.3V6K
CV395

0.47U_0201_6.3V6K
CV396

1U_0201_6.3V6M
CV18

1U_0201_6.3V6M
CV19

1U_0201_6.3V6M
CV20

1U_0201_6.3V6M
CV21

1U_0201_6.3V6M
CV22

1U_0201_6.3V6M
CV23

10U_0402_6.3V6M
CV24

10U_0402_6.3V6M
CV26
1 1 1 1 1 1 1 1 1 1 Under Near +1.0VSDGPU
GPU GPU
2 2 2 2 2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

1U_0201_6.3V6M
CV134

1U_0201_6.3V6M
CV13

1U_0201_6.3V6M
CV14

1U_0201_6.3V6M
CV33

1U_0201_6.3V6M
CV385

1U_0201_6.3V6M
CV386

4.7U_0402_6.3V6M
CV29

4.7U_0402_6.3V6M
CV16

4.7U_0402_6.3V6M
CV387

10U_0402_6.3V6M
CV28

10U_0402_6.3V6M
CV388

10U_0402_6.3V6M
CV389

22U_0603_6.3V6M
CV34

22U_0603_6.3V6M
CV390
1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
2 2 2 2 2 2 2 2 2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
reserve

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
1
UV1E 1
CHB
Part 5 of 7
/6*1uF+2*10uF
AA27 AG19
AA30 FBVDDQ_0 PEX_DVDD_0 AG21
0.47U_0201_6.3V6K
CV397

0.47U_0201_6.3V6K
CV398

1U_0201_6.3V6M
CV126

1U_0201_6.3V6M
CV127

1U_0201_6.3V6M
CV128

1U_0201_6.3V6M
CV129

1U_0201_6.3V6M
CV130

1U_0201_6.3V6M
CV131

10U_0402_6.3V6M
CV132

10U_0402_6.3V6M
CV133
1 1 1 1 1 1 1 1 1 1 FBVDDQ_1 PEX_DVDD_1
AB27 AG22
AB33 FBVDDQ_2 PEX_DVDD_2 AG24
AC27 FBVDDQ_3 PEX_DVDD_3 AH21
2 2 2 2 2 2 2 2 2 2 AD27 FBVDDQ_4 PEX_DVDD_4 AH25
VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
AE27 FBVDDQ_5 PEX_DVDD_5
@

VGA@

VGA@
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
2*22uF+3*10uF+3*4.7uF+7*1uF
B13 FBVDDQ_8 PEX_HVDD_0 AG15
Near +1.8VSDGPU_MAIN
reserve B19 FBVDDQ_9 PEX_HVDD_1 AG16
Under GPU
E13 FBVDDQ_11 PEX_HVDD_2 AG18
GPU
E19 FBVDDQ_12 PEX_HVDD_3 AG25

1U_0201_6.3V6M
CV399

1U_0201_6.3V6M
CV381

1U_0201_6.3V6M
CV380

1U_0201_6.3V6M
CV137

1U_0201_6.3V6M
CV136

1U_0201_6.3V6M
CV25

1U_0201_6.3V6M
CV15

4.7U_0402_6.3V6M
CV382

4.7U_0402_6.3V6M
CV17

4.7U_0402_6.3V6M
CV32

10U_0402_6.3V6M
CV30

10U_0402_6.3V6M
CV27

10U_0402_6.3V6M
CV383

22U_0603_6.3V6M
CV31

22U_0603_6.3V6M
CV384
FBVDDQ_14 PEX_HVDD_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
H10 AH15
H11 FBVDDQ_15 PEX_HVDD_5 AH18
H12 FBVDDQ_16 PEX_HVDD_6 AH26
FBVDDQ_17 PEX_HVDD_7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

VGA@

VGA@
H13 AH27

VGA@

VGA@

VGA@

VGA@

VGA@
GPU FBVDDQ_18 PEX_HVDD_8
H14 AJ27

VGA@

VGA@
VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
/5*22uF+2*10uF H18 FBVDDQ_19 PEX_HVDD_9 AK27
H19 FBVDDQ_22 PEX_HVDD_10 AL27
10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1 1 1 1 FBVDDQ_23 PEX_HVDD_11
H20 AM28
CV37

CV38

CV202

CV36

CV39

CV40

CV41
H21 FBVDDQ_24 PEX_HVDD_12 AN28

POWER
H22 FBVDDQ_25 PEX_HVDD_13
2 2 2 2 2 2 2 H23 FBVDDQ_26
H24 FBVDDQ_27
VGA@

VGA@
VGA@

VGA@

VGA@

VGA@

VGA@
H8 FBVDDQ_28 AH12
FBVDDQ_29 PEX_PLL_HVDD +1.8VSDGPU_MAIN
H9 1
L27 FBVDDQ_30 +FP_FUSE_GPU CV43 VGA@
M27 FBVDDQ_31 1U_0201_6.3V6M
Place close to N27 FBVDDQ_32
FBVDDQ_33 FP_FUSE_SRC
AG12 12mils
P27 2
GPU FBVDDQ_34 Near
R27
2 T27 FBVDDQ_35 +1.8VSDGPU_MAIN GPU 3*4.7uF+5*1uF +1.8VSDGPU_AON 2
T30 FBVDDQ_36 AG26
T33 FBVDDQ_37 NC
Y27 FBVDDQ_38
22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0201_6.3V6M
CV51

4.7U_0402_6.3V6M
CV393
10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0201_6.3V6M
CV135

1U_0201_6.3V6M
CV49

1U_0201_6.3V6M
CV391

1U_0201_6.3V6M
CV392

4.7U_0402_6.3V6M
CV50

4.7U_0402_6.3V6M
CV394
1 1 1 1 1 1 1 FBVDDQ_43 1 1 1 1 1 1 1 1
CV217

CV218

CV219

CV220

CV221

CV222

CV223

J8
1V8_AON K8
2 2 2 2 2 2 2 1V8_AON L8 2 2 2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
B16 NC M8
E16 FBVDDQ NC
@

@
@

H15 FBVDDQ
H16 FBVDDQ
V27 FBVDDQ AH8
near GPU for NV update spec 1210 W27 FBVDDQ IFPAB_PLLVDD AJ8 2 VGA@ 1
Under Near
W30 FBVDDQ IFPAB_RSET RG2841 1K_0402_1%
GPU GPU +1.8VSDGPU_MAIN
+1.35VSDGPU W33 FBVDDQ 2*4.7uF+1*1uF+2*0.1uF
RV394 2 N17P@ 1 0_0402_5%
FBVDDQ

www.laptoprepairsecrets.com
AF7
IFPCD_PLLVDD
2

AF8 2 VGA@ 1

0.1U_0201_10V6K
CV52

0.1U_0201_10V6K
CV53

1U_0201_6.3V6M
CV54

4.7U_0402_6.3V6M
CV55
IFPCD_RSET 1 1 1 1
RV45 RG38 1K_0402_1%
@ 0_0402_5%
AB8
IFPE_PLLVDD AD6 2 VGA@ 1 2 2 2 2

N17P@

N17P@

N17P@

N17P@
FB_VDDQ_SENSE IFPE_RSET
1

F1 RG3020 1K_0402_1%
<100> FB_VDDQ_SENSE FBVDDQ_SENSE 20191016
- DP change to Port E
TV10@ FB_GND_SENSE F2 AG8
Under
PROBE_FB_GND IFP_IOVDD AG9
+1.35VSDGPU IFP_IOVDD GPU Near
RV47 1 VGA@ 2 40.2_0402_1% FB_CAL_PD_VDDQ J27 AF6 GPU
FB_CAL_PD_VDDQ IFP_IOVDD AG6
IFP_IOVDD
FB_CAL_PU_GND +GPU_PLLVDD
RV48 1 VGA@ 2 40.2_0402_1% H27 AC7
FB_CAL_PU_GND IFP_IOVDD AC8

1U_0201_6.3V6M
CV215

1U_0201_6.3V6M
CV216
IFP_IOVDD 1 1
1 N17P@ 2 FB_CAL_TERM_GND H25
3 RV49 60.4_0402_1% FB_CAL_TERM_GND AG7 3
NC AN2 2 2

VGA@

VGA@
NC
RV49 N18P@ Under GPU
N18P-G0_FCBGA960~D
1 per ball
@ 3*4.7uF+9*1uF +1.0VSDGPU
40.2_0402_1%
SD034402A80

1U_0201_6.3V6M
CV214

1U_0201_6.3V6M
CV213

1U_0201_6.3V6M
CV212

4.7U_0402_6.3V6M
CV205

4.7U_0402_6.3V6M
CV204

4.7U_0402_6.3V6M
CV203
1 1 1 1 1 1

2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
Near
GPU

1U_0201_6.3V6M
CV211

1U_0201_6.3V6M
CV210

1U_0201_6.3V6M
CV206
1U_0201_6.3V6M
CV209

1U_0201_6.3V6M
CV208

1U_0201_6.3V6M
CV207
1 1 1 1 1 1

2 2 2 2 2 2

VGA@

VGA@
VGA@

VGA@

VGA@

VGA@
Under GPU 1
4 per ball 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(4/11)-G61/G62 POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 30 of 112
A B C D E
 A B C D E

UV1F
N17P VDDS
1uF*5/4.7uF*5 (under GPU) Part 6 of 7
330uF*1/22uF*3/10uF*2/4.7uF*2 A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
AB12 GND_4 GND_104 E25
AB14 GND_5 GND_105 E5
UV1G AB16 GND_6 GND_106 E7
+NVVDD1 +NVVDD1 AB19 GND_7 GND_107 F28
AB2 GND_8 GND_108 F7
AA14 Part 7 of 7 V17 AB21 GND_9 GND_109 G10
AA21 VDD_1 VDD_56 V20 A33 GND_10 GND_110 G13
1 VDD_4 VDD_58 GND_11 GND_111 1
AB13 V22 AB23 G16
AB15 VDD_6 VDD_59 W12 AB28 GND_12 GND_112 G19
AB17 VDD_7 VDD_60 W16 AB30 GND_13 GND_113 G2
AB18 VDD_8 VDD_62 W19 AB32 GND_14 GND_114 G22
AB20 VDD_9 VDD_63 W23 AB5 GND_15 GND_115 G25
AB22 VDD_10 VDD_65 Y13 AB7 GND_16 GND_116 G28
AC12 VDD_11 VDD_66 Y15 AC13 GND_17 GND_117 G3
AC16 VDD_12 VDD_67 Y17 AC15 GND_18 GND_118 G30
AC19 VDD_14 VDD_68 Y18 AC17 GND_19 GND_119 G32
AC23 VDD_15 VDD_69 Y20 AC18 GND_20 GND_120 G33
M12 VDD_17 VDD_70 Y22 AA13 GND_21 GND_121 G5
M16 VDD_18 VDD_71 AC20 GND_22 GND_122 G7
M19 VDD_20 AC22 GND_23 GND_123 K2
M23 VDD_21 AE2 GND_24 GND_124 K28
N13 VDD_23 U1 NVVDD & NVVDDS merge AE28 GND_25 GND_125 K30
N15 VDD_24 RSVD_VDDS_SENSE U2 AE30 GND_26 GND_126 K32
VDD_25 RSVD_GNDS_SENSE
confirm NV nc or not GND_27 GND_127
N17 AE32 K33
N18 VDD_26 +NVVDD1 AE33 GND_28 GND_128 K5
N20 VDD_27 AE5 GND_29 GND_129 K7
N22 VDD_28 U4 AE7 GND_30 GND_130 M13
P14 VDD_29 XVDD_4 U5 AH10 GND_31 GND_131 M15
POWER
P21 VDD_31 XVDD_5 U6 AA15 GND_32 GND_132 M17
R13 VDD_34 XVDD_6 U7 AH13 GND_33 GND_133 M18
R15 VDD_36 XVDD_7 U8 AH16 GND_34 GND_134 M20
R17 VDD_37 XVDD_8 AH19 GND_35 GND_135 M22
R18 VDD_38 AH2 GND_36 GND_136 N12
R20 VDD_39 V1 AH22 GND_37 GND_137 N14
R22 VDD_40 XVDD_9 V2 AH24 GND_38 GND_138 N16
T12 VDD_41 XVDD_10 V3 AH28 GND_39 GND_139 N19
T16 VDD_42 XVDD_11 V4 AH29 GND_40 GND_140 N2
T19 VDD_44 XVDD_12 V5 AH30 GND_41 GND_141 N21
T23 VDD_45 XVDD_13 V6 AH32 GND_42 GND_142 N23
U13 VDD_47 XVDD_14 V7 AH33 GND_43 GND_143 N28
U15 VDD_48 XVDD_15 V8 AH5 GND_44 GND_144 N30

GND
U18 VDD_49 XVDD_16 AH7 GND_45 GND_145 N32
2 U20 VDD_51 W2 AJ7 GND_46 GND_146 N33 2
U22 VDD_52 XVDD_17 W3 AK10 GND_47 GND_147 N5
V13 VDD_53 XVDD_18 W4 AK7 GND_48 GND_148 N7
V15 VDD_54 XVDD_19 W5 AL12 GND_49 GND_149 P13
VDD_55 XVDD_20 W7 AL14 GND_50 GND_150 P15
XVDD_21 W8 AL15 GND_51 GND_151 P17
XVDD_22 AL17 GND_52 GND_152 P18
AL18 GND_53 GND_153 P20
AA12 AL2 GND_54 GND_154 P22
AA16 VDD_72 Y1 AL20 GND_55 GND_155 R12
AA19 VDD_73 XVDD_20 Y2 AL21 GND_56 GND_156 R14
AA23 VDD_74 XVDD_21 Y3 AL23 GND_57 GND_157 R16
AC14 VDD_75 XVDD_22 Y4 AL24 GND_58 GND_158 R19
AC21 VDD_76 XVDD_23 Y5 AL26 GND_59 GND_159 R21
M14 VDD_77 XVDD_24 Y6 AL28 GND_60 GND_160 R23
M21 VDD_78 XVDD_25 Y7 AL30 GND_61 GND_161 T13

www.DeviceDB.xyz || Telegram: https://t.me/DeviceDB

VDD_79 XVDD_26 GND_62 GND_162

www.laptoprepairsecrets.com
P12 Y8 AL32 T15
P16 VDD_80 XVDD_27 AL33 GND_63 GND_163 T17
P19 VDD_81 AL5 GND_64 GND_164 T18
P23 VDD_82 AA1 AM13 GND_65 GND_165 T2
T14 VDD_83 XVDD_28 AA2 AM16 GND_66 GND_166 T20
T21 VDD_84 XVDD_29 AA3 AM19 GND_67 GND_167 T22
U17 VDD_85 XVDD_30 AA4 AM22 GND_68 GND_168 AG11
V18 VDD_86 XVDD_31 AA5 AM25 GND_69 GND_169 T28
W14 VDD_87 XVDD_32 AA6 AN1 GND_70 GND_170 T32
W21 VDD_88 XVDD_33 AA7 AN10 GND_71 GND_171 T5
VDD_89 XVDD_34 AA8 AN13 GND_72 GND_172 T7
XVDD_35 AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AB11 R11 AN22 GND_75 GND_175 U16
AB24 VDD_90 VDD_106 R24 AN25 GND_76 GND_176 U19
AD11 VDD_91 VDD_107 U11 AN30 GND_77 GND_177 U21
AD13 VDD_92 VDD_108 U24 AN34 GND_78 GND_178 U23
AD15 VDD_93 VDD_109 V11 AN4 GND_79 GND_179 V12
AD17 VDD_94 VDD_110 V24 AN7 GND_80 GND_180 V14
3 AD18 VDD_95 VDD_111 Y11 AP2 GND_81 GND_181 V16 3
AD20 VDD_96 VDD_112 Y24 AP33 GND_82 GND_182 V19
AD22 VDD_97 VDD_113 B1 GND_83 GND_183 V21
AD24 VDD_98 B10 GND_84 GND_184 V23
L11 VDD_95 B22 GND_85 GND_185 W13
L13 VDD_96 B25 GND_86 GND_186 W15
L15 VDD_97 B28 GND_87 GND_187 W17
L17 VDD_98 B31 GND_88 GND_188 W18
L18 VDD_99 B34 GND_89 GND_189 W20
L20 VDD_100 B4 GND_90 GND_190 W22
L22 VDD_101 B7 GND_91 GND_191 W28
L24 VDD_102 C10 GND_92 GND_192 Y12
N11 VDD_103 C13 GND_93 GND_193 Y14
N24 VDD_104 C19 GND_94 GND_194 Y16
VDD_105 C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
N18P-G0_FCBGA960~D C7 GND_98 GND_198
GND_99
@
L21 AA11
L23 GND_214 GND_200 AA24
M11 GND_215 GND_201 AC11
M24 GND_216 GND_202 AC24
P11 GND_217 GND_203 AD12
T11 GND_218 GND_204 AD14
T24 GND_219 GND_205 AD16
W11 GND_220 GND_206 AD19
W24 GND_221 GND_207 AD21
P24 GND_222 GND_208 AD23
GND_223 GND_209 L12
GND_210 L14
GND_211 L16
GND_212 L19
GND_213

4 AH11 RV395 2 N17P@ 1 0_0402_5% 4

NC
C16
GND_OPT W32
GND_OPT
N18P-G0_FCBGA960~D
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(5/11)-G61/G62 POWER & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 31 of 112
A B C D E
 A B C D E

UV4
MF=1 MF=2
UV5

C2 B4
<28> FBA_EDC0 C13 EDC0_A DQ0_A A3 FBA_D2 <28> change for GDDR6 C2 B4
<28> FBA_EDC1
T2 EDC1_A DQ1_A B3
FBA_D3 <28> <28> FBA_EDC5
C13 EDC0_A DQ0_A A3
FBA_D40 <28> change for GDDR6
<28> FBA_EDC3 T13 EDC0_B DQ2_A B2 FBA_D0 <28> <28> FBA_EDC4 T2 EDC1_A DQ1_A B3 FBA_D41 <28>
<28> FBA_EDC2 EDC1_B DQ3_A E3 FBA_D1 <28> <28> FBA_EDC6 EDC0_B DQ2_A FBA_D42 <28>
T13 B2
DQ4_A E2 FBA_D4 <28> change for GDDR6 <28> FBA_EDC7 EDC1_B DQ3_A E3 FBA_D43 <28>
D2 DQ5_A F2 FBA_D7 <28> DQ4_A E2 FBA_D45 <28>
<28> FBA_DBI0 DBI0#_A DQ6_A FBA_D5 <28> DQ5_A FBA_D44 <28>
D13 G2 D2 F2
<28> FBA_DBI1 R2 DBI1#_A DQ7_A B11 FBA_D6 <28> <28> FBA_DBI5 D13 DBI0#_A DQ6_A G2 FBA_D47 <28>
<28> FBA_DBI3 DBI0#_B DQ8_A FBA_D8 <28> <28> FBA_DBI4 DBI1#_A DQ7_A FBA_D46 <28>
R13 A12 R2 B11
<28> FBA_DBI2 DBI1#_B DQ9_A B12 FBA_D11 <28> <28> FBA_DBI6 R13 DBI0#_B DQ8_A A12 FBA_D34 <28>
DQ10_A B13 FBA_D10 <28> <28> FBA_DBI7 DBI1#_B DQ9_A B12 FBA_D35 <28>
DQ11_A FBA_D9 <28> DQ10_A FBA_D32 <28>
J10 E12 B13
<28> FBA_CLKA0 K10 CK DQ12_A E13 FBA_D12 <28> J10 DQ11_A E12 FBA_D33 <28>
<28> FBA_CLKA0# CK# DQ13_A FBA_D14 <28> <28> FBA_CLKA1 CK DQ12_A FBA_D36 <28>
G10 F13 K10 E13
<28> FBA_CMD7 M10 CKE#_A DQ14_A G13 FBA_D15 <28> <28> FBA_CLKA1# G10 CK# DQ13_A F13 FBA_D37 <28>
CKE#_B DQ15_A FBA_D13 <28> <28> FBA_CMD33 M10 CKE#_A DQ14_A G13 FBA_D38 <28>
CKE#_B DQ15_A FBA_D39 <28>
1 U4 1
DQ0_B V3 FBA_D25 <28> U4
DQ1_B FBA_D27 <28> DQ0_B FBA_D50 <28>
U3 V3
change for GDDR6 J5 DQ2_B U2 FBA_D26 <28> DQ1_B U3 FBA_D49 <28>
<28> FBA_CMD8 K5 CABI#_A DQ3_B P3 FBA_D24 <28> J5 DQ2_B U2 FBA_D48 <28>
CABI#_B DQ4_B FBA_D31 <28> <28> FBA_CMD30 CABI#_A DQ3_B FBA_D51 <28>
P2 K5 P3
DQ5_B N2 FBA_D29 <28> CABI#_B DQ4_B P2 FBA_D52 <28>
DQ6_B FBA_D28 <28> DQ5_B FBA_D53 <28>
M2 N2
DQ7_B U11 FBA_D30 <28> DQ6_B M2 FBA_D54 <28>
DQ8_B V12 FBA_D18 <28> DQ7_B U11 FBA_D55 <28>
DQ9_B FBA_D16 <28> DQ8_B FBA_D58 <28>
RV3663 2 VGA@ 1 121_0402_1% J14 U12 V12
2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBA_D17 <28> 2 VGA@ 1 J14 DQ9_B U12 FBA_D57 <28>
RV3662 121_0402_1% RV3664 121_0402_1%
ZQ_B DQ11_B P12 FBA_D19 <28> 2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBA_D59 <28>
RV3665 121_0402_1%
DQ12_B P13 FBA_D21 <28> ZQ_B DQ11_B P12 FBA_D56 <28>
DQ13_B N13 FBA_D20 <28> DQ12_B P13 FBA_D60 <28>
DQ14_B M13 FBA_D22 <28> DQ13_B N13 FBA_D61 <28>
DQ15_B FBA_D23 <28> DQ14_B M13 FBA_D63 <28>
DQ15_B FBA_D62 <28>
N5 H3
F10 TCK CA0_A G11 FBA_CMD13 <28> N5 H3
TDI CA1_A FBA_CMD15 <28> TCK CA0_A FBA_CMD29 <28>
N10 G4 F10 G11
F5 TDO CA2_A H12 FBA_CMD0 <28> N10 TDI CA1_A G4 FBA_CMD31 <28>
TMS CA3_A FBA_CMD9 <28> TDO CA2_A FBA_CMD16 <28>
H5 F5 H12
CA4_A H10 FBA_CMD11 <28> TMS CA3_A H5 FBA_CMD25 <28>
CA5_A J12 FBA_CMD12 <28> CA4_A H10 FBA_CMD22 <28>
CA6_A FBA_CMD3 <28> CA5_A FBA_CMD21 <28>
J11 J12
CA7_A J4 FBA_CMD4 <28> CA6_A J11 FBA_CMD24 <28>
CA8_A FBA_CMD6 <28> CA7_A FBA_CMD23 <28>
J3 J4
CA9_A FBA_CMD5 <28> CA8_A J3 FBA_CMD26 <28>
L3 CA9_A FBA_CMD17 <28>
FBA_WCK01 CA0_B FBA_CMD10 <28>
D4 M11 L3
<28> FBA_WCK01 FBA_WCK01# D5 WCK_A CA1_B M4 FBA_CMD1 <28> D4 CA0_B M11 FBA_CMD27 <28>
<28> FBA_WCK01# FBA_WCK23 WCK#_A CA2_B FBA_CMD32 <28> <28> FBA_WCKB45 WCK_A CA1_B FBA_CMD28 <28>
R11 L12 D5 M4
<28> FBA_WCK23 FBA_WCK23# R10 WCK_B CA3_B L5 FBA_CMD11 FBA_CMD14 <28> <28> FBA_WCKB45# R11 WCK#_A CA2_B L12 FBA_CMD19 <28>
<28> FBA_WCK23# WCK#_B CA4_B L10 FBA_CMD12 <28> FBA_WCKB67 R10 WCK_B CA3_B L5 FBA_CMD22 FBA_CMD20 <28>
CA5_B FBA_CMD3 <28> FBA_WCKB67# WCK#_B CA4_B FBA_CMD21
K12 L10
CA6_B K11 FBA_CMD4 CA5_B K12 FBA_CMD24
CA7_B K4 FBA_CMD6 CA6_B K11 FBA_CMD23
EH50F remove all reserve MEM_VREF schemat i c W=16mils CA8_B K3 FBA_CMD5 CA7_B K4 FBA_CMD26
+FBAA_VREFC K1
VREFC
CA9_B +1.35VSDGPU W=16mils
+FBAB_VREFC K1
CA8_B
CA9_B
K3 FBA_CMD17
+1.35VSDGPU
C1 VREFC
J1 VDDQ1 E1 C1
<28> FBA_CMD2 RESET# VDDQ2 H1 J1 VDDQ1 E1
VDDQ3 L1 <28> FBA_CMD18 RESET# VDDQ2 H1
B1 VDDQ4 P1 VDDQ3 L1
+FBAA_VREFC D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1
F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1
VSS3 VDDQ7 VSS2 VDDQ6
2

G1 K2 F1 J2
1K_0402_5%

M1 VSS4 VDDQ8 C4 +FBAB_VREFC G1 VSS3 VDDQ7 K2

RV3666

2 VGA@ N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4 2

VSS6 VDDQ10 VSS5 VDDQ9

2
R1 N4 N1 F4

1K_0402_5%
U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4

RV3667
VSS8 VDDQ12 VSS7 VDDQ11
1

A2 B5 VGA@ U1 T4
V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5
C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5
VSS11 VDDQ15 VSS10 VDDQ14

1
D3 U10 C3 B10
F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10
G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11
M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11
N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11
R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11
T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13
A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13
E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14
H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14
L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14
P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14
V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14
C5 VSS24 VDDQ28 V4 VSS23 VDDQ27 T14
T5 VSS25 C5 VSS24 VDDQ28
C10 VSS26 A1 T5 VSS25
T10 VSS27 VDD1 V1 C10 VSS26 A1
A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1
E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2
H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2
L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5
P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5
V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10
C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10
D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13
F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13
G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14
M12 VSS38 VDD12 +1.8VSDGPU_AON G12 VSS37 VDD11 V14
N12 VSS39 M12 VSS38 VDD12 +1.8VSDGPU_AON

www.laptoprepairsecrets.com
R12 VSS40 A5 N12 VSS39
T12 VSS41 VPP1 V5 R12 VSS40 A5
A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5
V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10
B14 VSS44 VPP4 V13 VSS43 VPP3 V10
D14 VSS45 R4 FBA_WCKB23 B14 VSS44 VPP4
F14 VSS46 WCK0_t_B,NC R5 FBA_WCKB23# FBA_WCKB23 <28> D14 VSS45 R4
G14 VSS47 WCK0_c_B,NC FBA_WCKB23# <28> VSS46 WCK0_t_B,NC FBA_WCK67 <28>
F14 R5
M14 VSS48 G5 G14 VSS47 WCK0_c_B,NC FBA_WCK67# <28>
N14 VSS49 RFU_A,NC M5 M14 VSS48 G5
R14 VSS50 RFU_B,NC N14 VSS49 RFU_A,NC M5
U14 VSS51
180-BALL D10 FBA_WCKB01# R14 VSS50 RFU_B,NC
VSS52 WCK1_c_A,NC D11 FBA_WCKB01 FBA_WCKB01# <28> U14 VSS51 D10
SGRAM GDDR6 180-BALL
WCK1_t_A,NC FBA_WCKB01 <28> VSS52 WCK1_c_A,NC D11 FBA_WCK45# <28>
SGRAM GDDR6
WCK1_t_A,NC FBA_WCK45 <28>
3 @ K4Z80325BC-HC14_FBGA180~D 3
@ K4Z80325BC-HC14_FBGA180~D

+1.35VSDGPU
+1.35VSDGPU +1.35VSDGPU +1.35VSDGPU
+1.35VSDGPU +1.35VSDGPU Close to DRAM Close to DRAM
Close to DRAM Close to DRAM

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CV551

CV555
CV550

CV552

CV553

CV554

CV562
1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M
CV549

CV565
CV544

CV545

CV546

CV547

CV548

CV563

CV564

CV566

CV567

CV568
1 1 1 1 1 1 2 2 2 2 2 2
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
CV559
CV557

CV558

CV561
CV556

CV560

2 2 2 2 2 2
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 2 2 2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1 1
1 1 1 1 1 1

+1.35VSDGPU Right under DRAM +1.35VSDGPU

Right under DRAM +1.35VSDGPU around DRAM
+1.35VSDGPU around DRAM

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M
1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
CV582

CV583

CV584

CV585
1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1
1

1
CV586

CV588

CV591
CV569

CV570

CV571

CV573

CV574

CV575

CV587

CV589

CV590
CV572

1 1 1 1 1 1 1
1

1
CV579

CV580

CV581
CV576

CV577

CV578

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

2
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 2 2 2 2
2

2 2
2

2 2 2 2 2

+1.35VSDGPU Close to DRAM +1.8VSDGPU_AON

+1.35VSDGPU Close to DRAM +1.8VSDGPU_AON

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M
CV602

CV607

CV608

CV610

CV611

CV612

CV613
CV603

CV604

CV605

CV606
1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M
CV596
CV592

CV593

CV595

CV598

CV599

CV601

CV609
CV594

CV600

1 1 1 1 1 1 1 1 1 1
4 4
CV597

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(6/11)-G61/G62 GDDR6 CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 32 of 112
A B C D E
 A B C D E

UV6
MF=1
UV7
MF=2
C2 B4
<28> FBB_EDC0 C13 EDC0_A DQ0_A A3 FBB_D0 <28> change for GDDR6
<28> FBB_EDC1 EDC1_A DQ1_A FBB_D1 <28> C2 B4
T2 B3
<28> FBB_EDC3 T13 EDC0_B DQ2_A B2 FBB_D2 <28> change for GDDR6 <28> FBB_EDC5 C13 EDC0_A DQ0_A A3 FBB_D42 <28> change for GDDR6
<28> FBB_EDC2 EDC1_B DQ3_A E3 FBB_D3 <28> <28> FBB_EDC4 T2 EDC1_A DQ1_A B3 FBB_D43 <28>
DQ4_A FBB_D4 <28> <28> FBB_EDC6 EDC0_B DQ2_A FBB_D40 <28>
E2 T13 B2
D2 DQ5_A F2 FBB_D5 <28> <28> FBB_EDC7 EDC1_B DQ3_A E3 FBB_D41 <28>
<28> FBB_DBI0 DBI0#_A DQ6_A FBB_D6 <28> DQ4_A FBB_D44 <28>
D13 G2 E2
<28> FBB_DBI1 R2 DBI1#_A DQ7_A B11 FBB_D7 <28> D2 DQ5_A F2 FBB_D47 <28>
<28> FBB_DBI3 R13 DBI0#_B DQ8_A A12 FBB_D10 <28> <28> FBB_DBI5 D13 DBI0#_A DQ6_A G2 FBB_D46 <28>
<28> FBB_DBI2 DBI1#_B DQ9_A FBB_D11 <28> <28> FBB_DBI4 DBI1#_A DQ7_A FBB_D45 <28>
B12 R2 B11
DQ10_A B13 FBB_D8 <28> <28> FBB_DBI6 R13 DBI0#_B DQ8_A A12 FBB_D34 <28>
DQ11_A FBB_D9 <28> <28> FBB_DBI7 DBI1#_B DQ9_A FBB_D35 <28>
J10 E12 B12
<28> FBB_CLKA0 K10 CK DQ12_A E13 FBB_D12 <28> DQ10_A B13 FBB_D32 <28>
<28> FBB_CLKA0# G10 CK# DQ13_A F13 FBB_D14 <28> J10 DQ11_A E12 FBB_D33 <28>
<28> FBB_CMD7 CKE#_A DQ14_A FBB_D15 <28> <28> FBB_CLKA1 CK DQ12_A FBB_D36 <28>
1 M10 G13 K10 E13 1
CKE#_B DQ15_A FBB_D13 <28> <28> FBB_CLKA1# G10 CK# DQ13_A F13 FBB_D37 <28>
<28> FBB_CMD33 CKE#_A DQ14_A FBB_D39 <28>
U4 M10 G13
DQ0_B V3 FBB_D26 <28> CKE#_B DQ15_A FBB_D38 <28>
change for GDDR6 DQ1_B U3 FBB_D27 <28> U4
DQ2_B FBB_D25 <28> DQ0_B FBB_D50 <28>
J5 U2 V3
<28> FBB_CMD8 K5 CABI#_A DQ3_B P3 FBB_D24 <28> DQ1_B U3 FBB_D49 <28>
CABI#_B DQ4_B FBB_D29 <28> DQ2_B FBB_D51 <28>
P2 J5 U2
DQ5_B N2 FBB_D31 <28> <28> FBB_CMD30 K5 CABI#_A DQ3_B P3 FBB_D48 <28>
DQ6_B M2 FBB_D28 <28> CABI#_B DQ4_B P2 FBB_D52 <28>
DQ7_B FBB_D30 <28> DQ5_B FBB_D55 <28>
U11 N2
DQ8_B V12 FBB_D18 <28> DQ6_B M2 FBB_D53 <28>
2 VGA@ 1 J14 DQ9_B U12 FBB_D17 <28> DQ7_B U11 FBB_D54 <28>
RV3668 121_0402_1%
2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBB_D19 <28> DQ8_B V12 FBB_D57 <28>
RV3670 121_0402_1%
ZQ_B DQ11_B P12 FBB_D16 <28> 2 VGA@ 1 J14 DQ9_B U12 FBB_D56 <28>
RV3669 121_0402_1%
DQ12_B P13 FBB_D20 <28> 2 VGA@ 1 K14 ZQ_A DQ10_B U13 FBB_D58 <28>
RV3671 121_0402_1%
DQ13_B N13 FBB_D21 <28> ZQ_B DQ11_B P12 FBB_D59 <28>
DQ14_B FBB_D22 <28> DQ12_B FBB_D61 <28>
M13 P13
DQ15_B FBB_D23 <28> DQ13_B N13 FBB_D60 <28>
DQ14_B M13 FBB_D63 <28>
DQ15_B FBB_D62 <28>
N5 H3
F10 TCK CA0_A G11 FBB_CMD13 <28>
TDI CA1_A FBB_CMD15 <28>
N10 G4 N5 H3
F5 TDO CA2_A H12 FBB_CMD0 <28> F10 TCK CA0_A G11 FBB_CMD29 <28>
TMS CA3_A H5 FBB_CMD9 <28> N10 TDI CA1_A G4 FBB_CMD31 <28>
CA4_A FBB_CMD11 <28> TDO CA2_A FBB_CMD16 <28>
H10 F5 H12
CA5_A J12 FBB_CMD12 <28> TMS CA3_A H5 FBB_CMD25 <28>
CA6_A FBB_CMD3 <28> CA4_A FBB_CMD22 <28>
J11 H10
CA7_A J4 FBB_CMD4 <28> CA5_A J12 FBB_CMD21 <28>
CA8_A J3 FBB_CMD6 <28> CA6_A J11 FBB_CMD24 <28>
CA9_A FBB_CMD5 <28> CA7_A FBB_CMD23 <28>
J4
L3 CA8_A J3 FBB_CMD26 <28>
FBB_WCK01 CA0_B FBB_CMD10 <28> CA9_A FBB_CMD17 <28>
D4 M11
<28> FBB_WCK01 FBB_WCK01# D5 WCK_A CA1_B M4 FBB_CMD1 <28> L3
<28> FBB_WCK01# FBB_WCK23 R11 WCK#_A CA2_B L12 FBB_CMD32 <28> D4 CA0_B M11 FBB_CMD27 <28>
<28> FBB_WCK23 FBB_WCK23# WCK_B CA3_B FBB_CMD11 FBB_CMD14 <28> <28> FBB_WCKB45 WCK_A CA1_B FBB_CMD28 <28>
R10 L5 D5 M4
<28> FBB_WCK23# WCK#_B CA4_B L10 FBB_CMD12 <28> FBB_WCKB45# R11 WCK#_A CA2_B L12 FBB_CMD19 <28>
CA5_B K12 FBB_CMD3 <28> FBB_WCKB67 R10 WCK_B CA3_B L5 FBB_CMD22 FBB_CMD20 <28>
CA6_B K11 FBB_CMD4 <28> FBB_WCKB67# WCK#_B CA4_B L10 FBB_CMD21
CA7_B K4 FBB_CMD6 CA5_B K12 FBB_CMD24
W=16mils
+FBBA_VREFC K1
CA8_B
CA9_B
K3 FBB_CMD5
+1.35VSDGPU
CA6_B
CA7_B
K11
K4
FBB_CMD23
FBB_CMD26
VREFC
C1
W=16mils
+FBBB_VREFC K1
CA8_B
CA9_B
K3 FBB_CMD17
+1.35VSDGPU
J1 VDDQ1 E1 VREFC
<28> FBB_CMD2 RESET# VDDQ2 H1 C1
VDDQ3 L1 J1 VDDQ1 E1
VDDQ4 <28> FBB_CMD18 RESET# VDDQ2
B1 P1 H1
+FBBA_VREFC D1 VSS1 VDDQ5 T1 VDDQ3 L1
F1 VSS2 VDDQ6 J2 B1 VDDQ4 P1
2 G1 VSS3 VDDQ7 K2 +FBBB_VREFC D1 VSS1 VDDQ5 T1 2
VSS4 VDDQ8 VSS2 VDDQ6
2

M1 C4 F1 J2
1K_0402_5%

N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2

RV3672

VSS6 VDDQ10 VSS4 VDDQ8

2
VGA@ R1 N4 M1 C4

1K_0402_5%
U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4

RV3673
A2 VSS8 VDDQ12 B5 VGA@ R1 VSS6 VDDQ10 N4
VSS9 VDDQ13 VSS7 VDDQ11
1

V2 U5 U1 T4
C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5
VSS11 VDDQ15 VSS9 VDDQ13

1
D3 U10 V2 U5
F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10
G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10
M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11
N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11
R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11
T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11
A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13
E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13
H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14
L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14
P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14
V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14
C5 VSS24 VDDQ28 P4 VSS22 VDDQ26 P14
T5 VSS25 V4 VSS23 VDDQ27 T14
C10 VSS26 A1 C5 VSS24 VDDQ28
T10 VSS27 VDD1 V1 T5 VSS25
A11 VSS28 VDD2 H2 C10 VSS26 A1
E11 VSS29 VDD3 L2 T10 VSS27 VDD1 V1
H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2
L11 VSS31 VDD5 P5 E11 VSS29 VDD3 L2
P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5
V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5
C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10
D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10
F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13
G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13

www.laptoprepairsecrets.com
M12 VSS38 VDD12 +1.8VSDGPU_AON F12 VSS36 VDD10 A14
N12 VSS39 G12 VSS37 VDD11 V14
R12 VSS40 A5 M12 VSS38 VDD12 +1.8VSDGPU_AON
T12 VSS41 VPP1 V5 N12 VSS39
A13 VSS42 VPP2 A10 R12 VSS40 A5
V13 VSS43 VPP3 V10 T12 VSS41 VPP1 V5
B14 VSS44 VPP4 A13 VSS42 VPP2 A10
D14 VSS45 R4 FBB_WCKB23 V13 VSS43 VPP3 V10
F14 VSS46 WCK0_t_B,NC R5 FBB_WCKB23# FBB_WCKB23 <28> B14 VSS44 VPP4
G14 VSS47 WCK0_c_B,NC FBB_WCKB23# <28> D14 VSS45 R4
VSS48 F14 VSS46 WCK0_t_B,NC R5 FBB_WCK67 <28>
M14 G5
N14 VSS49 RFU_A,NC M5 G14 VSS47 WCK0_c_B,NC FBB_WCK67# <28>
R14 VSS50 RFU_B,NC M14 VSS48 G5
U14 VSS51
180-BALL D10 FBB_WCKB01# N14 VSS49 RFU_A,NC M5
VSS52 SGRAM GDDR6 WCK1_c_A,NC D11 FBB_WCKB01 FBB_WCKB01# <28> R14 VSS50 RFU_B,NC
3 WCK1_t_A,NC FBB_WCKB01 <28> U14 VSS51 D10 3
180-BALL
VSS52 WCK1_c_A,NC D11 FBB_WCK45# <28>
SGRAM GDDR6
WCK1_t_A,NC FBB_WCK45 <28>
@ K4Z80325BC-HC14_FBGA180~D

@ K4Z80325BC-HC14_FBGA180~D

+1.35VSDGPU
+1.35VSDGPU +1.35VSDGPU
Close to DRAM Close to DRAM

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M
+1.35VSDGPU

CV615

CV616
CV614
1 1 1

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M
+1.35VSDGPU +1.35VSDGPU

CV617

CV618

CV619

CV620

CV621

CV622
2 2 2 2 2 2
Close to DRAM Close to DRAM VGA@ VGA@ VGA@
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

CV624
CV623

CV625

CV626

CV627

1 1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1
CV628

CV629

CV630

CV631

CV632

CV633
2 2 2 2 2 2
VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 1 1 1 1 1

+1.35VSDGPU Right under DRAM +1.35VSDGPU

around DRAM
Right under DRAM

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1U_0201_6.3V6M
+1.35VSDGPU +1.35VSDGPU

CV637
CV634

CV635

CV636

CV638

CV639

CV640

CV641

CV642
1 1 1 1 1 1 1 1 1
around DRAM

1
1

CV647
CV643

CV644

CV645

CV646

CV648
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

2
2 2 2 2 2 2 2 2 2
CV649

CV650

CV652
CV651

CV653

CV654

CV655

1 1 1 1 1 1 1
1
1

1
CV657

CV658

CV659
CV656

CV660

CV661

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2

2
2

2 2 2 2 2 2 2

+1.35VSDGPU Close to DRAM +1.8VSDGPU_AON

Close to DRAM

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

4.7U_0402_6.3V6M
+1.35VSDGPU +1.8VSDGPU_AON

CV663

CV669

CV671
CV662

CV664

CV665

CV666

CV667

CV670

CV672
1 1 1 1 1 1 1 1 1 1 1

CV668
4 4
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M

2 2 2 2 2 2 2 2 2 2 2
CV674

1
CV673

1
CV675

CV676

1
CV680

1
CV681

CV682

CV683
CV677

CV678

1 1 1 1 1 1 1
CV679

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(7/11)-G61/G62 GDDR6 CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 33 of 112
A B C D E
 A B C D E

+3V_OVRM

CSSP_B+ RV343 1 N18P@ 2 75K_0402_1% PFM_CH1_BS_IN1

1
CV361 RV344
2 1 1 2

2K_0402_5%
RV345

2K_0402_5%
RV346

2K_0402_5%
RV347

2K_0402_5%
RV348
1 1
649_0402_1%
1000P_0402_50V7K +3V_OVRM N18P@ N18P@ N18P@ N18P@
ON_X76@
N18P@

2
PFM_CH1_SH_IN_P3
CSSP_NVVDD RV349 1 N18P@ 2 75K_0402_1% PFM_CH1_BS_IN2 RV351 1 uPI_X76@
2 0_0402_5% PFM_CH1_SH_IN_N3
+3VSDGPU SNN_PFM_CH1_SH_IN_P4
SNN_PFM_CH1_SH_IN_N4
CV362
2 1 1
RV350
2
0730 FAE CF suggest RV399 1 ON_X76@
2 0_0402_5% +3VLP

2
649_0402_1%
0727 FAE CF suggest

0_0402_5%
RV352

0_0402_5%
RV353
1000P_0402_50V7K ON_X76@
N18P@

1
@ @ N18P@
CV363
UV47 1U_0201_6.3V6M
2
3 27
6 BS_IN1 VCC
PFM_CH1_BS_IN3 11 BS_IN2 2 PFM_CH1_SH_IN_P1 RV355 1 N18P@ 2 100_0402_1% CSSP_B+
PFM_CH1_BS_IN4 14 BS_IN3 SH_IN_P1 1 PFM_CH1_SH_IN_N1 1 2 0_0402_5% CSSN_B+ CSSP_B+ <97>
RV356 @
BS_IN4 SH_IN_N1 PFM_CH1_SH_IN_P2 CSSN_B+ <97>
5 RV357 1 N18P@ 2 100_0402_1% CSSP_NVVDD
SH_IN_P2 PFM_CH1_SH_IN_N2 CSSN_NVVDD CSSP_NVVDD <97>
4 RV358 1 @ 2 0_0402_5%
PFM_FILTER_GND_FET SH_IN_N2 PFM_CH1_SH_IN_P3 CSSN_NVVDD <97>
@1 RV354 2 9 12
GND_FET SH_IN_P3 13 PFM_CH1_SH_IN_N3
0_0402_5% SH_IN_N3 15 SNN_PFM_CH1_SH_IN_P4
RV359 1 2
ON_X76@ 475_0402_1% 32 SH_IN_P4 16 SNN_PFM_CH1_SH_IN_N4
RV360 1 2
ON_X76@ 475_0402_1% 7 SH_O1 SH_IN_N4 N18P@
2 RV361 1 @ 2 169_0402_1% 10 SH_O2 20 ADC_IN_P RV362 1 @ 2 0_0402_5% CV684 1 2 47P_0402_50V8J 2
RV363 1 @ 2 169_0402_1% 17 SH_O3 DIFF_OUT_P 19 ADC_IN_N RV364 1 @ 2 0_0402_5% CV685 1 2 47P_0402_50V8J
SH_O4 DIFF_OUT_N N18P@
1 1 1 1 ADC_IN_P <27>
30 PFM_PF_BSOK_R
0.015U_0402_16V7K

0.015U_0402_16V7K

0.015U_0402_16V7K

0.015U_0402_16V7K

BS_OK ADC_IN_N <27>

CV686

CV687

CV688

CV689

RV365
1 @ 2 PFM_ADC_MUX_SEL_R 29 8 SNN_ADC_CUSTOM8
2 2 2 2 MUX_SEL NC SNN_ADC_CUSTOM18 @TH46
0_0402_5% 18 @TH47
NC 21 SNN_ADC_CUSTOM21
PFM_ADC_FILTER_EN 28 NC SNN_ADC_CUSTOM31 @TH48
31 @TH49
20191015
ENABLE NC - Add test point ON_X76@ 243K_0402_1%
23 PFM_BG_REF_OUT RV366 1 2
PFM_SKIP_R 25 BG_REF_OUT 24 PFM_BS_REF
@ @ N18P@ N18P@ SKIP BS_REF 22 PFM_CM_REF_IN
CM_REF_IN

www.laptoprepairsecrets.com
1 1 1 RV367
PFM_ADC_FILTER_MODE

1
<27> GPIO22_OC_WARN# 26 33 1 2

1000P_0402_50V7K
CV370

1000P_0402_50V7K
CV371

1000P_0402_50V7K
CV372

10K_0402_1%
RV369 N18P@
MODE_SEL GND 1

1000P_0402_50V7K
CV373 N18P@
365K_0402_1%

681K_0402_1%
RV368 N18P@
2 2 2 N18P@
NCP45491XMNTWG_QFN32_4X4
2
SA0000C9Q00

2
ON_X76@ N18P@ N18P@ N18P@

2
+3V_OVRM

+3V_OVRM
1

RV370 +3V_OVRM
@ 10K_0402_1% RV371
3 1K_0402_1% 3

1
2

PFM_ADC_FILTER_EN RV372
2

N18P@ 10K_0402_1%
N18P@
1

PFM_SKIP_R
D
1

RV373

2
10K_0402_1% 2
OVRM_EN <17,58>
N18P@ G
1

S QV16 @ PFM_PF_BSOK_R
2

L2N7002WT1G_SC-70-3 RV400 VGA@ UV47 uPI_X76@

SB00001GE00 100K_0402_5%

S IC US5650QQKI WQFN 32P POWER MONITOR

2

+3V_OVRM
SA0000CMA00 0730 FAE CF suggest , reserve pull high only

RV344 uPI_X76@ RV359 uPI_X76@ RV366 uPI_X76@

1

RV374
@ 10K_0402_1% 487_0402_1% 357_0402_1% 324K_0402_1%
SD00000EL80 SD034357080 SD034324380
2

PFM_ADC_FILTER_MODE
RV350 uPI_X76@ RV360 uPI_X76@
1

RV375
4 10K_0402_1% 487_0402_1% 357_0402_1% 4
@
SD00000EL80 SD034357080
2

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N18P(10/11)-G61/G62 OVR-M
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 36 of 112
A B C D E
 5 4 3 2 1

+1.8V_AON/+3VSDGPU +1.8V_MAIN
+1.8VALW

+1.8VSDGPU_AON UV45
+1.8VALW UG27 1 +1.8VSDGPU_MAIN
1 14 2 VIN1
VIN1 VOUT1 1 VIN2
2 13 VGA@ CV357
VIN1 VOUT1 CG335 220P_0402_50V8J 1U_0201_6.3V6M 7 6
1V8_AON_EN 3 12 1 2 VIN thermal VOUT

10U_0402_6.3V6M
<27> 1V8_AON_EN ON1 CT1 1 2
D +5VALW 3 D

CG334 VGA@

10U_0402_6.3V6M

0.1U_0201_10V6K
CV360
+5VALW VBIAS 1 1
4 11

CV359 VGA@
VGA@
VBIAS GND CG336 220P_0402_50V8J 4 5
3VSDGPU_EN 5 10 1 2 2 <27> 1.8VSDGPU_MAIN_EN3V3 ON GND
<27,39> 3VSDGPU_EN ON2 CT2 +3VSDGPU 2 2
+3VS 1 1
6 9

VGA@
1 VGA@ @ CV400 VGA@ CV358 AOZ1334DI-01_DFN8-7_3X3
CG337 7 VIN2 VOUT2 8 0.1U_0201_10V6K 0.1U_0201_10V6K
VIN2 VOUT2 VGA@
0.1U_0201_10V6K
15 2 2 SA000070V00

10U_0402_6.3V6M
VGA@ 1
2 +1.8VALW GPAD

CG338 VGA@
EM5209VF_DFN14_2X3
VGA@ 2

22U_0603_6.3V6M
RV413 @

CG339
1M_0402_5% VGA@
2 1 1V8_AON_EN
2
RV342 @
1M_0402_5%
2 1 3VSDGPU_EN

C C

+1.8VSDGPU_AON

1
CV374
UV50
2.2U_0402_6.3V6M
1 +FP_FUSE_GPU

www.laptoprepairsecrets.com
N18P@
2 2 VIN1
VIN2 12mils
+5VALW 7 6
VIN thermal VOUT

1
3 1
VBIAS CV376 RV384
2 @ 1 GPIO26_FP_FUSE_R 4 5 2.2U_0402_6.3V6M 2.21K_0402_1%
<27> GPIO26_FP_FUSE ON GND N18P@ N18P@
RV382 2
1

2
2

10K_0201_5%
0_0402_5% @ AOZ1334DI-01_DFN8-7_3X3

RV383
CV375 N18P@
N18P@ 0.1U_0201_10V6K
2 SA000070V00

1
B B

+3VSDGPU +1.0VSDGPU

+NVVDD1
+1.35VSDGPU
2

VGA@
+5VS +5VS +5VS

2
N18P@ RV377

2
RV380 20_0402_5% +5VS VGA@ VGA@
1_0603_5% RV116 RV118
2

2
N18P@ VGA@ 20_0402_5% VGA@ 1_0603_5%
1

2
RV381 RV376 VGA@ RV117

1
100K_0402_5% 100K_0402_5% RV115 100K_0402_5%

1
100K_0402_5%
6

6
D D D
1

1
3VSDGPU_EN# 1VSDGPU_EN# NVVDD_EN#

6
2 QV15A 2 QV14A VGA@ D 2

1
G 2N7002KDW_SOT363-6 G 2N7002KDW_SOT363-6 1.35VSDGPU_EN# 2 G

3
N18P@ G D

3
S S D 5 S
<27,96> NVVDD1_EN
1

1
1
3

D D 5 S G QV10A
<27,100> 1.35VSDGPU_EN

1
3VSDGPU_EN 5 5 G QV11A 2N7002KDW_SOT363-6
G <27,102> 1VSDGPU_EN G S
2N7002KDW_SOT363-6 VGA@

4
S VGA@ QV10B

4
A S S QV11B A
2N7002KDW_SOT363-6
4

QV15B QV14B 2N7002KDW_SOT363-6 VGA@

2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 VGA@
N18P@ VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18P(11/11)-DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 37 of 112

5 4 3 2 1
 A B C D E

20191014
LCD POWER CIRCUIT - Change to +19VB
SM01000EJ00 3000ma
+3VS +LCDVDD
+19VB 220ohm@100mhz DCR
+INVPWR_B+
0.04
UX1 W=60mils
5 1 EMI@ W=60mils
IN OUT LX1
2

10U_0402_6.3V6M
CX3

0.1U_0201_10V6K
CX4
1 1 @ HCB2012KF-221T30_0805
GND 1 2
1U_0201_6.3V6M
CX2

1
4 3 W=60mils
<17> PCH_ENVDD EN OC
2 2 1 1
SY6288C20AAC_SOT23-5 XEMI@ EMI@
2

1
1 CX5 CX6 1
68P_0402_50V8J 1000P_0402_50V7K
RX1 2 2
100K_0402_5%

LCD enable signal

PCH_BKL_PWM RX10 1 @ 2 100K_0402_5%
<17> PCH_BKL_PWM
@ RX3 XESD@
0_0402_5% CX9 1 2 220P_0402_50V8J
1 2 EDP_HPD_R
<16> EDP_HPD
XESD@
BKOFF# CX10 1 2 220P_0402_50V8J
<58> BKOFF#
1

RX4 RX5 1 @ 2 10K_0402_5%

100K_0402_5%
20191014
2

- CX0/CX10 change to SE082221J80

Place closed to JEDP1 LED PANEL Conn.
+LCDVDD
+TS_PWR +3VS +INVPWR_B+
2 W=60mils CONN@ JEDP1 2
Panel OD USB/I2C Touch Screen Co-Lay +5VS +3VS
1 2 0_0603_5%
1
2 1

0.1U_0201_10V6K
CX7
RX6 @

0.1U_0201_10V6K
3 2

CX8

10U_0402_6.3V6M
CX1
1 1 @ 1
+LCDVDD RX7 1 2 0_0603_5% 4 3
5 4
PCH_BKL_PWM 6 5
2 2 2 6
1

BKOFF# 7
@ USB20_P6 TS_USB@ RX13 1 2 0_0402_5% TS_USBP_I2C_CLK +LCDVDD EDP_HPD_R 8 7
<14> USB20_P6 USB20_N6 TS_USBN_I2C_DA 8
RX11 TS_USB@ RX19 1 2 0_0402_5% 9
<14> USB20_N6 9
133K_0402_1% 10
I2C_SCL_TS TS_I2C@ RX20 1 2 0_0402_5% 11 10
<19> I2C_SCL_TS 11
2

PANEL_OD_EN I2C_SDA_TS TS_I2C@ RX21 1 2 0_0402_5% PANEL_OD_EN 12

<19> I2C_SDA_TS <19> PANEL_OD_EN 12

www.laptoprepairsecrets.com
13
EDP_AUXN CX20 1 2 0.1U_0201_10V6K EDP_AUXN_C 14 13
<6> EDP_AUXN EDP_AUXP EDP_AUXP_C 14
1

CX19 1 2 0.1U_0201_10V6K 15
+3VS <6> EDP_AUXP 15
@ 16
RX12 EDP_TXP0 CX11 1 2 0.1U_0201_10V6K EDP_TXP0_C 17 16
I2C_SCL_TS <6> EDP_TXP0 EDP_TXN0 CX12 EDP_TXN0_C 17
10K_0402_5% RX302 1 2 1K_0402_5% 1 2 0.1U_0201_10V6K 18
I2C_SDA_TS <6> EDP_TXN0 18
RX303 1 2 1K_0402_5% 19
19
2

EDP_TXP1 CX13 1 2 0.1U_0201_10V6K EDP_TXP1_C 20

<6> EDP_TXP1 EDP_TXN1 CX14 EDP_TXN1_C 20
1 2 0.1U_0201_10V6K 21
1 2 100K_0402_5% I2C_TS_INT# <6> EDP_TXN1 22 21
RX304
20190506 EDP_TXP2 CX15 1 2 0.1U_0201_10V6K EDP_TXP2_C 23 22
- RX11 change to unpop <6> EDP_TXP2 EDP_TXN2 CX16 EDP_TXN2_C 23
1 2 0.1U_0201_10V6K 24
- BIOS needs to detect panel I2C_TS_RST# <6> EDP_TXN2 TS_I2C_INT#_GND 25 24
to select H or L . RX305 1 2 100K_0402_5%
EDP_TXP3 CX17 1 2 0.1U_0201_10V6K EDP_TXP3_C 26 25
<6> EDP_TXP3 EDP_TXN3 CX18 1 2 0.1U_0201_10V6K EDP_TXN3_C 27 26
20190927 <6> EDP_TXN3 27
TS_I2C_RST#_GND 28
3 TS_USBP_I2C_CLK 29 28 3
I2C_TS_INT# RX22 1 2 0_0402_5% TS_I2C_INT#_GND TS_USBN_I2C_DA 30 29
<15> I2C_TS_INT# 30
TS_I2C@ 31
31
1

Touch +TS_PWR
32
NONTS_I2C@ 33 32
RX25
Screen TS_EN 34 33
<19,58> TS_EN 35 34 41
0_0402_5% +3VS
I2C_TS_RST# RX23 1 2 0_0402_5% TS_I2C_RST#_GND USB20_N5_CAMERA 36 35 GND 42
<15> I2C_TS_RST# 36 GND
2

TS_I2C@ USB20_P5_CAMERA 37 43
For 37 GND
1

38 44
NONTS_I2C@
Camera DMIC_CLK_R 39 38 GND 45
near JEDP1 <56> DMIC_CLK_R 39 GND
RX24 DMIC_DATA_R 40 46
<56> DMIC_DATA_R 40 GND
0_0402_5%
ACES_50203-04001-002
2

DMIC_CLK_R

near JEDP1 DMIC_DATA_R SP010014B10

20190921

2
CAMERA XESD@
DX1
YSLC05CH_SOT23-3
USB20_N5 RX8 1 @ 2 0_0402_5% USB20_N5_CAMERA
<14> USB20_N5
USB20_P5 RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA
<14> USB20_P5

1
20191016
- change to 0-ohm for EMI test
4 4
20200114
- RX8/RX9 Change to R-short

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 38 of 112
A B C D E
 A B C D E

+3VS_DP DP@ +3VALW +3VS_DP

CV410
0.1U_0201_10V6K UV3
W=40mils
2 1 5 1
DP@ @ DP@ DP@ DP@ DP@ IN OUT
2

10U_0402_6.3V6M

1U_0201_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

CV401
DP@
1 1 1 1 1 1 GND 1

CV308

CV309

CV310

CV313

CV311

CV312
SUSP# 4 3
<58,68,78,85,88,90> SUSP# EN OC
DP@ UT1
2 2 2 2 2 2 1 35 SY6288C20AAC_SOT23-5 2
VCC EQ1 TH42 TP@
6 38 TH40 TP@ DP@
20 VCC EQ0
VCC
0921 change souce to +3VALW, CTRL to SUSP#
28 17 I2C_EN_TBT
1 VCC I2C_EN 1

2 DPEQ1_TBT +3VS +3VS

DP@ CV403 2 1 .1U_0402_16V7K DP0_TXP0_C 9 DPEQ1 14 DPEQ0_A1_TBT +3VS_DP
<29> DP0_TXP0 DP0_TXN0_C DP0p DPEQ0/A1
DP@ CV402 2 1 .1U_0402_16V7K 10
<29> DP0_TXN0 DP0n

2
3 TH45 TP@ DP@ QY3
DP0_TXP1_C SSEQ1 A0_TBT

1
DP@ CV405 2 1 .1U_0402_16V7K 12 11 RY26 2
<29> DP0_TXP1 DP0_TXN1_C DP1p SSEQ0/A0 Gate
DP@ CV407 2 1 .1U_0402_16V7K 13 DP@ 1M_0402_5%
<29> DP0_TXN1 DP1n DP0_HPD
RV908 1
DP@ CV408 2 1 .1U_0402_16V7K DP0_TXP2_C 15 21 FLIP_TBT_CLK 100K_0402_5% Drain
<29> DP0_TXP2 DP2p FLIP/SCL

1
DP@ CV404 2 1 .1U_0402_16V7K DP0_TXN2_C 16 3
<29> DP0_TXN2 DP2n <16,27> DP0_HPD_PCH Source

2
CTL0_TBT_SDA GPU_DP_AUXN_C

2
22 DP@
DP@ CV406 2 1 .1U_0402_16V7K DP0_TXP3_C 18 CTL0/SDA GPU_DP_AUXP_C LBSS139WT1G_SC70-3 RY25
<29> DP0_TXP3
<29> DP0_TXN3
DP@ CV409 2 1 .1U_0402_16V7K DP0_TXN3_C 19 DP3p
DP3n CTL1
23 CTL1_TBT_HPDIN
To PCH 100K_0402_5%

1
DP@

1
DP0_RD_TXN3 31 34 DP0_RD_TXN2 RV321
DP0_RD_TXP3 30 RX1n TX1n 33 DP0_RD_TXP2 100K_0402_5%
RX1p TX1p

2
DP0_RD_TXN0 39 37 DP0_RD_TXP1
DP0_RD_TXP0 40 RX2n
RX2p
TX2p
TX2n
36 DP0_RD_TXN1 +3VS_DP W=40mils
CONN@ JDP1
8 5 20
RV300 1 DP@ 2 4.7K_0402_5% 7 SSTXp SSRXp 4 19 DP_PWR
+3VS_DP SSTXn SSRXn DP0_AUXN_C_SW GND
18
@ DP0_RD_TXN2 DP@ CV690 2 1 .1U_0402_16V7K DP0_RD_TXN2_C 17 AUX_CH-
RV301 1 2 4.7K_0402_5% 29 27 DP0_AUXP_C_SW 16 LAN2-
RESVD1 SBU1 TH43 TP@ DP0_RD_TXP2 DP0_RD_TXP2_C AUX_CH+
32 26 TH44 TP@ DP@ CV691 2 1 .1U_0402_16V7K 15
2
RESVD2 SBU2 14 LAN2+ 2
24 GPU_DP_AUXP_C 13 GND
DP0_HPD 1 DP@ 2 GPU_DP_HPD_RD 41 AUXp 25 GPU_DP_AUXN_C DP0_RD_TXN3 DP@ CV692 2 1 .1U_0402_16V7K DP0_RD_TXN3_C 12 GND
RV302 0_0402_5% PAD AUXn DP0_RD_TXN1 DP@ CV693 2 1 .1U_0402_16V7K DP0_RD_TXN1_C 11 LAN3- 21
DP0_RD_TXP3 DP@ CV694 2 1 .1U_0402_16V7K DP0_RD_TXP3_C 10 LAN1- GND 22
TUSB546_QFN40_4X6 DP0_RD_TXP1 DP0_RD_TXP1_C LAN3+ GND
1

DP@ CV695 2 1 .1U_0402_16V7K 9 23

8 LAN1+ GND 24
@ DP@ RV907 1 2 1M_0402_5% 7 GND GND
RV1654 DP_CA_DET 6 GND
100K_0402_5% DP0_RD_TXN0 DP@ CV696 2 1 .1U_0402_16V7K DP0_RD_TXN0_C 5 CA_DET
LAN0-
2

4
DP0_RD_TXP0 2 1 DP0_RD_TXP0_C 3 CFG1
DP@ CV697 .1U_0402_16V7K DP0_HPD 2 LAN0+
HP_DET

www.laptoprepairsecrets.com
+3VS_DP 20190924 Vender +3VS_DP +3VS_DP 1
GND
I2C_EN_TBT A0_TBT CTL0_TBT_SDA

1
RV316 1 @ 2 1K_0402_5% RV314 1 @ 2 1K_0402_5% RV306 1 @ 2 1K_0402_5% SDAN_613007-020231
DC06000AIB0
RV317 1 DP@ 2 1K_0402_5% RV315 1 DP@ 2 1K_0402_5% RV307 1 DP@ 2 1K_0402_5% RY35
1M_0402_5%
I2C Programming or pin strap programming select. SSEQ0,SSEQ1 : USB receiver equalizer gain DP@

2
I2C is only disable when this pin is '0' for upstream facing SSTXP/N +3VS_DP
0 : Pin Strap(I2C disable)(Default) F,F(Default) need check pin4 CFG1
R : TI test mode(I2C enable at 3.3V) When I2C_EN is not '0' SSEQ0 sets I2C adress CTL1_TBT_HPDIN RV304 1 DP@ 2 1K_0402_5%
F : I2C enabled at 1.8V
1 : I2C enabled at 3.3V RV305 1 @ 2 1K_0402_5%

+3VS_DP +3VS_DP

DPEQ1_TBT RV312 1 @ 2 1K_0402_5% FLIP_TBT_CLK RV308 1 @ 2 1K_0402_5%

3 3
RV313 1 DP@ 2 1K_0402_5% RV309 1 DP@ 2 1K_0402_5%

DPEQ0,DPEQ1 : DP Receiver equalization gain

F,F(Default)
When I2C_EN is not '0' DPEQ0 sets I2C adress OE# S INPUT/OUTPUT A Function +3VSDGPU
+5VS
+3VS_DP
L L B1 A=B1
DP@ CV339
1 2
DPEQ0_A1_TBT RV310 1 DP@ 2 1K_0402_5%

1
100K_0402_5%
DP@ RV320

100K_0402_5%
DP@ RV318

100K_0402_5%
DP@ RV319
L H B2 A=B2
0.1U_0201_10V6K
RV311 1 @ 2 1K_0402_5%

DP0_AUXP 1 6 DP0_AUXP_PROT
H X Z NC
D

<29> DP0_AUXP
S

2
DP@ DP@
+5VS QY4A UV42
2N7002KDW_SOT363-6 16
Vcc 4 DP0_AUXP_C_SW
G

1A
2
1

DP0_AUXP_PROT DP@ CV337 1 2 0.1U_0201_10V6K DP0_AUXP_C 2 7 DP0_AUXN_C_SW

R4080 DP_AUX_PROT 3 1B1 2A 9
DP0_AUXN_PROT DP@ CV338 1 2 0.1U_0201_10V6K DP0_AUXN_C 5 1B2 3A 12

100K_0402_5%
+5VS 10K_0402_5% 1 2B1 4A

1
DP@ DP@ 6
11 2B2 15

RV322
C2776
3B1 OE
2
1

DP_AUX_PROT
5

0.01U_0201_6.3V7K 10 1 DP_CA_DET
G

R4081 2 14 3B2 S
10K_0402_5% 13 4B1 8
4B2 GND 0:DP

2
DP@ 17 DP@
T-PAD 1:HDMI
1

C DP0_AUXN 4 3 DP0_AUXN_PROT
S

4 <29> DP0_AUXN 4
2

2
D

DP@ SN74CBT3257CRGYR_QFN16_4X3P5
B Q46 QY4B
E MMBT3904_SOT23-3 2N7002KDW_SOT363-6
3

DP@
1

R521 C
1 2 2
<27,37> 3VSDGPU_EN B DP@
Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% E Q45 2019/09/20 2020/09/20 Title
Issued Date Deciphered Date
3

DP@ MMBT3904_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DP CONN (TUSB546)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 39 of 112
A B C D E
 A B C D E

+1.2V_HDMI

+5VS
W=40mils +HDMI_5V_OUT
CV435 +5VALW HDMI_RT_R_CLKP HDMI_RT_CLKP
1U_0201_6.3V6M

22P_0402_50V8J
UY2

1
2 1

10U_0402_6.3V6M

10U_0402_6.3V6M
1
RV435 EMI@ LS15
U14 4.99K_0402_1% 3 4 3

CV437
+3VS 10 1 OUT
VDD VOUT 2 1 1 1
9 2 1

CV438

CV439
VIN VOUT @ IN

2
CV436 8 3 2 1 CY23
10U_0402_6.3V6M 7 VIN VOUT 4 2 0.1U_0201_10V6K
2 1 6 VIN ADJ/NC 5 2 2 HCM1012GH900BP_4P GND 2
EN PGOOD SM070003V00
1 1

1
11 HDMI_RT_R_CLKN HDMI_RT_CLKN AP2330W-7_SC59-3
PAD RV436
RT9059GQW_WDFN10_3X3 10K_0402_1% 20191206 DY1
SA000071S00 20191016 - Remove RY53/RY52/CY27 HDMI_RT_HPD 6 3 HDMI_CTRL_DAT
S IC RT9059GQW WDFN 10P LDO - Add for EMI test - LS15 change to pop (EMI@) I/O4 I/O2

2
+3VS 20191105 5 2
- DY1 DY2 DY3 for EE LL VDD GND

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0201_10V6K
+1.2V_HDMI HDMI_CTRL_CLK +HDMI_5V_OUT
1 1 1 4 1
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
XESD@

CV432

CV433

CV434
0.1U_0201_10V6K

0.01U_0402_16V7K

0.01U_0402_16V7K
0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0402_16V7K
2 2 2 SC300001G00
1 1 1 1 1 1
DY2 XESD@
U15 HDMI_RT_CLKN HDMI_RT_CLKN
1 9

CV425

CV426

CV428

CV430
CV427

CV429
6 1
2 2 2 2 2 2 30 VDD12 VDD33 24 HDMI_RT_CLKP 2 8 HDMI_RT_CLKP
DC coupling enable; Internal pull up, 3.3V I/O. VDD12 VDD33
L: DC coupling input 11
VDDA12 HDMI_RT_TX_N0 HDMI_RT_TX_N0
H: Default,AC coupling input 43 4 7
46 VDDRX12 23 HDMI_RT_R_TX_P2 RY44 1 2 0_0402_5% HDMI_RT_TX_P2
HDMI_DCIN_EN 15 VDDRX12 OUT_D2p 22 HDMI_RT_R_TX_N2 RY45 1 2 0_0402_5% HDMI_RT_TX_N2 HDMI_RT_TX_P0 5 6 HDMI_RT_TX_P0
18 VDDTX12 OUT_D2n
VDDTX12
1

37 20 HDMI_RT_R_TX_P1 RY46 1 2 0_0402_5% HDMI_RT_TX_P1

POWERSWITCH OUT_D1p 19 HDMI_RT_R_TX_N1 RY47 1 2 0_0402_5% HDMI_RT_TX_N1
RV440 CY20 1 2 .1U_0402_16V7K HDMI_TX_P2 38 OUT_D1n 3
<29> GPU_DP2_P0 HDMI_TX_N2 IN_D2p HDMI_RT_R_TX_P0 HDMI_RT_TX_P0
2 4.7K_0402_5% CY21 1 2 .1U_0402_16V7K 39 17 RY48 1 2 0_0402_5% 2
<29> GPU_DP2_N0 IN_D2n OUT_D0p HDMI_RT_R_TX_N0 HDMI_RT_TX_N0
16 RY49 1 2 0_0402_5% TVWDF1004AD0_DFN9
OUT_D0n
2

CY18 1 2 .1U_0402_16V7K HDMI_TX_P1 41

<29> GPU_DP2_P1
CY19 1 2 .1U_0402_16V7K HDMI_TX_N1 42 IN_D1p 14 HDMI_RT_R_CLKP SC300003Z00
<29> GPU_DP2_N1 IN_D1n OUT_CLKp HDMI_RT_R_CLKN
13 20191016
Receiver equalization setting(Internal 150K PD) CY16 1 2 .1U_0402_16V7K HDMI_TX_P0 44 OUT_CLKn - Add for EMI test DY3 XESD@
(*) L: programmable EQ for channel loss up to 5.3dB <29> GPU_DP2_P2 HDMI_TX_N0 IN_D0p HDMI_RT_TX_N1 HDMI_RT_TX_N1
CY17 1 2 .1U_0402_16V7K 45 33 TP@ T212 20191030 1 9
( ) H: programmable EQ for channel loss up to 10dB <29> GPU_DP2_N2 IN_D0n SDA_SRC/AUXN 34
( ) M: programmable EQ for channel loss up to 14dB TP@ T213
CY22 1 2 .1U_0402_16V7K HDMI_CLKP 47 SCL_SRC/AUXP 8 HDMI_CTRL_DAT HDMI_RT_TX_P1 2 8 HDMI_RT_TX_P1
<29> GPU_DP2_P3 HDMI_CLKN IN_CLKp SDA_SNK HDMI_CTRL_CLK
CY24 1 2 .1U_0402_16V7K 48 7
+3VS <29> GPU_DP2_N3 IN_CLKn SCL_SNK HDMI_RT_TX_N2 4 7 HDMI_RT_TX_N2

HDMI_DCIN_EN 3 40 HDMI_HPD HDMI_RT_TX_P2 5 6 HDMI_RT_TX_P2

DCIN_ENB HPD_SRC

www.laptoprepairsecrets.com
1

HDMI_EQ 5 21 HDMI_RT_HPD
@ HDMI_I2C_ADDR 31 EQ HPD_SNK HPD_SNK internal PD 150K ohm
RV441 I2C_ADDR
4.7K_0402_5% 10 3
25 RSV1 32 HDMI_ID
NC HDMI_ID
2

HDMI_EQ 26 9 TVWDF1004AD0_DFN9
RSV2 HDMI_CEC 12
Placed close to REXT pin. CEC_EN SC300003Z00
1

@ RV438 1 2 4.99K_0402_1% 36 29 TP@ T3

RV442 4 REXT CSCL 28 TP@
PDB CSDA T4 +HDMI_5V_OUT
4.7K_0402_5% RESET# 35
Enhance Vswing HDMI_PRE 27 RESETB
PRE
2

2 49
TESTMODEB EPAD HDMI_CTRL_DAT RY40 1 2 2.2K_0402_5% +1.8VSDGPU_AON
HDMI_CTRL_CLK RY41 1 2 2.2K_0402_5%
I2C Slave Address selection; Internal pull down;3.3V I/O GPU_DP2_CTRL_CLK RY42 1 2 2.2K_0402_5%
3 L: Default, Slave address 0x10-0x2F. PS8409AQFN48GTR2-A0_QFN48_6X6 GPU_DP2_CTRL_DAT RY43 1 2 2.2K_0402_5% 3
H: Alternative salve address 0x90-0x9F, 0xD0-0xDF.
SA0000AC320
S IC PS8409AQFN48GTR2-A2 QFN48P REPEATER
+3VS

+HDMI_5V_OUT HDMI connector

1

20191030 CONN@
@ - Vender confirm JHDMI1
RV443 HDMI_RT_HPD 19
4.7K_0402_5% 18 HP_DET
17 +5V
DDC/CEC_GND
2

HDMI_I2C_ADDR +3VS +3VS HDMI_CTRL_DAT 16

+1.8VSDGPU_AON HDMI_CTRL_CLK 15 SDA
Output pre-emphasis setting;Internal pull-up 3.3V I/O 14 SCL
Reserved
2

L: Pre-emphasis =2.5dB 13
H: Default, No Pre-emphasis HDMI_RT_CLKN 12 CEC 20
RY24 11 CK- GND 21
HDMI_PRE CK_shield GND
2

1M_0402_5% HDMI_RT_CLKP 10 22
G

CK+ GND

5
QY2A HDMI_RT_TX_N0 9 23
D0- GND
1
1

2N7002KDW_SOT363-6 8

G
4 3 HDMI_CTRL_CLK HDMI_RT_TX_P0 7 D0_shield
1 6 HDMI_HPD <29> GPU_DP2_CTRL_CLK HDMI_RT_TX_N1 6 D0+
@ RV444 QY1A

D
S

<16,27> HDMI_HPD_PCH 5 D1-

D

4.7K_0402_5% PJT138KA_SOT363-6
+3VS HDMI_RT_TX_P1 4 D1_shield
D1+
2

2
HDMI_RT_TX_N2 3
2 D2-
RY11 design guide rev2.0 RY11

G
D2_shield
2

use 20K pull down. 100K_0402_5% 1 6 HDMI_CTRL_DAT HDMI_RT_TX_P2 1

HDMI_ID enable ; Internal pull down;3.3V I/O <29> GPU_DP2_CTRL_DAT D2+
RV437 QY1B

D
L: Default, HDMI ID enable
H: HDMI ID disable 10K_0402_5% PJT138KA_SOT363-6 ACON_HMR2E-AK120D
4 4
1

3ohm/10pF DC232000Y00
3

D
1

+3VS RESET# 5 QY2B

+3VS G 2N7002KDW_SOT363-6
1
1

CV431 S
Security Classification Compal Secret Data Compal Electronics, Inc.
4

@ 1U_0201_6.3V6M
RV445
2 Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
4.7K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
2

HDMI_ID Size Document Number Rev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 40 of 112
A B C D E
 5 4 3 2 1

20191014
- Change to "with no Dual Role support"
- 5441E only uses the function of CC & Power SW

D D

+5VALW +5VALW_MUX

US14
5 1
IN OUT
2

10U_0402_6.3V6M

0.1U_0201_10V6K
GND 1 1
4 3

CS116

CS15
<58> USB_TYPEC_EN EN OC
SY6288C20AAC_SOT23-5 2 2

Close to Pin19

US3

VMON 17 12 CC1_VCONN CC1_VCONN CS130 1 2 220P_0402_50V8J

VMON CC1 CC2_VCONN CC1_VCONN <43> CC2_VCONN
14 CC2_VCONN <43> CS129 1 2 220P_0402_50V8J
OCP_DET# 16 CC2
<43> OCP_DET# OCP_DET
USBC_EN 15
<43> USBC_EN VBUS_EN Type-C Port Side
C 11 C
System side C_TX2_1P/2N 10
C_TX2_1N/2P
4
5 SSRX_1P/2N 24
SSRX_1N/2P C_RX2_1P/2N 1
C_RX2_1N/2P

6 10 Gbps 2:1 MUX 8

7 SSTX_1P/2N C_TX1_1P/2N 9
SSTX_1N/2P C_TX1_1N/2P

2
C_RX1_1P/2N

www.laptoprepairsecrets.com
3
PLUG_ORI 23 C_RX1_1N/2P
M1 21 GPIO
M0 22 CURRENT_M1
CURRENT_M0

VCON_IN
LDO_3V3
18
REXT

5V_IN
1

RS129 25
6.2K_0402_1% E-PAD
RTS5441E-GRT_QFN24_4X4

20

19

13
SA0000C3L00
2

+3VO_MUX +5VALW_MUX
B B

1 1
CS14 CS117
4.7U_0402_6.3V6M 0.1U_0201_10V6K
2 2
Close to Pin13
+3VO_MUX +3VO_MUX
1

+5VALW_MUX +USB3_VCCC
1

RS1 RS3
RS114 @ 10K_0402_5% 10K_0402_5%
1

10K_0402_5%
2

RS20 RS134
2

PLUG_ORI M1 M0 1 @ 2 4.7K_0402_5% 200K_0402_1%

TYPEC_1P5A_EC <43,58>
RS137 0_0402_5%
1

OCP_DET# VMON
RS115 RS2 @ RS4 @
1

10K_0402_5% 10K_0402_5% 10K_0402_5%

RS135
2

RS128 10K_0402_1%
10K_0402_5%
A A
2

5441E Current Limit

confirm realtek hand-shake
M1 M0 MODE RTS5441 M0 truth table by 2018 BIOS spec
L H 0.9A TYPEC_1P5A_EC
MODE limit point Condition
Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
H L 1.5A H 3A 3.5A AC mode or Battery >30% CC+USB TYPE C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
L Size Document Number Rev
H H 3A 1.5A 1.92A Battery <30% when DC mode AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 42 of 112
5 4 3 2 1
 5 4 3 2 1

USB3_PTX_DRX_P3 CS112 1 2 0.33U_0201_6.3V6M USB3_CC_TX_P3_C +5VALW +USB3_VCCC

<17> USB3_PTX_DRX_P3 USB3_PTX_DRX_N3
<17> USB3_PTX_DRX_N3 CS113 1 2 0.33U_0201_6.3V6M USB3_CC_TX_N3_C
USB3_CC_RX_P3_C
USB3_CC_RX_N3_C

SGA00003700
150U_D2_6.3VY_R15M
CS95
1
USB3_PRX_DTX_P3 CS121 1 2 0.33U_0201_6.3V6M USB3_CC_RX_P3_C

0.1U_0201_10V6K

0.1U_0402_25V6

22U_0805_25V6M

22U_0805_25V6M
<17> USB3_PRX_DTX_P3 1 1 1 1
USB3_PRX_DTX_N3 CS122 1 2 0.33U_0201_6.3V6M USB3_CC_RX_N3_C +

CS96

CS97 @

CS98 @

CS99 @
<17> USB3_PRX_DTX_N3

2
RS130 RS131
USB3_PTX_DRX_P4 CS114 1 2 0.33U_0201_6.3V6M USB3_CC_TX_P4_C 220K_0201_1% 220K_0201_1% 2 2 2 2 2
<17> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 CS115 1 2 0.33U_0201_6.3V6M USB3_CC_TX_N4_C US11
<17> USB3_PTX_DRX_N4

1
6 1
USB3_PRX_DTX_P4 CS123 1 2 0.33U_0201_6.3V6M USB3_CC_RX_P4_C IN OUT
D <17> USB3_PRX_DTX_P4 D
USB3_PRX_DTX_N4 CS124 1 2 0.33U_0201_6.3V6M USB3_CC_RX_N4_C
<17> USB3_PRX_DTX_N4 USB3_CC_RX_P4_C RSET 5 2
USB3_CC_RX_N4_C SET GND 1 @ 2
OCP_DET# <42>
RS136 0_0402_5%
20191014 4 3 1 @ 2
<42> USBC_EN EN FLAG USB_OC0# <14>

2
- Change to "with no Dual Role support" RS112 0_0402_5%

1
RS132 RS133 G518B1TP1U_TSOT23-6 20200114
- CS112/113/114/115 change to 0.33U 1 -RS112 Change to R-short
220K_0201_1% 220K_0201_1% RB77
47K_0402_5%
Footprint : G518 CS100
0.1U_0201_10V6K
20191016 PN : SA0000BDN00

1
2
- USB3 Port5 change to Port3 (SILERGY SY6861B1)

2
20191015 - Pin SWAP for layout RSET
20191016 For ESD request - Gen2 Solution SC300006T00

1
RS109 RS110
RS113
4.3K_0402_5% 8.2K_0402_5%
6.2K_0402_1%

3 2
DS6 ESD@
USB3_CC_TX_P4_C 1 9 USB3_CC_TX_P4_C D
5 TYPEC_3A <18>
USB3_CC_TX_N4_C 2 8 USB3_CC_TX_N4_C G

USB3_CC_RX_N3_C 4 7 USB3_CC_RX_N3_C G518 MOS Current Limit S QS2B

4
C GPP_B1 GPP_B4 RSET(kΩ ) MODE limit point 2N7002KDW_SOT363-6 C
USB3_CC_RX_P3_C USB3_CC_RX_P3_C

6
5 6 (TYPEC_1P5A) (TYPEC_3A) D
2
L L 6.2 0.9A 1.09A G
TYPEC_1P5A_EC <42,58>

3 L H 3.53 1.5A 1.92A S QS2A

1
TVWDF1004AD0_DFN9
H L 2.54 2A 2.67A 2N7002KDW_SOT363-6
check bios
SC300006T00 *H H 1.94 3A 3.5A 1050 is use PCH output
DS4 ESD@
1 9

www.laptoprepairsecrets.com
2 8
USB3_CC_TX_P3_C 4 7 USB3_CC_TX_P3_C

USB3_CC_TX_N3_C 5 6 USB3_CC_TX_N3_C

TVWDF1004AD0_DFN9 +USB3_VCCC +USB3_VCCC

SC300006T00
JTYPEC1 CONN@
DS3 ESD@ A1 B12
USB3_CC_RX_N4_C 1 9 USB3_CC_RX_N4_C GND GND
USB3_CC_TX_P4_C A2 B11 USB3_CC_RX_P4_C
B USB3_CC_RX_P4_C 2 8 USB3_CC_RX_P4_C USB3_CC_TX_N4_C A3 SSTXP1 SSRXP1 B10 USB3_CC_RX_N4_C B
0.1U_0402_25V6 2 1 CS84 SSTXN1 SSRXN1
TBTA_SBU1 4 7 TBTA_SBU1 A4 B9 CS87 1 2 0.1U_0402_25V6
VBUS VBUS
1
CC1_VCONN 5 6 CC1_VCONN CS13 A5 B8 TBTA_SBU2
<42> CC1_VCONN CC1 RFU2
10U_0603_25V6M
USB20_P4_L A6 B7 USB20_N4_L
2 USB20_N4_L A7 DP1 DN2 B6 USB20_P4_L
3 DN1 DP2

2
TBTA_SBU1 A8 B5
RFU1 CC2 CC2_VCONN <42>
TVWDF1004AD0_DFN9 0.1U_0402_25V6
SC300006T00 2 1 CS86 A9 B4 CS85 1 2 0.1U_0402_25V6
DS19 ESD@ VBUS VBUS
DS5 ESD@ PESD24VS2UT_SOT23-3 USB3_CC_RX_N3_C A10 B3 USB3_CC_TX_N3_C
CC2_VCONN 1 9 CC2_VCONN SCA00004500 USB3_CC_RX_P3_C A11 SSRXN2 SSTXN2 B2 USB3_CC_TX_P3_C
SSRXP2 SSTXP2
1

TBTA_SBU2 2 8 TBTA_SBU2 A12 B1

GND GND
USB20_N4_L 4 7 USB20_N4_L 1
2 GND 7
USB20_P4_L 5 6 USB20_P4_L 3 GND GND 8
4 GND GND 9
5 GND GND 10
6 GND GND
3 GND

TVWDF1004AD0_DFN9 SINGA_2UB3C02-008111F
SC300006T00 DC23300TZA0
A A
SINGA_2UB3C02-008111F_24P-T

LS10 EMI@
CC1_VCONN & CC2_VCONN need 20miil trace width.
USB20_N4 2 1 USB20_N4_L
<14> USB20_N4 2 1

<14> USB20_P4
USB20_P4 3
3 4
4 USB20_P4_L Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
DLM0NSN900HY2D_4P
SM070005U00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC+USB TYPE C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 43 of 112
5 4 3 2 1
 5 4 3 2 1

D D

20190918 C

LAN more to IO/B

www.laptoprepairsecrets.com
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Killer-E2600
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 51 of 112
5 4 3 2 1
 A B C D E

UART BT
Wireless LAN WAKE_BT_R
UART_WAKE#_R
PCM_CLK_R
UART_BT@
UART_BT@
UART_BT@
RM62
RM63
RM64
1
1
1
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
WAKE_BT
UART_WAKE#
PCM_CLK
WAKE_BT <19>
UART_WAKE# <18>
PCM_CLK <18>
PCM_OUT_R UART_BT@ RM65 1 2 0_0402_5% PCM_OUT
PCM_OUT <18>

+3VALW
W=60mils +3VS_WLAN 20191007
UM1 - Add RM62/63/64/65
5 1
1U_0201_6.3V6M
CM15

IN OUT
1
2
@ GND Co-layout with CNVi for SW debug
1 1
4 3
2 <58> WLAN_ON EN OC UART_2_PRXD_R_DTXD RM42 1 UART@ 2 0_0402_5%
UART_2_PTXD_R_DRXD UART_2_PRXD_DTXD <19>
SY6288C20AAC_SOT23-5 RM43 1 UART@ 2 0_0402_5%
UART_2_PTXD_DRXD <19>
IOAC@

20191210C [FH51M CNVi review] 20191205 [FH5VF CNVi review]

+3VALW +3VS_WLAN +3VS_WLAN
> RM69 change to 71.5k & CNVI@ Pin10 - RM41 Close to PCH
RM44 1 @ 2 0_0805_5% > RM70 set CNVI@ Pin14 - CLKREQ_CNV# PD RM69(71.5K) (Reserve) UART_WAKE#_R RM70 1 CNVI@ 2 4.7K_0402_5%
> RH22 change to 20K Pin20 - UART_WAKE PU RM70(4.7K) (Reserve)
+3VS reserve for cnvi CLKREQ_CNV# RM69 1 CNVI@ 2 71.5K_0402_1%
> RM36/RM37/RM67/RM68 change to 22 ohm Pin22 - RM36@M.2 / RH181@PCH
RM11 1 NIOAC@2 0_0805_5%
> RM16 recommend to 4.7K (no action) Pin32 - RM37@PCH / RH22@M.2
> RM199 recommend to pop (no action) Pin34 - RM67@M.2 / RH182@PCH
0.1U_0201_10V6K

0.1U_0201_10V6K
CM14
60mil 1 1 1 1@
> RM45 recommend to10K (no action) Pin36 - RM68@PCH / RH15@M.2
CM13 @
CM12 CM19
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M > WL_OFF# recommend to PU 10K (no action)
2 2 2 2
reserve 1000p for cnvi
KEY E +3VS_WLAN
CM18 1
@
2 1000P_0402_50V7K
+3VS_WLAN JNGFF1
1 2
GND_1 3.3VAUX_2 CNVI@
3 4 @ T52
1 RM41 2
<14> USB20_P14 USB_D+ 3.3VAUX_4
(For BT) 5 6 75K_0402_1%
<14> USB20_N14 USB_D- LED1# PCM_CLK_R
7 8
10U_0402_6.3V6M
@ CM51

0.01U_0201_6.3V7K
@ CM53

10U_0402_6.3V6M
@ CM52

0.01U_0201_6.3V7K
@ CM54

1 1 1 1 GND_7 PCM_CLK
2 9 10 CNV_RF_RESET#_R RM34 1 @ 2 0_0201_5% 2
<15> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC PCM_OUT_R CNV_RF_RESET# <18>
11 12
<15> CNV_PRX_DTX_P1 SDIO_CMD PCM_OUT CLKREQ_CNV#_R
13 14 RM35 1 @ 2 0_0201_5% CLKREQ_CNV# <18>
2 2 2 2 15 SDIO_DAT0 PCM_IN 16
<15> CNV_PRX_DTX_N0 SDIO_DAT1 LED2# @ T53
<15> CNV_PRX_DTX_P0
17 18
19 SDIO_DAT2 GND_18 20 UART_WAKE#_R
21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 22_0402_5%
<15> CLK_CNV_PRX_DTX_N 23 SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <15>
<15> CLK_CNV_PRX_DTX_P SDIO_RST
20200114 - For CNVi 24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 22_0402_5%
- CM51/CM53 Close to JNGFF1 Pin 2,4 UART_RX 26 CNV_RGI_PRX_R_DTX 1 CNVI@ 2 22_0402_5% CNV_RGI_PTX_DRX <15>
25 RM67
- CM52/CM54 Close to JNGFF1 Pin 64,66 GND_33 UART_RTS CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX <15>
27 28 RM68 1 CNVI@ 2 22_0402_5%
<17> PCIE_PTX_C_DRX_P15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R CNV_BRI_PTX_DRX <15>
29 30 RM12 1 @ 2 0_0201_5%
<17> PCIE_PTX_C_DRX_N15 PET_RX_N0 CLink_RST E51TXD_P80DATA <58>

www.laptoprepairsecrets.com
31 32 E51RXD_P80CLK_R RM13 1 @ 2 0_0201_5%
GND_39 CLink_DATA E51RXD_P80CLK <58>
33 34
NGFF WL+BT (KEY E) (link to PICE Port 3)
PCIE X1
<17> PCIE_PRX_DTX_P15
<17> PCIE_PRX_DTX_N15
35
37
PER_TX_P0
PER_TX_N0
CLink_CLK
COEX3
36
38
WAKE_BT_R
20191205
39 GND_45 COEX2 40 - RM66 Change to @ for Vender review
<15> CLK_PCIE_WLAN REFCLK_P0 COEX1 SUSCLK_R
41 42 RM66 1 @ 2 0_0402_5%
<15> CLK_PCIE_WLAN# REFCLK_N0 SUSCLK(32KHz) WL_RST#_R SUSCLK <18,68,69>
(From PCH CLKOUT2) 43 44 RM15 1 @ 2 0_0201_5%
45 GND_51 PERST0# 46 BT_ON PLT_RST_BUF# <16,68,69,73>
PCIE CLK <15> WLAN_CLKREQ# CLKREQ0# W_DISABLE2# BT_ON <16,58>
WLAN_PME# 47 48 WL_OFF#
49 PEWAKE0# W_DISABLE1# 50 WL_OFF# <58>
51 GND_57 I2C_DAT 52
<15> CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
53 54
<15> CNV_PTX_DRX_P1 55 RSVD/PCIE_RX_N1 I2C_IRQ 56 REFCLK_CNV_R RM40 1 ESD@ 2 0_0402_5%
GND_63 RSVD_64 REFCLK_CNV <15>
57 58
<15> CNV_PTX_DRX_N0 59 RSVD/PCIE_TX_P1 RSVD_66 60 For CNVi Feature
<15> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68 62
61 1
3 63 GND_69 RSVD_70 64 CM17 XESD@ 3
<15> CLK_CNV_PTX_DRX_N 65 RSVD_71 3.3VAUX_72 66 0.1U_0201_10V6K
<15> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74
67 For ESD req reserve LC filter
GND_75 68 2
69 GND1 close PCH
GND2
BELLW_80152-3221
CONN@ E51TXD_P80DATA_R
SP070013E00

1
RM19
100K_0402_5%
2 1 WLAN_PME#
+3VS_WLAN
RM16 10K_0402_5%

2
reserve for BT_ON OD pull high (1.0)

BT_ON 1 @ 2
4 +3VS_WLAN 4
8.2K_0402_5% RM45

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 Key E (WLAN)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 52 of 112
A B C D E
 5 4 3 2 1

Digital MIC

DMIC_DATA 2 1 DMIC_DATA_R
RA1 0_0402_5% DMIC_DATA_R <38>
PCH_DMIC_DATA0 2 @ 1
<18> PCH_DMIC_DATA0
RA3 33_0402_5%
PCH_DMIC_CLK0 2 @ 1 TO eDP cable
<18> PCH_DMIC_CLK0
SM01000EJ00 SM01000EJ00 RA4 33_0402_5%
0926 1004
+5VS 3000ma220ohm@100mhz +5VS_PVDD +5VS_AVDD 3000ma 220ohm@100mhz +5VS DMIC_CLK 2 1 DMIC_CLK_R
DCR 0.05 LA2 DCR 0.04 LA1 LA3 EMI@ BLM15PX221SN1D_2P DMIC_CLK_R <38>
D 1 2 1 2 SM01000Q500 D
HCB2012KF-221T30_2P_0805 HCB2012KF-221T30_2P_0805
20191008 Change PN to SM01000Q500

1
- change to unpop

100_0402_5%
RA2
XEMI@

10P_0402_50V8J
CA7
XEMI@
1 1 1 1 1 1

1
10U_0402_6.3V6M
CA8

0.1U_0201_10V6K
CA9

10U_0402_6.3V6M
CA5

0.1U_0201_10V6K
CA3

10U_0402_6.3V6M
CA6

0.1U_0201_10V6K
CA4
1 1 1 1

10U_0402_6.3V6M
CA10

0.1U_0201_10V6K
CA11

10U_0402_6.3V6M
CA12

0.1U_0201_10V6K
CA13

2
2 2 2 2 2 2

2
2 2 2 2

near

330P_0402_50V7K
CA1
XEMI@
near near GNDA Pin40 1
Pin41 Pin46
2

+1.8VS_AVDD 1 @ 2
RA5 0_0402_5%
+1.8VS Fallow Raptor
near CA14 1 2 0.1U_0201_10V6K
Pin18 1 1
CA17 1 2 10U_0402_6.3V6M

10U_0402_6.3V6M
CA15

0.1U_0201_10V6K
CA16
1 @ 2 +3VS_DVDDIO 2 2
+3VS
RA6 0_0402_5% Headphone Out
+3VS_DVDD near
GNDA Pin20 +MIC2_VREFO_R
+3VS 1 @ 2
RA7 0_0402_5% +MIC2_VREFO_L

1
2.2K_0402_5%
RA8
1 1 1

1
1 2 0_0402_5%

10U_0402_6.3V6M
CA18

0.1U_0201_10V6K
CA19

0.1U_0201_10V6K
CA20

2.2K_0402_5%
RA10
RA9 @ +5VALW

2
2 2 2
SLEEVE

18

41

46

40

20

33
HDA_BITCLK_AUDIO SLEEVE <73>

2
3
UA1
near RING2
Pin3 RING2 <73>

PVDD1

PVDD2

AVDD1
DVDD

DVDD-IO

5VSTB/AUX MODE
CPVDD/AVDD2
C C

1
XEMI@
RA11
0_0402_5% HPOUT_R 1 2 HPOUT_R_1
LINE1_L 36 HPOUT_R_1 <73>
RA16 47_0402_5%
LINE1_R LINE1-L(PORT-C-L) HPOUT_L HPOUT_L_1

2
35 1 2
LINE1-R(PORT-C-R) HPOUT_L_1 <73>
1 RA17 47_0402_5%
XEMI@
RING2 30 43 SPKL- CA23
SLEEVE 31 MIC2-L(PORT-F-L) /RING2 SPK-OUT-L- 42 SPKL+ 22P_0402_50V8J LINE1_R CA28 1 2 4.7U_0402_6.3V6M
MIC2-R(PORT-F-R) /SLEEVE SPK-OUT-L+ 2
LINE1_L 2 2

3
45 SPKR+ CA24 1 2 4.7U_0402_6.3V6M

TVNST52302AB0_SOT523-3
D2
@
330P_0402_50V7K
CA26
@

330P_0402_50V7K
CA27
@
DMIC_DATA 4 SPK-OUT-R+ 44 SPKR-
1 GPIO0/DMIC-DATA12 SPK-OUT-R-
DMIC_CLK 5 GPIO2/DMIC-DATA34 1 1
GPIO1/DMIC-CLK 27 HPOUT_L
7 HPOUT-L(PORT-I-L) 26 HPOUT_R 20191016
I2C-CLK HPOUT-R(PORT-I-R)

1
6 - RA14 change to 0-ohm

www.laptoprepairsecrets.com
I2C-DATA 15 HDA_SYNC_R
AUDIOLINK:SYNC 14 HDA_BITCLK_AUDIO 1 2 HDA_SYNC_R <18> GNDA GND 20191104
11 AUDIOLINK:BCLK 17 HDA_SDOUT_R RA14 0_0402_5% HDA_BIT_CLK_R <18> - Config change to @
8 I2S-MCLK AUDIOLINK:SDATA-OUT 16 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <18>
I2S-IN AUDIOLINK:SDATA-IN HDA_SDIN0 <18>
12 RA15 22_0402_5%
10 I2S-LRCK
9 I2S-BCLK 29 +3VS_DVDD
I2S-OUT MIC2-VREFO-R +MIC2_VREFO_R
20191025 28 +MIC2_VREFO_L
- CA25 Change to 0201 SE00000UC00 MIC2-VREFO-L

100K_0402_1%
RA20
1
CA25 1 2 1U_0201_6.3V6M
23 39
24 CBP LDO1-CAP 21
CBN LDO2-CAP 19
LDO3-CAP TO Audio Jack
MONO_IN SENSE_A HP_PLUG#

2
34 2 1
PCBEEP CODEC_VREF HP_PLUG# <73>

1
38 RA21 200K_0402_1%

10U_0402_6.3V6M
CA29

10U_0402_6.3V6M
CA30

10U_0402_6.3V6M
CA31

100K_0402_5%
RA19
VREF 1 1 1
13

0.1U_0201_10V6K
CA35
DC-DET/EAPD 1
MUTE# 2
PDB 25 CPVEE 2 2 2
SENSE_A CPVEE

2
B 48 B
47 HP/LINE1-JD(JD1) 37 2

1U_0201_6.3V6M
CA32

2.2U_0402_6.3V6M
CA33
I2S-IN/I2S-OUT-JD(JD2) AVSS1 22
1 1 RA21
32 AVSS2 49
MIC2-CAP Thermal Pad HP-JD LINE1-JD
1 2 2 GNDA GNDA
CA34 ALC299-CG_MQFN48_6X6 Near pin 48 200K 100K
10U_0402_6.3V6M
2 GNDA GNDA GNDA
SA0000A5L00
GNDA 20191025
ALC295 use ALC299 symbol - CA32 Change to 0201 SE00000UC00
Speaker
CONN@
MUTE# +3VS_DVDD SPKR+ LA6 1
EMI@
2 HCB1608KF-121T30_0603 SPK_R+ 1
JSPK1

M/B SPKR- LA7 1

EMI@
2 HCB1608KF-121T30_0603 SPK_R- 2 1
2 3
G1 4
Raptor:289 G2

1
CVILU_CI4202M2HR0-NH
RA22 SP02001CK00
10K_0402_5% SPKL+ SPKL+ <73>
IO/B SPKL- SPKL- <73>

2
RA23 2 1 10K_0402_5%
<58> EC_MUTE#
RA24 2 @ 1 10K_0402_5% MUTE#
<18> HDA_RST#_R
BEEP
1
@ RA25
10K_0402_5%
BEEP#_R MONO_IN
2

RA30 1 @ 2 0_0402_5% RA39 2 1 22K_0402_5% CA36 1 2 0.1U_0201_10V6K

<58> BEEP#
RA31 1 @ 2 0_0402_5%
RA38 2 1 22K_0402_5%
A <18,19> PCH_SPKR A

1
RA32 1 @ 2 0_0402_5% 1
@
RA33 1 @ 2 0_0402_5% CA37 RA40
100P_0402_50V8J 5.1K_0402_1%
RA34 1 @ 2 0_0402_5% 2

2
20191008
RA35 1 @ 2 0_0402_5% - RA39/RA38 change to 22k
RA36 1 @ 2 0_0402_5% - RA40 change to 5.1k
RA37 1 @ 2 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Code ALC295
GND GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 56 of 112
5 4 3 2 1
 A B C D E

RB3 Board ID
PVT@
- Analog Board ID definition,Please see page 3.
S RES 1/16W 20K +-1% 0402
SD034200280 +3VLP_EC

+3VLP_EC +3VLP_ECA

2
+3VLP LB1 RB3
JPB1 FBMA-L11-160808-800LMT_0603 RB1
1 2 1 2 +3VLP_ECA PVTRGB@ 100K_0402_1%
1 2 Ra
+3VLP_EC S RES 1/16W 43K +-1% 0402
JUMP_43X39 SD034430280
EC_PME# AD_BID

1
1 2 47K_0402_5%

0.1U_0201_10V6K

0.1U_0201_10V6K
RB4 @ @ 1 1 1

CB1

CB2
CB3

2
20200211 @
- ADD PVT@ & PVTRGB@ for PVT BOM 1
1 For Power consumption 2 2
@ RB2
2
0.1U_0201_10V6K RB3 @ CB4 1
0_0402_5% 0_0402_5% Rb 0.1U_0201_10V6K
Measurement
ECAGND 2
ECAGND <66,84>

1
+3VLP_LPC
CB14 1 2 0.1U_0201_10V6K EC_RST#

125
111
22
33
96

67
9
UB1 near SOC PCH_RTCRST# <18>
ESPI Bus Pin : 1~5.7.8.10.12.14

VCC

VCC

AVCC
VCC
VCC

VCC0
VCC_LPC
D

1
LPC Bus Pin : 3~5.7.8.10.12.13
EC_CLR_CMOS 2 QB6
G L2N7002WT1G_SC-70-3
EC_VCCST_PG_R

1
For turn off internal LPC module of KB9032 SUSPWRDNACK 1 21 S SB00001GE00
<18> SUSPWRDNACK GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <10,78>

3
CHG_CTL3 2 23 BEEP# RB26
<71> CHG_CTL3 TPM_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <56>
XESD@ 10K_0402_5%
1 2 100P_0402_50V8J PLT_RST# <17,66> TPM_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 FAN_PWM2 FAN_PWM1 <77>
CB5
<17> LPC_FRAME# LPC_AD3 LPC_FRAME# PWM Output AC_OFF/GPIO13 FAN_PWM2 <77>
5
<17> LPC_AD3 LPC_AD2 LPC_AD3

2
7
20200114 <17> LPC_AD2 LPC_AD1 LPC_AD2 BATT_TEMP
CB6 1 2 100P_0201_50V8J ACIN 8 63
- CB6 Change to SE00000SE00 (0201) <17> LPC_AD1 LPC_AD0 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 CHG_CTL1 BATT_TEMP <84,85>
<17> LPC_AD0 LPC & MISC
LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I CHG_CTL1 <71>
65
CLK_LPC_R ADP_I/AD2/GPIO3A AD_BID ADP_I <84,85>
XEMI@ XEMI@ 12 AD Input 66 20191025 20200114
2 1 2 1 CLK_LPC_R <17> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 - Reserved Thermal_ALERT# - RB87 Change to R-short
<16,27,66> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 VRAM_TEMP <66,84>
CB7 RB6 37 76 IDCHG
<77> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 IDCHG <85>
22P_0402_50V8J 33_0402_5% RB87 1 @ 2 0_0402_5%
<19> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E GPU_OVERT# <27>
<52> WLAN_ON CLKRUN#/GPIO1D 1 2 THERMAL_ALERT#
GPIO3F @
USB_TYPEC_EN THERMAL_ALERT# <66>
68 RB86 0_0402_5%
<63> KSI[0..7] DA0/GPIO3C EC_TP_INT# USB_TYPEC_EN <42>
DA Output 70
EN_DFAN1/DA1/GPIO3D VR_PWRGD EC_TP_INT# <16,63>
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 GPIO3F
+3VLP_EC KSI2 57 KSI1/GPIO31 DA3/GPIO3F
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN EC_MUTE# <56> SYS_PWROK_R
RB10 1 2 2.2K_0402_5% KSI4 59 84 1 @ 2 SYS_PWROK <18,78>
2 EC_SMB_DA1 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B USB_EN <73> 2
RB11 1 2 2.2K_0402_5% KSI5 60 85 RB7 0_0402_5%
61 KSI5/GPIO35 PSCLK2/GPIO4C 86 EC_SMB_CK3 <63>
KSI6 PS2 Interface
62 KSI6/GPIO36 PSDAT2/GPIO4D 87 TP_CLK EC_SMB_DA3 <63>
KSI7
+5VS <63> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <63>
KSO0 39 88
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <63> +3VS
KSO1 40
RB79 1 2 4.7K_0402_5% EC_SMB_CK3 KSO2 41 KSO1/GPIO21
RB80 1 2 4.7K_0402_5% EC_SMB_DA3 KSO3 42 KSO2/GPIO22 97 ENBKL
43 KSO3/GPIO23 ENKBL/GPXIOA00 98 TP_PWR_EN ENBKL <17>
KSO4
20191206 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <63>
KSO5/GPIO25 Int. K/B
KSO5
- RB79/RB80 change power source to +5VS ME_EN/GPXIOA02 VCIN0_PH ME_EN <18> GPU_OVERT#
KSO6 45 109 RB12 1 VGA@ 2 10K_0402_5%
for power leakage .
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <84>
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
KSO9 48 119
49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON_R RB85 1 2 0_0402_5% BT_ON SPOK_5V <86>
KSO10 @
SPOK_3V KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <16,52> +3VLP_EC
RB72 1 @ 2 0_0402_5% KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
51 KSO11/GPIO2B 128 FP_PWR_EN
KSO12
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <66> EC Internal PU

www.laptoprepairsecrets.com
KSO13 52
SPOK_5V RB73 1 @ 2 0_0402_5% SPOK_3V5V KSO14 53 KSO13/GPIO2D LID_SW# RB13 1 2 100K_0402_1%
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R TYPEC_1P5A_EC <42,43>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89
KSO17/GPIO49 GPIO50 BATT_BLUE_LED# BATT_4S <85>
90
For abnormal
shutdown BATT_CHG_LED#/GPIO52 91 TURBO_LED# BATT_BLUE_LED# <62>
For Thermal Portect Shutdown
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# TURBO_LED# <77>
SPOK_3V5V EC_RSMRST# <84,85> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <62>
1 2 78 93
<84,85> EC_SMB_DA1 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <62>
DB2 RB751V-40_SOD323-2 SYSON DB1
<18,27,66> PCH_SML1CLK EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <78,88>
80 RB751V-40_SOD323-2
<18,27,66> PCH_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 CHG_ILMSEL VR_ON <78,90,91> 3V_EN
MAINPWON 1 2
1 2 PCH_PWROK PU at CPU side DPWROK_EC/GPIO59 CHG_ILMSEL <71> 3V_EN <86>
SM Bus 1
DB3 RB751V-40_SOD323-2 RB14
PM_SLP_S3# 6 100 EC_RSMRST# CB8 3V_EN_R 1 2 RB15 1 2
<18,78> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <18>
0.1U_0201_10V6K 1M_0402_5%
EC_VCCST_PG_R <17,36> OVRM_EN GPIO07 GPXIOA04 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <19,27,85> 2
1 2 15 102 XESD@ 1K_0402_5%
<86,89> SPOK_3V TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <84>
DB4 RB751V-40_SOD323-2
<63> TP_EN GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104
GPIO0B 17 MAINPWON
18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 MAINPWON <77,84,86>
3 GPIO0C BKOFF# 3
AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 EC_PME# BKOFF# <38>
<18> AC_PRESENT AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R EC_PME# <16,73>
25 107
<63> KBL_EN FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10
28 108 @ RB17
VCOUT1_PROCHOT <77> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 CHG_EN <71>
29 0_0402_5%
<77> FAN_SPEED2 E51TXD_P80DATA 30 FANFB1/GPIO15 1 2 VR_HOT#
<52> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 VR_HOT# <91>
2

110 ACIN
<52> E51RXD_P80CLK PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 EC_ON ACIN <85>
RB19 @ RB18
<18,78> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <86>
@ 0_0402_5% 114 ON/OFFBTN# 0_0402_5%
<62> PWR_SUSP_LED# TURBO_EN# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 ON/OFFBTN# <63> H_PROCHOT#
36 GPI 115 LID_SW# 1 2 SW_PROCHOT#
<77> TURBO_EN# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <66> <10,85> H_PROCHOT#
116 SUSP#
SUSP#/GPXIOD05 SW_PROCHOT# SUSP# <39,68,78,85,88,90>
1

117
DGPU_AC_DETECT SW_PROCHOT# GPXIOD06 118 EC_PECI 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <10,17>
122 RB16 33_0402_1%
<18> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D
@ @ 123 124
<18,78> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC
QB1A QB1B
3
6

AGND

2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6
GND
GND
GND
GND
GND

VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT
G G
KB9022QD_LQFP128_14X14
11
24
35
94
113

ECAGND 69

S S
CO-LAY with KB9032QA (SA000080J00) 20mil
1

CB9 1 2 BATT_TEMP 20200114

100P_0201_50V8J - CB6 Change to SE00000SE00 (0201)
LB2 2 1
FBMA-L11-160808-800LMT_0603
20191008
- For KC3810
2015/1/9 acer require:
reserved protact circuit when
XESD@ <59> ESB_CLK
ESB_CLK RB84 1 @ 2 0_0402_5% adaptor 107% happen
CB10 1 2 .1U_0402_16V7K SUSP# ESB_DAT RB83 1 @ 2 0_0402_5%
<59> ESB_DAT
XESD@
CB11 1 2 .1U_0402_16V7K TS_EN RB82 1 2 0_0402_5% GPIO0B
4 <19,38> TS_EN 4
WL_OFF# RB81 1 2 0_0402_5% GPIO0C
<52> WL_OFF#
ESD@
CB12 SYSON
33P_0402_50V8J
ESD@ +3VALW
CB13
33P_0402_50V8J RB78 1 2 10K_0402_5% TURBO_EN#
Security Classification Compal Secret Data Compal Electronics, Inc.
20191211B 2019/09/20 2020/09/20 Title
- CB12/CB13 change to 33p for ESD & ESD@ Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9022
RB76 2 @ 1 0_0402_5% VR_PWRGD Size Document Number R ev
<91> VCCCORE_VR_PWRGD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 58 of 112

A B C D E
 5 4 3 2 1

*NMI_DBG#: is a debug pin for EC to

infrom BIOS after press hot key.
OMEN New ESB CLK&DAT for Extend I/O

KC3810@
D UK3 D
+3VLP_EC ESB_CLK 1 13
<58> ESB_CLK ESB_CLK TEST_EN#
2 14
GPIO00 GPIO08/CAS_DAT
KC3810_RST#
1

KC3810@ 3 15
RK20 RST# GPIO09
ESB_DAT 4 16
47K_0201_5% <58> ESB_DAT ESB_DAT GPIO0A
5 17
GPIO01 GPIO0B
2

KC3810_RST# 6 18
GPIO02 GPIO0C/PWM0
2 7 19
KC3810@ GPIO03 GPIO0D/PWM1
CK16 8 20
GPIO04 GPIO0E/PWM2
0.1U_0201_10V6K
1 9 21
GPIO05 GPIO0F/PWM3
10 22
GPIO06 GPIO10/ESB_RUN#
11 23
GPIO07/CAS_CLK GPIO11/BaseAddOpt
12 24
+3VLP_EC

GND
GND VCC
+3VLP_EC

0.1U_0201_10V6K

KC3810@
CK202
KC3810NF-A0_QFN24_4X4 1

25
KC3810@ SA00002AI00
RK207 2 1 4.7K_0402_5% ESB_CLK

RK208 2 1 4.7K_0402_5% ESB_DAT 2

KC3810@
C C

www.laptoprepairsecrets.com
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E-GDDR6_D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 59 of 112

5 4 3 2 1
 5 4 3 2 1

2.2K 2.2K
+3VALW
+3VS
2.2K +3VS 2.2K
D
PCH_SMBCLK D_CK_SCLK D

(QH7)
PCH_SMBDATA 2N7002DW D_CK_SDATA SO-DIMM A & B

PCH_SML0CLK 499

+3VALW 1.8K
PCH_SML0DATA 499
Cannonlake 2K
2.2K +1.8VSDGPU_AON
PCH - H 1.8K +1.8VSDGPU_AON
+3VALW 2K
2.2K +1.8VSDGPU_MAIN
I2CB_SCL
PCH_SML1CLK EC_SMB_CK2 VGA_I2CS_SCL
I2CB_SDA
(RH189/RH190) (QV2)
PCH_SML1DATA R-short EC_SMB_DA2 PJT138KA VGA_I2CS_SDA 2K

2.2K
N17P-G0-K1 2K
+1.8VSDGPU_AON

2.2K
+3VLP_EC N18P-G0 I2CC_SCL

EC_SMB_CK1 100 ohm EC_SMB_CK1-1 I2CC_SDA NVVDD controller

BATTERY
EC_SMB_DA1 100 ohm EC_SMB_DA1-1 CONN
C C

KB9022 0 ohm EC_SMB_CK1_CHGR

2.2K
0 ohm EC_SMB_DA1_CHGR Charger
+3VS
+3VS 2.2K
EC_SMB_CK2
TMS_SMB_CLK
(QF1)
EC_SMB_DA2 2N7002DW THERMAL SENSOR
TMS_SMB_DATA
4.7K 2.2K
+5VALW +5VS_BL

EC_SMB_CK3

EC_SMB_DA3
4.7K

www.laptoprepairsecrets.com
+5VS_BL

(QE62)
2N7002DW
EC_SMB_CK3_LEDDRV

EC_SMB_DA3_LEDDRV
2.2K

LED driver

0 ohm
0 ohm

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-GDDR5_D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 61 of 112

5 4 3 2 1
 5 4 3 2 1

Battery LED 20200211

- RG4/RG11 change to 1k
RG4 LED1
1K_0402_5%
BATT_AMB_LED# 1 2 3 4
D
<58> BATT_AMB_LED# A +5VALW D

BATT_BLUE_LED# 1 2 1 2
<58> BATT_BLUE_LED# B

RG6
560_0402_5% LTST-C295TBKF-CA_AMBER-BLUE

Power LED
RG11 LED2
1K_0402_5%
PWR_SUSP_LED# 1 2 3 4
<58> PWR_SUSP_LED# A

PWR_LED# 1 2 1 2
<58> PWR_LED# B +5VALW
RG10
560_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE

C C

www.laptoprepairsecrets.com
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 62 of 112

5 4 3 2 1
 A B C D E

ON/OFF BTN Touch Pad +3V_PTP

- For TEST +3VLP

R17
100K_0402_5%
2 1
+3VALW
+3V_PTP

2 @ 1
+3VALW
0_0402_5% RK5
UK1 +3VS 2 @ 1
5 1

4.7U_0402_6.3V6M
<58> ON/OFFBTN# ON/OFFBTN# 0_0402_5% RK6
IN OUT +3V_PTP
2 1
2

CK2
@ CK1
RK18 1 @ 2 0_0603_5% CK3 GND 0.1U_0201_10V6K JTP1

2
1U_0201_6.3V6M 4 3 2 1 1
1 EN OC 2 TP_CLK 2 1
SY6288C20AAC_SOT23-5 RK7 TP_DATA 3 2
10K_0402_5%
EC PS2 4 3
I2C_1_SDA_R 5 4
1 5 1

1
EC_TP_INT# I2C_1_SCL_R 6
SW1 EVT@ <58> TP_PWR_EN PCH I2C EC_TP_INT# 7 6
<16,58> EC_TP_INT# TP_EN 8 7
TJG-533-V-T/R_6P TP_PWR_EN follow SYSON behavior <58> TP_EN 8
1 3 9
20191206 10 GND
GND

1
2 4 - Add CK203 for ESD ESD@
20200114 +3V_PTP +3V_PTP CK203 JXT_FP202DH-008M10M
- set EVT@ 20191211A 680P_0402_50V7K CONN@
6
5

2
- CK203 change to 680p for ESD
20191017 SP010020L00

1
- Add for EVT

1
2
DK2 XESD@ RK8 RK9 +3V_PTP

G
TP_DATA 6 3 TP_EN QK1A 2.2K_0402_5% 2.2K_0402_5%
I/O4 I/O2 2N7002KDW_SOT363-6

2
I2C_1_SCL_R

1
6 1
<19> I2C_1_SCL

S
5 2 RK10 RK11

D
+3V_PTP VDD GND 1 @ 2 CK6 33P_0402_50V8J 4.7K_0402_5% 4.7K_0402_5%
RK12 0_0402_5%
XESD@
TP_CLK EC_TP_INT#

2
5
4 1

G
I/O3 I/O1 QK1B CK7 33P_0402_50V8J
AZC099-04S.R7G_SOT23-6 2N7002KDW_SOT363-6 TP_CLK
TP_DATA TP_CLK <58>
SC300001G00 XESD@
3 4 I2C_1_SDA_R TP_DATA <58>
<19> I2C_1_SDA

S
D
1 2
RK13 @ 0_0402_5%

2
LED driver 20191001
- Change to +5VS only
- KBL_EN only (Check EC Code)
KB Conn. / Backlight 2
- pop (Normal & RGB)
20191016
- Remove QE62/RE70/RE69 20200115
- R41/R18 change to R-short
- PU +5VALW @ EC
+5VS +5VS_BL CONN@
U4 JKB1
R41 1 @ 2 0_0603_5% 5 1 30
IN OUT 29 GND2
2 28 GND1

0.1U_0201_10V6K
KSO16
GND KSI[0..7] 27 28

C32
KSO17
1 2 0_0201_5% 4 3 KSI[0..7] <58> 26 27
<58> KBL_EN R18 @ 1 KSO0
EN OC KSO[0..17] KSO1 25 26
KSO[0..17] <58> 25
SY6288C20AAC_SOT23-5 @ KSO2 24
24

www.laptoprepairsecrets.com
KSO3 23
2 KSO4 22 23
KSO5 21 22
KSO6 20 21
KSO7 19 20
KSO8 18 19
KSO9 17 18
KSO10 16 17
KSO11 15 16
KSO12 14 15
KSO13 13 14
KSO14 12 13
KSO15 11 12
KSI0 10 11
KSI1 9 10
KSI2 8 9
KSI3 7 8
KSI4 6 7
KSI5 5 6
4 5
3
+5VS_BL
AD3 AD2 AD1 AD0 +5VS_BL
KSI6
KSI7 3 4
3

2 3
0 0 0 1 ON/OFFBTN# 1 2
1
1

RE65 LED14P@
4.7K_0402_1% 1 ACES_85201-2805
CE3 LED14P@ SP01000GO00
UE4 0.1U_0201_10V6K
2
2

24 27 CONN@ +5VS_BL CONN@

RESET Vcc JBL2 JBL1
3 KB_A_LED_R_DRV# 16 1
EC_SMB_CK3 RE1 2 @ 1 0_0402_5% EC_SMB_CK3_LEDDRV 25 OUT0 4 KB_A_LED_G_DRV# 15 GND 2 1
<58> EC_SMB_CK3 EC_SMB_DA3 EC_SMB_DA3_LEDDRV SCL OUT1 KB_A_LED_B_DRV# GND 2
RE2 2 @ 1 0_0402_5% 26 5 +5VS_BL 3
<58> EC_SMB_DA3 SDA OUT2 KB_B_LED_R_DRV# 3
6 4
AD0 31 OUT3 8 KB_B_LED_G_DRV# 4
AD1 32 A0 OUT4 9 KB_B_LED_B_DRV# 14 5
AD2 1 A1 OUT5 10 KB_C_LED_R_DRV# 13 14 6 GND
AD3 2 A2 OUT6 11 KB_C_LED_G_DRV# KB_A_LED_R_DRV# 12 13 GND
A3 OUT7 14 KB_C_LED_B_DRV# KB_A_LED_G_DRV# 11 12 ACES_51524-0040N-001
12 OUT8 15 KB_D_LED_R_DRV# KB_A_LED_B_DRV# 10 11
AD0
N.C. OUT9 KB_D_LED_G_DRV# KB_B_LED_R_DRV# 10 SP010022M00
AD1 13 16 9
AD2 28 N.C. OUT10 17 KB_D_LED_B_DRV# KB_B_LED_G_DRV# 8 9
AD3 29 N.C. OUT11 19 KB_B_LED_B_DRV# 7 8
30 N.C. OUT12 20 KB_C_LED_R_DRV# 6 7
N.C. OUT13 KB_C_LED_G_DRV# 6
1

21 5
OUT14 KB_C_LED_B_DRV# 5
1

RE75 RE74 RE73 RE72 22 4

4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% RE64 OUT15 KB_D_LED_R_DRV# 3 4
LED14P@ LED14P@ LED14P@ LED14P@ @ 7 23 KB_D_LED_G_DRV# 2 3
10K_0402_5% GND GND 2
18 33 KB_D_LED_B_DRV# 1
GND GND 1
2

ACES_51522-01401-P01
TLC59116FIRHBR_VQFN32_5X5 SP01001R800
- Raptor: NC for 59116F LED14P@

4 - Set RE64 to 10k / output = 1.875mA 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 63 of 112
A B C D E
 5 4 3 2 1

CONN@
3V_PEN FWE 1
JEMR1

+3VALW +3VS +3V_PEN EMR 1A modify

I2C_0_SCL_R
I2C_0_SDA_R
PEN_PDCT_R#
2
3
4
1
2
3
D 5 4 D
@ 6 5
RH271 1 2 0_0402_5% +3V_PEN PEN_IRQ_R# 7 6
PEN_RST_R# 8 7
WC33V@ +1.8V_3V_PEN RH298 1 @ 2 0_0402_5% +3V_PEN_R 9 8
RH272 1 2 0_0402_5% 10 9
RH299 1 @ 2 0_0402_5% +1.8V_3V_PEN_R 11 10
12 11
13 12
14 GND1
GND2
ACES_50208-01201-P01
SP01001UP00

1.8V_PEN

+3VALW +1.8VALW +1.8VS +1.8V_3V_PEN

@
RH277 1 2 0_0402_5%

WC18V@
RH278 1 2 0_0402_5%

WC33V@
C RH297 1 2 0_0402_5% C
+1.8V_3V_PEN

1
RH295
2.2K_0402_5%
@

2
FWE

20191008
www.laptoprepairsecrets.com 1A modify

1
- QY6/QY8 change to SB000016K00
RH296
Default use 0ohm(WC33V@) 2.2K_0402_5%
WC33V@
+1.8V_3V_PEN

2
+1.8V_3V_PEN MISC signal
I2C

WC18V@

5
WC18V@ QY8A
5

QY6A PJT138KA_SOT363-6

G
PJT138KA_SOT363-6 4 3 PEN_IRQ_R# +1.8V_3V_PEN
G

4 3 I2C_0_SCL_R <19> PEN_IRQ#

WC18V@

D
B <19> I2C_0_SCL B
RH287 QY10
S

RH279 1 2 2
1 2 0_0402_5% Gate
0_0402_5% WC33V@ 1 PEN_RST_R#
WC33V@ Drain
3
<19> PEN_RST# Source
WC18V@

2
WC18V@ QY8B LBSS139WT1G_SC70-3
2

QY6B PJT138KA_SOT363-6

G
PJT138KA_SOT363-6 1 6 PEN_PDCT_R#
G

1 6 I2C_0_SDA_R <19> PEN_PDCT#

RH293

D
<19> I2C_0_SDA 1 2
RH288
S

1 2 0_0402_5%
RH280 0_0402_5% WC33V@
1 2 WC33V@
0_0402_5%
WC33V@
3ohm/10pF +3VALW 20191206
- RH285/RH286/RH292 power source change to +3VALW
WC33V@
PEN_IRQ# RH286 2 1 2.2K_0402_5%
PEN_PDCT# RH285 2 1 2.2K_0402_5% +3VALW
3ohm/10pF +1.8V_3V_PEN WC33V@ WC33V@
WC18V@ +1.8V_3V_PEN PEN_RST# RH292 2 1 2.2K_0402_5%
I2C_0_SCL_R RH275 2 1 2.2K_0402_5% WC18V@
I2C_0_SDA_R RH276 2 1 2.2K_0402_5% PEN_IRQ_R# RH284 2 1 2.2K_0402_5%
WC18V@ PEN_PDCT_R# RH283 2 1 2.2K_0402_5% +1.8V_3V_PEN
WC18V@ WC18V@
PEN_RST_R# RH290 2 1 2.2K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E-GDDR6_D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 64 of 112

5 4 3 2 1
 5 4 3 2 1

THERMAL SENSOR Close to Thermal SKIN

To Hall sensor/B +3VS +3VS
+3VS

+3VLP

1
CONN@ RF9 TMS@
JHS1 RF10 +3VS RF26
2.2K_0402_5% SMBUS ADDRESS

5
1 TMS@ 2.2K_0402_5% TMS@ 10K_0402_5%
1001_1010b

G
2 1 QF1B TMS@ CF21 TMS@
<58> LID_SW# 2

2
3 2N7002KDW_SOT363-6 0.1U_0201_10V6K TMS@ UF3
3 TMS_SMB_CLK

2
4 2 1 1 8
4 3 4 TMS_SMB_CLK 2 VCC SMBCLK 7 TMS_SMB_DATA

0.1U_0201_10V6K

XESD@
<18,27,58> PCH_SML1CLK DXP SMBDATA

S
5 3 6 THERMAL2_ALERT#

C60

D
1 GND DXN #ALERT
1 TMS@ 2 TH2_THERM#

2
6 TMS@ 4 5
+3VS

G
D GND QF1A RF25 10K_0402_5% #THERM GND D
ACES_51524-0040N-001 2N7002KDW_SOT363-6 G781-1P8F_MSOP8
2
SP010022M00 TMS_SMB_DATA SA00000V200
6 1
<18,27,58> PCH_SML1DATA

S
D
20191008
- C60 change to @
Close to VRAM choke 20191029
+3VLP_ECA
- RF12 & RH250 change to unpop
Close to SO-DIMM - Use PH204 @ Power
+3VS
+3VS

1
@
RF12
TMS@ CF20
1 SMBUS ADDRESS 16.5K_0402_1%
1001_1000b

1
0.1U_0201_10V6K TMS@

2
TMS@ UF2 RF24
2 1 8 TMS_SMB_CLK 10K_0402_5%
VDD SCL VRAM_TEMP <58,84>
2 7 TMS_SMB_DATA
D+ SDA

1
@
3 6 THERMAL_ALERT# RH250
D- ALERT# THERMAL_ALERT# <58>
100K_0402_1%_TSM0B104F4251RZ
1 TMS@ 2 TH_THERM# 4 5
+3VS T_CRIT# GND SL200002H00
RF23 10K_0402_5%

2
NCT7718W_MSOP8 RK2091 @ 2 0_0402_5% THERMAL2_ALERT#
ECAGND <58,84>
SA000067P00
C C

TPM Finger Print

+3VALW R45 +3VALW_TPM +3VS R46 +3VS_TPM

0_0603_5% 0_0603_5%
1 @ 2 1 @ 2

www.laptoprepairsecrets.com
0.1U_0201_10V6K

0.1U_0201_10V6K
C58
10U_0402_6.3V6M

10U_0402_6.3V6M

0.1U_0201_10V6K
C57

0.1U_0201_10V6K
C55
1 1 1 1 1 1
C56

C59

C54

+3VALW @
RK14 1 2 0_0402_5%
2 2 TPM@ near 2 2 2 2 +FP_VCC
TPM@

TPM@ TPM@ TPM@ TPM@

pin1 +5VALW
JFP1
RK15 1 FP@ 2 0_0402_5%
8
+FP_VCC USB20_P8_L 7 8 10
2 USB20_N8_L 7 G2
6 9
near FP@ CK4 UK2 5 6 G1
+3VALW pin8,22 1U_0201_6.3V6M 5 1 4 5
R48 TPM@ 1 IN OUT 3 4
1 3
10K_0402_5% 2 FP@ 2
1 2 PCH_SPI_CS#2 GND CK5 1 2
FP_PWR_EN 4 3 4.7U_0402_6.3V6M 1
<58> FP_PWR_EN EN OC 2 ACES_51522-00801-001
B B
SY6288C20AAC_SOT23-5 SP01001AE00
FP@
CONN@
R50 1 TPM@ 2 33_0402_1% PCH_SPI_SO_TPM_R
<16> PCH_SPI_SO_R 1 TPM@ 2 33_0402_1% PCH_SPI_SI_TPM_R
R51
<16> PCH_SPI_SI_R R52 1 TPM@ 2 33_0402_1% PCH_SPI_CLK_TPM_R
<16> PCH_SPI_CLK_R

1 @ 2 USB20_N8_L
<14> USB20_N8
RK16 0_0402_5%

U9 +3VALW_TPM 1 @ 2 USB20_P8_L
<14> USB20_P8
TH41 1 RK17 0_0402_5%
@ 29 VSB +3VS_TPM
30 SDA/GPIO0 8
SCL/GPIO1 VHIO 22
1 2 R47 TPM_BADD 6 VHIO
0_0402_5% @
GPIO3 2
PIN ETU801 FA577E-1200
PCH_SPI_SO_TPM_R 24 NC 3
PCH_SPI_SI_TPM_R 21 MISO NC 5 DK1 FPESD@
1 +FP_VCC(5V) +FP_VCC(3V)
18 MOSI/GPIO7 NC 7 USB20_P8_L 6 3
<17,58> TPM_SERIRQ PIRQ/GPIO2 NC 9 I/O4 I/O2 2 USBP D+
NC 10
PCH_SPI_CLK_TPM_R 19 NC 11
3 USBN D-
20 SCLK NC 12 5 2
<16> PCH_SPI_CS#2 17 SCS/GPIO5 NC 14
+FP_VCC VDD GND 4 GND GND
<16,27,58> PLT_RST# 27 PLTRST NC 15
13 NC NC 26
5 NC NC
GPIO4 NC 25 4 1 USB20_N8_L
NC 28 I/O3 I/O1 6 NC NC
4 NC 31
PP/GPIO6 NC 32
AZC099-04S.R7G_SOT23-6 7 NC
NC SC300001G00
A A
16
8 NC
GND 23
GND 33
PGND
NPCT750AAAYX_QFN32_5X5
TPM@
SA0000AQ250 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
SA0000AQ250, S IC NPCT750AABYX QFN 32P TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sensors/FP/TPM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 66 of 112

5 4 3 2 1
 A B C D E

+5VS_HDD FFC Type

100mils

10U_0402_6.3V6M
CO12
1

1
CONN@
1 CO13 JHDD1 1
0.1U_0201_10V6K 14
GND

2
2 @ +5VS +5VS_HDD 13
GND
RO4 1 @ 2 0_0805_5% 12
11 12
10 11
RO25 1 2 0_0201_5% G_INT2_R 9 10
20200114 @
9
- RO25 change to R-short 8
7 8
SATA_PRX_DTX_P0B CO14 2 1 0.01U_0201_6.3V7K SATA_PRX_C_DTX_P0B 6 7
<17> SATA_PRX_DTX_P0B SATA_PRX_DTX_N0B CO15 2 1 0.01U_0201_6.3V7K SATA_PRX_C_DTX_N0B 5 6
<17> SATA_PRX_DTX_N0B 4 5
SATA_PTX_DRX_N0B CO16 2 1 0.01U_0201_6.3V7K SATA_PTX_C_DRX_N0B 3 4
<17> SATA_PTX_DRX_N0B SATA_PTX_DRX_P0B CO17 2 1 0.01U_0201_6.3V7K SATA_PTX_C_DRX_P0B 2 3
<17> SATA_PTX_DRX_P0B 1 2
1
ACES_51625-01201-001
20191016 change to SATA Port 0B SP010028W00

2 2

www.laptoprepairsecrets.com
3 3

20190918
Remove HDD Re-driver
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ Re-Driver/ G-sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 67 of 112

A B C D E
 5 4 3 2 1

20191017 Power source

+3VALW
> +3VS_SSD2 : JSSD2
> +3VS_SSD3 : JSSD1 & JSSD3 UM2 +3VS_SSD2
1 14 +3VS_SSD_2 1 @ 2
2 VIN1 VOUT1 13 RM54 0_0805_5%
VIN1 VOUT1
RM53 1 @ 2 0_0201_5% +3V_NGFF_GATE 3 12 1 2
<39,58,78,85,88,90> SUSP# ON1 CT1 CM37 1000P_0402_50V7K
4 11

0.1U_0201_10V6K
1 +5VALW VBIAS GND

CM32 @
+3VS_SSD2 5 10 1 2
ON2 CT2 CM38 1000P_0402_50V7K
2 6 9 +3VS_SSD3
CONN@ 7 VIN2 VOUT2 8 +3VS_SSD_3 1 @ 2
D JSSD2 VIN2 VOUT2 RM55 0_0805_5% D
1
1 2 15

10U_0402_6.3V6M

0.1U_0201_10V6K
GND 3.3VAUX 1 2 + GPAD
3 4 CM3
PCIE_PRX_DTX_N9 5 GND 3.3VAUX 6 CM1 CM2 150U_D2_6.3VY_R15M +3VALW EM5209VF_DFN14_2X3
<17> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 PERn3 N/C 8 SGA00003700 +3VS_SSD_2 +3VS_SSD_3
<17> PCIE_PRX_DTX_P9 9 PERp3 N/C 10 2 1 2
CM6 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N9 11 GND DAS/DSS# 12

1U_0201_6.3V6M

1U_0201_6.3V6M
<17> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn3 3.3VAUX 2 2 2 2
CM4 1 2 0.22U_0402_16V7K 13 14

CM33

CM34
<17> PCIE_PTX_DRX_P9 15 PETp3 3.3VAUX 16 CM35 CM36
PCIE_PRX_DTX_N10 17 GND 3.3VAUX 18
PERn2 3.3VAUX 0.1U_0201_10V6K 0.1U_0201_10V6K
<17> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 20 1 1 1 1
<17> PCIE_PRX_DTX_P10 21 PERp2 N/C 22
CM5 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N10 23 GND N/C 24
<17> PCIE_PTX_DRX_N10 CM7 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P10 25 PETn2 N/C 26
<17> PCIE_PTX_DRX_P10 27 PETp2 N/C 28
PCIE_PRX_DTX_N11 GND N/C
Place CM33 close UM2 pin 1&2
29 30 Place CM34 close UM2 pin 6&7
<17> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 PERn1 N/C 32
<17> PCIE_PRX_DTX_P11 33 PERp1 N/C 34
CM8 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N11 35 GND N/C 36
<17> PCIE_PTX_DRX_N11 CM9 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P11 37 PETn1 N/C 38 SSD_DEVSLP1
<17> PCIE_PTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP1 <17>
39 40
PCIE_PRX_DTX_P12 41 GND N/C 42
<17> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 PERn0/SATA_B+ N/C 44
<17> PCIE_PRX_DTX_N12 45 PERp0/SATA_B- N/C 46
CM10 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N12 47 GND N/C 48
<17> PCIE_PTX_DRX_N12 CM11 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P12 49 PETn0/SATA_A- N/C 50
<17> PCIE_PTX_DRX_P12 PETp0/SATA_A+ PERST# SSD2_CLKREQ#_R PLT_RST_BUF# <16,52,68,69,73>
51 52 RM7 1 @ 2 0_0201_5%
GND CLKREQ# SSD2_CLKREQ# <15>
53 54
<15> CLK_PCIE_NGFF1# REFCLKn PEWake#
55 56
<15> CLK_PCIE_NGFF1 REFCLKp N/C
57 58
GND N/C
Pull high at PCH side 67 68 SUSCLK_SSD2
C RM8 1 @ 2 0_0201_5%
SUSCLK <18,52,68,69>
C
RM10 1 @ 2 0_0201_5% SSD2_DET# 69 N/C SUSCLK 70
<17> SATA_GP1 PEDET 3.3VAUX
71 72
73 GND 3.3VAUX 74
75 GND 3.3VAUX
PEDET(NC-PCIE/GND-SATA) GND PLT_RST_BUF# CM16
XESD@
2 1 100P_0402_50V8J
SATA Device 0 GND
76
77
PCIE Device 1 GND
Place close to JSSD pin 50
BELLW_80159-4221 ESD request to reserve.
SP07001D300

www.laptoprepairsecrets.com
1
CONN@
JSSD1
M.2 SSD
2
+3VS_SSD3

10U_0402_6.3V6M

0.1U_0201_10V6K
GND 3.3VAUX 1 2 +
3 4 CM50
5 GND 3.3VAUX 6 CM46 CM44 150U_D2_6.3VY_R15M
<14> PCIE_PRX_DTX_N24 7 PERn3 N/C 8 SGA00003700
<14> PCIE_PRX_DTX_P24 9 PERp3 N/C 10 2 1 2
CM41 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N24 11 GND DAS/DSS# 12
<14> PCIE_PTX_DRX_N24 CM49 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P24 13 PETn3 3.3VAUX 14
<14> PCIE_PTX_DRX_P24 15 PETp3 3.3VAUX 16
17 GND 3.3VAUX 18
<14> PCIE_PRX_DTX_N23 19 PERn2 3.3VAUX 20
<14> PCIE_PRX_DTX_P23 21 PERp2 N/C 22
B CM48 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N23 23 GND N/C 24 B
<14> PCIE_PTX_DRX_N23 CM40 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P23 25 PETn2 N/C 26
<14> PCIE_PTX_DRX_P23 27 PETp2 N/C 28
29 GND N/C 30
<14> PCIE_PRX_DTX_N22 31 PERn1 N/C 32
<14> PCIE_PRX_DTX_P22 33 PERp1 N/C 34
CM47 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N22 35 GND N/C 36
<14> PCIE_PTX_DRX_N22 CM42 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P22 37 PETn1 N/C 38
<14> PCIE_PTX_DRX_P22 39 PETp1 DEVSLP 40
41 GND N/C 42
<14> PCIE_PRX_DTX_P21 43 PERn0/SATA_B+ N/C 44
<14> PCIE_PRX_DTX_N21 45 PERp0/SATA_B- N/C 46
CM45 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N21 47 GND N/C 48
<14> PCIE_PTX_DRX_N21 CM43 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P21 49 PETn0/SATA_A- N/C 50 PLT_RST_BUF#
<14> PCIE_PTX_DRX_P21 PETp0/SATA_A+ PERST# SSD1_CLKREQ#_R PLT_RST_BUF# <16,52,68,69,73>
51 52 RM56 1 @ 2 0_0201_5%
GND CLKREQ# SSD1_CLKREQ# <15>
53 54
<15> CLK_PCIE_NGFF3# REFCLKn PEWake#
55 56
<15> CLK_PCIE_NGFF3 REFCLKp N/C
57 58
GND N/C

67 68 SUSCLK_SSD1 RM57 1 @ 2 0_0201_5%

SSD1_DET# N/C SUSCLK SUSCLK <18,52,68,69>
69 70
T211 @ PEDET 3.3VAUX
71 72
73 GND 3.3VAUX 74 XESD@
75 GND 3.3VAUX PLT_RST_BUF# CM39 2 1 100P_0402_50V8J
GND
76
GND 77
GND Place close to JSSD pin 50
ESD request to reserve.
BELLW_80159-4221
A SP07001D300 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA/PCIE-SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 68 of 112

5 4 3 2 1
 5 4 3 2 1

1004
1210B +3VS_SSD3 - Remove UM3
- Add SSD3 config - Power source merge +3VS_SSD3
D CONN@ D
JSSD3 1
1 2

10U_0402_6.3V6M
CM28
SSD3@

0.1U_0201_10V6K
CM26
SSD3@
1 2 SSD3@
3 GND 3.3VAUX 4 + CM20
5 GND 3.3VAUX 6 150U_B2_6.3VM_R35M
<17> PCIE_PRX_DTX_N20 7 PERn3 N/C 8 SGA00009M00
<17> PCIE_PRX_DTX_P20 9 PERp3 N/C 10 2 1 2
SSD3@ CM23 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N20 11 GND DAS/DSS# 12
<17> PCIE_PTX_DRX_N20 SSD3@ CM31 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P20 13 PETn3 3.3VAUX 14
<17> PCIE_PTX_DRX_P20 15 PETp3 3.3VAUX 16
17 GND 3.3VAUX 18
<17> PCIE_PRX_DTX_N19 19 PERn2 3.3VAUX 20
<17> PCIE_PRX_DTX_P19 21 PERp2 N/C 22
SSD3@ CM29 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N19 23 GND N/C 24
<17> PCIE_PTX_DRX_N19 SSD3@ CM22 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P19 25 PETn2 N/C 26
<17> PCIE_PTX_DRX_P19 27 PETp2 N/C 28
29 GND N/C 30
<17> PCIE_PRX_DTX_N18 31 PERn1 N/C 32
<17> PCIE_PRX_DTX_P18 33 PERp1 N/C 34
SSD3@ CM30 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N18 35 GND N/C 36
<17> PCIE_PTX_DRX_N18 SSD3@ CM24 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P18 37 PETn1 N/C 38 SSD_DEVSLP4
<17> PCIE_PTX_DRX_P18 PETp1 DEVSLP SSD_DEVSLP4 <17>
39 40
41 GND N/C 42 20191025
<17> PCIE_PRX_DTX_P17 43 PERn0/SATA_B+ N/C 44 - SATA Port 4
<17> PCIE_PRX_DTX_N17 45 PERp0/SATA_B- N/C 46
SSD3@ CM27 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N17 47 GND N/C 48
<17> PCIE_PTX_DRX_N17 SSD3@ CM25 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P17 49 PETn0/SATA_A- N/C 50 PLT_RST_BUF#
<17> PCIE_PTX_DRX_P17 PETp0/SATA_A+ PERST# SSD3_CLKREQ#_R PLT_RST_BUF# <16,52,68,73>
51 52 RM48 1 @ 2 0_0201_5%
GND CLKREQ# SSD3_CLKREQ# <15>
53 54
<15> CLK_PCIE_NGFF2# REFCLKn PEWake#
55 56
<15> CLK_PCIE_NGFF2 REFCLKp N/C
57 58
GND N/C
C C
67 68 SUSCLK_SSD3 RM52 1 @ 2 0_0201_5%
SSD3_DET# N/C SUSCLK SUSCLK <18,52,68>
<17> SATA_GP4 RM61 1 @ 2 0_0201_5% 69 70
71 PEDET 3.3VAUX 72
20191206 73 GND 3.3VAUX 74
- PEDET change to SATA_GP4 PEDET(NC-PCIE/GND-SATA) 75 GND 3.3VAUX XESD@
SATA Device 0 GND PLT_RST_BUF# CM21 2 1 100P_0402_50V8J
76
PCIE Device 1 GND 77
GND
Place close to JSSD pin 50
BELLW_80159-4221 ESD request to reserve.
SP07001D300

www.laptoprepairsecrets.com
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E-GDDR6_D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 69 of 112

5 4 3 2 1
 A B C D E

USB3.0
20191016 For ESD request
- Gen2 Solution SC300006T00
+USB3_VCCA
DS1 ESD@
1 2 USB3_PTX_C_DRX_P1 RS86 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P1 USB3_PTX_L_DRX_P1 1 9 USB3_PTX_L_DRX_P1 W=100mils
<17> USB3_PTX_DRX_P1
CS2 .1U_0402_16V7K
1 2 USB3_PTX_C_DRX_N1 RS89 1 @ 2 0_0402_5% USB3_PTX_L_DRX_N1 USB3_PTX_L_DRX_N1 2 8 USB3_PTX_L_DRX_N1
1 2
1
<17> USB3_PTX_DRX_N1 1
CS3 .1U_0402_16V7K

RS90 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P1

USB3_PRX_L_DTX_P1 4 7 USB3_PRX_L_DTX_P1 CS5
150U_D2_6.3VY_R15M
+ CS6 EMI@
0.1U_0201_10V6K
USB3.0 Conn.
<17> USB3_PRX_DTX_P1 USB3_PRX_L_DTX_N1 5 6 USB3_PRX_L_DTX_N1 1
RS91 1 @ 2 0_0402_5% USB3_PRX_L_DTX_N1
SGA00003700
2 GEN2 CONN.
<17> USB3_PRX_DTX_N1
CONN@
3 JUSB1
1
TVWDF1004AD0_DFN9 CHR_USB20_N1_R 2 VBUS
CHR_USB20_P1_R 3 D-
SC300006T00 D+
4
USB3_PRX_L_DTX_N1 5 GND
USB3_PRX_L_DTX_P1 6 SSRX- 10
LS3 EMI@ DS2 ESD@ 7 SSRX+ GND 11
CHR_USB20_P1 2 1 CHR_USB20_P1_R 6 3 CHR_USB20_N1_R USB3_PTX_L_DRX_N1 8 GND GND 12
2 1 I/O4 I/O2 USB3_PTX_L_DRX_P1 9 SSTX- GND 13
+USB3_VCCA SSTX+ GND
CHR_USB20_N1 3 4 CHR_USB20_N1_R ACON_GTRA0-9U1391
3 4 5 2
DLM0NSN900HY2D_4P VDD GND
SM070005U00
CHR_USB20_P1_R 4 1
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
SC300001G00

2 2

USB Host Charger

0
1
1
+5VALW

CHG_CTL2
www.laptoprepairsecrets.com +5VALW
0904 vendor recommend

1 2 10K_0402_5%

22U_0603_6.3V6M

0.1U_0201_10V6K
1 RS14 1 1

CS9

CS7
@
@ +USB3_VCCA
RS15 1 2 10K_0402_5% CHG_ILMSEL 2 2 US12

1 12
0911 Rerserve PU, vendor suggest to EC control VIN VOUT
if future need support SDP2 2
<14> USB20_N1 3 DM_OUT
RS11
3 <14> USB20_P1 DP_OUT 10 CHR_USB20_P1 3
0_0201_5%
2 @ 1 13 DP_IN 11 CHR_USB20_N1
<14> USB_OC1# FAULT# DM_IN
1 4
<58> CHG_ILMSEL ILIM_SEL
CS8
<58> CHG_EN
5
EN ILIM_L
15 0831 Reserve ILIM_L R as vendor recommend
0.1U_0201_10V6K 16
USB Host Charger Truth Table @ 2 ILIM_HI

1
6
<58> CHG_CTL1 CHG_CTL2 7 CTL1 9

22.1K_0402_1%

39K_0402_1%
CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note CTL2 NC
8 14

RS12

RS13
Setting <58> CHG_CTL3 CTL3 GND
Thermal Pad
17 ILM R vaule
0 1 0 1 SDP1-OFF ILIM_H Port power off @ Ios(mA)=50250/R(Kohm)

2
1
0 1 0 1 SDP1 ILIM_H Data Lines Connected @ SLGC55544CVTR_TQFN16_3X3 ILIM_Hi=2273mA
RS138 ILIM_L=1288mA(reserve)
0 1 1 1 DCP ILIM_H Data Lines Disconnected 0_0402_5%
Auto

2
1 1 1 1 CDP ILIM_H Data Lines Connected
20191014
- For SDP measure

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Conn/USB Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 71 of 112

A B C D E
 5 4 3 2 1

D D

20190918 C

USB3 Port3 move to

www.laptoprepairsecrets.com
IO/B
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E-GDDR6_D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 72 of 112

5 4 3 2 1
 A B C D E

IO/B CONN CONN@

JIO1
EMI@ LS13 40
USB20_N3 1 2 USB20_L_N3 USB3_PTX_DRX_P5 39 40
<14> USB20_N3 1 2 20191016 <17> USB3_PTX_DRX_P5 USB3_PTX_DRX_N5 39
38
- Change to Port5 <17> USB3_PTX_DRX_N5 38
37
USB20_P3 4 3 USB20_L_P3 USB3_PRX_DTX_P5 36 37
<14> USB20_P3 4 3 <17> USB3_PRX_DTX_P5 USB3_PRX_DTX_N5 36
35
<17> USB3_PRX_DTX_N5 35
DLM0NSN900HY2D_4P 34
USB20_L_N3 33 34
SM070005U00
USB20_L_P3 32 33
1 32 1
EMI@ LS12 31
USB20_N2 1 2 USB20_L_N2 USB20_L_N2 30 31
<14> USB20_N2 1 2 USB20_L_P2 30
1209A 29
28 29
USB20_P2 4 3 USB20_L_P2 - IO_B change pin define USB3_PTX_DRX_P2 27 28
<14> USB20_P2 4 3 <17> USB3_PTX_DRX_P2 USB3_PTX_DRX_N2 27
<17> USB3_PTX_DRX_N2
26
DLM0NSN900HY2D_4P 25 26
USB3_PRX_DTX_P2 24 25
SM070005U00 <17> USB3_PRX_DTX_P2 USB3_PRX_DTX_N2 23 24
<17> USB3_PRX_DTX_N2 23
22
PCIE_PRX_DTX_N14 21 22
LAN_PME# <17> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 21
1 2 20191008 20
+3VALW - LAN PCIE&CLK Remove AC Cap > Vender confirm <17> PCIE_PRX_DTX_P14 20
RL1 4.7K_0402_5%~D 19
(CL136/137/138/139) PCIE_PTX_DRX_N14 18 19
remind : if no support wake,don't monitor this pin "PME#". <17> PCIE_PTX_DRX_N14 18
PCIE_PTX_DRX_P14 17
<17> PCIE_PTX_DRX_P14 17
16
CLK_PCIE_LAN 15 16
<15> CLK_PCIE_LAN CLK_PCIE_LAN# 15
<15> CLK_PCIE_LAN#
14
13 14
USB_EN 12 13
<58> USB_EN 12
+3VALW
11
10 11
LAN_CLKREQ# 9 10
<15> LAN_CLKREQ# LAN_PME# 9
8
<16,58> EC_PME# PLT_RST_BUF# 7 8
<16,52,68,69> PLT_RST_BUF# 6 7
GNDA HP_PLUG# 6
5
<56> HP_PLUG# 5
<56> RING2 RING2 4
2 SLEEVE 3 4 42 2
<56> SLEEVE HPOUT_R_1 3 G2
2 41
<56> HPOUT_R_1 HPOUT_L_1 2 G1
<56> HPOUT_L_1
1
1
ACES_51540-04001-P01

CONN@
JIO2
<56> SPKL- SPKL- 1 7
SPKL+ 2 1 G1
<56> SPKL+ 2
+3VS
3
3

www.laptoprepairsecrets.com
4
5 4
6 5 8
+5VALW 6 G2
ACES_88231-06001
20191023
- Add +3VS

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IO/B_LAN E2600
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 73 of 112
A B C D E
 Screw Hole 20191210B
- H6 change to GNDA for Layout Stand OFF@ H10 CLIP1
Clips CLIP18
H_3P3 EMIST_SUL-12A2M_1P CLIP12 EMIST_SUL-12A2M_1P CLIP19 FD1
+5VS @ H2 @ H3 @ H4 @ H5 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
H_3P0 H_3P0 H_4P0 H_3P0
1 @ 2 +VCC_FAN1 @

1
RF4 0_0603_5%
+VCC_FAN2 40mil

1
1 @ 2 FIDUCIAL_C40M80

1
1 1 RF7 0_0603_5% @ H11 CLIP2 CLIP13
H_3P3 EMIST_SUL-12A2M_1P CLIP7 EMIST_SUL-12A2M_1P CLIP20 FD2
CF6 CF5 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
1000P_0402_50V7K 10U_0402_6.3V6M @ H6 @ H7 @ H8 @ H9
2 2 H_4P0 H_5P6 H_4P0 H_4P0 @
@ @

1
1

1
FIDUCIAL_C40M80
@ H12 CLIP3 CLIP14

1
H_3P3 EMIST_SUL-12A2M_1P CLIP8 EMIST_SUL-12A2M_1P CLIP21 FD3
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
GNDA
@ H14 @ H15 @ H16 @ H23 @

1
H_3P8 H_3P8 H_3P8 H_3P0X2P5

1
FIDUCIAL_C40M80

FAN Conn @ H13

H_3P3
CLIP4
EMIST_SUL-12A2M_1P CLIP9
CLIP15
EMIST_SUL-12A2M_1P CLIP22 FD4

1
+3VS EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

1
1

1 @ H17 @ H18 @ H19 @ H21

1
RF3 CF13 H_2P5 H_3P0 H_3P0 H_5P6 FIDUCIAL_C40M80
10K_0402_5% 4.7U_0402_6.3V6M @ H20 CLIP5 CLIP16
CONN@ H_3P3 EMIST_SUL-12A2M_1P CLIP10 EMIST_SUL-12A2M_1P CLIP23
2 JFAN1 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
+VCC_FAN1
2

1
1
2 1
<58> FAN_SPEED1 FAN_PWM1 2

1
3
<58> FAN_PWM1 3

1
1 4
CF7 5 4 @ H22 CLIP6 CLIP17
1000P_0402_50V7K 6 G1 @ H24 @ H25 H_3P3 EMIST_SUL-12A2M_1P CLIP11 EMIST_SUL-12A2M_1P
XEMI@ G2 H_1P4X3P5 H_1P4X4P6 EMIST_SUL-12A2M_1P
2 ACES_50278-00401-001
SP02000RR00

1
1

1
+3VS

Turbo Key
1

1
RF5 CF12
10K_0402_5% 4.7U_0402_6.3V6M
CONN@
2 JFAN2
2

+VCC_FAN2 1
2 1
<58> FAN_SPEED2 FAN_PWM2 2 +5VALW
3 CONN@
<58> FAN_PWM2 3
1 4 JTURBO1
CF10 5 4 1
1000P_0402_50V7K 6 G1 TURBO_LED# 2 1
G2 <58> TURBO_LED# TURBO_EN# 3 2 5
XEMI@
2 <58> TURBO_EN# 3 G1
ACES_50278-00401-001 4 6
4 G2
SP02000RR00
ACES_51575-00401-001
SP01002LG00

www.laptoprepairsecrets.com
+3VLP 1 @ 2
MAINPWON <58,84,86>
Reset Circuit R23 0_0402_5%

1 @ 2
EC_RST# <58>
2

R24 0_0402_5%
R25
10K_0402_5%
1

Q1A D
BI_GATE# 2
BI_GATE PH to +RTCVCC at PWR G
side 2N7002KDW_SOT363-6
S
1

1
3

Q1B D C40
BI_GATE 5 0.1U_0201_10V6K
<84> BI_GATE G 2
2N7002KDW_SOT363-6
S
4

Reset Button
@
SW3
BI_GATE 1 2 BI_GATE

3 4

SKRPABE010_4P
SN10000CV00
change PN to SN10000CV00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 77 of 112
 A B C D E

System DC inferface For Power ON/Off Sequence

@
CQ2 1 2 0.1U_0201_10V6K UQ1 @ JPQ2 PM_SLP_S3
1 14 +5VS_OUT 1 2 +3VALW
+5VALW VIN1 VOUT1 1 2 +5VS

2
2 13

G
VIN1 VOUT1

1
JUMP_43X118
SUSP# RQ1 1 @ 2 0_0402_5% 5VS_ON 3 12 1 2 R37 Q10A
ON1 CT1 CQ1 1000P_0402_50V7K 100K_0402_5% 2N7002KDW_SOT363-6
4 11 1 6

S
+5VALW VBIAS GND EC_VCCST_PG_R <10,58>

D
1 1

2
RQ2 2 @ 1 0_0402_5% 3VS_ON 5 10 1 2 MOW14, For tCPU28 200us(max)
ON2 CT2 CQ3 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion

5
@ 6 9 @ JPQ1

G
+3VALW VIN2 VOUT2 +3VS_OUT 1
CQ4 1 2 0.1U_0201_10V6K 7 8 2
VIN2 VOUT2 1 2 +3VS
Q10B
15 JUMP_43X118 2N7002KDW_SOT363-6
GPAD Q11A 4 3

S
VR_ON <58,90,91>

D
EM5209VF_DFN14_2X3 2N7002KDW_SOT363-6 D
+3VALW +5VALW +3VS_OUT +5VS_OUT 2 MOW14, For tPLT17 200us(max)
<18,58> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion

5
G
2 2 2 2
S

1
CQ7 CQ8 CQ5 CQ6 Q11B
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K 2N7002KDW_SOT363-6
1 1 1 1 4 3 SUSP#

D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable

2
Place CQ7 close UQ1 pin 1&2

G
@
Place CQ8 close UQ1 pin 6&7 Q12A
2N7002KDW_SOT363-6
1 6

S
SYS_PWROK <18,58>

D
5
G
+3VALW @
+5VALW +0.6VS_VTT +5VALW +1.2V_VDDQ Q12B
2N7002KDW_SOT363-6

1
4 3

S
PCH_PWROK <18,58>
2

D
R38

2
@ R27 @ R28 R30 R29 100K_0402_5%
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @

2
2 PM_SLP_S4 2
1

1
discharge Q13A

5
SUSP discharge SYSON# 2N7002KDW_SOT363-6 D

G
trace 20 mils 2
trace 20 mils <18,58> PM_SLP_S4# G Q13B
2N7002KDW_SOT363-6
6

Q7A D D Q7B S 4 3 SYSON

S
1
3

6
2 5 SUSP MOW14, For tPLT15 200us(max)

D
Q8B D D Q8A
<39,58,68,85,88,90> SUSP# G G SYSON 5 2 SYSON# SLP_S4# to VDDQ ramp down
<58,88> SYSON G G
@ @
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1

4
1

2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6

1
R32
10K_0402_5%
@ @
P/N: SB00000EO00 footprint use SB00000ZU00
@

www.laptoprepairsecrets.com
2

+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW

@ +1.05V_VCCST
2
CQ15 1 2 0.1U_0201_10V6K UQ2
3 1 14 +1.05V_VCCST_OUT RQ5 1 @ 2 0_0603_5% CQ12 3
+1.05VALW VIN1 VOUT1
2 13 1U_0201_6.3V6M
VIN1 VOUT1 1 UC4 +1.05VS_VCCSTG
SYSON RQ4 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 1
ON1 CT1 CQ14 1000P_0402_50V7K +5VALW 2 VIN1
4 11 VIN2
+5VALW VBIAS GND 7 6
SUSP# RQ8 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 +1.8VS VIN thermal VOUT
ON2 CT2 CQ16 1000P_0402_50V7K 3
+1.8VS_OUT VBIAS 2
+1.8VALW 6 9 RQ9 1 @ 2 0_0603_5%
@ 7 VIN2 VOUT2 8 SUSP# RQ3 2 @ 1 0_0402_5% EN_1.0V_VCCSTG 4 5 CQ10
CQ20 1 2 0.1U_0201_10V6K VIN2 VOUT2 ON GND
0.1U_0201_10V6K
15 1
GPAD 1
@
EM5209VF_DFN14_2X3 CQ13 AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
2 +1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us

+1.05VALW +1.05V_VCCST_OUT +1.8VS_OUT

+1.8VALW
2 2 2
2
CQ11 CQ9 CQ22
1U_0201_6.3V6M CQ24 0.1U_0201_10V6K 0.1U_0201_10V6K
1 1 1
1U_0201_6.3V6M
1
4 4

Place CQ11 close UQ2 pin 1&2

Place CQ24 close UQ2 pin 6&7

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FH51M M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 78 of 112
A B C D E
 A B C D E

1
@ PJP101
+19V_ADPIN FBMA-L11-201209-800LMA50T
EMI@ PL101 +19V_VIN 1

1 1 2
1 2 EMI@ PL102
2

1000P_0402_50V7K
3 FBMA-L11-201209-800LMA50T

EMI@ PC104
3

1
4

100P_0402_50V8J
PR103

EMI@ PC102
4 5 1 2 PR102
5

1
6 4.7_1206_5% EMI@ PL103
6

1
7 FBMA-L11-201209-800LMA50T 4.7_1206_5%
7

2
8
8

2
9 1 2
9

2
1
10
10

1
PC101 EMI@ EMI@ PC105
0.1U_0603_25V7K Bead SM01000U600 0.1U_0603_25V7K

2
SINGA_2DC3207-000111F

2
2 2

ADAPDET <85>

3
www.laptoprepairsecrets.com 3

@0@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC

4 4

Security Classification
Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DCIN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FXXXX M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 82 of 112
A B C D E
 A B C D E

+3VLP

1
@EMI@
1 PC205 1
0.1U_0603_25V7K

1
@
PR207 100_0402_1% @ PR215 PR214
1 2 26.7K_0402_1%

100K_0402_1%
21.5K_0402_1%
EC_SMB_DA1 <58,85>

PR213
PR205 100_0402_1%

2
1
1 2
EC_SMB_CK1 <58,85>
PU201 @
1 8
VCC TMSNS1
(Common Part)
<45,47> 2 7 2 1
Battery Bot Side PR202
GND RHYST1 SL200002H00

2
200K_0402_1%
@

1
1 2 MAINPWON 3 6 @ PR216
+3VLP <58,77,86> MAINPWON OT1 TMSNS2

100K_0402_1%_NCP15WF104F03RC
@ PJP201 10K_0402_1% @
PIN1 GND 1 4 5
1 2 OT2 RHYST2
PIN2 GND 2 3 EC_SMB_DA1-1
1 2
BATT_TEMP <58,85>

PH202
G718TM1U_SOT23-8
PIN3 SMD 3 4

2
EC_SMB_CK1-1 PR203 1K_0402_1%
4 5 BATT_TS
PIN4 SMC 5 6 BATT_B/I
PIN5 TEMP 6 7 PH202 Near fan.
7 8
PIN6 BI 8 9 +RTCVCC
GND 10
PIN7 Batt+ GND
PIN8 Batt+ CVILU_CI9908M2HR0-NH

1
PR212
100K_0402_5%

2
D

1
2 2
2 PQ201
<77> BI_GATE G LBSS139LT1G 1N SOT-23-3
+17.4V_BATT+ S

3
EMI@ PL201
FBMA-L11-201209-800LMA50T
1 2 BI_S
+17.4V_BATT
EMI@ PL202
When PR204=18.7K

1
FBMA-L11-201209-800LMA50T @0@
1 2 PR217
0_0402_5%
For KB9022
OTP
Active Recovery

www.laptoprepairsecrets.com
2
design reserve VCIN0_PH(V) 89'C, 1V 56'C, 2V
1

PC201 EMI@ PC202 EMI@

1000P_0402_50V7K 0.01U_0402_50V7K
2
2

+3VLP_ECA PH202(ohm) 8.0524K 26.11K

3/27 thermal PH1 92'C ->89'C

1
+3VLP_ECA
PR218 VGA@ PR206
16.5K_0402_1% 10K_0402_1%
1 2
ADP_I <58,85>

2
<58,66> VRAM_TEMP

1
3 3
PR204
18.7K_0402_1%
VCIN1_ADP_PROCHOT <58>

2
100K_0402_1%_NCP15WF104F03RC

100K_0402_1%_NCP15WF104F03RC
VCIN0_PH <58>
1

1
(Common Part) PC203 must close to EC pin

1
PH203 @VGA@

PH204 VGA@
SL200002H00 PR208
10K_0402_1% PH201

2
@ PC203
100K_0402_1%_NCP15WF104F03RC
2

2
0.1U_0402_25V6

1
2
PH203 Near VGA CORE CHOKE.
T202@ PH201 is Common Part SL200002H00

T201@
ECAGND<58,66>
PH204 Near VRAM CHOKE. T202 T201 must close to PH201

ADP_I=20*I(adapter)*0.01
I(adapter)=adapter(W)*130%/19
4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN/OTP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FXXXX M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 84 of 112
A B C D E
 5 4 3 2 1

PRB1
D

1
1M_0402_1%
2 1 2 PQB1
+19VB PQB2
G L2N7002WT1G_SC70-3 AON7380_DFN3X3-8-5 +17.4V_BATT_CHG
PRB2 S 1

3
2 1 +19V_P1 +19V_P2 2
5 3
PQB3 3M_0402_5% PQB4
EMP21N03HC_EDFN5X6-8-5
1 1
AON7380_DFN3X3-8-5 PRB3
0.005_1206_1% EMI@ PLB1
+19V_CHG

4
2 2 5A_Z80_0805_2P
5 3 3 5 1 4 1 2
+19V_VIN

EMI@ PCB5 2200P_0402_50V7K

2 3

EMI@ PCB4 0.1U_0402_25V6

EMI@ PCB8 0.1U_0402_25V6

PCB9 10U_0603_25V6M
PCB6 10U_0603_25V6M
D D

0.047U_0603_25V7M
4

4
1000P_0603_50V7K
PCB2
1 2

1
ACP ACN

PCB1

PCB3
2

1
4.7_0603_1%
0.022U_0603_25V7K

PRB4

4.02K_0402_1%
2

10_0402_1%
1

1
PCB11
PCB10

2
10U_0603_25V6M
0.1U_0402_25V6 PCB7

PRB6
PRB5
2 1 1 2 1 2

10U_0603_25V6M
1

PCB14
PCB13
0.01U_0402_25V7K~N @

2
0.1U_0603_25V7K

2
@
PRB7
+19V_VIN BATDRV_CHG
Close to B2B first mos 4.02K_0402_1%
1 2 ACDRV_CHG

1
PRB37
PRB8 PRB9
1 2 0_0402_5% 0_0402_5%
2 1CMSRC_CHG BATSRC_CHG
PRB10
0_0402_5%

2
1 PRB38 4.02K_0402_1%
+19V_VIN 0_0402_5%

ACN_CHG
ACP_CHG
PDB1 PRB12 @ PCB15
S SCH DIO BAS40CW SOT-323 10_0805_5% 1000P_0402_50V7K
1 2
1

3 1 2
499K_0402_1%

+19V_VIN 1 2 1
PRB35

PRB11 2 ACDRV_CHG
+19VB
422K_0402_1% PCB16 1U_0603_25V6K +6V_CHG_REGN
2 1 PCB17 PQB5
2

2.2U_0603_16V6K
2

5
<82> ADAPDET ACDET PUB1

AON7506_DFN33-8-5
1 2 Choke 4.7uH SH00000YC00 (Common Part)

ACP

ACN
ACDRV
1

28
215K_0402_1%

66.5K_0402_1% 0_0402_5%
L2N7002WT1G_SC70-3

D VCC (Size:6.6 x 7.3 x 3 mm)

1
PRB36

PRB39

2 CMSRC_CHG 3 24 (DCR:28m~33m)
PQB11

CMSRC REGN
1

G PRB16 PCB19 4
S PCB18 6 0_0603_5% 0.047U_0603_25V7M
ACDET BST_CHG 1 2BST_CHG_R 1
2

2200P_0402_25V7K 25 2
C EC_SMB_DA1_CHG 11 BTST C
2

PRB17 1 2 0_0402_5%
<58,84> EC_SMB_DA1 SDA
1

EC_SMB_CK1_CHG 12 UG_CHG +17.4V_BATT

3
2
1
1 2 0_0402_5% 26
PRB13

PRB14 PRB19
<58,84> EC_SMB_CK1 SCL HIDRV PLB2 0.01_1206_1%
ACPRN_CHG 5 4.7UH_PCMB063T-4R7MS_8A_20%
<58,84> ADP_I PCB20 ACOK 27 LX_CHG 1 2 1 4
PHASE
2

1 2 PRB181 2 0_0402_5% 7
IADP 2 3
LG_CHG

1
8 23

4.7_1206_5%
Close to EC 100P_0402_50V8J
IDCHG LODRV
PQB6

EMI@ PRB20
<58> IDCHG 9

AON7506_DFN33-8-5
@ PCB21 PMON
1 2 10 22

10U_0603_25V6M
SRP SRN

10U_0603_25V6M

10U_0603_25V6M
PRB21 316K_0402_1%
/PROCHOT GND

1SNUB_CHG 2

1
1 2

PCB22

PCB23

PCB24
@0@ 100P_0402_50V8J
+3VLP 4
PRB22 PRB23 150K_0402_1%
ILIM_CHG

2
0_0402_5% 13 21 1 2
1 2 GND ILIM PRB24 @
<10,58> H_PROCHOT# 14

680P_0402_50V7K
@0@ 10_0402_1%

www.laptoprepairsecrets.com
NC SRP_CHG

3
2
1
20 1 2 ILIM=charge current limit

EMI@ PCB25
PRB25
0_0402_5% SRP
1 2 15 19 SRN_CHG 1 2 Rsr=input current sense
/BATPRES SRN I(CHG_LIM)=V(ILIM)/(20*Rsr)

2
BATDRV_CHG
PRB26 =(3.3*150/466)/(20*0.01)
16 18 10_0402_1% PCB26
/TB_STAT BATDRV 0.1U_0402_25V6
=5.31A
29 17 BATSRC_CHG 1 2
PWPD BATSRC
<58,84> BATT_TEMP
BQ24781RUYR_WQFN28_4X4

H/L Side AON7506 SB000010A00

0.1U_0402_25V6

0.1U_0402_25V6
Rds(on):13~15.8mohm

1
1

PCB27

PCB28
Vgs=20V
Vds=30V

2
ID= 10.5A (Ta=70C)

B B

+3VS
For 4S per cell 4.35V battery +6V_CHG_REGN

ACDET
1

1
PRB27
1

10K_0402_1% @ PRB29 @ PRB30

PRB28 PRB31 10K_0402_1% 10K_0402_1%
2M_0402_1% 10K_0402_1%
ACPRN_CHG
2

1 2
<58> ACIN

2
DGPU_AC_DETECT <19,27,58>
2

PRB32
1

PRB33 12K_0402_1% @ PQB7A

6
0_0402_5% D 2N7002KDW_SOT363-6
2

2
G
2

1
S

1
1

@ PQB9 @ PQB7B

3
PQB8 RUM001L02_VMT3 D 2N7002KDW_SOT363-6
PRB34 LTC015EUBFS8TL_UMT3F H_PROCHOT# 2 ACIN 5
100K_0402_1% G
1 2 2
<58> BATT_4S S

4
3
3

D
1

A 2 PQB10 A
<39,58,68,78,88,90> SUSP# G L2N7002WT1G_SC70-3
S
3

Security
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered
Deciphered Date
Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FXXXX M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 85 of 112

5 4 3 2 1
 A B C D E

PR301
499K_0402_1%
ENLDO_3V5V 1 2
EN1 and EN2 dont't floating +19VB

1
150K_0402_1%
+19VB EMI@ PL311 @0@ PR303 PC301

PR302
FBMA-L11-201209-800LMA50T 0_0603_5% 0.1U_0603_25V7K Choke 2.2uH SH00000YV00 (Common Part)
1
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2 1

2200P_0402_50V7K
7x7X3

10U_0603_25V6M
10U_0603_25V6M
Isat:10A

2
EMI@ PC304
EMI@ PC302
0.1U_0402_25V6
1

1
PU301

PC306
PC305
DCR:13.5mΩ /15mΩ
SY8288BRAC_QFN20_3X3

1
2

2
PL301 Imax=4.9A, Ipeak=7A, Iocp:8.4A

IN

IN

BS
IN

IN
2.2UH_7.8A_20%_7X7X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
8 18 @EMI@
+3VALWP GND GND PR304

@ PC307

PC309
PC308

@ PC310

PC311

PC312
SPOK_3V 9 17 4.7_1206_5%
PG LDO +3VLP

2
SN_3V 2
1
10 16
NC NC

1
PC313

OUT
EN2

EN1
21 4.7U_0402_6.3V6M

NC
FF
GND

2
PR305
100K_0402_5%

11

12

13

14

15

1
@EMI@

2
PC314
680P_0402_50V7K
Vout is 3.234V~3.366V
<58,89> SPOK_3V

2
3.3V LDO 150mA~300mA

ENLDO_3V5V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
FB_3V 1 2 FB_3V_R 1 2
<58> 3V_EN

@ PJ302
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
2 2

keep short pad,

snubber is for EMI only.

+19VB EMI@ PL511 @0@ PR501 PC501

FBMA-L11-201209-800LMA50T 0_0402_5% 0.1U_0603_25V7K
+19VB_5V BST_5V BST_5V_R 1

www.laptoprepairsecrets.com
1 2 1 2 2
Choke 1.5uH SH000016700 (Common Part)
2200P_0402_50V7K
0.1U_0402_25V6

PU502
7x7X3
10U_0603_25V6M
10U_0603_25V6M

Isat:18A
5

SY8288CRAC_QFN20_3X3
1

1
EMI@ PC504
@EMI@ PC517

PC502

PC503

DCR:14mΩ /15mΩ
BS
IN

IN
IN

IN

LX_5V6 20 PL501 Imax=4.9A, Ipeak=7A, Iocp:8.4A

LX LX
2

1.5UH_9A_20%_7X7X3_M
7 19 LX_5V 1 2
GND LX +5VALWP
8 18
GND GND

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
+3VLP 17 VCC_5V

1
9 1 2
PG VCC

1
PR502

PC509

PC510
PC507

PC508

PC511

PC512
4.7_1206_5%
10 16

@EMI@
PC506
NC NC

2
1

2.2U_0402_6.3V6M
OUT

LDO
EN1
EN2

21 @
FF

PR503
GND

2
100K_0402_5%
11

12

13

14

15
2

1SN_5V
3 +5VLP 3

5V LDO 150mA~300mA

680P_0402_50V7K
4.7U_0402_6.3V6M

<58> SPOK_5V
ENLDO_3V5V
1

@EMI@
PC514

PC513
2
2

PR504
2.2K_0402_5% 5V_EN

<58> EC_ON
1 2 Iocp=12A
@0@ PR505
0_0402_5%
1 2 EN1 and EN2 dont't be floating.
<58,77,84> MAINPWON EN :H>0.8V ; L<0.4V PC515 PR506 @ PJ502
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
Fsw : 600K Hz FB_5V 1 2 FB_5V_R 1 2 1 2
JUMP_43X118
5V_EN
1M_0402_1%
1

1
PR507

PC516
4.7U_0402_6.3V6M

www.DeviceDB.xyz
2
2

Telegram Group
4
@DeviceDB 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
+3VALW/+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
FXXXX M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 86 of 112

A B C D E
 A B C D E

Pin19 need pull separate from +1.35VP.

+19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
1 2 +19VB_1.2VP PRM11
Peak Current 1A
+19VB EMI@ PLM11 2.2_0603_5%
HCB2012KF-121T50_0805 BST_1.2VP_R 1 2 BST_1.2VP
+1.2VP

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

2200P_0402_50V7K
1

1
PCM2

PCM3

PCM4
EMI@ PCM20
UG_1.2VP +0.6VSP

2
1 1

1
PCM5

EMI@
0.1U_0603_25V7K LX_1.2VP

22U_0603_6.3V6M

10U_0603_6.3V6M
2

1
PCM6

PCM7
16

18

19
17

20
4 PUM1

2
@

VLDOIN
PHASE

UGATE

BOOT

VTT
21
PAD
PQM1 LG_1.2VP 15 1
LGATE VTTGND

1
2
3
AONR32320C_DFN3X3-8-5
IOCP
14 2
PLM1 PRM1 PGND VTTSNS
1UH_11A_20%_7X7X3_M 20K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PCM8 CS RT8207PGQW_WQFN20_3X3 GND

1
1U_0201_6.3V6K
VTTREF_1.2VP

5
1 2 12 4
@EMI@ PRM2 PRM3 VDDP VTTREF
4.7_1206_5% 5.1_0603_5% 35.4
1 2 VDD_1.2VP 11 5
PCM9

PCM10

PCM11

PCM12

PCM14
PCM13

VDD VDDQ +1.2VP

1
PCM16

PGOOD
1 1 1 1 1 1 4 +5VALW 2 1

TON
1
SN_1.2VP
PCM17 0.033U_0402_16V7K

FB
S5

S3

2
1
PDM1

@
PQM2 1U_0201_6.3V6K 30MA_30V_0.5UA_0.4V_SOD323-2
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10
2

6
2 2 2 2 2 2 AON7506_DFN3X3-8-5 PRM4
35.4

1
2
3
2.2_0402_1%
1

FB_1.2VP
2

EN_1.2VP
@EMI@ PCM15 PRM5

EN_0.6VSP
680P_0402_50V7K 6.19K_0402_1%
+5VALW

TON_1.2VP
+1.2VP
2

Frequency 1 2

PRM6
470K_0402_1%
+19VB_1.2VP

1
1 2 Vout=0.75V* (1+Rup/Rdown)
2 2
H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm @0@ PRM8 PRM7 =0.75*(1+(6.19/10))
0_0402_5% 10K_0402_1% =1.214V 1.2%
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A 1 2
<58,78> SYSON

2
L/S AON7506 Rds(on) :typ:13m Ohm, max:15.8m Ohm Vout=0.75V* (1+Rup/Rdown)

1
Idsm(TA=25)=12A, Idsm(TA=70)=10.5A @ PCM18
0.1U_0402_16V7K =0.75*(1+(8.2/10))
=1.365V 1.1%

2
Choke 1uH SH00000YE00 (Common Part) Choke: SH00000YE00 Size:7x7x3 (Common Part)
Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC @
(Size:6.86 x 6.47 x 3 mm) PRM9
(DCR:6.2m~7.2m Ohm) Rdc=Xmohm(Typ), 11mohm(Max) TOKO 0_0402_5%
Isat:15A Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers 1 2
Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech <39,58,68,78,85,90> SUSP#
Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin @ PJM2
Mode Level +0.675VSP VTTREF_1.35V Rdc=6.9± 15% Panasonic @0@ PRM10 JUMP_43X118

www.laptoprepairsecrets.com
S5 L off off 0_0402_5% +1.2VP 1 2 +1.2V_VDDQ
1 2 1 2
S3 L off on Switching Frequency: 530kHz <10> SM_PG_CTRL
S0 H on on Imax=A, Iocp=A

1
@ PCM19 @ PJM3
Iocp=10.63~12.76A JUMP_43X39
Note: S3 - sleep ; S5 - power off OVP: 110%~120% 0.1U_0402_16V7K 1 2
+0.6VSP 1 2 +0.6VS_VTT

2
VFB=0.607V, Vout=1.214V

+3VALW
3 3

+5VALW
1

@ PJ2501
1

JUMP_43X39
2
2

PC2501

1U_0402_6.3V6K
2
1

PC2502
FB=0.8V
PU2501
22U_0603_6.3V6M Note:Iload(max)=4A
2

G9661MF11U_SO8 @ PJ2502
@0@ PR2501 4 5 JUMP_43X39
0_0402_5% VIN_2.5V 3 VPP NC 6 1 2
SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP +2.5VP 1 2 +2.5V
GND

1 VEN ADJ 8
22U_0603_6.3V6M

22U_0603_6.3V6M

POK GND
0.01U_0402_25V7K
1
0.1U_0402_16V7K

PR2503
PC2504
9
1

PR2502 Rup
PC2503

PC2505

@ PC2506

21.5K_0402_1%
2

1M_0402_5%
2

2
2

@ FB_2.5V
1

PR2504

10K_0402_1%
Rdown Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008)
2

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
DDR4
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FXXXX M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 88 of 112
A B C D E
 A B C D E

Choke 1uH SH00000YE00 (Common Part)

(Size:6.86 x 6.47 x 3 mm)
(DCR:6.2m~7.2m Ohm)
Choke: SH00000YE00 Size:7x7x3 (Common Part)
Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC
Rdc=Xmohm(Typ), 11mohm(Max) TOKO
Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers
Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech
Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin
Rdc=6.9± 15% Panasonic

1
+19VB_1VALW 1
EN pin don't floating @EMI@ PR1101 @EMI@ PC1101
If have pull down resistor at HW side, pls delete PR702 4.7_1206_5% 680P_0402_50V7K @ PJ1101
@ PJ1102 1 2 SNUB_1VALW 1 2 JUMP_43X118
+19VB 1
JUMP_43X79
2 +19VB_1VALW 2
PU1101
9
@0@ PR1102
+1.05VALWP
1
1 2
2
+1.05VALW
PC1106
1 2 IN PG 0_0603_5% 0.1U_0603_25V7K

10U_0603_25V6M
3 1 BST_1VALW 1 2 BST_1VALW_R 1 2 PL1101

2200P_0402_50V7K
IN BS

0.1U_0603_25V7K
1

1
1UH_6.6A_20%_5X5X3_M

EMI@ PC1102

EMI@ PC1103

PC1105
LX_1VALW
4
IN LX
6 1 2
+1.05VALWP

2
5 19

15.4K_0402_1%

330P_0402_50V7K
IN LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
7 20

PR1104

PC1107

PC1108

PC1109

PC1110

PC1111
GND LX
8 14 FB_1VALW Rup
GND FB

2
PR1110
LDO_3V_1VALW

2
18 17 1K_0402_1%
GND VCC 1 2
EN_1VALW

1
11 10
EN NC
ILMT_1VALW
PC1113 FB = 0.6V

1
13 12 2.2U_0402_6.3V6M
LDO_3V_1VALW ILMT NC

2
+3VALW 15
BYP NC
16 Rdown PR1106
20K_0402_1%
1

21
PAD

2
@0@
PR1103 SY8288RAC_QFN20_3X3

1
0_0402_5%
PC1114
ILMT_1VALW
2

1U_0201_6.3V6M

2
1

@
PR1105
Vout=0.6V* (1+Rup/Rdown)
0_0402_5% =0.6*(1+(15.4/20))
Vout=1.062V
2

2 2
PR1107
10K_0402_1%
1 2 PG_1.8VALWP
8288RAC
Min @ PR1108
ILMT='0' 8A 10K_0402_1%
ILMT=Floating 12A EN_1VALW 1 2
ILMT='1' 16A +3VALW
1

@ PC1115
PR1109
0.22U_0402_16V7K
2

1M_0402_1%
2

www.laptoprepairsecrets.com PR1809
100K_0402_5%
2 1
+3VALW
Choke 1uH SH00000Z200 (Common Part)
PG_1.8VALWP 5x5x3
Isat:11A
DCR:13mΩ /14mΩ

EMI@ PL1802
+19VB FBMA-L11-201209-800LMA50T PU1801
1 2 +19VB_1.8VALWP 2 9 @0@ PR1808 PC1810 @EMI@ PR1802 @EMI@ PC1806
3 IN PG 0_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0402_50V7K 3
10U_0603_25V6M

3 1 BST_1.8VALWP 1 2 1 2 1 2 SNB_1.8VALWP 1 2
IN BS
0.1U_0402_25V6

2200P_0402_50V7K
1

1
PC1801
PC1816

PC1815

4 6
IN LX
2

5
IN LX
19 PL1801 Imax=2.16A, Ipeak=3.09A, Iocp:6.2A
1UH_6.6A_20%_5X5X3_M
LX_1.8VALWP
7 20 1 2
+1.8VALWP
EMI@
EMI@

GND LX
8 14 FB_1.8VALWP

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
GND FB
LDO_1.8VALWP

1
@0@ PR1801 18 17 (R1)
0_0402_5% GND VCC

PC1813
PC1812

PC1804

PC1805
330P_0402_50V7K
1

1
1 2 11 10 PC1809
EN NC

2
1
<58,86> SPOK_3V 2.2U_0402_6.3V6M PR1803

PC1803
ILMT_1.8VALWP 13 12 20.5K_0402_1%
ILMT NC
2

2
1

15 16
+3VALW BYP NC

2
1

PR1805
1M_0402_1% @ PC1811 21 PR1810
PAD
1

0.47U_0402_6.3V6K 1K_0402_1%
2

SY8286RAC_QFN20_3X3 1 2
LDO_1.8VALWP
2

PC1807
2

FB = 0.6V
1U_0201_6.3V6M
1

@0@ @ PJ1801
PR1807 JUMP_43X79

1
0_0402_5% 1 2
PR1804 +1.8VALWP 1 2 +1.8VALW
2

ILMT_1.8VALWP 10K_0402_1%
(R2)
1

2
@
PR1806 Vout=0.6V* (1+Rup/Rdown)
0_0402_5% Vout=0.6V*(1+20.5/10)
=1.83V (x1.017)
2

4 4

8288RAC
Min
ILMT='0' 8A
ILMT=Floating 12A
Compal Electronics, Inc.
ILMT='1' 16A Security Classification Compal Secret Data
Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
1V
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FXXXX M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 89 of 112
A B C D E
 5 4 3 2 1

D D

Choke: SH00000Z300 (Common Part)

Isat=14A
Rdc=10mohm(Typ), 12mohm(Max) Size:6*5.4*3 Tai-Tech
Rdc=11mohm(Typ), 12mohm(Max) Size:5.3*4.9*3 Maglayers
@EMI@ PRH1 @EMI@ PCH1 @ PJH1
can improve CNVI lose issue 4.7_1206_5%
SNB_VCCIOP
680P_0402_50V7K
+1.0VS_VCCIOP
1
1 2
2
+VCCIO
1 2 1 2
JUMP_43X118
EMI@ PLH11
HCB2012KF-121T50_0805
1 2

PUH1 @0@ PRH2 PCH4

+19VB_VCCIOP 2 9 0_0603_5% 0.1U_0603_25V7K
+19VB IN PG
3 1 BST_VCCIOP 1 2BST_VCCIOP_R 1 2 PLH1

10U_0603_25V6M
2200P_0402_50V7K
IN BS

0.1U_0402_25V6
1

1
PCH2 0.68UH_7.9A_20%_5X5X3_M

PCH3

PCH5
LX_VCCIOP
2
4
IN LX
6 1 2
+1.0VS_VCCIOP

1
5 19

PCH10
330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX
@EMI@

1
7 20 Note:Iload(max)=5.5A
EMI@

PCH6

PCH7

PCH8

PCH9

PCH11

PCH12
10_0402_1%
GND LX

2
@

PRH3
8 14 FB_VCCIOP
GND FB IOCP=7A~8A(typ)

2
2
PRH4

1K_0402_1%
18 17 LDO_3V_VCCIOP @
GND VCC

2
EN_VCCIOP

1
11 10 PCH13 @
EN NC 2.2U_0402_6.3V6M Vout=0.6V* (1+Rup/Rdown)

1
ILMT_VCCIOP FB = 0.6V
13
ILMT NC
12 Rup =0.6*(1+(12k/20.5k))

2
1 2
15 16 OVP=0.95V*115%=1.0925V
+3VALW BYP NC PRH5
1

21 12K_0402_1% Vout=0.951 V 2%
PCH14 PAD
C C

20.5K_0402_1%
1
1U_0201_6.3V6M SY8286RAC_QFN20_3X3
2

Rdown
PRH6
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15

2
PRH7 @0@ 0_0402_5%
VCC_SENSE_VCCIO_R 1 2 VCC_SENSE_VCCIO
LDO_3V_VCCIOP VCC_SENSE_VCCIO <12>

PRH8 @0@ 0_0402_5%

VSS_SENSE_VCCIO
1

@ PRH9 1 2
VSS_SENSE_VCCIO <12>
0_0402_5%
@ PRH10 VR_ON 1 2
0_0402_5% <58,78,91> VR_ON

www.laptoprepairsecrets.com
ILMT_VCCIOP
2

PRH11
1K_0402_5%
EN_VCCIOP
1

SUSP# 1 2
<39,58,68,78,85,88> SUSP#
@ PRH12

0.1U_0402_25V6
1M_0402_5%
1

1
check delay time with HW

PCH15
0_0402_5%

PRH13
2

2
2
8286RAC
Min Typ Max
ILMT='0' 6.5A 7.5A 8.5A
ILMT=Floating 9.5A 10.5A 11.5A
ILMT='1' 12.5A 13.5A 14.5A

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
1.0VS_VCCIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FXXXX M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 90 of 112
5 4 3 2 1
 1 2 3 4 5

Place close to Choke in VCCSA first phase circuit

PHZ1 PRZ1 PRZ2 PR1199 NA, need confirm
100K_0402_1%_TSM0B104F4251RZ 12K_0402_1% 7.5K_0603_1%
PCZ1 1 2 1 2 1 2
PRZ3 100_0402_1% 2200P_0402_50V7K
<93> CSN_1PH SW_1PH <93>
+1.05V_VCCST

1
1 2 1 2 PCZ2

100_0402_1%
1

2
PRZ4 0.01U_0402_50V7K

499_0402_1%

45.3_0402_1%
45.3_0402_1%
@0@ PRZ9 PRZ10 10_0402_1% 1 2 PCZ3

PRZ5

PRZ6

PRZ7

PRZ8
A 0_0402_5% 1K_0402_5% A
VSN_1PH 0.1U_0402_25V6

1
1 2 1 2
<12> VSS_SENSE_SA

2
@

2
2
2 1 1 2 @
PCZ4 LA-F611PR01_0531D.DSN

CSP_1PH
1000P_0402_50V7K PRZ12 PCZ5 PCZ6 PRZ13
PROCHOT# change to H_PROCHOT#(P.72 PUZ01.39)

470P_0402_50V8J
1
1.62K_0402_1% 3300P_0402_50V7-K 2200P_0402_50V7K 100_0402_1%
VSP_1PH CSN_1PH_R LA-F611PR01_0531C.DSN 81215_VR_HOT

1
1 2 1 2 1 2

PCZ7

29.4K_0402_1%
<12> VCC_SENSE_SA
+3VS PCH_PWROK change to IMVP_VR_PG(P.72 PUZ01.45)
VR_HOT# <58>

PRZ14
@0@ PRZ11 PCZ8
SVID_CLK_PWR_CPU

2
PRZ15 100_0402_1% 0_0402_5% 1 2 1000P_0402_50V7K 1 2
CPU_SVID_CLK_R <10>
1 2 1 2 PRZ16 49.9_0402_1%

IMON_1PH
+VCC_SA PWM1_1PH/ICCMAX1 <93>

1
PCZ9
1000P_0402_50V7K PRZ19 SVID_ALERT#_PWR_CPU
2 1
CPU_SVID_ALERT#_R <10>
12.4K_0402_1% PRZ17 @0@ PRZ18 0_0402_5%
2 1 10K_0402_1% PRZ23
PRZ21 100_0402_1% 34.8K_0402_1% SVID_DAT_PWR_CPU
1 2
<58> VCCCORE_VR_PWRGD CPU_SVID_DAT_R <10>

2
1 2 PRZ22 PCZ10 PRZ20 10_0402_1%
+VCC_CORE 1.5K_0402_1% 0.01U_0402_25V7K
CPU_EN
1 2
@0@ PRZ24 2 1 2 1
0_0402_5% SVID_CLK_PWR_CPU
<11> VCC_SENSE_IA
1 2 VSP_4PH SVID_ALERT#_PWR_CPU
SVID_DAT_PWR_CPU
1 2
VR_ON <58,78,90>
LA-F611PR01_0531C.DSN
1 2
IMVP_VR_ON change to VR_ON(P.72 PUZ01.43)

2
@0@ PRZ25
PCZ12 PCZ11 0_0402_5% PRZ26 100_0402_1%
1000P_0402_50V7K PRZ28 15P_0402_50V8J 1 2 +VCC_GT

1
1K_0402_1%
1 2 1 2 VSN_4PH VSN_1PH @0@ PRZ30
<11> VSS_SENSE_IA
0_0402_5%

ILIM_1PH
@0@ PRZ27 1 2

COMP_1PH
VSP_1PH VCC_SENSE_GT <11>
PRZ29 100_0402_1% 0_0402_5% 1 2
1 2

1
PCZ13 PCZ14
2200P_0402_50V7K PRZ31 1000P_0402_50V7K
1.37K_0402_1%

2
1 2 1 2 VSS_SENSE_GT <11>
CML@ PRZ47 CML@ PRZ50
191K_0603_1% 191K_0603_1% @0@ PRZ32
PUZ1 1 2 0_0402_5% PRZ33 100_0402_1%
PCZ16 PRZ34 PCZ17 NCP81215PNTXG_QFN52_6X6 1 2

46

42
53

52
51
50
49
48
47

45
44
43

41
40
15P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J PCZ15
1 2 1 2 1 2 PRZ35 2200P_0402_50V7K

TAB

SCLK
VSP_1PH
VSN_1PH

ILIM_1PH

EN

SDIO
COMP_1PH

CSP_1PH
IMON_1PH

ALERT#
VR_RDY
B

CSN_1PH
B

PWM_1PH/ICCMAX_1PH
26.1K_0402_1%
PRZ36 PRZ37 2 1 PRZ38 PCZ19 PCZ20
CML@ PRZ52 CML@ PRZ54 3.65K_0402_1% 1K_0402_1% PRZ39 49.9_0402_1% 470P_0402_50V8J 15P_0402_50V8J
191K_0603_1% 191K_0603_1% 1 2 1 2 1 2 29.4K_0402_1% 1 2 1 2 1 2
PCZ21 VSP_4PH 1 39 81215_VR_HOT 1 2
PCZ18 470P_0402_50V8J VSN_4PH 2 VSP_4PH VRHOT# 38 VSP_2PH PCZ23 2 1 1 2 1 2
2200P_0402_50V7K 2 1 3 VSN_4PH VSP_2PH 37 VSN_2PH 470P_0402_50V8J
DIFFOUT_4PH 4 IMON_4PH VSN_2PH 36 1 2 PRZ40 PRZ41 PCZ22
FB_4PH 5 DIFFOUT_4PH IMON_2PH 35 DIFFOUT_2PH 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
COMP_4PH 6 FB_4PH DIFFOUT_2PH 34 FB_2PH
Place close to Choke in VCORE CFL@ 1 2 ILIM_4PH 7 COMP_4PH FB_2PH 33 COMP_2PH
CSCOMP_4PH PRZ42 30.1K_0402_1% 8 ILIM_4PH COMP_2PH 32 ILIM_2PH 1 2
first phase circuit CSSUM_4PH CSCOMP_4PH ILIM_2PH CSCOMP_2PH
1

9 31 PRZ43 12K_0402_1%
75K_0402_1%

CSSUM_4PH CSCOMP_2PH CSSUM_2PH

1
PHZ2 10 30
680P_0402_50V7K
PRZ44

75K_0402_1%
82P_0402_50V8J

CSP1_4PH 11 CSREF_4PH CSSUM_2PH 29 PHZ3

680P_0402_50V7K
82P_0402_50V8J

PRZ45
CSP2_4PH CSP1_4PH CSREF_2PH CSP1_2PH
1

220K_0402_5%_ERTJ0EV224J 12 28 220K_0402_5%_ERTJ0EV224J

PWM1_4PH/ICCMAX_4PH
PCZ24

PWM1_2PH/ICCMAX_2PH
PCZ25

CSP3_4PH CSP2_4PH CSP1_2PH

2

1
PWM4_4PH/ROSC_MPH
PCZ26 13 27 2 1 Place close to Choke in VCCGT first phase circuit

PWM2_2PH/ROSC_1PH

PCZ27

PCZ28
CSP3_4PH CSP2_2PH
+5VALW
2

1 2

CFL@ PRZ47

TTSENSE_1PH/PSYS
165K_0402_1%

2
1
PWM3_4PH/VBOOT
118K_0603_1% 0.1U_0402_25V7K PRZ46

PWM2_4PH/ADDR
www.laptoprepairsecrets.com
1

2
1 2 CML@ PRZ42 1K_0402_1% PCZ29
PRZ48

<91,92> SW1_4PH

1
TTSENSE_2PH
CFL@ PRZ50 18.7K_0402_1% 0.1U_0402_25V7K

TSENSE_4PH

2
118K_0603_1% PRZ49

CSP4_4PH
1 2 165K_0402_1%
<91,92> SW2_4PH
2

CFL@ PRZ52 PRZ51

DRON
VRMP
118K_0603_1% 80.6K_0603_1%

VCC

2
1 2 2 1 1 2
<91,92> SW3_4PH SW1_2PH <91,93>
CFL@ PRZ54
118K_0603_1% PRZ55 @ PRZ53
+5VALW

25
14
15
16
17
18
19
20
21
22
23
24

26
1 2 1K_0402_1% 1K_0402_1%
<91,92> SW4_4PH
1 2 PCZ30
CSREF_4PH
+19VB_CPU 0.1U_0402_25V6 CSP4_4PH
PCZ31 2 1 TSENSE_4PH PCZ32
<92> CSREF_4PH
0.01U_0402_50V7K 0.1U_0402_25V6 PRZ57
1 2 TSENSE_2PH 1 2 24.9K_0402_1% CSREF_2PH
CSREF_2PH <93>
1 2 1 2
1U_0402_6.3V6K
<92,93> DRVON PWM2_2PH/ROSC1
PRZ59 +5VALW PRZ56 1 2
1

3.74K_0402_1% 2.2_0603_5% PRZ58

PCZ33

1 2 CSP1_4PH 25.5K_0402_1%
PRZ61
110K_0402_1%
<91,92> SW1_4PH

1
2
2

4.32K_0402_1%

24.9K_0402_1%

97.6K_0402_1%

97.6K_0402_1%
PWM1_2PH/ICCMAX2 <93>

1
C PCZ34 @ PRZ60 C
0.047U_0402_25V7K 100K_0402_1% PRZ66

PRZ62

PRZ63

PRZ64

PRZ65
1

3.74K_0402_1%
CSREF_4PH CSP1_2PH
2

1 2
<92> PWM1_4PH/ICCMAX4 SW1_2PH <91,93>
1

PRZ67

2
2

2
3.74K_0402_1%
1 2 CSP2_4PH PCZ35
<91,92> SW2_4PH <92> PWM2_4PH/ADDR
0.047U_0402_25V7K

1
2

PCZ36 @ PRZ68 CSREF_2PH

0.047U_0402_25V7K 100K_0402_1%
1

CSREF_4PH <92> PWM3_4PH/VBOOT

1

PRZ69
3.74K_0402_1%
CSP3_4PH <92> PWM4_4PH/ROSCM
1 2
<91,92> SW3_4PH
2

PCZ37 @ PRZ70
0.047U_0402_25V7K 100K_0402_1%
1

CSREF_4PH
TSENSE_4PH TSENSE_2PH
1

PRZ71
1

1
3.74K_0402_1% 0_0402_5%
0_0402_5%
@0@ PRZ72

@0@ PRZ73

1 2 CSP4_4PH
<91,92> SW4_4PH
2

PCZ38 @ PRZ74 Place close to H-side,L-side MOS

2

0.047U_0402_25V7K 100K_0402_1% Place close to H-side,L-side MOS in VCCGT first phase

1

1
1

CSREF_4PH
in VCORE first phase
1

1
1

PHZ4 PRZ75 PHZ5 PRZ76

61.9K_0402_1% 61.9K_0402_1%
220K_0402_5%_ERTJ0EV224J 220K_0402_5%_ERTJ0EV224J
2

2
2

D D

Security Classification Compal Secret Data

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CPU IC CFL_H 42
Date: Tuesday, February 11, 2020 Sheet 91 of 112

1 2 3 4 5
 5 4 3 2 1

Main Func = CORE

MOSFET: DFN 5X6E

H/S Rds(on): 7.1mohm(Typ), 9.1mohm(Max)
L/S Rds(on): 2mohm(Typ), 2.5mohm(Max)
EMI@ PLZ11
HCB2012KF-121T50_0805
PRZ85 +19VB_CPU 1 2
0_0603_5%
+19VB
1 2 UG1_VCORE_R PCZ39 PCZ46 EMI@ PLZ12
HCB2012KF-121T50_0805

0.1U_0603_25V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
1

1
1 2

10U_0603_25V6M

10U_0603_25V6M

EMI@ PCZ60
EMI@ PCZ58

EMI@ PCZ59
1 1

33U_25V_M

33U_25V_M
D + + D
PRZ77

PCZ65
PCZ48
2

2
2.2_0603_5%
BST1_VCORE BST1_VCORE_R

2
1 2
PQZ1 2 2

D1
G1
AONY36352_DFN5X6D-8-7
PCZ50
0.22U_0603_25V7K 7
PUZ2 D2/S1 PLZ1

1
NCP81151MNTBG_DFN8_2X2 0.15UH_NA__35A_20%

S2-3

S2-2

S2-1
1 9 1 4
+VCC_CORE

G2
BST FLAG
UG1_VCORE

2
<91> PWM1_4PH/ICCMAX4
2
PWM DRVH
8 2 3 SH00001EF00(common part)

3
3 7 LX1_VCORE 7x7X3
<91,93> DRVON EN SW Isat:45A
DCR:0.9m Ω +/-5%

1
4 6 @EMI@
+5VALW VCC GND PRZ78
5 LG1_VCORE
4.7_1206_5%
DRVL 1 2 CSREF_4PH<91>

1
PCZ49

2
PRZ89 10_0402_1%
2.2U_0402_6.3V6M SNB1_VCORE

2
SW1_4PH<91>

1
@EMI@
PCZ51
680P_0402_50V7K

2
PRZ84
0_0603_5%
+19VB_CPU
1 2 UG2_VCORE_R PCZ66 PCZ67

+VCC CORE

1
10U_0603_25V6M

10U_0603_25V6M
PRZ79
TDC= 80A->86A
Peak Current= 128A->140A

2
2.2_0603_5%
BST2_VCORE BST2_VCORE_R

2
1 2
PQZ2
OCP Current= 154A->168A

D1
Load Line= 1.8mV/A

G1
AONY36352_DFN5X6D-8-7
PCZ53
0.22U_0603_25V7K 7 Vboot= 0V
PUZ3 D2/S1 PLZ2

1
NCP81151MNTBG_DFN8_2X2 0.15UH_NA__35A_20%

S2-3

S2-2

S2-1
1 9 1 4
+VCC_CORE

G2
BST FLAG
C C
UG2_VCORE

2
2 8 2 3 SH00001EF00(common part)
<91> PWM2_4PH/ADDR PWM DRVH

3
DRVON 3 7 LX2_VCORE 7x7X3
EN SW Isat:45A
+5VALW 4 6 DCR:0.9m Ω +/-5%
VCC GND

1
@EMI@
5 LG2_VCORE PRZ80
DRVL
4.7_1206_5%
1

PCZ52 1 2

2
2.2U_0402_6.3V6M PRZ90 10_0402_1%
SNB2_VCORE
2

SW2_4PH<91>

1
@EMI@
PCZ54
680P_0402_50V7K

2
www.laptoprepairsecrets.com 1
PRZ83
0_0603_5%
2 UG3_VCORE_R PCZ45 PCZ44
+19VB_CPU

1
10U_0603_25V6M

10U_0603_25V6M
PRZ81

2
2.2_0603_5%
BST3_VCORE BST3_VCORE_R
1

2
1 2
PQZ3

D1
G1

AONY36352_DFN5X6D-8-7
PCZ56
0.22U_0603_25V7K 7
PUZ4 D2/S1 PLZ3
1

NCP81151MNTBG_DFN8_2X2 0.15UH_NA__35A_20%
S2-3

S2-2

S2-1

1 9 1 4
+VCC_CORE
G2

BST FLAG
UG3_VCORE
2

2 8 2 3
<91> PWM3_4PH/VBOOT PWM DRVH
6

LX3_VCORE
SH00001EF00(common part)
DRVON 3 7
EN SW 7x7X3
4 6 Isat:45A
+5VALW VCC GND DCR:0.9m Ω +/-5%

1
@EMI@
5 LG3_VCORE PRZ82
DRVL
4.7_1206_5%
1

PCZ55 1 2
B B

2
2.2U_0402_6.3V6M PRZ91 10_0402_1%
SNB3_VCORE
2

SW3_4PH<91>

1
@EMI@
PCZ57
680P_0402_50V7K

2
PRZ86
0_0603_5%
+19VB_CPU
1 2 UG4_VCORE_R PCZ70 PCZ71

1
10U_0603_25V6M

10U_0603_25V6M
PRZ87

2
2.2_0603_5%
BST4_VCORE BST4_VCORE_R
1

1 2
PQZ4
D1
G1

AONY36352_DFN5X6D-8-7
PCZ62
0.22U_0603_25V7K 7
PUZ5 D2/S1 PLZ4
1

NCP81151MNTBG_DFN8_2X2 0.15UH_NA__35A_20%
S2-3

S2-2

S2-1

1 9 1 4
+VCC_CORE
G2

BST FLAG
UG4_VCORE
2

2 8 2 3
<91> PWM4_4PH/ROSCM PWM DRVH
6

LX4_VCORE
SH00001EF00(common part)
DRVON 3 7 7x7X3
EN SW
4 6 Isat:45A
+5VALW VCC GND DCR:0.9m Ω +/-5%
1

@EMI@
5 LG4_VCORE PRZ88
DRVL
4.7_1206_5%
1

PCZ61 1 2
2

2.2U_0402_6.3V6M PRZ92 10_0402_1%

SNB4_VCORE
2

SW4_4PH<91>
1

A @EMI@ A
PCZ64
680P_0402_50V7K
2

Security Classification Compal Secret Data

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 92 of 112
5 4 3 2 1
 5 4 3 2 1

Main Func = VCCGT/+VCCSA

MOSFET: DFN 5X6E +19VB_CPU

H/S Rds(on): 7.1mohm(Typ), 9.1mohm(Max) PCG4 PCG3 PCG8 PCG9
L/S Rds(on): 2mohm(Typ), 2.5mohm(Max)

1
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
PRG1

2
D 2.2_0603_5% D
BST_VCCGT 1 2 BST_VCCGT_R 1 2 UG_VCCGT_R
SH00001EF00(common part)
PRG3 0_0603_5% 7x7X3 +VCCGT

1
PCG6
Isat:45A TDC= 25A

2
0.22U_0603_25V7K
PUG1 PQG1 DCR:0.9m Ω +/-5% Peak Current= 32A

G1

D1
2
NCP81151MNTBG_DFN8_2X2 PLG1
1 9
AONY36352_DFN5X6D-8-7
0.15UH_NA__35A_20%
OCP Current= 39A
BST FLAG
UG_VCCGT
7
D2/S1
LX_VCCGT 1 4
+VCC_GT Load Line= 2.7mV/A
2 8
<91> PWM1_2PH/ICCMAX2 PWM DRVH 2 3 Vboot= 0V

S2-2

S2-1
S2-3
DRVON 3 7 LX_VCCGT

G2
EN SW
4 6 near choke
+5VALW VCC GND

1
@EMI@
5 LG_VCCGT PRG2 PRG4
DRVL 10_0402_1%
4.7_1206_5%
CSREF_2PH<91>
1

PCG5 1 2

2
2.2U_0402_6.3V6M
2

SNB_VCCGT

SW1_2PH <91>

1
@EMI@
PCG7
680P_0402_50V7K

2
C C

+19VB_CPU
PCA2 PCA1

1
1

10U_0603_25V6M

10U_0603_25V6M
2
2
1
PRA2
2.2_0603_5%
2
PCA5
0.22U_0603_25V7K
BST_VCCSA_R 1 2 www.laptoprepairsecrets.com
UG_VCCSA

Choke 0.47uH SH00001ED00 (Commom Part)

+VCCSA
TDC= 10A
PQA1 (Size:5.7 x 5.4 x 3.0 mm) Peak Current = 11A
PUA1
(DCR:6.2m +-5%) OCP Current= 13A
1

NCP81253MNTBG_DFN8_2X2 EMB09A03VP_EDFN3X3-8-10
Load Line= 10.3mV/A
G1

D1

D1

D1

BST_VCCSA 1 8 PLA1
BST DRVH 0.47UH_MMD05CZR47M_12A_20% Vboot= 1.05V
B 2 7 LX_VCCSA 9 10 LX_VCCSA 1 4 B
<91> PWM1_1PH/ICCMAX1 PWM SW D2/S1 D1 +VCC_SA
3 6 2 3
<91,92> DRVON EN GND
G2

S2

S2

S2

4 5
+5VALW VCC DRVL
PAD

@EMI@
8

PRA1
4.7_1206_5%
9
1

PCA4
CSN_1PH<91>
2

2.2U_0402_6.3V6M LG_VCCSA
2

SNB_VCCSA
1

@EMI@
PCA6 SW_1PH <91>
680P_0402_50V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCC_GT/+VCC_SA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FXXXX M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 93 of 112

5 4 3 2 1
 A

D
+VCC_CORE

Acoustic
for
Reverse
2 1 2 1 2 1 2 1 2 1 2 1 2 1

+VCC_CORE
2

1
+
@

@
PCZ159 PCZ149 PCZ139 PCZ134 PCZ124 PCZ114 @ PCZ104 PCZ176
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R4.5M

2 1 2 1 2 1 2 1 2 1 2 1 2 1
5

5
2

1
+
@

@
PCZ160 PCZ150 PCZ140 PCZ135 PCZ125 PCZ115 @ PCZ105 CML@ PCZ101
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D1_2VY_R9M

2 1 2 1 2 1 2 1 2 1 2 1 2 1

1
+
@

24 +6@
22 +19@
1
2
CFL H82
PCZ161 PCZ151 PCZ141 PCZ136 PCZ126 PCZ116 PCZ106 PCZ102
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D1_2VY_R9M

2 1 2 1 2 1 2 1 2 1 2 1 2 1

1
+
@
PCZ162 PCZ152 PCZ142 PCZ137 PCZ127 PCZ117 @ PCZ107 PCZ103
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D1_2VY_R9M

X 220uF_D7_2V
X 1uF_0201
X 22uF_0603_X5R for H62
X 330uF_D1_2V
Total VCORE Output Capacitor:
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

@
CML@ PCZ163 PCZ153 PCZ143 PCZ138 PCZ128 PCZ118 PCZ108 PCZ170
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1 2 1 2 1

CML@ PCZ164 PCZ154 PCZ144 PCZ129 PCZ119 PCZ109 PCZ171

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1 2 1 2 1

@
CML@ PCZ165 PCZ155 PCZ145 PCZ130 PCZ120 PCZ110 PCZ172
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1 2 1 2 1

@
CML@ PCZ166 PCZ156 PCZ146 PCZ131 PCZ121 @ PCZ111 PCZ173
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1 2 1 2 1

@
CML@ PCZ167 PCZ157 PCZ147 PCZ132 PCZ122 PCZ112 PCZ174

30
41
1
3
CML
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
4

4
2 1 2 1 2 1 2 1 2 1 2 1 2 1

X 220uF_D7_2V
X 1uF_0201
X 22uF_0603_X5R for H62
X 330uF_D1_2V
H82 Total VCORE Output Capacitor:
@
CML@ PCZ168 PCZ158 PCZ148 PCZ133 PCZ123 @ PCZ113 PCZ175
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

www.laptoprepairsecrets.com

+VCC_GT
2 1 2 1 2 1 2 1

PCG133 PCG123 PCG113 PCG103

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1

PCG134 PCG124 PCG114 PCG104

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1

+VCC_GT
@ PCG135 PCG125 PCG115 PCG105
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
+
PCG101
2 1 2 1 2 1 2 1 220U_D2_2V_Y

@ PCG136 PCG126 PCG116 PCG106

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
+
2 1 2 1 2 1 2 1

@
PCG102
220U_D2_2V_Y
3

3
@ PCG137 PCG127 PCG117 PCG107
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AN

2 1 2 1 2 1 2 1
Issued Date

@ PCG138 PCG128 PCG118 PCG108

12+8@
18+2@
2
Total VCCGT Output Capacitor:
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1

@ PCG139 PCG129 PCG119 PCG109

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

X 1uF_0201
X 22uF_0603_X5R
X 220uF_D2_2V
2 1 2 1 2 1 2 1

@ PCG140 PCG130 PCG120 PCG110

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1

@ PCG141 PCG131 @ PCG121 PCG111

2019/09/20

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1

@ PCG142 PCG132 @ PCG122 PCG112

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Secret Data
Deciphered Date

+VCC_SA
2

2
 5 4 3 2 1

@ PCV1
0.1U_0402_25V6
2 1

PRV1 PRV3
1
0_0402_5%
2 1
34K_0402_1%
2 NVVDD1
TDC 45A
PCV2 NVVDD_B+
0.1U_0402_25V6 +5VCC PRV6
Peak Current 120.5A
+3VS 1 2 4.3K_0402_1% OCP 200A
2 1
Fsw=300kHz

91K_0402_1%
PRV9

PRV8
10K_0402_1%
10K_0402_1%
1

1
3.6K_0402_1%
2 1

PRV139

PRV140
D PRV11 D

2
10K_0402_1% PRV2 +5VCC
2 1 4.99K_0402_1%
2

2
VGA_I2CC_SDA_PWR 2 1
VGA_I2CC_SCL_PWR PCV4 @ PCV5 PRV4
0.1U_0402_25V6 0.1U_0402_25V6 3.4K_0402_1%
1

1 1 2 1 2 2 1
0_0402_5%

0_0402_5%
@ PRV142

@ PRV141 2 1 2 1 PRV7
PRV12 PRV13 442_0402_1%
0_0402_5% 0_0402_5% 1 2
2

1
1 2 2 1 PCV3

0_0402_5%
PCV6 PRV15 1U_0402_6.3V6K

PRV16
0.015U_0402_16V7K 2.4K_0402_1% 1 2

2 1 1 2

2
PRV18 @ PCV7
@0@ PRV20 0_0402_5% 0.1U_0402_25V6 PRV14
<29> VCC_SENSE_NVVDD1 0_0402_5% 2K_0402_1%

2
2 1 1 2

PRV21

0_0402_5%
1 2 @ @0@ PRV145

FDMF3170_REFIN
+NVVDD1

ADDR/FSW_GPU
PRV22 +5VCC 0_0402_5%

VINMON_GPU
10_0402_1% 2 1
FDMF3170_IMON1 <97>

COMP_GPU

IMON_GPU

0.1U_0402_25V6
DAC_GPU
EAP_GPU

LPC_GPU

PCV8
1
@ PRV25 @ PCV11 @ PRV19

100K_0402_1%
1
0_0402_5% 0.1U_0402_25V6 1K_0402_1%

2
1 2 1 2 +5VCC

@
PRV10
VOUT_S

2
@0@ PRV146

24

21
23

22

20

19

18

17
0.1U_0402_25V6

C C
2 1 PUV1 0_0402_5%
PCV14

2
2

PRV31 2 1

100K_0402_1%
REFOUT
VINMON
COMP

ADDR

IMON
EAP

DAC

LPC
FDMF3170_IMON2 <97>

1
1K_0402_1%

0.1U_0402_25V6
1
@

PRV29
1

CSPSUM_GPU

1
25 16

@ PCV13
FB CSPSUM @ PRV30
@0@ PRV34 NVVDD1_FBRTN 26 15 CSNSUM_GPU 1K_0402_1%
FBRTN CSNSUM

2
<29> VSS_SENSE_NVVDD1 0_0402_5%

2
2 1 TSENSE_GPU 27 14 CSP1_GPU
<97> TSENSE_GPU TSENSE CSP1
VGA_I2CC_SDA_PWR CSP2_GPU FDMF3170_REFIN <97>
1 2 28 13
PRV35 <27> VGA_I2CC_SDA_PWR SDA UP9512QQKI_WQFN32_4X4 CSP2
10_0402_1% VGA_I2CC_SCL_PWR 29 12 CSP3_GPU
NVVDD1_FBRTN <27> VGA_I2CC_SCL_PWR SCL CSP3 +5VS
+5VCC
1 2 EN_GPU 30 11

www.laptoprepairsecrets.com
+3VALW EN CSP4
PRV39
PSI_GPU
1

10K_0402_1% 31 10 2 1
10K_0402_1%

PSI 5VCC PRV42

4.7U_0402_6.3V6M
PRV40

NVVDD1_PG
DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6

1
32 9

PCV18
2.2_0603_5%
PGOOD PWM1
0.1U_0402_25V6
6

REFADJ
33

CH_OC
GND

PWM4
REFIN
2

PWM3

PWM2

2
1

VREF
PQV01A

PQV01B

@ PCV10

VID
2 5
<27,37> NVVDD1_EN
2

8
1

1 2
REFADJ_GPU

PWM4_GPU

PWM3_GPU
+3VS

VREF_GPU

CH_OC_GPU
REFIN_GPU

PWM2_GPU

PWM1_GPU
VID_GPU

@0@ PRV46
0_0402_5%

@0@
PRV50
NVVDD_PSI <27> 0_0402_5%
B 1 2 B
6.19K_0402_1%
1

PRV44

1 2 R1
@ PRV52 @0@ PRV54
0_0402_5% 0_0402_5%
2

2 1 GPU_PWM1 <97>
PRV61
100K_0402_1% 2 1 GPU_PWM2 <97>
+3VS 1 2 2 1
@0@ PRV56
PRV53 0_0402_5%
PRV69 232K_0402_1%

PRV63
PRV71 113K_0402_1%

@ PRV72 22.6K_0402_1%

PRV73 63.4K_0402_1%

@0@ PRV70 4.32K_0402_1%

0_0402_5% R3
16.5K_0402_1%

1
1

+5VS 1 2
1

@ PCV9
PRV57

@ 100K_0402_1%
<27> NVVDD_VID
1
1U_0402_6.3V6K
2
R4
@ PUV8
2
2

TC7SH08FU_SSOP5~D R2
2

2
5

+5VS 1 PRV66
P

B 4 GPU_DRVON <97> 20.5K_0402_1%

EN_GPU 2 O 2 1
A
G
3

4700P_0402_50V7K

1
309_0402_1%
1

@0@
PCV26

PRV64

PRV51 C R5
1U_0402_6.3V6K

0_0402_5%
PWMVID 的 RC BOM
2

1 2
PCV25

請 根 據 GPU 's conf i g 設定

2

A A
1

NVVDD1_FBRTN

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VGA_UP9512P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FXXXX M/B LA-J871P
Date: Tuesday, February 11, 2020 Sheet 96 of 112
5 4 3 2 1
 1 2 3 4 5

GPU_B+ NVVDD_B+
EMI@ PLV11
+NVVDD1
+19VB PRV74 PRV75 TDC 45.8A
HCB2012KF-121T50_0805
1 2 1 4 1 4
Peak Current 120.5A
EMI@ PLV12 2 3 2 3 OCP current 144.6A
HCB2012KF-121T50_0805
1 2 fsw=300kHz
0.005_1206_1% 0.005_1206_1%

+5VS
A A

2
<36> CSSP_B+ <36> CSSN_B+ CSSP_NVVDD <36> <36> CSSN_NVVDD
NCP303150@
PRV77
0_0402_5%
PRV76 NVVDD_B+

1
30K_0402_5%
1 2
Use 0805 size
@0@ PRV82
96> TSENSE_GPU
0_0402_5%

PCV30

PCV31
2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK

10U_0805_25VAK
10U_0805_25VAK

10U_0805_25VAK

10U_0805_25VAK
0.1U_0402_25V6
1
1 2 TMON1_FDMF3170 BST1_FDMF3170
1 2

33U_25V_M
1

1
+

PCV39

PCV249
PCV32

PCV33

PCV34

PCV35

PCV38
PRV80
2.2_0603_1%

2
2

1
+5VS

EMI@

EMI@
17

11

13
16

10

9
PCV40
0.1U_0603_25V7K

FAULT

BOOT
ZCD_EN

N/C

VIN1

VIN

2
@0@ PRV85
0_0402_5%
PCV27 +NVVDD1 1 2 VOS1_FDMF3170 1
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE1_FDMF3170
PVCC PHASE
1 2 VCC1_FDMF3170 3
PRV78 VCC
2_0402_5% 2
AGND
1

PCV37
2.2U_0402_6.3V6M 5 PUV2
PGND QD9619AQR1
2

20
PGND2
PLV2 +NVVDD1
B S COIL 0.22UH 20% MMD-10DZIR22MER1L 50A B
1 2 PWM1_FDMF3170 14 8 LX1_FDMF3170 1 2
GPU_DRVON <96> <96> GPU_PWM1 @0@ PRV79 0_0402_5% PWM SW
EN1_FDMF3170

1
1 2 15
@0@ PRV84 0_0402_5% DISB# 10X10X4
FDMF3170_IMON1 18 EMI@ PRV154
<96> FDMF3170_IMON1 IMON Isat:90A
4.7_1206_5%
1 2 FDMF3170_REFIN1 19 DCR:0.55m Ω (+/-5%)

PGND1
REFIN

2
@0@ PRV81 0_0402_5% GPU1_SNB1
GL

TP

1
EMI@ PCV255
6

21

7
680P_0402_50V7K

2
www.laptoprepairsecrets.com
+5VS
2

NCP303150@
PRV87
0_0402_5%
PRV88 NVVDD_B+
1

30K_0402_5% Use 0805 size co-lay 0603 low noise MLCC

1 2

@0@ PRV92
0_0402_5%

PCV47

PCV48
2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M
0.1U_0402_25V6

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M
1 2 TMON2_FDMF3170 BST2_FDMF3170
1 2

1
1

1
PCV49

PCV363

PCV365

PCV366

PCV369
PCV41

PCV362

PCV368
PRV90

PCV364

PCV367
C C
2.2_0603_1%

2
2
1

+5VS

EMI@

EMI@
11
16

17

10

13
9

PCV57 @ @ @ @ @ @ @ @
0.1U_0603_25V7K
BOOT
FAULT

VIN1
ZCD_EN

N/C

VIN

@0@ PRV95
0_0402_5%
PCV44 +NVVDD1 1 2 VOS2_FDMF3170 1
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE2_FDMF3170
PVCC PHASE
1 2 VCC2_FDMF3170 3
PRV86 VCC
2_0402_5% 2
AGND
1

PCV54
2.2U_0402_6.3V6M 5
PGND PUV3
2

20 QD9619AQR1
PGND2
PLV3 +NVVDD1
S COIL 0.22UH 20% MMD-10DZIR22MER1L 50A
1 2 PWM2_FDMF3170 14 8 LX2_FDMF3170 1 2
<96> GPU_PWM2 @0@ PRV89 0_0402_5% PWM SW
EN2_FDMF3170
1

1 2 15
@0@ PRV94 0_0402_5% DISB#
FDMF3170_IMON2 18 EMI@ PRV93 10X10X4
<96> FDMF3170_IMON2 IMON 4.7_1206_5% Isat:90A
1 2 FDMF3170_REFIN219
PGND1

REFIN DCR:0.55m Ω (+/-5%)

2

@0@ PRV91 0_0402_5% GPU1_SNB2

GL

TP

FDMF3170_REFIN <96>
1

EMI@ PCV60
6

21

D 680P_0402_50V7K D
2

Security
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued
Issued Date
Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+NVVDD1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FXXXX M/B LA-J871P 1.0

Date: Tuesday, February 11, 2020 Sheet 97 of 112

1 2 3 4 5
 A
B
C
D

+NVVDD1
2 1 2 1 2 1

2
1
+

@
PCV155 PCV159 PCV251 PCV135
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 560U_D2_2VM_R4.5M
2 1 2 1 2 1

5
5

2
1
+
PCV156 PCV160 PCV140 PCV136
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 330U_D1_2VY_R9M
2 1 2 1 2 1

2
1
+
PCV157 PCV161 PCV141 PCV137
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 330U_D1_2VY_R9M
2 1 2 1 2 1

2
1
+
PCV158 PCV258 PCV142 PCV138
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 560U_D2_2VM_R4.5M
2 1 2 1 2 1

2
1
PCV162 PCV149 PCV143 +
PCV139
1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 560U_D2_2VM_R4.5M
2 1 2 1 2 1
2
1
+

PCV163 PCV150 PCV144 PCV272

1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM 560U_D2_2VM_R4.5M
2 1 2 1 2 1

PCV164 PCV151 PCV145

1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM
2 1 2 1 2 1

PCV165 PCV152 PCV146

1U_0201_6.3VAM 1U_0201_6.3VAM 1U_0201_6.3VAM
2 1 2 1

PCV153 PCV147
1U_0201_6.3VAM 1U_0201_6.3VAM
2 1 2 1

PCV154 PCV148
1U_0201_6.3VAM 1U_0201_6.3VAM

4
4

+NVVDD1
+NVVDD

2 1
2 1 2 1 2 1
N18P-G62

PCV215
560uF X 5

PCV283 PCV225 PCV235 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1 2 1
PCV216
1uF_0201 X 28

PCV280 PCV226 PCV236 10U_0402_6.3V6M

10uF_0402X 34
22uF_0603 X 15

10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1

2 1 2 1 2 1
PCV217
PCV237 PCV227 PCV279 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1 2 1
PCV218
PCV276 PCV229 PCV282 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV219

3
3

PCV228 PCV287 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV220
PCV230 PCV250 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV221
PCV231 PCV275 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV222
Issued Date

PCV232 PCV281 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
Security Classification

PCV223
PCV233 PCV284 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV224
PCV234 PCV277 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M
2019/09/20
+NVVDD1

2 1 2 1

PCV254 PCV243
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

PCV253 PCV244
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
2

PCV252 PCV245
22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Secret Data

2 1 2 1
Deciphered Date

PCV257 PCV246
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

PCV256 PCV247
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
www.laptoprepairsecrets.com

PCV248
22U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2020/09/20

2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PCV358
22U_0603_6.3V6M
2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PCV359
22U_0603_6.3V6M
2 1

PCV360
22U_0603_6.3V6M
Size
Title

Date:

2 1

PCV361
22U_0603_6.3V6M
Document Number

Tuesday, February 11, 2020

1
1

Sheet
FXXXX M/B LA-J871P
98
PWR_VGA DECOUPLING
Compal Electronics, Inc.

of
112
R ev
1.0
A
B
C
D
 5 4 3 2 1

co-lay 0603 low noise MLCC

EMI@ PLW11
FBMA-L11-201209-800LMA50T
B+_+1.35VS_VGAP 1 2 GPU_B+

2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK

10U_0805_25VAK
0.1U_0402_25V6

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M

10U_0603-H1_2_25V6M
PRW1

PCW1

PCW2
1

1
1K_0402_1%

PCW3

PCW4

PCW5

PCW25

PCW26
PCW24
1 2
<27,37> 1.35VSDGPU_EN
D D

2
PCW6

EMI@

EMI@
0.1U_0402_25V6 MOSFET: DFN 5X6E @ @ @
1 2 H/S Rds(on): 5.2mohm(Typ), 7mohm(Max)
Samesung & Micron VRAM +3VALW L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max)
When,VRAM_VDD_CTL=High UG1_+1.35VS_VGAP +1.35VSDGPU
Vboot=1.25V N18P-G62
SW1_+1.35VS_VGAP
When,VRAM_VDD_CTL=Low

1
PRW10
TDC 17.2A
Vboot=1.2V 31.6K_0402_1% 13X8X4 Peak Current 18.4A
@ PRW3
Isat:55A OCP current 30A
DCR:1.3mΩ (+/-5%)

2
0_0402_5%
1 2
fsw=400kHz
<27> FBVDDQ_PSI
PQW1 PLW1
AOE6930_DFN5X6E8-10 0.47UH_MHT-MHDZIR47MEM1-RT_30A_20%
SW1_+1.35VS_VGAP-1

4
PRW6
1 2
+1.35VSDGPU

G1

D2/S1_3 S1/D2

D1_1

D1_2
10K_0402_1%
VREF_+1.35VS_VGAP

1
9 10

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PRW4 D1_3 S2 1 1 1 1 1

D2/S1_2

D2/S1_1
@0@ 2.2_0603_5% EMI@ PRW8

330U_D1_2VY_R9M

330U_D1_2VY_R9M

330U_D1_2VY_R9M

330U_D1_2VY_R9M
330U_D1_2VY_R9M

1
PRW9 2 1 4.7_1206_5% + + + + +

PCW23

PCW9

PCW10

PCW29

PCW13
PCW28

PCW11

PCW12
0.1U_0402_25V6

0_0402_5%

BOOT1_+1.35VS_VGAP_R
4.99K_0402_1%

G2

2
1

<27> VRAM_VDD_CTL 1 2
PCW20

2
2 2 2 2 2

BOOT1_+1.35VS_VGAP
PRW22

SNB1_+1.35VS_VGAP
8

5
REF1 @ @ @

UG1_+1.35VS_VGAP
VID_+1.35VS_VGAP

PSI_+1.35VS_VGAP
2

EN_+1.35VS_VGAP
0.1U_0402_16V7K
LG1_+1.35VS_VGAP

1
REFADJ

@ PCW15
2

1
PRW28
10K_0402_1%
C PRW25 C

2
120K_0402_1%
REFADJ_+1.35VS_VGAP_R 2 REFADJ_+1.35VS_VGAP

2
1

1
EMI@ PCW16
PCW21
2200P_0402_50V7K

1
PUW1 680P_0402_50V7K
1

1
RT8816BGQW_WQFN20_3X3 PCW14
3.3K_0402_1%

2
PRW23

0.22U_0603_25V7K

VID

EN
PSI

BOOT1
UGATE1

2
RBOOT
2

REFADJ_+1.35VS_VGAP 6 20 SW1_+1.35VS_VGAP
REFADJ PHASE1
2

REFIN_+1.35VS_VGAP 7 19 LG1_+1.35VS_VGAP
REFIN_+1.35VS_VGAP REFIN LGATE1 PRW11
2.2_0603_5%
VREF_+1.35VS_VGAP 8 18 PVCC_+1.35VS_VGAP 1 2
VREF PVCC +5VALW
PRW12 PRW13
2200P_0402_50V7K
1

2.2_0402_1% 453K_0402_1%
PRW24
14K_0402_1%

PCW22

TON_+1.35VS_VGAP
1

2 1 2 1 9 17 PCW17
B+_+1.35VS_VGAP TON LGATE2

1
2.2U_0402_6.3V6M
REF2
2

OCSET/SS
RGND 10 16
PCW18 RGND PHASE2
2

2
UGATE2
PGOOD

BOOT2
1TON_+1.35VS_VGAP_R

2
2

VSNS
GND
0_0402_5%
@ PRW14
0.1U_0402_25V6

21

11

1OCset_+1.35VS_VGAP 12

13

14

15
1

1.35VSDGPU_PG
Vsense_+1.35VS_VGAP
B B

www.laptoprepairsecrets.com

PRW17 36.5K_0402_1%
PRW19
100_0402_1%
1 2
+1.35VSDGPU

2
PCW27
@

0.1U_0402_25V6 PRW18
1 2 10K_0402_1%
1 2 +3VS

Rocset for 75.6A

1 2
<30> FB_VDDQ_SENSE
PRW20
@

1.35VSDGPU_PG <27>
0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.5VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 100 of 112
5 4 3 2 1

SKL_H 42
 A B C D E

1 1

@0@ PR1010
0_0402_5%
EN_1VSDGPU 1 2
1VSDGPU_EN <27,37>

1
Current limit = 4.7A(min) PR1008 @ PC1014
0.1U_0402_16V7K

2
PR1009 1M_0402_5%
10K_0402_5% Choke 1uH SH00000YG00 (Common Part)

2
2 1
+3VALW (Size:3.8 x 3.8 x 1.9 mm)
Isat:3.42A
(DCR:20m~25m)
PU1002 Choke: SH00000YG00 Size:4x4x2 (Common Part)
<27> PG_1VSDGPU 9
1 PGND 8
Rdc=27± 20% Taiyo
FB SGND Rdc=20mohm(Typ), 25mohm(Max) Cyntec
@ PJ1001 2
PG EN
7 PL1002 Imax=1.6A, Ipeak=2.23A, Iocp:2.68A Rdc=27± 20% 3L
JUMP_43X79 1UH_2.8A_30%_4X4X2_F Rdc=30± 20% Tai-Tech
1 2 VIN_1.0VSDGPUP 3 6 LX_1.0VSDGPUP 1 2
+3VALW 1 2 IN LX +1.0VSDGPUP Rdc=32± 20% Chilisin
4 5 Rdc=36mohm(Typ), Xmohm(Max) Maglayers

68P_0402_50V8J
PGND NC

1
Rup

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
PC1013 EMI@

PC1012

1
SY8003ADFC_DFN8_2X2 PR1007 PR1011

PC1009

PC1010

@ PC1011
22U_0603_6.3V6M 4.7_0603_5% 13.7K_0402_1%
2

2
2

2
FB_1.0VSDGPUP

1
2 EMI@ Rdown 2

1
FB=0.6V PC1008
Note:Iload(max)=3A 680P_0402_50V7K PR1012
20K_0402_1%

2
VFB=0.6V @ PJ1003

2
JUMP_43X79
Vout=0.6V* (1+Rup/Rdown) 1 2
+1.0VSDGPUP 1 2 +1.0VSDGPU
=0.6V* (1+13.7/20)
Vout=1.011V

www.laptoprepairsecrets.com
3 3

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
1.05VSDGPU
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FXXXX M/B LA-J871P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 102 of 112
A B C D E
 5 4 3 2 1

Version change list Page 1 of 1

(P.I.R. List) for PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
PUZ1 change from ncp81215m_SA0000AQE00 to ncp81215p_SA0000CTW00 1202 DVT
01 NA for cost down
PCZ24, PCZ27 change from 82P_0402_SE000014700 to 82p_0402_SE071820J80
PCB17 change from 2.2u_0603_25V_SE00000WP00 to 2.2u_0603_16V_SE000006S80
D PCB20 & PCB21 change from 100p_0603_SE024101J80 to 100p_0402_SE071101J80 D

PCM6 change from 10u_0603_SE000005T80 to 22u_0603_SE00000M000

PCM7 10u_0603_SE000005T80 change to unpop
PRB12 change form 10_1206_SD011100A80 to 10_0805_SD002100A80
avoid incomplete P85 PQB1 & PQB11 change from 2n7002_SB000009Q80 to 2n7002_SB00001GE00 1202 DVT
02 NA replacement
03 NA sourcer request P84 PQ201 change from BSS139_SB00001GD00 to BSS138_SB00000PF00 1202 DVT
04 NA NA P85 Add PRB37 & PRB38 & PRB39 0_0402_SD028000080. avoid chager B2B damage 1209 DVT
05 NA for acoustic noise P97 Co-lay PCV362~PCV369 10u_0603_SE00000X210 for acoustic noise. 1209 DVT
06 NA for acoustic noise P100 Co-lay PCW24~PCW26 10u_0603_SE00000X210 for acoustic noise. 1209 DVT
07 NA CPU transient P91 PRZ49 change from 274k_0402_SD034274380 to 165k_0402_SD034165380 1212 DVT
PRZ14 change from 28k_0402_SD034280280 to 29.4k_0402_SD034294280
08 NA CPU transient P95 PCZ101 330u_D2_SGA00009S00 change to unpop for CFL 1212 DVT
PCZ102 & PCZ103 330u_D2_SGA00009S00 change to SMT for CFL
PCZ108, PCZ109, PCZ110, PCZ112, PCZ119, PCZ125, PCZ133, PCZ137 change to SMT for CFL
C C
PCZ163, PCZ164, PCZ165, PCZ166, PCZ167, PCZ168 1u_0201_SE00000UC00 change to SMT for CFL
PCZ107, PCZ113, PCZ114, PCZ115, PCZ116, PCZ121, PCZ123, PCZ127, PCZ128, PCZ130, PCZ131, PCZ132,
PCZ172, PCZ173, PCZ174 change to unpop for CFL
PCZ104, PCZ105, PCZ107, PCZ111, PCZ113, PCZ114, PCZ115, PCZ116, PCZ118, PCZ120, PCZ121, PCZ123,
PCZ124, PCZ126, PCZ127, PCZ128, PCZ130, PCZ131, PCZ132, PCZ134, PCZ135, PCZ136, PCZ138, PCZ172,
PCZ173, PCZ174 22u_0603_SE00000M000 change to unpop for CML
09 NA for efficiency P100 PRW13 change from 383k_SD034383380 to 453k_SD034453380 1212 DVT
10 NA for DFB issue P85 PRB3 footprint change from R_1206_4P to R_1206_4P-D 0114 PVT
11
12
NA
NA
NA
NA
P100
P84 www.laptoprepairsecrets.com
reserve PCW28 & PCW29 330_D1_SGA00009S00
PH204 SL200002H00 change to SMT
PH203 SL200002H00 change to unpop
0114
0114
PVT
PVT

13 NA NA PR217,PRB22,PRB25,PRV50,PRV51,PRW9 change from 0_0402 to R-short 0114 PVT

14 NA for DFB issue P85 PRB19 footprint change from R_1206_4P to R_1206_4P-D 0116 PVT

B B

A A

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FXXXX M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 110 of 112
5 4 3 2 1
 5 4 3 2 1

Version change list Page 1 of 1

(P.I.R. List) for PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase

change PR1009 from 100K_0402_5% (SD028100380) to 10K_0402_5% (SD028100280)

change PG pull high from +3VS to +3VALW
D
change PRW1 from 20K_0402_1% (SD034200280) to 1K_0402_1% (SD034100180) D
01 Design Update For EA Turning and HW 93, 94 Change the PCW27 from pop to un-pop, and . PCW27.2 net name change from +1.35VSDGPU to Vsense_+1.35VS_VGAP.
sequence 95, 97 unpop PCV135
89, 92 Change the PUV8, PCV9 from pop to un-pop. 11/14 A
Add location PRV51 0_0402_5% (SD028000080), and pop.
Change the PCW21, PCW22 From 4700P_0402_50V (SE074472K80) to 2200P_0402_50V(SE074222K80).
Delete PL1111 (HCB2012KF-121T50_0805)

Change the PQB2,PQM2 from AON7506 (SB000010A00) to EMB12N03V (SB00001HV00)

83, 85 update location PRG5 PRA3 to PUG1 PUA1
02 Design Update solution change 90, 91 PLZ1,PLG1,PLZ2,PLZ3,PLZ4 change to common part P/N (SH00001EE00) 11/16 A
pop PQZ2, PQZ4 unpop PQZ1, PQZ3

83, 85 Change PRM10, PRM8, PRV82, PRV85, PRV92, PRV95, PRV79, PRV81, PRV84, PRV89, PRV91, PRV94, PRV54, PRV56, PRV70, PRV145,
03 Design Update 0 ohm to R-short 90, 91 PRV146, PRZ72, PRZ73, PRZ25, PRZ30, PRZ32, PRZ18, PRZ9, PRZ11, PRZ24, PRZ27,PRV20, PRV34 11/16 A

change PRZ12 from 1.78K_0402_1%(SD00000WY80) to 1.62K_0402_1%(SD000003380)

change PRZ14 from 31.6K_0402_1%(SD034316280) to 28K_0402_1%(SD034280280)
change PCZ24 from 470P_0402_50V8J(SE071471J80) to 220P_0402_50V8J(SE082221J80)
change PRZ51 from 84.5K_0603_1%(SD014845280) to 100K_0603_1%(SD014100380)
C
04 Design Update For CPU transient 89, 92 PRZ61=110k ohm @H82, PRZ61=102k ohm @H62 C

PRZ35=25.5k ohm @H82, PRZ35=28k ohm @H62 11/19 A

unpop PCZ101, PCZ103, PCG102
pop PCZ176
un pop PCZ120, PCZ104, PCZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124 for H82
un pop PCZ120, PCZ104, CZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124, PCZ123, PCZ127, PCZ107, PCZ113, PCZ116, PCZ114 for H62

Change the PL501 1.5uH to common part

05 Design Update solution change 84 Change the PCZ47, PCZ48, PCZ65, PCV36, PCV249 from 33U_25V_NC_6.3X4.5 (SF000007200) to 33U_25V_M (SF000007700) 12/3 A

06 Design Update solution change 87

www.laptoprepairsecrets.com
Chnage the PRZ43 from 12.1K_0402_1% (SD034121280) to 12K_0402_1% (SD034120280)

unpop PC1811 0.47U_0402_6.3V6K (SE124474K80) 12/12 B

pop PCV149~PCV158, PCV162~PCV165, PCV258 (1U_0201_6.3V6M) 12/18 B

07 Design Update solution change 83, 97 reserve PDB2 for dead battery
12/18 B
08 Design Update solution change 87, Change PR1010, PRW9, PR1801, PR2501 from 0ohm to r-short
93, 94
B B

09 Design Update For ESD request 82 Pop PC205 0.1U_0603_25V7K (SE042104K80) HS 附附附附附附附 ,附 附 能能能能
E SD 附附附 HS小小小HS cable 1/15 B
c o u p l i n g 到到小到到 fail

10 Design Update For EMI request 93, 96 Pop PCW1, PCV48 2200P_0402_50V7K (SE074222K80) for EMI request 1/15 B
Pop PCW2, PCV47 0.1U_0402_25V6 (SE00000G880) for EMI request

11 Design Update Design change 90, 87 delete boost circuit and PCZ47 5/7 FH58F EVT

12 Design Update Design change 90, 87 delete PC1112 5/7 FH58F EVT

change PCB15 from S CER CAP 1U 6.3V K X5R 0402(SE000000K80) to 1U 16V K X5R 0402(SE00000OU00)
13 Design Update Design change change PCB16 from S CER CAP 1U 6.3V K X5R 0402(SE000000K80) to S CER CAP 2.2U 16V K X5R 0402(SE000013780) 6/25 INV2
88, 93
Add PLV2, PLV3 second source S COIL .22UH TMPC1004H-R22MG-R5505-D 50A(SH00001XH00)

14 Design Update change CH_OC to 75A 95 change PRV71 from S RES 1/16W 133K +-1% 0402(SD034133380) to S RES 1/16W 113K +-1% 0402(SD034113380) 6/25 FH58F PVT

A A

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FXXXX M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 111 of 112
5 4 3 2 1
 A B C D E

Version change list (P.I.R. List) Page 1 of 2 for HW

Item Page Title Date Issue Description Solution Description Phase Rev.
1 52 CNVi 1205B CNVi-Intel review (FH5VF) Add RM67 / RM68 0-ohm
Add PU RM70 / PD RM69 (Reserve)
2 52 UART_BT 1205B UART_BT review RM66 Change to @ for Vender review
3 81-111 PWR SCH 1206A POWER update Combined Power SCH (1204)
4 40 HDMI 1206B HDMI EMI solution Remove RY52/RY53/CY27 , LS15 change to pop (EMI@) .
5 17/69 JSSD3 1206B JSSD3 SATA/PCIE detect SATAGP change to GP4 & RH303 PU
1 1
6 64 EMR 1206B EMR Power source RH285/RH286/RH292 power source change to +3VALW
7 63 Touch Pad 1206B ESD Add CK203(100p) for ESD
8 27 VGA 1206C CLKREQ RV83 change to pop(VGA@) / CV226 change to unpop (@)
9 19 PROJECT ID 1206C PROJECT ID defined as Project - 50 ( ID1:H / ID0:L )
10 38 Panel OD 1206C Panel OD function RX11 change to unpop & BIOS needs to detect panel to select H or L .
11 16/58 BT_ON 1206C BT_ON change to PCH RH304 pop (PCH) & RB85 unpop (EC)
12 73 IO_B conn. 1209A IO_B conn. IO_B change pin define
13 15/68/69 M.2 SSD 1209B Fixed naming > SSD1 - GPP_B9/CLKREQ4# (PCIE only) (2018 @SSD2)
> SSD2 - GPP_B8/CLKREQ3# (PCIE/SATA) (2018 @SSD1)
> SSD3 - GPP_B10/CLKREQ5# (PCIE/SATA) (2019 NEW)
14 52 CNVi 1209B CNVi-Intel review (FH5VF) RM70 change power source to +3VS_WLAN
15 81-111 PWR SCH 1209C POWER update Combined Power SCH (1209)
16 81-111 PWR SCH 1210A POWER update Combined Power SCH (1209B)
17 77 H6 1210B For Layout H6 change to GNDA for Layout .
18 69 SSD3 1210B BOM Config ADD "SSD3@" for BOM
19 58 Board ID 1210B Board ID config ADD DVT@ & DVTRGB@ for DVT BOM
20 52 CNVi 1210C CNVi-Intel review (FH51M) > RM69 change to 71.5k & CNVI@
> RM70 set CNVI@
> RH22 change to 20K
2 > RM36/RM37/RM67/RM68 change to 22 ohm 2

21 63 ESD 1211B > Pop CK203 680p & ESD@

> CB12/CB13 change to 33p for ESD & ESD@
PVT Rev 1.0
22 63 SW 0114A BTN SW1 set EVT@
23 58 0114A Action plan CB6/CB9 100P 0402 Change to SE00000SE00 (0201)
24 15 0114A Action plan CH7/CH8 10P 0402 Change to SE173100J80 (0201)
25 0114A Action plan RO25 Change to 0201 R-short
26 0114A Action plan RH100 Change to 0603 R-short
27
28

29
30
52

81-111
63
CNVi

PWR SCH
0114A
0114A

0114B
0115B
Action plan
CNVi-Intel review (FH5VF)

POWER update
Action plan
www.laptoprepairsecrets.com
RS112/RS137/RA9/RB87/RX8/RX9 Change to 0402 R-short
Add CM51/CM52 10U
Add CM53/CM54 0.01U
Combined Power SCH (0114B)
R41 Change to 0603 R-short
R18 Change to 0201 R-short
*remove KBLED@
31 81-111 PWR SCH 0116A POWER update Combined Power SCH (0116)
32 6 CPU/PCH 0211A Update CPU/PCH PN & config
33 62 LED 0211A RG4/RG11 change to 1k
34 58 Board ID 0211A Board ID config ADD PVT@ & PVTRGB@ for PVT BOM
3 3

4 4

Security Classification
2019/09/20
Compal Secret Data
2020/09/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW1
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FH51M M/B LA-J871P

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 11, 2020 Sheet 112 of 112
A B C D E