1

Fault Models of Inverter-Interfaced Distributed

Generators: Experimental Verification and
Application to Fault Analysis
Cornelis A. Plet, Student Member, IEEE, Maria Brucoli, John D.F. McDonald and Timothy C. Green, Senior
Member, IEEE

Abstract—This paper investigates the fault behaviour of for use in loadflow based methods. This approach is not
inverter-interfaced distributed generators in stand-alone net- analytically rigorous and ignores the effect of the control
works. It is shown that the rapid transient response of the inverter system. The analysis presented in [10] does not provide an
control system allows its fault behaviour to be characterised by
quasi steady-state equivalent fault models. The choice of inverter efficient method or insight into inverter fault response as it
control strategy, control reference frame and the method of active relies on the numerical solution of a state-space representa-
current limiting dominate the fault response, especially in case tion of the complete system including inverters. In [11] the
of unbalanced faults. The proposed fault models can be directly test results of subjecting commercially available inverters to
incorporated in conventional fault analysis methods of which an faults are presented, without providing details on the inverter
example is given for a faulty islanded microgrid. Model validation
is carried out by comparing experimental measurements with control system. Analytical fault models based on a popular
results of analytical fault analysis using the developed fault grid-connected inverter control strategy are presented in [19]
models and PSCAD time domain simulations. together with their application in loadflow based fault studies
Index Terms—inverter, fault response, island, fault model, including an experimental validation. The presented models
distributed generation do, however, not apply to islanded or stand-alone operation.
To date, there are no reported studies on the fault behaviour
I. I NTRODUCTION of islanded IIDG sources. This paper aims to develop analyti-
cal models that characterise islanded IIDG sources under fault

T HE integration of DG into the utility grid faces a number

of technical issues such as their impact on feeder voltage
profiles and the distribution network existing protection sys-
conditions. The paper is organized as follows. In Section 2 the
control of inverters operating in islanded-mode is described.
Two different inverter fault models are developed and their
tem. In contrast to conventional generators, no tried-and-tested characteristics described in Section 3. An islanded microgrid
analytical fault models exist for inverters, forcing protection supplied by an IIDG unit has been modelled in PSCAD
engineers to employ complex and time consuming full time and recreated in an experimental setup to back the proposed
domain models of the inverter and its control systems [3], models and illustrate their application. Section 4 illustrates
[4]. The fault response of an inverter is dominated by its the application of the fault models to fault analysis and then
control system which actively limits the available fault current compares the analytical results with the experimental and time-
to safeguard the semiconductor switches [5], [6]. This limit domain simulation results.
can be increased by over-engineering the inverter hardware
and is typically set at twice the nominal current rating [5].
If a substantial amount of conventional generation is replaced II. S TAND ALONE INVERTER CONTROL
by IIDG, or indeed if the IIDG is the only power source as The presence of DG can provide a supply to customers in
in the case of an islanded network, the resulting low fault a network where the utility connection is unavailable due to
level can interfere with the proper operation of the incumbent unplanned or planned islanding [12]. A typical IIDG unit and
over-current based protection system [7], [8], [9]. its control structure for islanded-mode operation is shown in
To facilitate the anticipated rise in DG connections, it is figure 1. The primary source produces DC power which is
imperative to develop and test inverter fault models that can stored in the DC bus and then converted to AC power by
be used in conventional fault analysis techniques yet reflect the inverter. For the purpose of analyzing the inverter fault
the inverter’s control strategy and current limiting method. response, the primary source is considered as ideal and the
In [4] an attempt is made by considering a grid-connected DC bus dynamics are neglected [10], [4].
IIDG. An approximated model based on observation of the The control of a single inverter operating in islanded mode is
inverter’s response during simulations in EMTP is developed focused on regulating output voltage magnitude and frequency.
The multi-loop control structure in figure 1 is popular be-
This research was supported by funding from the Engineering and Physical cause it provides good dynamic performance and disturbance
Sciences Research Council as part of the Supergen FlexNet consortium. rejection and the presence of an explicit current reference
C.A. Plet ([email protected]), M.Brucoli, J.D.F.McDonald and
T.C. Green are with the Department of Electronic and Electrical Engineering, facilitates inclusion of a current limit [12]. The inverter is
Imperial College, London, SW7 2AZ, UK interfaced to the network through a low pass filter (Lf and
978-1-4577-1002-5/11/$26.00 ©2011 IEEE

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 2

iL Lf io Lc

v o* + + i L* iL* ,sat + vi*

Gv(s) Gc(s) vi Cf vo vg
- + -

F
iL
io
vo

Figure 1: Multi-loop control of a stand-alone inverter.

Cf ) and a coupling inductance (Lcc ). The inner loop regulates can then be adapted to the two control schemes under study
the inductor current iL and is usually designed to have a (SynRF and NatRF) to yield specific fault models.
high bandwidth (e.g. here around 1.6kHz). The outer loop
regulates the output voltage vo across the filter capacitor by A. Multi-loop controlled inverter during a network fault
setting a current demand for the inner loop and is designed
with a slower bandwidth (e.g. 400Hz). Blocks Gv (s) and It is common practice to summarise the control strategy
Gc (s) contain the transfer functions of the voltage and current by expressing the relation between the output voltage vo , the
regulators and F is a feed-forward transfer function chosen reference vo∗ and the load current io . The relationship can be
to attenuate output current disturbances. In case of a single expressed in the complex frequency domain by replacing the
inverter, it is sufficient to hold the output voltage reference current control loop in figure 1 with its closed-loop transfer
vo∗ constant (in magnitude and frequency). For a system with function Gcc (s) [12]:
multiple inverters, frequency and voltage droops might be Vo (s) = G(s)Vo∗ (s) − Zo (s)Io (s) (1)
applied for power sharing [14].
The multi-loop control structure in figure 1 can be im- where
Gv (s)Gcc (s)
plemented in various reference frames. A popular choice of G(s) = (2)
reference frame [12], [14], is the Synchronous Reference sCf − Gv (s)Gcc (s)
Frame (SynRF or dq0 coordinates). The new variables result is the inverter voltage gain and
from the Clarke and Park transformation of the original phase
F Gcc (s) − 1
variables. If only the Clarke transformation is applied [15], Zo (s) = − (3)
then the control is implemented in the Stationary Reference sCf + Gv (s)Gcc (s)
Frame (StatRF or αβ0 coordinates). If no transformation is is the output impedance. The inverter is therefore modelled as
involved, the control is implemented in the Natural Reference an equivalent two-terminal circuit as shown in figure 2a. A
Frame (NatRF or abc coordinates), as described in [16]. The design objective for Gv (s) would be to make G(s) close to
control in the SynRF is popular because the DC signals unity in the low frequency range.
resulting from the Park transformation can be regulated to Under fault conditions, the current limit of the inverter will
zero steady-state error by PI compensators. However, with the be applied using a saturation function on the inductor current
advent of P+R (proportional + resonant) compensators, the reference i∗L , as shown in figure 1. In the event of a fault, the
use of the NatRF has been gaining popularity for control of current in the network increases and as saturation is reached,
islanded inverters [17], grid-connected inverters [18], [19] and the voltage feedback loop is broken. This break in the loop
in particular where there is a need for good synchronization reduces the two-loop control of the inverter to a single current
during unbalanced operation [20]. As a result, in this paper, loop control. The output voltage is then determined by the
control in both reference frames is considered and analyzed current injected into the filter capacitor and the following
for four-leg three-phase inverters. This is necessary if single relationship applies:
phase loads are to be supplied. The fourth leg also provides a   1
∗
return path for any fault current. How to orderly resume power Vo (s) = Gcc (s)IL,sat − Io (s) (4)
sCf
export once a fault has been cleared is considered out of scope.
All calculations have been performed in actual values rather where i∗L,sat is the reference maximum inductor current.
than in per unit as the paper considers a network with only Rearranging (4):
one voltage level. ∗
Io (s) = Gcc (s)IL,sat − sCf Vo (s) (5)
III. I NVERTER FAULT M ODELS At the operating frequency, the transfer function Gcc (s) has a
An understanding of inverter fault behaviour can be de- gain close to unity and so the inverter behaves like a constant
veloped by starting with the equivalent model of the multi- current source with a parallel impedance as shown in figure
loop inverter control in figure 1 and then by analyzing how 2b. There will also be an initial transient resulting from the
it changes in the event of a fault. This general fault model dynamics of the current control loop. However, because of the

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 3

3a. The values of the current sources can be calculated from

Io Io ∗ ∗
Zo (s) IL,sat,d and IL,sat,q as follows:
∗
 ∗
IL,sat,a = 2/3IL,sat,dq ejφdq
G(s) ˜Vo* Vo Gcc(s)˜ IL*,sat Cf Vo ∗
IL,sat,b = α2 IL,sat,a
∗
(8)
∗ ∗
IL,sat,c = αIL,sat,a
√
(a) with multi-loop control (b) with current limiting where α = −0.5 + j0.5 3 is the Fortescue∗ operator,
∗ ∗2 ∗2 I
IL,sat,dq = IL,sat.d + IL,sat,q , φdq = arctan IL,sat,q
∗ and
Figure 2: Equivalent two-terminal circuit of a stand-alone ∗
L,sat,d

inverter IL,sat,0 = 0A.

C. Fault model of an inverter controlled in the NatRF

high bandwidth of this loop, the settling time of this transient Control of an islanded inverter in the NatRF again requires
can be assumed near-instantaneous. The general model shown three multi-loop controllers [16], one for each phase coordi-
in figure 2b, must now be adapted to the particular response nate. The key differences between control in the NatRF and in
of the inverter controllers according to the employed reference the SynRF are the ability of the NatRF controller to regulate
frame and the type of fault. the voltage of each phase independently and the possibility to
limit the inductor phase currents separately. Latching current
B. Fault model of an inverter controlled in the SynRF limits are used which apply a sinusoidal reference current
The control of an islanded inverter using dq0-coordinates of amplitude equal to the maximum inverter current to the
requires three loops identical to the one in figure 1, one for phases that experienced an over-current until the fault clears.
each coordinate [12]. The saturation blocks are placed in the The healthy phases continue to operate in voltage control
each of the three current loops to limit ILd ∗ ∗
, ILq and IL0∗
. mode. As a consequence, the equivalent fault model of the
The current limits latch and hold the current to a limited inverter depends on the type of fault. For example, for a
∗
value (i.e. IL,sat,d ∗
,IL,sat,q ∗
and IL,sat,0 ) until the fault clears. single phase-to-ground (A-G) fault on phase a, only phase
Without such a provision, the saturation would be applied to a is current limited and the equivalent circuit of figure 2b
the instantaneous values which can lead to harmonic distortion applies while phases b and c are voltage controlled and the
(clipping). From figure 1 and applying the current saturation, Thevenin equivalent circuit of figure 2a applies. The resulting
(4) can be written for each coordinate as: equivalent fault model of the inverter in phase coordinates is
shown in figure 3b. In the circuit corresponding to phase a,
  1 ∗ ∗
∗
vod = Gcc (s)IL,sat,d − Iod + ωCf voq the current source is given by Gcc (s)IL,sat,a , where IL,sat,a
sCf is the maximum inverter current and the parallel impedance
 ∗
 1 Zc,a (s) is equal to ZCf (s) = sC1 f . The closed loop transfer
voq = Gcc (s)IL,sat,q − Ioq + ωCf vod (6)
sCf function of the current loop can be expressed as:
 ∗
 1
vo0 = Gcc (s)IL,sat,0 − Io0 Gc (s)N (s)
sCf Gcc (s) = (9)
1 + Gc (s)N (s)
It is apparent that during a fault the inverter becomes equiv-
where N (s) is the LC filter transfer function, as explained in
alent to a balanced, three-phase, positive sequence current
Appendix A, and defined as follows:
source parallel to the filter capacitor, the equivalent single-
In the circuits corresponding to phases b and c in figure 3b,
line diagram of which is shown in figure 2b. The appearance
the voltage sources are given by G(s)V0∗b and G(s)V0∗c where
of the coupling terms stems from the application of the ∗ ∗
G(s) is the inverter voltage gain and V0b and V0c are the
Park transformation to the capacitor voltages and represent
nominal reference phase voltage values. The inverter voltage
the capacitor’s conductance at the grid frequency. Assuming
gain is calculated as in (2) and the series connected output
the closed current loop transfer function has a unity gain at
impedances are given by:
the system operating frequency and deals with the capacitive
coupling, the inverter fault model in abc-coordinates can be F GCC (s) − 1
Z0b(s) = Z0c(s) = Z0 (s) = − (11)
found by applying inverse Park and Clarke transformations to sCf + GV (s)GCC (s)
(6): In order to use the same form of model for each phase, the
 ∗  1 Thevenin models of the healthy phases can be transformed to
voa = IL,sat,a − Ioa
sCf their Norton equivalents as shown in figure 3c. The Norton
 ∗  1 equivalent source current is given by:
vob = IL,sat,b − Iob (7)
sCf G(s) ∗
 ∗  1 IN orton (s) = V (12)
voc = IL,sat,c − Ioc Zo (s) o
sCf The models in figure 3a and figure 3c refer to different control
The three-phase, positive sequence equivalent current source methods but are presented in the same form. This common rep-
with parallel filter capacitor described by (7) is shown in figure resentation helps in understanding the different fault response

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 4

IL (s) s (Lf + 2Ln ) + Rf + 2Rn

N (s) = =   (10)
vi (s) − vo (s) s Lf + 3Lf Ln + s (2Rf Lf + 3Rf Ln + 3Rn Lf ) + Rf2 + 3Rf Rn
2 2

Ioa Ioa Ioa

I L* , sat , a Cf Voa I L* , sat , a Cf Voa I L* , sat , a Cf Voa

Iob Iob Iob

Zob(s)

G( s) ˜ Vob*

Zob (s)
I L* ,sat ,b Cf Vob G(s) ˜Vob* Vob Vob
Z ob ( s)

Ioc Ioc Ioc

Zoc (s)

G(s) ˜ Voc*

Zoc (s)
I L* , sat ,c Cf Voc G(s) ˜Voc* Voc Voc
Zoc (s)

(a) Model for any type of fault (b) Model for a single phase fault (c) Model for a single phase fault
with control in SynRF with control in NatRF with control in NatRF (Norton
equivalent)

Figure 3: Equivalent phase networks of a three-phase inverter

given by the two control methods. In particular, it should be 1 4

P 7 10
Zcc Zline Zline
noted that in figure 3a the impedances are physical but in a
2 5 8 11
Zcc Zline Zline
figure 3c two impedances are equivalent output impedances b
3 6 9 12
determined by the control of the inverters. Moreover, the c
Zcc Zline Zline

amplitude and transfer functions of the current sources also

Zfault

Zfault

Zfault
differ.

Zload

Zload

Zload
Zib

Zia
Zic

IV. S IMULATION AND E XPERIMENTAL R ESULTS n 0 0 0

To validate the models developed in the previous section, an
experimental set-up has been created in which a single 3kV A Figure 4: Test network
inverter feeds a single 1.7kW load through a 300Vrms,l−l
distribution line. At t = 0s a fault is applied in the middle
of the line. A per-phase representation of the test network is symmetrical components is difficult to apply in the case of an
illustrated in figure 4 showing the inverter parallel impedances inverter under NatRF control facing an asymmetric fault. In
Zc , the coupling impedances Zcc , the line impedances Zline , this case, the inverter presents unbalanced phase impedances,
the fault impedances Zf ault , and the load impedances Zload . while the use of symmetrical components is normally based on
The inverter AC front end is connected to the terminals a single point of unbalance, being the fault itself. Nevertheless,
labelled a, b, c and n. Due to practical restrictions, there is no the behaviour of the two example microgrid models in the
impedance in the neutral return path. The fault impedances event of a fault can still be assessed using circuit analysis
are connected between nodes 7,8,9 and 0, and can be ar- if an equivalent direct phase coordinate representation of the
ranged so as to recreate any type of fault. The inverter is network is constructed as shown in figure 4. This circuit
controlled using the T RIPHASE rapid prototyping software can be represented by an equivalent bus impedance matrix
suite [22] which allows M ATLAB S IMULINK control programs ZBU S based on an explicit representation of every node in
to be run on a real-time Linux PC as inverter controller. the network. After ZBU S is determined, the system behaviour
Current and voltage measurements are downloaded back into is described by the relationship:
M ATLAB for immediate plotting and analysis. The parameters
V = ZBU S I (13)
of the test network components have been given in table
I. The quasi steady-state fault models will now be used to where V are the node voltages referred to the reference
quantify the fault currents and voltages for comparison with node and I are the currents entering the nodes from the
the experimental results. Traditional fault analysis based on current sources. Voltages and currents are expressed in phase

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 5

Table I: Test Network Parameters of (3). It is thus a virtual impedance which depends
Symbol Value Unit on physical impedances as well as control system
parameters:
Lf 2.3 mH
Rf 0.01 Ω F Gcc (s) − 1
Cf 26.4 μF Zi,healthy (s) = Zo (s) = −
ESR 0.05 Ω sCf + Gv (s)Gcc (s)
Ln 1.15 mH 3) Construct the bus impedance matrix ZBUSfault corre-
Rn 0.01 Ω
Lcc 0.93 mH sponding to the faulty microgrid.
Rcc 0.01 Ω 4) Determine the current vector representing the currents
Lline 0.35 mH injected into each node of the test network. Only nodes
Rline 0.2 Ω
Rload 52.9 Ω connected to the inverter will have non-zero values:
Rf 2 Ω a) If the inverter is controlled in the SynRF, then for
∗
IL,sat,dq 15 + j0 A any type of fault the inductor currents are given by
|vo∗ | 300 Vrms,l−l (8) and the current vector I is given by
∗ ∗ ∗ T
Table II: Inverter controller realisations I= IL,sat,a IL,sat,b IL,sat,c 0 ... 0

SynRF Gv (s) Gc (s) F

b) If the inverter is controlled in the NatRF, then the
   
inductor currents in the faulty phase are given by
d&q 0.05 1 + 1000
s
23 1 + 1600
s
0.7 the corresponding inductor phase current in (8):
s
 1600
 
0 0.05 + 200 s2 +ω 30 1 + 0.7 ∗ 2/3I ∗
aulty = α
2 n jφdq
s s IL,f L,sat,dq e
NatRF Gv (s) Gc (s) F
where n = 3, 2, 1 for phases a, b and c, respec-
a,b & c 0.12 17 1 tively. The healthy phases maintain voltage control
and are replaced with their Norton equivalent cir-
cuits as shown in figure 3c. The Norton equivalent
quantities because the bus impedance matrix is built by source current is given by (12):
considering each single node in the network. In the event
of a fault, the original ZBU S of (13) can be replaced by G(s) ∗
IN orton (s) = V
ZBU Sf ault which incorporates the modifications introduced by Zo (s) o
the fault impedance and the appropriate inverter parallel output and the current vector I for e.g. a single phase to
impedances. The node voltages can be determined by applying ground fault (A-G) is given by:
the injected currents corresponding to the models in figures 3a ∗
T
and 3c. The fault analysis using (13) is completely general and I= IL,sat,a G(s)
V∗
Zob (s) ba
G(s)
V∗
Zoc (s) oc
0 ... 0
can be extended to multiple inverters. The analytical process 5) Compute V = ZBU S I to find the nodal voltages. Line
to find the fault currents and voltage in the microgrid consists currents can be obtained from the nodal voltages and
of the following steps: line impedances.
1) Include fault impedances in the network of figure 4 to In the same manner, inductor currents and output voltages
represent the desired type of fault. A three phase to have been calculated for inverters under both SynRF and
ground fault is shown. NatRF control for no fault, three phase, single phase, and
2) Based on the quasi steady state models developed in this phase-phase faults. The results have been shown in table III.
paper choose the right value for the parallel impedances The fault response of an inverter operating in islanded-mode
Zia , Zib and Zic : is almost instantaneous. Indeed, the only dynamic process
a) If the inverter is controlled in the SynRF, then the involved is that of the current loop which is designed with
parallel impedances are physical and equal to the a high bandwidth. It is therefore possible to represent the
filter capacitor impedance: islanded inverter, in the event of a fault, with quasi stead-state
Zia (s) = Zib (s) = Zic (s) models like the ones in figure 2. The models are considered
 valid until the fault clears or until the inverter is disconnected
1
= ZCf (s) = ESR + Ω because the fault has not cleared within an expected time.
jωs Cf Focusing now only on the islanded microgrid, the results of
b) If the inverter is controlled in the NatRF, then only two experiments are presented: in the first one the inverter
the faulty phase will go into current limiting mode is controlled in the SynRF, in the second one the NatRF
and the healthy phases remain in voltage control control is used. Each plot in figure 5 shows the measured
mode. For the faulty phases, the parallel impedance output voltage (top) and inductor current (bottom) as thick
is again given by the filter capacitor impedance: solid sinusoidal lines. The analytical results from table III
have been plotted as thin black dotted horizontal lines for
Zi,f aulty (s) = ZCf (s)
direct comparison with the peak values of the experimental
and for the healthy phases the parallel impedance is measurements. The envelope created by these analytical results
given by the Norton equivalent output impedance has been plotted as a thick horizontal black line. Results

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 6

NatRF
no fault 3φ − g 1φ − g φ−φ
IˆLa [A] 5.0∠23.4 ◦
12.2∠ − 3.8 ◦
12.2∠ − 3.8 ◦
12.2∠ − 3.8◦
IˆLb [A] 5.0∠ − 96.6◦ 12.2∠ − 123.8◦ 5.0∠ − 101.2◦ 12.2∠ − 123.8◦
IˆLc [A] 5.0∠143.4◦ 12.2∠116.2◦ 5.0∠138.8◦ 5.0∠138.8◦
◦ ◦ ◦
v̂oa [V ] 244.9∠0 26.6∠5.8 26.6∠5.8 290.0∠ − 85.2◦
v̂ob [V ] 244.9∠ − 120◦ 26.6∠ − 114.2◦ 245.2∠ − 124.6◦ 309.6∠ − 89.1◦
v̂oc [V ] 244.9∠120◦ 26.6∠125.8◦ 245.2∠115.4◦ 245.2∠115.4◦
SynRF

IˆLa [A] 5.0∠23.4◦ 12.2∠ − 3.8◦ 12.2∠ − 3.8◦ 12.2∠ − 3.8◦

IˆLb [A] 5.0∠ − 96.6◦ 12.2∠ − 123.8◦ 12.2∠ − 123.8◦ 12.2∠ − 123.8◦
IˆLc [A] 5.0∠143.4◦ 12.2∠116.2◦ 12.2∠116.2◦ 12.2∠116.2◦
v̂oa [V ] 244.9∠0◦ 26.6∠5.8◦ 26.6∠5.8◦ 290.0∠ − 85.2◦
v̂ob [V ] 244.9∠ − 120◦ 26.6∠ − 114.2◦ 597.3∠ − 147.2◦ 307.6∠ − 89.1◦
◦ ◦ ◦
v̂oc [V ] 244.9∠120 26.6∠125.8 597.3∠92.8 597.3∠92.8◦

Table III: Fault currents and voltages

from time domain simulations in PSCAD have been plotted In the event of a fault, the supply of power is kept unchanged
underneath the measured variables where appropriate, as thin in the healthy phases while the current is only actively limited
grey solid lines to show where the experimental measurements in the faulty phases. This behaviour could be particularly
deviate from the ideal results. This is only visible when the advantageous when the number of disrupted single-phase
inverter voltage clips due to a limited DC link voltage. customers has to be kept to a minimum. Finally, from figures
Figures 5a, 5c and 5e show the response of the inverter 5b, 5d and 5f it is confirmed that, under control in the NatRF
controlled in the SynRF to a three-phase, single-phase and the transient response of the inverter is again very rapid.
phase-to-phase fault applied at point P in figure 4 at time It can be seen that, except for the case where voltage
t = 0s. Voltages voa , vob and voc represent the phase voltages limiting occurs, the analytical results from table III match the
at the output of the filter while IL,a , IL,b and IL,c are the experimental results from figure 5 very well i.e. the calculated
controlled inductor currents. voltage and current magnitudes agree with the measurements.
It is clear that, following the fault, the inverter quickly This proves that with simple analytical models, fault cur-
establishes a new set of currents and voltages. As the inverter rents and voltages can be calculated for single inverter-fed
attempts to inject balanced set of fault currents, the network microgrids with relative ease. It also provides a case against
voltages are dependent on fault type. The balanced fault current limiting in the dq0-reference frame as it a) can lead to
leads to uniform under-voltage whereas the single phase fault harmonic distortion due to a limited DC-link voltage and b)
produces a large over-voltage on the healthy phases. This can it means the inverter fault current is actively pushed through
lead to a current controller voltage demand which exceeds healthy phases, and therefore through the loads connected to
the maximum available DC-link voltage. This then results in them. This can lead to adverse side effects in load operation.
the clipping observed in figures 5c and 5e. The thin grey lines
indicate the bridge voltage trajectory that the current controller V. C ONCLUSION
was attempting to follow. This clipping introduces harmonic As the number of inverter-interfaced DG sources increases,
distortion and causes the current control loop to be broken, it is important to understand and visualise how these sources
leading to distortion of the inductor current. respond in the event of a fault and how they contribute
Turning now to NatRF control, figures 5b, 5d and 5f show to system fault behaviour. This paper has outlined the de-
the response to a three-phase fault, a single phase fault and a velopment of analytical fault models for inverter-interfaced
phase-phase fault. The response to the three-phase fault is very DG sources that can be integrated into traditional impedance
similar to that for SynRF control because the fault model is models of faulted networks. The focus is placed on capturing
similar (i.e., figure 3a). In contrast, the response to the single and illustrating the inverter control loops and their reference
phase-to-ground fault is very different. Under NatRF control, frame implementation as these are the main factors responsible
the injection of fault current occurs only for the faulted phase for shaping the response of the inverter in the event of a fault.
a, whereas the healthy phases b and c remain uder voltage To validate the developed models, a laboratory scale is-
control and do not experience a voltage rise. landed microgrid has been built and subjected to various types
This ability of the control in NatRF to regulate the voltage of fault. Measurements from the experiments for different
of each phase independently can be considered an advantage. faults are shown to be in good agreement with numerical

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 7

(a) SynRF inverter response to 3φ fault (b) NatRF inverter response to 3φ fault

(c) SynRF inverter response to 1φ − g fault (d) NatRF inverter response to 1φ − g fault

(e) SynRF inverter response to φ − φ fault (f) NatRF inverter response to φ − φ fault

Figure 5: Matlab plots of experimental (thick dark grey solid sinusoidal), analytical (thin black horizontal dotted) & simulation
(thin light grey solid sinusoidal) results

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.
 8

results from the analytical faults studies of the example system. [21] M.J. Newman, D.N. Zmood, and D.G. Holmes, “Stationary frame
The experimental results also highlight the comparatively harmonic reference generation for active filter systems”, IEEE Trans.
Ind. Appl., vol. 38, no. 6, pp. 1591–1599, November 2002.
small fault currents but fast transient response characterising [22] “http://www.triphase.com/”.
inverter-interfaced sources. The difference in fault response
due to choice of reference frame is shown by representing both
cases in a per-phase coordinate representation. It is shown that
current limiting in the synchronously rotating reference frame
can lead to overvoltages and harmonic distortion and is thus
undesirable. Finally, the paper gives an example on how to
include these models in quasi steady-state fault analysis based
on a per-phase coordinate representation of the network.
Cornelis A. Plet (S’09) received the M.Eng. degree
R EFERENCES (first class honours) in electrical & electronic engi-
neering from Imperial College, London, UK in 2007
[1] F. Blaabjerg, C. Zhe, and S. Kjaer, “Power electronics as efficient and is currently working towards a PhD in the Con-
interface in dispersed power generation systems”, IEEE Trans.Power trol & Power Group at Imperial College, London,
Electron., vol. 19, no. 5, pp. 1184–1194, September 2004. UK. He developed an interest for power engineering
[2] M. Prodanovic, K.D. Brabandere, J.V.D. Keybus, T.C. Green, and during work placements with EDF Energy Networks
J. Driesen, “Harmonic and reactive power compensation as ancillary and the Electrical Engineering Department of Shell
services in inverter-based distributed generation”, IET Generation, Global Solutions. His research interests are power
Transmission and Distribution, vol. 1, no. 3, pp. 432–438, May 2007. electronics, network protection, and renewable en-
[3] C6.04.01 Taskforce, “Connection criteria at the distribution network for ergy integration.
distributed generation”, Tech. Rep., CIGRE, February 2007.
[4] M.E. Baran and I. El-Markaby, “Fault analysis on distribution feeders
with distributed generators”, IEEE Trans.Power Syst., vol. 2, no. 4, pp.
945–950, November 2005.
[5] S.R. Wall, “Performance of inverter interfaced distributed generation”,
in IEEE/PES Transmission and Distribution Conference Exposition,
October 2001, vol. 2, pp. 945–950.
[6] “Ieee 929-2000 recommended practice for utility interface of photo-
voltaic systems”, 2000.
[7] M. Brucoli, Fault behaviour and fault detection in islanded inverter-only
microgrids, PhD thesis, Imperial College London, 2008. Maria Brucoli received her Laurea cum summa
[8] B. Lasseter, “Microgrids”, in IEEE Power engineering society winter laude in Electrical Engineering from Politecnico di
meeting, January 2002, vol. 1, pp. 305–308. Bari, Italy in 2004. From 2004 to 2009 she was
[9] H. Nikkhajoei and B. Lasseter, “Microgrid protection”, in IEEE Power with the Department of Electrical and Electronic
engineering society general meeting, June 2007, pp. 1–6. Engineering at Imperial College, London. Here she
[10] R.A.N. Nimpitiwan, G.T. Heydt, and Suryanarayanan, “Fault current received her PhD in 2008 and worked as a research
contribution from synchronous machine and inverter based distributed associate. Her research at Imperial College was
generators”, IEEE Trans. Power Del., vol. 22, no. 1, pp. 634–641, focused on fault response and modelling of inverter-
January 2007. interfaced power sources and microgrids protection.
[11] J. Keller and B. Kroposki, “Understanding fault characteristics of She is currently working as an electrical engineer
inverter-based distributed energy resources”, Tech. Rep. NREL/TP-550- with Arup and her interest is now focused on
46698, National Renewable Energy Laboratory, January 2010. building-integrated renewable generation. She is a member of IEEE and IET
[12] M. Prodanovic and T.C. Green, “High-quality power generation through and a professional engineer in Italy.
distributed control of a power park microgrid”, IEEE Trans. Ind.
Electron., vol. 53, no. 5, pp. 1471–1482, October 2006.
[13] F. Katiraei and M.R. Iravani, “Power management strategies for a
microgrid with multiple generation units”, IEEE Trans. Power Electron.,
vol. 21, no. 4, pp. 1821–1831, November 2006.
[14] N. Pogaku, M. Prodanovic, and T.C. Green, “Modeling, analysis and
testing of autonomous operation of inverter-based microgrids”, IEEE
Trans. Power Electron., vol. 22, no. 2, pp. 613–625, March 2007.
[15] Y. Li, M. Vilathgamuwa, and P.C. Loh, “Microgrid power quality en-
hancement using a three-phase four-wire grid-interfacing compensator”,
IEEE Trans. Ind. Appl., vol. 41, no. 6, pp. 1707–1719, November 2005. Timothy C. Green (M’1989, SM’02) received the
[16] N. Abdel-Rahim and J. Quaicoe, “Three phase voltage source ups B.Sc. degree (first class honours) in electrical en-
inverter with voltage controlled current regulated feedback control gineering from Imperial College, London, U.K., in
scheme”, in International conference on industrial electronics, Control 1986 and the Ph.D. degree in electrical engineering
& Instrumentation, September 1994, vol. 1, pp. 497–502. from Heriot-Watt University, Edinburgh, U.K., in
[17] Y. Li, M. Vilathgamuwa, and P. Loh, “Design, analysis, and real-time 1990. He was a Lecturer at Heriot Watt University
testing of a controller for multibus microgrid system”, IEEE Trans. until 1994 and is now a Professor of electrical power
Power Electron., vol. 19, no. 5, pp. 1195–1204, September 2004. Engineering at Imperial College London, deputy
[18] R. Teodorescu, F. Blaabjerg, M. Liserre, and P. Loh, “Proportional head of Control and Power Group and Deputy head
+ resonant controllers and filters for grid-connected voltage-source of the Department of Electrical and Electronic Engi-
converters”, in IEE Proc. Electric Power Applications, September 2006, neering. His research interests are power electronic
vol. 153, pp. 750–762. and control to enhance power quality and power delivery. Professor Green is
[19] C.A. Plet, M. Graovac, T.C. Green, and R. Iravani, “Fault response a Chartered Engineer in the U.K. and MIEE.
of grid-connected inverter dominated networks”, in Power & Energy
Society General Meeting. IEEE, July 2010.
[20] A.V. Timbus, R. Teodorescu, F. Blaabjerg, M. Liserre, and A.D. Aquila,
“Independent synchronization and control of three phase grid convert-
ers”, in International symposium on power electronics, electrical drives,
automation and motion, March 2006, pp. 1246–1251.

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 12:51:40 UTC from IEEE Xplore. Restrictions apply.