Accelerating FPGA/ASIC Design and
Verification
Tabrez Khan – Senior Application Engineer
Vidya Viswanathan – Application Engineer
© 2015 The MathWorks, Inc.
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Agenda
Challeges with Traditional Implementation workflow
Model-Based Design for Implementation
Generate VHDL® and Verilog® code from MATLAB, Simulink, and
Stateflow®
Optimize the generated RTL design for area and/or speed
Develop system-level test benches in MATLAB and Simulink for RTL
verification with EDA tools
Automate verification with FPGA-in-the-Loop
Summary & next steps
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Traditional Implementation Workflow
Long development cycles
DESIGN
Prevents short iteration cycles
Difficult to optimize the
Algorithm
MATLAB algorithm at a system level
Simulink
Development
Stateflow
Fixed Point Conversion
FPGA Verification
HDL Code Creation
HDL Verification
HDL Refinement
HDL Verification
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Separate Views of DSP Implementation
Algorithm Hardware
Designer Designer
Software
Designer
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Separate Views of DSP Implementation
System Designer FPGA Designer
Algorithm Design System Test Bench RTL Design Verification
Fixed-Point Environment Models IP Interfaces Behavioral Simulation
Timing / Control Logic Analog Models Hardware Architecture Functional Simulation
Architecture Exploration Digital Models Static Timing Analysis
Algorithms / IP Algorithms / IP Timing Simulation
Back Annotation
Implement Design
FPGA Requirements Synthesis
Map
Hardware Specification
Place & Route FPGA Hardware
Test Stimulus
5
Model-Based Design for Implementation
MATLAB® and Simulink®
Algorithm and System Design
Algorithm Design System Test Bench RTL Design Verification
Fixed-Point Environment Models IP Interfaces Behavioral Simulation
Timing / Control Logic Analog Models Hardware Architecture Functional Simulation
Architecture Exploration Digital Models Static Timing Analysis
Algorithms / IP Algorithms / IP Timing Simulation
Back Annotation
Implement Design
FPGA Requirements Synthesis
Map
Hardware Specification
Place & Route FPGA Hardware
Test Stimulus
6
Model-Based Design for Implementation
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
RTL Design Verification
IP Interfaces Behavioral Simulation
Automatic HDL Hardware Architecture Functional Simulation
Code Generation Static Timing Analysis
Timing Simulation
Back Annotation
Implement Design
Synthesis
Map
Place & Route FPGA Hardware
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Model-Based Design for Implementation
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
Verification
Behavioral Simulation
Automatic HDL Functional Simulation
HDL Co-Simulation
Code Generation Static Timing Analysis
Behavioral Simulation Timing Simulation
Back Annotation
Implement Design
Synthesis
Map
Place & Route FPGA Hardware
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Model-Based Design for Implementation
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
Verification
Automatic HDL Functional Simulation
HDL Co-Simulation
Code Generation Static Timing Analysis
Behavioral Simulation Timing Simulation
Back Annotation
Implement Design
Back Annotation
Synthesis
Map
Implement Design Verification Place & Route FPGA Hardware
Functional Simulation
Synthesis
Static Timing Analysis
Map
Timing Simulation
Place & Route
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Model-Based Design for Implementation
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
Automatic HDL
HDL Co-Simulation
Code Generation
Behavioral Simulation
Back Annotation
Implement Design Verification FPGA Hardware
Functional Simulation
Synthesis
Static Timing Analysis
Map
Timing Simulation
Place & Route
FPGA Hardware
FPGA-in-the-Loop
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Model-Based Design for Implementation
Integrated Workflow
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
Automatic HDL
HDL Co-Simulation
Code Generation
Behavioral Simulation
Back Annotation
Implement Design Verification
Functional Simulation
Synthesis
Static Timing Analysis
Map
Timing Simulation
Place & Route
FPGA Hardware
FPGA-in-the-Loop
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Why Model-Based Design: Achieving the Shift-Left
Reduce overall development time
Reduced FPGA prototype development schedule
Shorter design iteration cycle by 80%
Improved product quality
Increase Decrease
detailed downstream
modelling development time
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Automatic HDL Code Generation
HDL Coder
Automatically generate bit-true,
cycle-accurate HDL code from
Simulink, MATLAB and Stateflow
Full bi-directional
traceability!!
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HDL Code Generation Example
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Generate Verilog or VHDL code
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Code Generation Report
Traceability Report
Resource Utilization
Report
Critical Path
Estimation Report
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What’s new?
Native Floating-Point
Generate target-independent
synthesizable RTL from single-precision
floating-point models
Good for:
– Designs with high dynamic range calculations
– Getting started prototyping FPGAs without
having to perform fixed-point conversion
Mix integer, fixed-point, and floating point
operations to balance numerical accuracy
versus hardware resource usage
Over 130 Simulink blocks supported
Demo video
» edit hdlcoderFocCurrentFloatScript
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HDL Optimizations: What, How and Why?
Does it fit on
Does this my FPGA?
meet timing?
The three golden questions:
1. Speed: Does it meet timing?
Does it do the 2. Area: Does it fit on my FPGA?
right thing?
3. Validation: Does it do the right thing?
FPGA Engineer
HDL optimizations assists the engineer in meeting these constraints
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Critical Timing Path
Critical path highlighting
Helps you identify speed bottlenecks
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Speed Optimization
Maximum rate = 145 MHz
Is this the best
rate that is
achievable??
Register
Register
Register
Smaller
critical path Automatic pipelining
Helps you meet speed objectives
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Speed Optimization
Output Pipelining
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Speed Optimization
Output Pipelining
Where do I place
the pipeline
registers??
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Speed Optimization
Distributed Pipelining
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Speed Optimization
Distributed Pipelining Maximum rate = 235 MHz
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Area Optimization
1 multiplier running at ‘N’ (20)
‘N’ (say 20) multipliers, each clock cycles
running at 1 clock cycle 25
Area Optimization
Resource Sharing
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Area Optimization
Resource Sharing
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Area Optimization
Resource Sharing
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What’s new?
Adaptive Pipelining
Specify synthesis tool and target clock
frequency for automatic pipeline TargetFrequency=500
insertion and balancing
Automatically inserts pipeline registers to
meet target frequency
– On by default
– Adds pipeline registers on parallel paths to
balance number of stages
Good for:
– Getting started prototyping FPGAs without
worrying about manually inserting Delay blocks
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Integrated HDL Verification
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
Automatic HDL
HDL Co-Simulation
Code Generation
Behavioral Simulation
Back Annotation
Implement Design Verification
Functional Simulation
Synthesis
Static Timing Analysis
Map
Timing Simulation
Place & Route
FPGA Hardware
FPGA-in-the-Loop
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Co-Simulation with HDL Simulator
Test Bench Stimuli Algorithm
+ Results Test Bench
Simulink
-
HDL Verifier
Proof your HDL matches
the MATLAB/Simulink
specification
Re-using MATLAB/Simulink
testbench HDL Simulator 31
Model-Based Design for Implementation
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware
Automatic HDL
HDL Co-Simulation
Code Generation
Behavioral Simulation
Back Annotation
Implement Design Verification
Functional Simulation
Synthesis FPGA Hardware
Static Timing Analysis
Map
Timing Simulation
Place & Route
FPGA Hardware
FPGA in the Loop
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FPGA-in-the-Loop (FIL)
for any HDL code
Part of HDL Verifier
Easy to setup using FIL Wizard
Fast simulation
– HDL runs on FPGA
– Gigabit Ethernet data transfer
Supported Xilinx boards
KC 705 SP605
ML605 SP601 Supported Altera boards
ML505 ML401 Arria II Cyclone III
ML506 ML402 DE2-115 Cyclone IV
ML507 ML403
XUP Atlys 33
XUP-V5
Automation FPGA-in-the-Loop Verification
Integration with FPGA
development boards
Add your own FPGA
board (needs Ethernet)
Automatic creation of
FPGA-in-the-Loop
verification models
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New FPGA Families and Boards Supported by FIL
FPGA Family
– Virtex Ultrascale
FPGA board
– Artix-7 Arty (JTAG)
– Virtex-7 VC709 (JTAG, PCIe)
– Virtex Ultrascale VCU110 (JTAG)
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SystemVerilog DPI Test Bench
Previously only available via command-line interface
Now it’s available in Config Param as well as HDL Workflow Advisor
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HDL Verifier: HDL Code Coverage
Activate HDL simulator code coverage
in generated test benches
Works for cosimulation, SystemVerilog DPI,
or vector-based testbenches
Supports Mentor Graphics Questa Sim and
Cadence Incisive
» makehdltb('sfir_fixed/symmetric_fir',...
» 'GenerateSVDPITestBench','ModelSim', ...
» 'HDLCodeCoverage', 'on', )
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HDL Verifier: FPGA Data Capture
Probe internal FPGA signals to analyze
in MATLAB or Simulink
Debug signals in a free-running FPGA
directly in MATLAB or Simulink
Generates a block to add into the
VHDL/Verilog design going onto the FPGA
Collects and visualizes the data in MATLAB
or Simulink
Demo video
Available as part of HDL Verifier Xilinx/Intel hardware
support packages
» generateFPGADataCaptureIP
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Harris Accelerates Verification of Signal
Processing FPGAs
Challenge
Streamline a time-consuming manual process for
testing signal processing FPGA implementation
Harris FPGA-based system.
Solution
Use HDL Verifier to verify the HDL design from within MATLAB
Results “HDL Verifier enabled us to greatly
Functional verification time cut by more than 85% reduce functional verification
100% of planned test cases completed development time by providing a direct
Design implemented defect-free cosimulation interface between our
MATLAB model and our logic simulator.
As a result, we verified our design
earlier, identified problems faster,
completed more tests, and compressed
our entire development cycle.”
Jason Plew
Harris Corporation
Link to user story
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Lockheed Martin Develops Configurable,
Space-Qualified Digital Channelizer Using
MathWorks Tools
Challenge
Design and implement a reconfigurable, space-qualified
Artist’s rendition of one of the satellites
digital channelizer that will carry Lockheed Martin’s digital
channelizer.
Solution
Use Simulink to model and simulate the system, and
HDL Verifier with Mentor Graphics ModelSim to verify the
VHDL implementation “With Simulink and HDL Verifier,
Results simulation and verification are
Verification time reduced by 90% performed in one environment. As
Overall development time shortened by eight a result, we can test the design
months from end to end, improving quality
Key algorithms reused, saving 50% of design effort and ensuring design accuracy and
on subsequent projects
validity."
Bradford Watson
Lockheed Martin Space Systems
Link to user story
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Summary
Respect project timeline
– Discover issues early through simulation
– Fast code turnarounds allow better design trade-offs
Collaborate in multidisciplinary teams
???
– Use one Model for Design and Implementation
– Seamlessly integrate version management
– Graphically compare models
Create working code
– Analyze fixed-point impact before going to implementation
– Auto-generate bug free code
– Verify early through co-simulation with FPGA’s
Achieve required efficiency
– Optimize through advisors and automatic optimizations
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Call To Action
Learn more with recorded webinars & videos
Accelerate Design Space Exploration Using HDL Coder Optimizations
Using HDL Coder and HDL Verifier for FPGA and ASIC Designs
HDL Implementation and Verification of a High-Performance FFT
Using Custom Boards for FPGA-in-the-Loop Verification
A Guided Workflow for Zynq Using MATLAB and Simulink
HDL Verifier: FPGA Data Capture
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Generating HDL Code from Simulink
two-day course shows how to generate and verify HDL code from a Simulink® model using HDL
Coder™ and HDL Verifier™
Topics include:
Preparing Simulink models for HDL code generation
Generating HDL code and testbench for a compatible Simulink model
Performing speed and area optimizations
Integrating handwritten code and existing IP
Verifying generated HDL code using testbench and cosimulation
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Programming Xilinx Zynq SoCs with MATLAB and Simulink
two-day course focuses on developing and configuring models in Simulink® and deploying on
Xilinx® Zynq®-7000 All Programmable SoCs. For Simulink users who intend to generate, validate, and
deploy embedded code and HDL code for software/hardware codesign using Embedded Coder® and
HDL Coder™.
A ZedBoard™ is provided to each attendee for use throughout the course. The board is programmed
during the class and is yours to keep after the training.
Topics include:
Zynq platform overview and environment setup, introduction to Embedded Coder and HDL
Coder
IP core generation and deployment, Using AXI4 interface
Processor-in-the-loop verification, data interface with real-time application
Integrating device drivers, custom reference design
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DSP for FPGAs
This three-day course will review DSP fundamentals from the perspective of implementation within the FPGA fabric.
Particular emphasis will be given to highlighting the cost, with respect to both resources and performance, associated
with the implementation of various DSP techniques and algorithms.
Topics include:
Introduction to FPGA hardware and technology for DSP applications
DSP fixed-point arithmetic
Signal flow graph techniques
HDL code generation for FPGAs
Fast Fourier Transform (FFT) Implementation
Design and implementation of FIR, IIR and CIC filters
CORDIC algorithm
Design and implementation of adaptive algorithms such as LMS and QR algorithm
Techniques for synchronisation and digital communications timing recovery
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Speaker Details Contact MathWorks India
Email: [email protected]
[email protected] Products/Training Enquiry Booth
Call: 080-6632-6000
Email: [email protected]
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