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B6804-CPLD & Fpga Architecture & Applications

The document is a past exam paper for a course on CPLD and FPGA architecture and applications. It contains 8 questions related to topics like programmable logic devices, lookup tables, in-system programmability of CPLDs, realizing logic functions using logic cells, state machine design and more.

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sudhakar k
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63 views2 pages

B6804-CPLD & Fpga Architecture & Applications

The document is a past exam paper for a course on CPLD and FPGA architecture and applications. It contains 8 questions related to topics like programmable logic devices, lookup tables, in-system programmability of CPLDs, realizing logic functions using logic cells, state machine design and more.

Uploaded by

sudhakar k
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Code No: B6804


NR
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech II Semester Supplementary Examinations March 2010
CPLD & FPGA ARCHITECTURE & APPLICATIONS
(COMMON TO VLSI & EMBEDDED SYSTEMS, EMBEDDED SYSTEMS &
VLSI DESIGN)
Time: 3hours Max.Marks:60
Answer any five questions
All questions carry equal marks
---

1.a) Explain in how many ways the programmable interconnections between the
configurable logic blocks and I/O blocks can be made.
b) What is a registered output in PAL devices?

2.a) How many inputs can a look up table accept in an Altera FLEX 10K logic
element? How can this be expanded?
b) What is meant by “a device is in-system programmable?”

i)
ii)
EPM7032
EPM7064 D
Out of the given CPLD’s list the in-system Programmable devices.

L
3.
iii)
iv)
EPM7128 S
EPM 7160 S

O R
Given f (T , U , V , W , X , Y ) = VWX + UVWY + TVWY . Show how ‘f’ can be

4.
U W
realized using a single 4000 series, logic cell.

The SM charts for three linked machines are given below. All state changes occur

T
during the falling edge of a common clock. Complete a timing chart including ST,
Wa, A, B, C and D. All state machines start in the state with an asterisic (*)

N
J

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5. Draw an ASM chart for a binary multiplier. Design the control logic using one-
hot design.

6. Design a digital system that converts an 8 bit signed integer to a floating point
number. Use non-registered PCDs.

7. Write a brief note on ASIC design flow using EDA tools.

8. Write a brief note on:


a) Cypress FLASH 370 device technology
b) Routing architectures of FPGAs.

******

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O R
U W
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