Academic Curriculum and Syllabi- R2019(Revised)
R19EC252-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
(CommontoAIDS, CSE, CCE, CSBS, IT)
Programme L T P C
B.E-Electronics and Communication Engineering
&Branch 3 0 2 4
Course Objectives:
1 To understand the working of logic gates and Apply minimization techniques
2 To design of combinational logic circuits
3 To comprehend the operation of sequential logic circuits
4 To understand the basic computer organization
Course Outcomes: BLOOMS
Upon completion of the course, students shall have ability to Taxonomy
CO1 Understand the working of logic gates and Apply minimization techniques K3-Apply
CO2 Design of combinational logic circuits K3-Apply
CO3 Comprehend the operation of sequential logic circuits K2-Understand
CO4 Understand the basic computer organization K2-Understand
CO5 Understand the various performance enhancement techniques K2-Understand
UNIT–I LOGIC GATES AND MINIMIZATION TECHNIQUES: 9
Basic Theorems and properties of Boolean algebra – canonical form and standard forms – digital
logic gates – Minimization Techniques: K-Map (upto 4 variables) – Don’t care condition - NAND &
NOR Implementation.
UNIT–II COMBINATIONAL LOGIC CIRCUITS: 9
Combinatorial Logic Circuits: Design Procedure – Half adder and Full adder – Half Subtractor and
Full Subtractor – Magnitude comparator – Encoder and Decoder - Multiplexer and Demultiplexer –
code converter (binary to gray, BCD to excess-3 and vice versa)
UNIT– III SEQUENTIAL LOGIC CIRCUITS: 9
Sequential Circuits: Flip-flops-Triggering of Flip-flops- Registers – Shift Registers – Ripple Counters
-Synchronous counters (up and down counter) – Random Access Memory (RAM)
UNIT – IV BASIC COMPUTER ORGANIZATION: 9
Data Representation: Fixed and Floating Point – Micro operations: Arithmetic, Logic, shift –
Arithmetic Logic Shift Unit – Instruction Codes – Computer registers – Computer Instructions –
Timing and control – Instruction Cycle – Design of Basic computer
UNIT–V PERFORMANCE ENHANCEMENT TECHNIQUES: 9
Parallel processing - Pipelining – Arithmetic and Instruction pipeline – RISC pipeline - Memory
hierarchy Main memory - Cache memory – Characteristics and Multiprocessors – Interconnection
Structures.
Total Hours (Theory): 45
LISTOF LABORATORY EXPERIMENTS /EXERCISES:
1. Verification of Boolean theorems using logic gates.
2. Implementation of half adder and full adder using logic gates
3. Implementation of Multiplexer and De-multiplexer using logic gates.
4. Verification of JK and D Flip-flops.
5. Implementation of SISO and PIPO 4-bit shift register using Flip- flops.
6. Construction and verification of 4 bit ripple counter.
7. Design and implementation of 2 bit ALU using various combinational circuits
Total Hours (Lab): 15
Total Hours (45+15) 60
TEXTBOOKS:
1. M. Morris Mano, Michael D Ciletti, “Digital Design”, Pearson, 6/e, 2018 (Module I, II, III)
2. Computer System Architecture, M. Morris Mano, Pearson Education, 3/e, 2017 (Module IV &
V)
REFERENCE BOOKS:
1. Donald P. Leach and Albert Paul Malvino, “Digital Principles and Applications”, MGH, 8/e,
2014
2. Thomas L. Floyd, “Digital Fundamentals”, Pearson, 11/e, 2017
3. John L. Hennessy, David A. Patterson, “Computer Architecture A Quantitative Approach”,
Morgan Kaufmann Press, 5/e, 2012
4. William Stallings, “Computer Organization and Architecture: Designing for Performance”,
Pearson, 10/e, 2016
