MOBILE

APPLICATION
DEVELOPMENT
By Ankit Attkan
Department of Computer Engineering
National Institute of Technology, Kurukshetra
ARM AND INTEL ARCHITECTURE
 While choosing mobile device like smartphone or tablet, we have some models using Intel
processors and other using ARM (Advance RISC Machine) architecture based processors.
 Both families of chips are designed for low-power operation, to give mobile devices the long
battery life they need.
 Technically, they represent different philosophies:
 the ARM architecture is designed to be as simple as possible, to keep energy wastage to a
minimum whereas Intel’s range of processors uses a more complex design that benefits from
compatibility with the company’s (much more power-hungry) desktop and laptop CPUs.
 ARM has been powering portable devices for decades, while Intel is a relative newcomer to
this area.
 ARM is very much the dominant architecture: iPads and iPhones use ARM exclusively, as do
Windows Phone devices
ARM AND INTEL
 Processors are a small chip that provides the input and output communications of a computer.
 ARM is a type of architecture and therefore they do not have only one manufacturer. Both Apple
and Android manufacturers use this technology in their mobile devices whereas Intel is generally
used in computers.
 Intel processors are commonly found in larger tech like desktop computers while ARM is often
found in mobile devices.
 ARM processors rely heavily on software for performance features while Intel relies on hardware
 ARM (generally) works better in smaller tech that does not have access to a power source at all
times and Intel focuses more on performance making it the better processor for larger tech.
 ARM is also making great strides in the tech industry and is expected to far surpass Intel in the
near future.
ARM AND INTEL
 Power Consumption: ARM processors not only uses less battery life but also have reduced
operating temperature than the Intel processors. Intel processors are focused on performance,
and for most PC or laptop users this isn’t a problem at all because the computer is constantly
connected to power.
 Speed: ARM chips are usually slower than their Intel counterparts, because ARM is designed to
compute with low power consumption. While most users wouldn’t notice a difference in their
respective devices, Intel processors are designed for faster computing.
 Android Processors: Intel was once a part of a few Android mobile devices but the ARM
processors still reign in this market.
 Intel-based devices can run the full range of Android apps, even those that were originally written
for the ARM architecture.
 If app contains an ARM-specific code, then it must be translated before it can be executed.
 Intel based android devices does tend to trail behind ARM in term of battery life while overall
performance is generally very good.
CISC VS. RISC
 CISC stands for Complex Instruction Set Computing while RISC is Reduced Instruction Set
Computing.
 Intel processors (commonly referred to as X86 in correlation with Windows 32-bit programs) use
Complex Instruction Set Computing while ARM uses Reduced Instruction Set Computing.
 RISC is perceived by many as an improvement over CISC.
 RISC-based machines execute one instruction per clock cycle while CISC machines can have
special instructions as well as instructions that take more than one cycle to execute.
 Same instruction executed on a CISC architecture might take several instructions to execute on
a RISC machine.
 CISC is Hardware-centric design while RISC is Software-centric design.
 CISC uses RAM more efficiently than RISC, as RISC cause heavy use of RAM (Bottleneck
condition if RAM is limited).
HISTORY
 The first integrated chip was designed in 1958 by Jack Kilby.
 Microprocessors were introduced in the 1970s, the first commercial one coming from Intel
Corporation.
 By the early 1980s, the RISC architecture had been introduced.
 The RISC design came about as a total redesign because the CISC architecture was becoming
more complex.
 John Cocke of IBM comes up with the idea of RISC concept.
 Some major changes in the microprocessor architecture to make it faster leads to idea of RISC,
including a uniform format for instructions and easily pipelined instructions. (Pipelining means
the processor starts to execute the next instruction before the present instruction is completed).
 In the 1970s, memory was costly, so smaller programs were a focus.
ARM
 The ARM architecture processor is an advanced reduced instruction set computing [RISC]
machine.
 ARM makes 32-bit and 64-bit RISC multi-core processors.
 The ARM microcontroller is one of the extensive and most licensed processor cores in the world.
 The first ARM processor was developed in the year 1978 by Cambridge University and First ARM
RISC processor was produced by the Acorn Group of Computers in 1985.
 These processors are specifically used in portable devices like digital cameras, mobile phones,
home networking modules and wireless communication technologies and other embedded
systems
 The Key benefits of ARM are low power consumption, reasonable performance, portability.
 The ARM architecture comes with different versions like ARMv1, ARMv2, etc.
ARM
 The ARM architecture is used in a range of technologies, integrated into System-on-
Chip (SoC) devices such as smartphones, microcomputers, embedded devices, and
even servers.
 There are three architecture profiles: A, R and M.
 A-Profile (Applications): Designed to run a complex operating system, such as
Linux or Windows.
 R-Profile (Real-Time): Designed of networking equipment, and embedded control
systems.
 M-Profile (Microcontroller): Small, highly power-efficient devices.

 32-bit Arm architecture, such as Armv7 is most widely used architecture in mobile
devices as of 2011.
ARM
 ARM cortex is a complicated microcontroller within the ARM family that has ARMv7
design.
 3 subfamilies within the ARM cortex family:
• ARM Cortex Ax-series
• ARM-Cortex Rx-series
• ARM-Cortex Mx-series
ARM ARCHITECTURE
 32-bit ARM architecture along with some 62-bit ARM incorporated a number of features from the
Berkeley RISC design along with some additional features:
 a load-store architecture;
• Uniform 16 × 32-bit register file (including the program counter, stack pointer and the link register).
• fixed-length 32-bit instructions: Fixed instruction width of 32 bits to ease decoding and pipelining, at the
cost of decreased code density.
• 3-address instruction formats
• Mostly single clock-cycle execution.
• Conditional execution of most instructions reduces branch overhead and compensates for the lack of
a branch predictor in early chips.
• 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and
address calculations.
• Has powerful indexed addressing modes.
• A link register supports fast leaf function calls.
• A simple, but fast, 2-priority-level interrupt subsystem.
ARM ARCHITECTURE
 32-bit Arm architecture specifies several CPU modes, depending on the implemented
architecture features. At any moment in time, the CPU can be in only one mode, but it
can switch modes due to external events (interrupts) or programmatically.
• User (usr) mode: The only non-privileged mode.
• Fast-Interrupt (FIQ) mode: A privileged mode that is entered whenever the processor accepts
a fast interrupt request.
• Interrupt (IRQ) mode: A privileged mode that is entered whenever the processor accepts an
interrupt.
• Supervisor (svc) mode: A privileged mode entered whenever the CPU is reset or when an SVC
instruction is executed.
• Abort (abt) mode: A privileged mode that is entered whenever a prefetch abort or data abort
exception occurs.
• Undefined mode: A privileged mode that is entered whenever an undefined instruction
exception occurs.
ARM ARCHITECTURE
• System (sys) mode (Armv4 and above): The only privileged mode that is not entered by an
exception. It can only be entered by executing an instruction that explicitly writes to the mode bits
of the Current Program Status Register (CPSR) from another privileged mode (not from user
mode).
• Monitor mode (Armv6 and Armv7 Security Extensions, Armv8 EL3): A monitor mode is introduced
to support TrustZone extension in Arm cores.
• Hyp mode (Armv7 Virtualization Extensions, Armv8 EL2): A hypervisor mode that
supports virtualization requirements for the non-secure operation of the CPU.
• Thread mode (Armv6-M, Armv7-M, Armv8-M): A mode which can be specified as either privileged
or unprivileged. Whether the Main Stack Pointer (MSP) or Process Stack Pointer (PSP) is used can
also be specified in CONTROL register with privileged access. This mode is designed for user
tasks in RTOS environment but it's typically used in bare-metal for super-loop.
• Handler mode (Armv6-M, Armv7-M, Armv8-M): A mode dedicated for exception handling (except
the RESET which are handled in Thread mode). Handler mode always uses MSP and works in
privileged level.
ARM ARCHITECTURE
ARM ARCHITECTURE
 32-bit Arithmetic Logic Unit (ALU): ALU performs all the arithmetic and logical operations of the processor.
The ALU receives two 32 bit inputs, one from a register and other from the shifter. The ALU can alter the status
flag according to the results of the operation it performs.
 Arm includes integer arithmetic operations for add, subtract, and multiply; some versions of the architecture
also support divide operations.
 Arm supports 32-bit × 32-bit multiplies with either a 32-bit result or 64-bit result, though Cortex-
M0 / M0+ / M1 cores don't support 64-bit results. Some Arm cores also support 16-bit × 16-bit
and 32-bit × 16-bit multiplies.
 The divide instructions are only included in the following Arm architectures:
• Armv7-M and Armv7E-M architectures always include divide instructions.
• Armv7-R architecture always includes divide instructions in the Thumb instruction set, but
optionally in its 32-bit instruction set.
• Armv7-A architecture optionally includes the divide instructions. The instructions might not be
implemented, or implemented only in the Thumb instruction set, or implemented in both the
Thumb and Arm instruction sets, or implemented if the Virtualization Extensions are included.
ARM ARCHITECTURE
 Register: The ARM cortex-M3 consists of 37 register sets wherein 31 are 32-bit
general purpose registers and 6 are status registers.
 When writing user-level programs, only the 15 general-purpose 32-bit registers (r0 to r14), the program
counter (r15) and the current program status register (CPSR) need be considered. The remaining registers
are used only for system-level programming and for handling exceptions (for example, interrupts).
• Aliases, R13 is also referred to as SP, the Stack Pointer, R14 is also referred to as LR, the Link Register and Saved
Program Status Register (SPSR) stores the current value of the CPSR when an exception is taken
ARM ARCHITECTURE
 Current Program Status Register (CPSR): is used in user-level programs to store the
condition code bits. Current Program Status Register (CPSR) has the following 32 bits:
M (bits 0–4) is the processor mode bits.
T (bit 5) is the Thumb state bit.
F (bit 6) is the FIQ disable bit.
I (bit 7) is the IRQ disable bit.
A (bit 8) is the imprecise data abort disable bit.
E (bit 9) is the data endianness bit.
IT (bits 10–15 and 25–26) is the if-then state bits.
GE (bits 16–19) is the greater-than-or-equal-to bits.
DNM (bits 20–23) is the do not modify bits.
J (bit 24) is the Java state bit.
Q (bit 27) is the sticky overflow bit.
V (bit 28) is the overflow bit.
C (bit 29) is the carry/borrow/extend bit.
Z (bit 30) is the zero bit.
N (bit 31) is the negative/less than bit.
ARM ARCHITECTURE
 Barrel Shifter: The barrel shifter is a functional unit which can perform five different
kinds of shift and rotate operation: Logical left shift, Logical right shift, Arithmetic
shift right, Rotate right and Rotate right extended.
 Multiplier: ARM microprocessor uses 32 bit booth multiplier for multiplication. Booth
multiplier uses booth multiplication algorithm (Multiplication and division algorithms).
 Priority encoder: It is used in the load and store instruction to point out which register
within the register set to be loaded or stored.
 Control unit: The control unit sends control signals to different components of the
processor to control their operations.
 Instruction decode unit decodes all ARM instructions and also handles the sequencing
of exceptions, debug events, reset initialization, Memory Built-In Self Test (MBIST),
wait-for-interrupt, other unusual events.
INTEL ARCHITECTURE
 Intel Architecture (IA) can be traced back through the 8085 and 8086 microprocessors
to the 4004 microprocessor (the first microprocessor, designed by Intel in 1969).
 First actual processor in the IA family is the 8086, quickly followed by a more cost
effective version for smaller systems, the 8088.
 The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit addressing
giving a 1- MByte address space.
 The 8088 is identical except for a smaller external data bus of 8 bits.
 The Intel 80286 processor introduced the Protected Mode into the IA. This new mode
uses the segment register contents as selectors or pointers into descriptor tables.
The descriptors provide 24-bit base addresses, allowing a maximum physical memory
size of up to 16 MBytes, support for virtual memory management on a segment
swapping basis, and various protection mechanisms.
INTEL ARCHITECTURE
 Intel386™ processor introduced 32-bit registers into the architecture, for use both as operands
for calculations and for addressing.
 The 32-bit addressing was supported with an external 32-bit address bus, giving a 4-GByte
address space.
 Intel486™ processor added more parallel execution capability by (basically) expanding the
Intel386™ processor’s Instruction Decode and Execution Units into five pipelined stages, where
each stage (when needed) operates in parallel with the others on up to five instructions in
different stages of execution.
 Intel Pentium® processor added a second execution pipeline to achieve superscalar
performance (two pipelines, known as u and v, together can execute two instructions per clock).
 Intel Pentium® Pro processor introduced “Dynamic Execution” (micro-data flow analysis, out-of-
order execution, superior branch prediction, and speculative execution).
INTEL ARCHITECTURE
 Pentium® Pro processor also has an expanded 36-bit address bus, giving a maximum physical
address space of 64 GBytes.
 Later, Pentium II– with MMX (multimedia) instruction set, Pentium III with SIMD (streaming
extensions) instructions (SSE), Pentium 4 with NetBurst micro-architecture, tuned for
multimedia are launched.
 Atom is a System on Chip (SoC) platform designed for smartphones and tablet computers,
launched by Intel in 2012.
 Intel (x86) made Bonnell microarchitecture & Silvermont microarchitecture for Android devices.
These microarchitecture supports the Android operating system on Intel x86 processors.
 Bonnell is a CPU microarchitecture used by Intel Atom processors which can execute up to two
instructions per cycle.
 Silvermont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors
used in systems on a chip (SoCs) made by Intel.
INTEL ARCHITECTURE
 Android-x86 is an open source project that makes an unofficial porting
of Google's Android mobile operating system to run on devices powered
by AMD and Intel x86 processors, rather than RISC-based ARM chips.
• Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package.
The type of package is DIP (Dual Inline Package).
• Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 =
1 Mbyte of memory.
 It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
 8086 contains two independent functional units: a Bus Interface Unit (BIU) and
an Execution Unit (EU).
INTEL ARCHITECTURE
INTEL ARCHITECTURE
 Bus Interface Unit (BIU): The segment registers, instruction pointer and 6-byte instruction
queue are associated with the bus interface unit (BIU).
• Handles transfer of data and addresses,
• Fetches instruction codes, stores fetched instruction codes in first-in-first-out register
set called a queue,
• Reads data from memory and I/O devices,
• Writes data to memory and I/O devices,
• It relocates addresses of operands since it gets un-relocated operand addresses from
EU. The EU tells the BIU from where to fetch instructions or where to read data.
 Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next
instruction and stores them in the instruction queue and this process is known as
instruction pre fetch. This process increases the speed of the processor.
INTEL ARCHITECTURE
• Segment Registers: A segment register contains the addresses of instructions and data in
memory which are used by the processor to access memory locations. It points to the starting
address of a memory segment currently being used.
• There are 4 segment registers in 8086 as given below:
• Code Segment Register (CS): Code segment of the memory holds instruction codes of a
program.
• Data Segment Register (DS): The data, variables and constants given in the program are
held in the data segment of the memory.
• Stack Segment Register (SS): Stack segment holds addresses and data of subroutines. It
also holds the contents of registers and memory locations given in PUSH instruction.
• Extra Segment Register (ES): Extra segment holds the destination addresses of some data
of certain string instructions.
• Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a program
counter. It indicates to the address of the next instruction to be executed.
INTEL ARCHITECTURE
 Execution Unit (EU): The EU receives opcode of an instruction from the queue,
decodes it and then executes it. While Execution, unit decodes or executes an
instruction, then the BIU fetches instruction codes from the memory and stores them
in the queue.
• The BIU and EU operate in parallel independently. This makes processing faster.
• General purpose registers, stack pointer, base pointer and index registers, ALU, flag registers
(FLAGS), instruction decoder and timing and control unit constitute execution unit (EU). Let's
discuss them:
• General Purpose Registers: There are four 16-bit general purpose registers: AX (Accumulator
Register),
16-bitBX (Base Register), CX8-bit
registers (Counter) and DX. Each of8-bit
high-order registers these 16-bit
low-order registers are further
registers
subdivided into 8-bit registers as shown below:
AX AH AL
BX BH BL
CX CH CL
DX DH DL
INTEL ARCHITECTURE
• Index Register: The following four registers are in the group of pointer and index registers:
• Stack Pointer (SP)
• Base Pointer (BP)
• Source Index (SI)
• Destination Index (DI)
• ALU: It handles all arithmetic and logical operations. Such as addition, subtraction, multiplication, division,
AND, OR, NOT operations.
• Flag Register: It is a 16 bit register which exactly behaves like a flip-flop, means it changes states according
to the result stored in the accumulator. It has 9 flags and they are divided into 2 groups i.e. conditional and
control flags.
• Conditional Flags: This flag represents the result of the last arithmetic or logical instruction executed.
Conditional flags are: Carry Flag, Auxiliary Flag, Parity Flag, Zero Flag, Sign Flag, Overflow Flag
• Control Flags: It controls the operations of the execution unit. Control flags are: Trap Flag, Interrupt
Flag, Direction Flag
INTEL ARCHITECTURE
 Interrupt is a process of creating a temporary halt during program execution and allows peripheral
devices to access the microprocessor.
 Hardware interrupts are that type of interrupt which are caused by any peripheral device by sending a
signal through a specified pin to the microprocessor. The Intel 8086 has two hardware interrupt pins:
• NMI (Non-Maskbale Interrupt)
• INTR (Interrupt Request) Maskable Interrupt.

 NMI: NMI is a single Non-Maskable Interrupt having higher priority than the maskable interrupt.
• It cannot be disabled (masked) by user using software.
• It is used by the processor to handle emergency conditions. For example: It can be used to save program
and data in case of power failure. An external electronic circuitry is used to detect power failure, and to
send an interrupt signal to 8086 through NMI line.
 INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt flag (IF). After
receiving INTR from external device, the 8086 acknowledges through INTA signal.
INTEL ARCHITECTURE
 Software Interrupt: A microprocessor can also be interrupted by internal abnormal
conditions such as overflow; division by zero; etc.
 A programmer can also interrupt microprocessor by inserting INT instruction at the
desired point in the program while debugging a program. Such an interrupt is called a
software interrupt.
• TYPE 0 (division by zero)
• TYPE 1 (single step execution for debugging a program)
• TYPE 2 represents NMI (power failure condition)
• TYPE 3 (break point interrupt)
• TYPE 4 (overflow interrupt)
WHICH IS BEST ARCHITECTURE?
 Both ARM and Intel processors have their own benefits and drawbacks. Choosing which
is better for you heavily depends on what you’d like to do with your tech devices and if
they’re compatible with other hardware and software.
 Intel is faster and more powerful than ARM processors. But, ARM processors are more
mobile-friendly than Intel processors (in most cases).
 The past two years have caused an upset for people who were diehard one or the other.

 Intel-based Macs will soon be released with Apple’s own ARM processors, while we’ve
seen some great things coming from Microsoft.
 Only time will tell, but there are constant improvements to both processors meaning
what’s great now may not be so great in a year.
 With the M1 chip from Apple hitting the market in 2021, the company claims that this
ARM chip will produce twice the power for one-third of the battery consumption.
THANK YOU