A B C D E

DDP00
MODEL NAME :
DDB00

PCB NO : LA-G341P
1 BOM P/N : Dell/Compal Confidential 1

Schematic Document
Superveloce
(Berlinetta CFL 4-Phase Design)
2018-05-10
Rev: Pilot A00
2 @ : Nopop Component 2

XDP@ : Nopop Component

CONN@ : Connector Component
TPM@ : TPM funct i on
EMC@ : Pop of EMI parts
VRAMS@ : Samsung GDDR5
VRAMM@ : Micron GDDR5
G0VRAMH@: Samsung GDDR5 for G0-GPU
NDS@@ : Nopop Component
N18PQ1@ : GPU N18PQ1
3 N18PQ3@ : GPU N18PQ3 3

N17PG0@ : GPU N17PG0

N17PG1@ : GPU N17PG1
UMA@ : UMA
DIS@ : DIS
UMAP@ : UMA for Presist i on
UMAX@ : UMA for XPS
3PHASEPCB@ : PCB for 3Phase
4PHASEPCB@ : PCB for 4Phase
3PHASE@ : PCB for 3Phase
4 4PHASE@ : PCB for 4Phase 4

VPRO@ : For VPRO SKU

NVPRO@ : For No-VPRO SKU
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P01-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 1 of 76
A B C D E
 A B C D E

256M*32 x4 =8Gb ,128-bit Memory

GDDR5, VRAM * 4
8Gbit GDDR5 memory P.28~30

Memory Bus (DDR4) DDRIV-DIMM X2

GPU GB4C-128 CPU XDP
Intel Dual Channel 1.2V DDR4 2666 MHz P.14~15 Conn. P.6
GTX N17P-G0 40W/4GB
1 GTX N17P-G1 MaxQ 35W/4GB Coffee Lake-H 32GB Max (4G, 8G,16G) 1

Quadro PEG 3.0 x16 lane HDMI 2.0/HDCP2.2

N18P-Q1 30W/4GB
Processor DDI x 1 port 3 DP to HDMI Converter HDMI
Parade PS175 B2 P.39 LSPCon Conn.
N18P-Q3 30W MaxQ /4GB 45W 6C+2 4096x2160 60Hz P.40
P.23~27 42 x 28mm
BGA 1440 Balls
DDI x 2 port1,2 USB3.1 Type C (TBT)
UHD 3840x2160@60Hz Intel Alpine Ridge TBT
eDP *4 lane P.7~13 Conn.
(4K*2K, eDP 1.4a, PSR2) PCI-E Gen3 x 4 SP C-stepping
PCH Port 17,18,19,20 (Gen 2 10Gbps) P.38
P.34 P.35~36
DMI x4
100MHz
8GB/s

SATA3.0 Port 1B HDD Conn.

M.2 Slot A Key-E PCI-E Gen2 x 1 Port 1 TI PD
P.44
(WLAN+BT5.0) USB2.0 Port 4 TPS65982DC
P.42 P.37
Port 1A
M.2 Slot C Key-M
2 2
3 in 1 Socket for UHS-II PCI-E x4 (SATA/PCIe SSD)
Card Reader SD4.0 PCI-E Gen2 x 1 Port 2 P.43
SD/SDHC/SD3.0/SD 4.0
P.50 RTS5242-GR
P.50 Intel
USB 3.1 Gen1 Port 1 USB 3.1 Gen1 Re-Driver
CNL-H-PCH PS8713 P.46 USB 3.1 Gen 1 (5Gbps)
USB 3.1 Gen 1 (5Gbps) USB 3.1 Gen1 Port 2
24 x 25mm Type A Conn.
USB2.0 Port 1 USB Powershare
Type A Conn. ( USB Charger )
Port 2 USB2.0 P.47
( USB Charger ) USB Powershare BGA 837 Balls USB2.0 Port 9 Touch Panel TPS2546
P.47 P.45
TPS2546 P.45
Conn. P.34
I2C Bus Port 0 Touch Panel
RGB Camera Port 12 USB2.0 Conn. P.34
CM246 (Wacom G12+ Controller)
720P HD P.34 USB2.0 Port 7 Finger Print
(leveraged with Berlinetta MLK) Conn.
contact USB 2.0 FFC P.48
SPI Flash SPI (in Power Button leveraged with (LaFerrari) )
(BIOS 32MB)P.17 HD Audio
x9 Common Audio Codec
3
ALC3266 Headphone / Mic. Jack 3
FFS P.52 ( Combo ) P.53
SMBus ARD
LNG2DMTR DMIC
connect to Audio Board
P.44
P16~22 PCH

AMP TAS5768M

GPU sequence chip eSPI Bus

TPM 2.0 SPI
SLG4U41821VTR NPCT750JAAYX 33MHz
Power On/Off CKT. x9 Common code P.41 Int. Speaker x2
P.41
MEC 5105
DC/DC Interface CKT. Rev:C KB Board
P.31~33 P.48

PWM PS/2 Digital MIC Conn.

DC-IN Conn. I2C
P.54

4 Fan Control Touch Pad BCBUS KBC KSIO Int.KBD 4

P.40
ECE1117
P.40
HZH-1-TR C

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P02-Block Diagram

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 2 of 76
A B C D E
 A B C D E

Compal Confidential
Project Code : DDP00 / DDB00
File Name :

1 1

LA-G341P MB

LS-E331P
Audio Board

2 2

JAUDIO
BtB Conn.

JKB Finger Print JTP

8 pin
15 pin 8 pin
FFC
FFC FFC

Touch Pad
LS-E332P
KB controller
Board JLED

3 3

4 pin FFC
Front Side LED/B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P03-Daughter/B block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 3 of 76
A B C D E
 A

Board ID Resistor USB3.1 DESTINATION USB 2.0 DESTINATION USB OC# DESTINATION
X00 4.3K 1 USB Conn 1 (Right Side) 1 USB Conn 1 (Right Side) 0 USB Conn 1 (Right Side)
X01 2K 2 USB Conn 2 (Left Side) 2 USB Conn 2 (Left Side) 1 USB Conn 2 (Left Side)
X02 3 None 3 None 2

X03 4 None 4 NGFF-1 WLAN + BT 3

A00 1K 5 None 5 None 4

6 None 6 None 5

7 Finger Print 6

PCI EXPRESS DESTINATION USB3.0 DESTINATION 8 None 7

Lane 1 NGFF-1 WLAN + BT 7 None 9 Touch Screen

Lane 2 None 8 None 10 None

Lane 3 None 9 None 11 None

Lane 4 None 10 None 12 RGB CAMERA

Lane 5 CARD READER

Lane 6 None CLKOUT_PCIE DESTINATION CLKOUT_PCIE DESTINATION

Lane 7 None 0 None 10 None

Lane 8 None 1 None 11 None

1 Lane 9 SSD 2 None 12 None 1

Lane 10 SSD SATA DESTINATION 3 NGFF-1 WLAN 13 None

Lane 11 SSD 0A N/A 4 CARD READER 14 None

Lane 12 SSD 1A SSD 5 Thunderbolt 15 None

Lane 13 None 0B N/A 6 NGFF-2 SSD

Lane 14 None 1B N/A 7 GPU

Lane 15 None 2 HDD 8 None

Lane 16 None 3 N/A 9 None

Lane 17 4 N/A

Lane 18 5 N/A
Alpine Ridge
Lane 19 The 30 HSIO lanes on PCH-H supports the following configurations:
1. Up to 24 PCIe* Lanes
‧
— A maximum of 16 PCIe* Ports (or devices) can be enabled
When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
Lane 20 Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured
2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
DDI DESTINATION LPC DESTINATION — SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

1 Alpine Ridge ESPI/LPC0 MEC5105 5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express * (PCIe*) ” chapt er f or t he P CH PCI e* Controllers,configuration
s
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
2 Alpine Ridge LPC1 DEBUG PORT 6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
3 HDMI 2.0

Symbol Note : Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P04-Notes List

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
: means Digital Ground : means Analog Ground 1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 4 of 76
A
 5 4 3 2 1

1K 1K
SMBUS Address [0x9a]
+3V_PCH +3VS
1K 1K
SMBCLK
+3VS
AW44 PCH_SMBCLK
SMBDATA
DMN65D8
BB43 PCH_SMBDATA DIMMA
DMN65D8
D D
5.1K QH4
DIMMB
+3VS
5.1K
AR38 I2C0_SCK 4.7K
PCH I2C0_SCK_TS
AT42 I2C0_SDA Touch Screen FFS
I2C0_SDA_TS
4.7K
2.4K
XDP
+3VS_TP
2.4K
I2C1_SCK_TP
+3VS_TP
AR41 I2C1_SCK_TP_C
I2C1_SDA_TP DMN65D8 TP
AR44 I2C1_SDA_TP_C
DMN65D8
AW45 AW42
QE2

SML1_SMBCLK 1K

SML1_SMBDAT 1K
+3V_PCH Connect PCH SMB03
C C

2.2K

+3VALW_5105
E11 D8 2.2K
N10 PBAT_SMBCLK 100 ohm
A12 100 ohm
PBAT_SMBDAT BATT 0x16 PBAT DATA/CLK SMB06
10K

+3VALW_5105
10K
M3 CHARGER_SMBCLK 0 ohm CHARGER_SCL
N2 0 ohm CHARGER 0x12 Power Charger SMB10
MEC5105 CHARGER_SMBDAT
2.2KK
CHARGER_SDA

+3VALW_5105
2.2K
M3 UPD_SMBCLK UPD_SMBCLK_R
B B
N2 UPD_SMBDAT UPD_SMBDAT_R PD Controller PD SMB04
2.2KK
1.8K

+3VALW_5105
2.2K DGPU_PEX_RST# +3VALW_5105
1.8K
B6 GPU_SMBCLK DMN65D8
F7 GPU_SMBDAT DMN65D8
GPU 0x9E GPU SMB05

QV21
+3VS
I2C0_SCK_DSP
E7 AUDIO_AMP_SMBCLK DMN65D8
D7
Codec
AUDIO_AMP_SMBDAT I2C0_SDA_DSP
DMN65D8
QE18 Audio + AMP SMB00

AMP

2.2K +3VALW_5105

A 2.2K A

E10
CLK_TP_SIO
C12 DAT_TP_SIO Touch PAD Touch Pad SMB02

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P05-SMBus block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 5 of 76
5 4 3 2 1
 5 4 3 2 1

+1V_PCH JTAG +1V_PCH

RH492 1 2 XDP_PLTRST#
CPU
1
2.2K_0402_5% XDP@
CH3 RH474 1 XDP@ 2 1K_0402_5% CFG3
+3V_PCH 0.1U_0402_25V6 XDP_TDO RH540 1 @ 2 0_0402_1%
2 CPU_XDP_TDO <9>
+1V_PCH RH475 1 @ 2 0_0402_5% +1V_PCH
RH493 1 2 PCH_SYS_PWROK_XDP
2.2K_0402_5% JXDP
D
1 2 XDP_TDI RH541 1 @ 2 0_0402_1% D
GND0 GND1 CPU_XDP_TDI <9>
3 4
<9,22> XDP_PREQ# OBSFN_A0 OBSFN_C0 CFG17 <9>
<9,22> XDP_PRDY# 5 6 CFG16 <9>
+VCCST 7 OBSFN_A1 OBSFN_C1 8
CFG0 9 GND2 GND3 10
<9> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <9>
11 12
<9> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <9> XDP_TMS CPU_XDP_TMS <9>
13 14 RH542 1 @ 2 0_0402_1%
RH97 1 @ 2 100_0402_5% PCH_JTAG_TDO 15 GND4 GND5 16
<9> CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 <9>
CFG3 17 18
<9> CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 <9>
RH98 1 @ 2 51_0402_5% PCH_JTAG_TMS 19 20
21 GND6 GND7 22 XDP_TRST# RH543 1 @ 2 0_0402_1%
<9> XDP_BPM#0 OBSFN_B0 OBSFN_D0 CFG19 <9> CPU_XDP_TRST# <9,22>
RH100 1 @ 2 51_0402_5% PCH_JTAG_TDI 23 24
<9> XDP_BPM#1 OBSFN_B1 OBSFN_D1 CFG18 <9>
25 26
27 GND8 GND9 28
<9> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <9>
<9> CFG5 29 30 CFG13 <9>
+VCCSTG 31 OBSDATA_B1 OBSDATA_D1 32
33 GND10 GND11 34
<9> CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 <9>
<9> CFG7 35 36 CFG15 <9>
37 OBSDATA_B3 OBSDATA_D3 38
RH494 1 2 51_0402_5% CPU_XDP_TMS XDP_PWRGOOD 39 GND12 GND13 40
PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4 PCH_XDP_CLK_P <17>
41 42
HOOK1 ITPCLK#/HOOK5 PCH_XDP_CLK_N <17>
RH495 1 2 51_0402_5% CPU_XDP_TDI 43 44
PWR_DEBUG#_XDP 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_PLTRST#
RH496 1 2 51_0402_5% CPU_XDP_TDO PCH_SYS_PWROK_XDP 47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
49 HOOK3 DBR#/HOOK7 50
51 GND14 GND15 52 XDP_TDO
<14,15,18,44> PCH_SMBDATA SDA TD0 XDP_TRST#
53 54
<14,15,18,44> PCH_SMBCLK PCH_JTAG_TCK SCL TRST# XDP_TDI
55 56
RH95 1 @ 2 100_0402_5% PCH_JTAG_TCK <18> PCH_JTAG_TCK CPU_XDP_TCK 57 TCK1 TDI 58 XDP_TMS

RH498 1 2 51_0402_5% CPU_XDP_TCK <18> PCH_JTAGX

<9> CPU_XDP_TCK
RH491 1 @ 2 0_0402_1% 59 TCK0
GND16
TMS
GND17
60 PCH_SPI_WP#_XDP RH573 1 XDP@ 2 1K_0402_5% PCH_SPI_WP# <17> PCH
SAMTE_BSH-030-01-L-D-A
RH497 1 @ 2 51_0402_5% CPU_XDP_TRST# CONN@

C
XDP_TMS RH12 1 @ 2 0_0402_1% PCH_JTAG_TMS C
PCH_JTAG_TMS <18>

XDP_TDI RH477 1 @ 2 0_0402_1% PCH_JTAG_TDI

PCH_JTAG_TDI <18>

XDP_PWRGOOD XDP_TDO RH478 1 @ 2 0_0402_1% PCH_JTAG_TDO

RH479 1 XDP@ 2 0_0402_5% PCH_JTAG_TDO <18>
<18> PCH_ITP_PMODE
XDP_PLTRST#

.1U_0402_16V7K
1 @ 2
<9,16> PLTRST_CPU# RH480 1K_0402_5%
1

CD3328
<17> PCH_SPI_SI RH489 1 XDP@ 2 1K_0402_5%

RH490 1 @ 2 0_0402_5% PCH_SYS_PWROK_XDP 2

<18,48> SYS_PWROK

<18,48> PCH_RSMRST#_EC RH481 1 XDP@ 2 1K_0402_5%

RH482 1 @ 2 1K_0402_5% XDP_PWRGOOD

<9,33> H_VCCST_PWRGD +3VS

+3V_PCH_DSW

+VCCIO

1
1

@ RH5
RH483 RH2 3K_0402_5%
150_0402_5% 1K_0201_5%

2
2

PWR_DEBUG#_XDP RH488 1 XDP@ 2 1K_0402_5% CFG0 PWRBTN#_XDP RH6 1 2 0_0402_5% XDP_DBRESET# RH8 1 @ 2 0_0402_1%
SIO_PWRBTN# <18,48> SYS_RESET# <18,51>
B B
0.1U_0402_25V6

0.1U_0402_25V6
1

1
CH174

CH175
XDP@
XDP@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P06-XDP CONN

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 6 of 76
5 4 3 2 1
 5 4 3 2 1

CFL-H
UH1C
PEG_GTX_C_HRX_P15 E25 B25 PEG_HTX_GRX_P15 DIS@ CH5 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P15
PEG_GTX_C_HRX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PEG_HTX_GRX_N15 DIS@ CH6 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P[0..15] PEG_RXN_0 PEG_TXN_0
<23> PEG_HTX_C_GRX_P[0..15] PEG_GTX_C_HRX_P14 PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14
E24 B24 DIS@ CH7 1 2 0.22U_0201_6.3V6M
PEG_HTX_C_GRX_N[0..15] PEG_GTX_C_HRX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PEG_HTX_GRX_N14 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N14
<23> PEG_HTX_C_GRX_N[0..15] DIS@ CH8
PEG_RXN_1 PEG_TXN_1
PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_P13 E23 B23 PEG_HTX_GRX_P13 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P13
<23> PEG_GTX_C_HRX_P[0..15] DIS@ CH9
PEG_GTX_C_HRX_N13 D23 PEG_RXP_2 PEG_TXP_2 A23 PEG_HTX_GRX_N13 DIS@ CH10 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N13
PEG_GTX_C_HRX_N[0..15] PEG_RXN_2 PEG_TXN_2
<23> PEG_GTX_C_HRX_N[0..15] PEG_GTX_C_HRX_P12 PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12
E22 B22 DIS@ CH11 1 2 0.22U_0201_6.3V6M
PEG_GTX_C_HRX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PEG_HTX_GRX_N12 DIS@ CH12 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N12
PEG_RXN_3 PEG_TXN_3
PEG_GTX_C_HRX_P11 E21 B21 PEG_HTX_GRX_P11 DIS@ CH13 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P11
D PEG_GTX_C_HRX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_HTX_GRX_N11 DIS@ CH14 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N11 D
PEG_RXN_4 PEG_TXN_4
PEG_GTX_C_HRX_P10 E20 B20 PEG_HTX_GRX_P10 DIS@ CH15 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P10
PEG_GTX_C_HRX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PEG_HTX_GRX_N10 DIS@ CH16 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N10
PEG_RXN_5 PEG_TXN_5
PEG_GTX_C_HRX_P9 E19 B19 PEG_HTX_GRX_P9 DIS@ CH17 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P9
PEG_GTX_C_HRX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PEG_HTX_GRX_N9 DIS@ CH18 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N9
PEG_RXN_6 PEG_TXN_6
PEG_GTX_C_HRX_P8 E18 B18 PEG_HTX_GRX_P8 DIS@ CH19 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P8
PEG_GTX_C_HRX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PEG_HTX_GRX_N8 DIS@ CH20 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N8
PEG_RXN_7 PEG_TXN_7
PEG_GTX_C_HRX_P7 D17 A17 PEG_HTX_GRX_P7 DIS@ CH21 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P7
PEG_GTX_C_HRX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_HTX_GRX_N7 DIS@ CH22 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N7
PEG_RXN_8 PEG_TXN_8
PEG_GTX_C_HRX_P6 F16 C16 PEG_HTX_GRX_P6 DIS@ CH23 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P6
PEG_GTX_C_HRX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PEG_HTX_GRX_N6 DIS@ CH24 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N6
PEG_RXN_9 PEG_TXN_9
PEG_GTX_C_HRX_P5 D15 A15 PEG_HTX_GRX_P5 DIS@ CH25 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P5
PEG_GTX_C_HRX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PEG_HTX_GRX_N5 DIS@ CH26 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N5
PEG_RXN_10 PEG_TXN_10
PEG_GTX_C_HRX_P4 F14 C14 PEG_HTX_GRX_P4 DIS@ CH27 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P4
PEG_GTX_C_HRX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PEG_HTX_GRX_N4 DIS@ CH28 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N4
PEG_RXN_11 PEG_TXN_11
PEG_GTX_C_HRX_P3 D13 A13 PEG_HTX_GRX_P3 DIS@ CH29 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PEG_HTX_GRX_N3 DIS@ CH30 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N3
PEG_RXN_12 PEG_TXN_12
PEG_GTX_C_HRX_P2 F12 C12 PEG_HTX_GRX_P2 DIS@ CH31 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PEG_HTX_GRX_N2 DIS@ CH32 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N2
PEG_RXN_13 PEG_TXN_13
PEG_GTX_C_HRX_P1 D11 A11 PEG_HTX_GRX_P1 DIS@ CH33 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PEG_HTX_GRX_N1 DIS@ CH34 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N1
PEG_RXN_14 PEG_TXN_14
+VCCIO PEG_GTX_C_HRX_P0 F10 C10 PEG_HTX_GRX_P0 DIS@ CH35 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P0
PEG_GTX_C_HRX_N0 E10 PEG_RXP_15 PEG_TXP_15 B10 PEG_HTX_GRX_N0 DIS@ CH36 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N0
PEG_RXN_15 PEG_TXN_15

RH24 1 2 24.9_0201_1% PEG_RCOMP G2

PEG_RCOMP
C C
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

D8 B8
<19> DMI_CRX_PTX_P0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_P0 <19>
<19> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <19>
DMI_RXN_0 DMI_TXN_0

<19> DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1 <19>

F6 DMI_RXP_1 DMI_TXP_1 B6
<19> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 <19>

<19> DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 <19>

E5 DMI_RXP_2 DMI_TXP_2 A5
<19> DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 <19>
J8 D4
<19> DMI_CRX_PTX_P3 DMI_RXP_3 3 OF 13 DMI_TXP_3
DMI_CTX_PRX_P3 <19>
J9 B4
<19> DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 <19>
CFL-H_BGA1440
@

CFL-H
UH1D

K36 D29
<35> CPU_DP1_P0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 <34>
<35> CPU_DP1_N0 K37 E29 EDP_TXN0 <34>
B
J35 DDI1_TXN_0 EDP_TXN_0 F28 B
<35> CPU_DP1_P1 DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 <34>
J34 E28
<35> CPU_DP1_N1 DDI1_TXN_1 EDP_TXN_1 EDP_TXN1 <34>
<35> CPU_DP1_P2 H37 A29 EDP_TXP2 <34>
To Alpine Ridge H36 DDI1_TXP_2 EDP_TXP_2 B29
<35> CPU_DP1_N2 DDI1_TXN_2 EDP_TXN_2 EDP_TXN2 <34>
<35> CPU_DP1_P3 J37 C28 EDP_TXP3 <34>
J38 DDI1_TXP_3 EDP_TXP_3 B28
<35> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <34>

<35> CPU_DP1_AUXP D27 C26 EDP_AUXP <34>

E27 DDI1_AUXP EDP_AUXP B26
<35> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN <34>
H34
<35> CPU_DP2_P0 DDI2_TXP_0 +VCCIO
H33
<35> CPU_DP2_N0 DDI2_TXN_0 EDP_DISP_UTIL
<35> CPU_DP2_P1 F37 A33 RH456 1 @ 2 0_0402_5% BIA_PWM_PCH <16,34>
G38 DDI2_TXP_1 EDP_DISP_UTIL
<35> CPU_DP2_N1 DDI2_TXN_1
<35> CPU_DP2_P2 F34
To Alpine Ridge F35 DDI2_TXP_2 D37 EDP_COMP RH30 1 2 24.9_0402_1%
<35> CPU_DP2_N2 DDI2_TXN_2 DISP_RCOMP
E37
<35> CPU_DP2_P3 DDI2_TXP_3
<35> CPU_DP2_N3 E36 EDP_COMP
DDI2_TXN_3 CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
F26
<35> CPU_DP2_AUXP DDI2_AUXP
E26
<35> CPU_DP2_AUXN DDI2_AUXN
C34
<39> CPU_DP3_P0 DDI3_TXP_0
<39> CPU_DP3_N0 D34
B36 DDI3_TXN_0
<39> CPU_DP3_P1 DDI3_TXP_1
B34
<39> CPU_DP3_N1 DDI3_TXN_1
<39> CPU_DP3_P2 F33
To DP to HDMI Converter E33 DDI3_TXP_2
(UM1/PS175B2) <39> CPU_DP3_N2
C33 DDI3_TXN_2 Close to CPU
<39> CPU_DP3_P3 DDI3_TXP_3
B33
<39> CPU_DP3_N3 DDI3_TXN_3 G27
PROC_AUDIO_CLK AUD_AZA_CPU_SCLK <18>
<39> CPU_DP3_AUXP A27 G25 AUD_AZA_CPU_SDO <18>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 AUD_AZA_CPU_SDI RH145 1 2 20_0402_5%
<39> CPU_DP3_AUXN DDI3_AUXN 4 ofPROC_AUDIO_SDO
13
AUD_AZA_CPU_SDI_R <18>

CFL-H_BGA1440
A @ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P07-CPU(1/7) DMI,PEG,DDI,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 7 of 76
5 4 3 2 1
 5 4 3 2 1

Interleave
CFL-H
UH1A CFL-H
UH1B
DDR CHANNEL A DDR CHANNEL B
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_B_D0 BT11 AM9
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 M_CLK_DDR0 <14> DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 M_CLK_DDR2 <15>
BT6 AG2 BR11 AN9
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 M_CLK_DDR#0 <14> DDR_B_D6 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 M_CLK_DDR#2 <15>
<14> DDR_A_D[0..63] BP3 AK2 M_CLK_DDR1 <14> BT9 AM7 M_CLK_DDR3 <15>
DDR_A_D7 BR3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 AK1 DDR_B_D2 BR8 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 AM8
<14> DDR_A_MA[0..13] DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 M_CLK_DDR#1 <14> DDR_B_D4 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 M_CLK_DDR#3 <15>
<14> DDR_A_DQS#[0..7] BN5 AL3 BP11 AM11
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
<14> DDR_A_DQS[0..7] DDR_A_D6 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR_B_D3 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2
BP2 AL2 BP8 AJ10
DDR_A_D3 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1 DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_A_D9 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_B_D12 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_A_D13 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_B_D8 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8
D DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_CKE0_DIMMA <14> DDR_B_D9 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_CKE2_DIMMB <15> D
BL2 AT2 BL8 AT10
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR_CKE1_DIMMA <14> DDR_B_D10 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 DDR_CKE3_DIMMB <15>
BM1 AT3 BJ8 AT7
<15> DDR_B_D[0..63] DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR_B_D14 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2
<15> DDR_B_MA[0..13] BK4 AT5 BJ11 AT11
DDR_A_D8 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_B_D11 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
<15> DDR_B_DQS#[0..7] DDR_A_D14 DDR0_DQ_13/DDR0_DQ_13 DDR_B_D13 DDR1_DQ_13/DDR0_DQ_29
<15> DDR_B_DQS[0..7] BK1 AD5 DDR_CS0_DIMMA# <14> BL7 AF11 DDR_CS2_DIMMB# <15>
DDR_A_D15 BK2 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 AE2 DDR_B_D15 BJ7 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 AE7
DDR_A_D20 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR_CS1_DIMMA# <14> DDR_B_D16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 DDR_CS3_DIMMB# <15>
BG4 AD2 BG11 AF10
DDR_A_D16 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_A_D23 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_B_D21 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7
DDR_A_D21 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 M_ODT0 <14> DDR_B_D18 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 M_ODT2 <15>
BG2 AE4 BF11 AE8
DDR_A_D17 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 M_ODT1 <14> DDR_B_D22 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 M_ODT3 <15>
BG1 AE1 BF10 AE9
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_B_D20 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_A_D18 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_B_D26 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BS0 <14> DDR_B_D24 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_RAS# <15>
BD1 AH1 BC11 AH11
DDR_A_D26 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BS1 <14> DDR_B_D31 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_WE# <15>
BC4 AU1 BB8 AF8
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <14> DDR_B_D25 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_CAS# <15>
BC5 BC8
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_RAS# <14> DDR_B_D30 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BS0 <15>
BD4 AG4 DDR_A_WE# <14> BB10 AH9 DDR_B_BS1 <15>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_B_D29 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_CAS# <14> DDR_B_D27 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <15>
BC2 BB7
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0 DDR_B_D34 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_A_D33 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D38 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D32 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
DDR_A_D35 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR_B_D36 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D35 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_A_D37 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D39 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D37 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_A_D39 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D33 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_A_D44 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_A_D45 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_A_D43 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D41 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_A_D47 U2 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AN2 DDR_A_MA11 DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_A_D41 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12 DDR_B_D43 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_A_D40 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_A_D42 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_B_D45 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_A_D46 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <14> DDR_B_D47 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13
C U4 AU3 DDR_A_ACT# <14> V7 AR7 DDR_B_BG1 <15> C
DDR_A_D53 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_B_D46 V8 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 AT9
DDR_A_D51 DDR0_DQ_48/DDR1_DQ_32 DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <15>
P5 AG3 DDR_A_PAR <14> R11
DDR_A_D49 R4 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR AU5 DDR_B_D51 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7
DDR_A_D55 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <14> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_PAR <15>
P4 P7 AR8
DDR_A_D52 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) DDR_B_D52 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <15>
R5 R8
DDR_A_D54 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0 DDR_B_D53 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D48 R1 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 BL3 DDR_A_DQS#1 DDR_B_D55 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_A_D50 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2 DDR_B_D49 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 DDR_B_DQS#1
DDR_A_D56 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#3 DDR_B_D54 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_B_DQS#2
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4 DDR_B_D58 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_B_DQS#3
DDR_A_D58 L4 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 U3 DDR_A_DQS#5 DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#4
DDR_A_D63 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6 DDR_B_D59 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 DDR_B_DQS#5
DDR_A_D60 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 DDR_A_DQS#7 DDR_B_D61 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_D62 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0 DDR_B_D60 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_A_D59 L1 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 BK3 DDR_A_DQS1 DDR_B_D56 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2 DDR_B_D63 L8 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 BJ9 DDR_B_DQS1
LP3/DDR4 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS3 DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4 AW11 LP3/DDR4 DDR1_DQSP_2/DDR0_DQSP_6 BB9 DDR_B_DQS3
BA1 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_A_DQS5 AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 DDR_B_DQS5
AY5 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 M3 DDR_A_DQS7 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7
BA4 NC/DDR0_ECC_4 AY3 AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM AY7 NC/DDR1_ECC_5 AW9 For ECC DIMM
AY2 NC/DDR0_ECC_6 1 OFDDR0_DQSN_8/DDR0_DQSN_8
13 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
For ECC DIMM NC/DDR0_ECC_7 For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
CFL-H_BGA1440
@

RH148 1 2 121_0201_1% DDR_RCOMP0 G1 BN13 +V_DDR_REFA_R

RH149 1 2 75_0201_1% DDR_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
DDR_RCOMP_1 DDR0_VREF_DQ +0.6V_A_VREFDQ
RH150 1 2 100_0201_1% DDR_RCOMP2 J2 2 OF 13 BR13
DDR_RCOMP_2 DDR1_VREF_DQ +V_DDR_REFB_R
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
B @ B

A A

Security Classification Compal Secret Data

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P08-CPU(2/7) DDR4

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 8 of 76
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

+VCCST

CFL-H
Stall reset sequence after PCU PLL lock until de-asserted 1 2 H_THERMTRIP#_R UH1E
RH163 1K_0402_5%

1 2 XDP_PREQ# B31 BN25 CFG0

1 = (Default) Normal Operation; No stall. @
CFG0 * RH156 51_0201_5%
H_VCCST_PWRGD
<17>
<17>
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N A32 BCLKP
BCLKN
CFG_0
CFG_1
CFG_2
BN27
BN26
CFG1
CFG2
CFG0
CFG1
CFG2
<6>
<6>
<6>
1 2 <17> PCH_CPU_PCIBCLK_P D35 BN28 CFG3 CFG3 <6>
D
C36 PCI_BCLKP CFG_3 BR20 CFG4 D
0 = Stall. RH164 1K_0402_5% <17> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG_4 CFG4 <6>
BM20 CFG5
VR_SVID_DATA CFG_5 CFG5 <6>
1 2 <17> CPU_24MHZ_P E31 BT20 CFG6 CFG6 <6>
RH151 100_0402_5% D31 CLK24P CFG_6 BP20 CFG7
<17> CPU_24MHZ_N CLK24N CFG_7 CFG7 <6>
CFG0 1 @ 2 BR23 CFG8 CFG8 <6>
RH183 1K_0402_5% 1 2 VR_SVID_ALERT# CFG_8 BR22 CFG9
CFG_9 CFG9 <6>
RH152 56.2_0402_1% BT23 CFG10
CFG_10 CFG10 <6>
BT22 CFG11 CFG11 <6>
1 @ 2 H_CATERR# CFG_11 BM19 CFG12
CFG_12 CFG12 <6>
RH570 49.9_0201_1% BR19 CFG13 CFG13 <6>
CFG_13 BP19 CFG14
VR_SVID_ALERT# CFG_14 CFG14 <6>
RH153 1 2 220_0402_5% VR_SVID_ALERT#_R BH31 BT19 CFG15
<62> VR_SVID_ALERT# VIDALERT# CFG_15 CFG15 <6>
<62> VR_SVID_CLK BH32
VR_SVID_DATA BH29 VIDSCK BN23 CFG17
<62> VR_SVID_DATA H_PROCHOT# VIDSOUT CFG_17 CFG17 <6>
<48,58,62> H_PROCHOT# RH158 1 2 499_0201_1% H_PROCHOT#_R BR30 BP23 CFG16 CFG16 <6>
+VCCSTG PROCHOT# CFG_16 BP22
Display Port Presence Strap DDR_VTT_PG_CTRL CFG_19
CFG19 CFG19 <6>
BT13 BN22 CFG18
DDR_VTT_CNTL CFG_18 CFG18 <6>

1 : Disabled; No Physical Display Port

CFG4 BR27
attached to Embedded Display Port 1 2 H_PROCHOT# BPM#_0 BT27
XDP_BPM#0 <6>
BPM#_1 CPU_BPM#2 XDP_BPM#1 <6>
RH165 1K_0201_5% BM31 T4971 PAD~D @
H_VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#_2 BT30 CPU_BPM#3
0 : Enabled; An external Display Port device is T4972 PAD~D @
* connected to the Embedded Display Port
<6,33> H_VCCST_PWRGD

<18> H_CPUPWRGD
RH154 60.4_0402_1%
PLTRST_CPU#
BT31
VCCST_PWRGD

PROCPWRGD
BPM#_3

CPU_XDP_TDO
BP35 BT28
<6,16> PLTRST_CPU# H_PM_SYNC_R RESET# PROC_TDO CPU_XDP_TDI CPU_XDP_TDO <6>
BM34 BL32
<16> H_PM_SYNC_R H_PM_DOWN H_PM_DOWN_R PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <6>
<16> H_PM_DOWN RH155 1 2 20_0402_5% BP31 BP28 CPU_XDP_TMS <6>
CFG4 1 2 RH190 1 @ 2 0_0402_1% H_PECI_R BT34 PM_DOWN PROC_TMS BR28 CPU_XDP_TCK
<16,48> H_PECI H_THERMTRIP#_R PECI PROC_TCK CPU_XDP_TCK <6>
RH185 1K_0402_5% <16,48> H_THERMTRIP#_R J31
THERMTRIP# BP30 CPU_XDP_TRST#
PROC_DETECT#_R PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <6,22>
RH519 1 @ 2 0_0402_5% BR33 BL30
<16> PROC_DETECT# SKTOCC# PROC_PREQ# XDP_PRDY# XDP_PREQ# <6,22>
BN1 BP27 XDP_PRDY# <6,22>
RH1958 1 2 0_0402_5% PROC_SELECT# PROC_PRDY#
H_CATERR# BM30
CATERR# BT25 CFG_RCOMP
@ PAD~D T4969 CEZVM# AT13 CFG_RCOMP
@ PAD~D T4970 CEMSM# AW13 ZVM#
C C
MSM#

1
PCIE Port Bifurcation Straps
+1.2V_DDR @ PAD~D T4967 CERSVD1 AU13 RH59
UC1 @ PAD~D T4968 CERSVD2 AY13 RSVD1 49.9_0201_1%
5 1 RSVD2
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: +3VS VCC NC 5 OF 13

2
2 DDR_VTT_PG_CTRL
CFG[6:5] x8, x8 - Device 1 function 1 enabled ; function 2 1 A
@ 4 CFL-H_BGA1440
disabled Y

1
CH197 3 @
GND
01: Reserved - (Device 1 function 1 disabled ; function RH525
2
0.1U_0402_10V7K
100K_0402_5% 74AUP1G07GW_TSSOP5
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

2
H_PECI_R

<61> SM_PG_CTRL

1
CFG2 1 2
RH184 1K_0402_5% RH200
@ 300_0201_1%

2
CFG5 1 @ 2
RH186 1K_0402_5%
CFL-H
CFG6 1 @ 2 UH1M
RH187 1K_0402_5%
CMRSVD_TP5 E2
Impedance Spectrum Tool Trigger @ PAD~D T39
IST_TRIG_T RSVD_TP5
@ PAD~D T40 E3
@ PAD~D T41 CMRSVD_TP4 E1 IST_TRIG
@ PAD~D T42 CMRSVD_TP3 D1 RSVD_TP4
RSVD_TP3
@ PAD~D T43 CMRSVD_TP1 BR1 BK28 CMRSVD11 T66 PAD~D @
CMRSVD_TP2 BT2 RSVD_TP1 RSVD11 BJ28
PEG DEFER TRAINING @ PAD~D T44
RSVD_TP2 RSVD10
CMRSVD10 T67 PAD~D @

@ PAD~D T45 CMRSVD15 BN35

RSVD15
1: (Default) PEG Train immediately following xxRESETB
B
CFG7 * de assertion @
@
PAD~D
PAD~D
T46
T47
CMRSVD28
CMRSVD27
J24
H24 RSVD28
RSVD27
B

@ PAD~D T48 CMRSVD14 BN33

CMRSVD13 BL34 RSVD14
0: PEG Wait for BIOS for training @ PAD~D T49
RSVD13
@ PAD~D T50 CMRSVD30 N29
@ PAD~D T51 CMRSVD31 R14 RSVD30
CFG7 1 @ 2 @ PAD~D T52 CMRSVD2 AE29 RSVD31
RH188 1K_0402_5% @ PAD~D T53 CMRSVD1 AA14 RSVD2
@ PAD~D T4966 CMRSVD5 AP29 RSVD1
@ PAD~D T4965 CMRSVD4 AP14 RSVD5
A36 RSVD4
VSS_A36
A37
VSS_A37
PCH_TRIGGER RH167 1 2 30_0402_5% PCH_TRIGGER_R H23
<22> PCH_TRIGGER CPU_TRIGGER CPU_TRIGGER_R PROC_TRIGIN
<22> CPU_TRIGGER RH192 1 2 30_0402_5% J23
PROC_TRIGOUT
@ PAD~D T57 CMRSVD24 F30
RSVD24

@ PAD~D T58 CMRSVD23 E30

RSVD23

@ PAD~D T59 CMRSVD7 B30 BL31 CMRSVD12 T82 PAD~D @

@ PAD~D T60 CMRSVD21 C30 RSVD7 RSVD12 AJ8 CMRSVD3 T83 PAD~D @
RSVD21 RSVD3 G13 CMRSVD25 T84 PAD~D @
RSVD25
@ PAD~D T61 CMRSVD26 G3
@ PAD~D T62 CMRSVD29 J3 RSVD26 C38 CMRSVD22 T85 PAD~D @
RSVD29 RSVD22 C1 CMRSVD20 T86 PAD~D @
RSVD20 BR2 CMRSVD17 T87 PAD~D @
@ PAD~D T63 CMRSVD19 BR35 RSVD17 BP1 CMRSVD16 T88 PAD~D @
@ PAD~D T64 CMRSVD18 BR31 RSVD19 RSVD16 B38 CMRSVD8 T89 PAD~D @
@ PAD~D T65 CMRSVD9 BH30 RSVD18 RSVD8 B2 CMRSVD6 T90 PAD~D @
RSVD9 RSVD6
13 OF 13
A A
CFL-H_BGA1440
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P09-CPU(3/7) RSVD,CFG,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 9 of 76
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE

96000mA(Hexa Core GT2)

D D

CFL-H
CFL-H UH1J
UH1I
AA13 AH13 K14 W35
AA31 VCC1 VCC64 AH14 L13 VCC1 VCC64 W36
AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
AA37 VCC7 VCC70 AJ29 N32 VCC7 VCC70 Y32
AA38 VCC8 VCC71 AJ30 N35 VCC8 VCC71 Y33
AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AB35 VCC13 VCC76 AJ35 P14 VCC13
AB36 VCC14 VCC77 AJ36 P29 VCC14
AB37 VCC15 VCC78 AK31 P30 VCC15
AB38 VCC16 VCC79 AK32 P31 VCC16
AC13 VCC17 VCC80 AK33 P32 VCC17
AC14 VCC18 VCC81 AK34 P33 VCC18
AC29 VCC19 VCC82 AK35 P34 VCC19
AC30 VCC20 VCC83 AK36 P35 VCC20
AC31 VCC21 VCC84 AK37 P36 VCC21
AC32 VCC22 VCC85 AK38 R13 VCC22
AC33 VCC23 VCC86 AL13 R31 VCC23
AC34 VCC24 VCC87 AL29 R32 VCC24
AC35 VCC25 VCC88 AL30 R33 VCC25
AC36 VCC26 VCC89 AL31 R34 VCC26
C
AD13 VCC27 VCC90 AL32 R35 VCC27 C
AD14 VCC28 VCC91 AL35 R36 VCC28
AD31 VCC29 VCC92 AL36 R37 VCC29
AD32 VCC30 VCC93 AL37 R38 VCC30
AD33 VCC31 VCC94 AL38 T29 VCC31
AD34 VCC32 VCC95 AM13 T30 VCC32
AD35 VCC33 VCC96 AM14 T31 VCC33
AD36 VCC34 VCC97 AM29 T32 VCC34
AD37 VCC35 VCC98 AM30 T35 VCC35
AD38 VCC36 VCC99 AM31 T36 VCC36
AE13 VCC37 VCC100 AM32 T37 VCC37
AE14 VCC38 VCC101 AM33 T38 VCC38
AE30 VCC39 VCC102 AM34 U29 VCC39
AE31 VCC40 VCC103 AM35 U30 VCC40
AE32 VCC41 VCC104 AM36 U31 VCC41
AE35 VCC42 VCC105 AN13 U32 VCC42
AE36 VCC43 VCC106 AN14 U33 VCC43
AE37 VCC44 VCC107 AN31 U34 VCC44
AE38 VCC45 VCC108 AN32 U35 VCC45
AF29 VCC46 VCC109 AN33 U36 VCC46
AF30 VCC47 VCC110 AN34 V13 VCC47
AF31 VCC48 VCC111 AN35 V14 VCC48
AF32 VCC49 VCC112 AN36 V31 VCC49
AF33 VCC50 VCC113 AN37 V32 VCC50
AF34 VCC51 VCC114 AN38 V33 VCC51
AF35 VCC52 VCC115 AP13 V34 VCC52
AF36 VCC53 VCC116 AP30 V35 VCC53
AF37 VCC54 VCC117 AP31 V36 VCC54
AF38 VCC55 VCC118 AP32 V37 VCC55
AG14 VCC56 VCC119 AP35 +VCC_CORE V38 VCC56
AG31 VCC57 VCC120 AP36 W13 VCC57
AG32 VCC58 VCC121 AP37 W14 VCC58
AG33 VCC59 VCC122 AP38 W29 VCC59
VCC60 VCC123 VCC60
1

AG34 K13 W30

AG35 VCC61 VCC124 RH197 W31 VCC61
B B
AG36 VCC62 W32 VCC62 10 OF 13
VCC63 100_0402_1% VCC63
CFL-H_BGA1440
2

VCC_SENSE_R @
AG37 RH198 1 @ 2 0_0402_1% VCC_SENSE <62>
9 OF 13 VCC_SENSE AG38 VSS_SENSE_R RH465 1 @ 2 0_0402_1%
VSS_SENSE VSS_SENSE <62>
CFL-H_BGA1440
1

@
RH466
100_0402_1%
2

1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC10, RC11 should be placed within 2 inches (50.8 mm) of CPU

A A

Security Classification Compal Secret Data

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P10-CPU(4/7) PWR,VCore,RSVD
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 10 of 76
5 4 3 2 1
 5 4 3 2 1

570805_CFL_EDS_Vol1_Rev0.7
+1.2V_VDDQ_CPU
Max: 3300mA
570805_CFL_EDS_Vol1_Rev0.7
+VCC_SA +1.2V_DDR
Max: 11100mA VDDQ_DDR 571483_CFL_H_RVP_CRB_TDK_Rev0p5
D D
+1.05VS_VCCSTG: 1uF * 1
@ PJP1604
+VCCSA 1 2
Board Edge cap
PAD-OPEN 3x3m
A00_4P_0524 : Material shortage issue
+VCCSTG +VCCST EE remove 2pcs SE00000ZH00 and power add 5pcs SE00001CA00
CFL-H +VCCSA +VCCSA
UH1L

J30 AA6
VCCSA1 VDDQ1

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

10U_0402_6.3V6M
K29 AE12
VCCSA2 VDDQ2

22U_0603_6.3V6M

22U_0603_6.3V6M

47U_0805_4VAM

47U_0805_4VAM
K30 AF5 1 1 1 1 1 1
VCCSA3 VDDQ3

CH105

CH106

CH107

CH108

CH109

CH110
K31 AF6 1 1
VCCSA4 VDDQ4

1
CH134

CH135

CH136

CH138
K32 AG5
K33 VCCSA5 VDDQ5 AG9 @ @
K34 VCCSA6 VDDQ6 AJ12 2 2 2 2 2 2

2
K35 VCCSA7 VDDQ7 AL11 2 2
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12
L36 VCCSA11 VDDQ11 AR6
L37 VCCSA12 VDDQ12 AT12
L38 VCCSA13 VDDQ13 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6 +VCCSA +VCCSA
M32 VCCSA17 VDDQ17 K12
570805_CFL_EDS_Vol1_Rev0.7 M33 VCCSA18 VDDQ18 K6
+VCC_IO M34 VCCSA19 VDDQ19 L12 570805_CFL_EDS_Vol1_Rev0.7 +1.2V_VCCPLL_OC +VCCST
Max: 6400mA
M35 VCCSA20 VDDQ20 L6 +1.2V_VCCPLL_OC
M36 VCCSA21 VDDQ21 R6 Max: 130mA
+VCCIO VCCSA22 VDDQ22

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M
C T6 C
VDDQ23 W6 +1.2V_VCCPLL_OC +1.2V_DDR

1U_0201_6.3V6M

1U_0201_6.3V6M
VDDQ24 1 1 1 1 1 1 1 1

4.7U_0402_6.3V6M
CH3334

CH111

CH112

CH113

CH114

CH115

CH116

CH117

CH133
Y12 1 1 1
AG12 VDDQ25 RH530 1 @ 2 0_0402_5%
G15 VCCIO1

CH3332

CH3333
G17 VCCIO2 2 2 2 2 2 2 2 2
G19 VCCIO3 BH13 2 2 2
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA
H19 VCCIO8 VCCST +VCCSTG
H20 VCCIO9 H29 Max: 20mA
H21 VCCIO10 VCCSTG2
H26 VCCIO11 G30
close CPU ball close CPU ball
VCCIO12 VCCSTG1
H27
VCCIO13
+VCCST H28,J28
J15 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 RH201 1 2 100_0402_1%
VCCIO17 VCCSA_SENSE_R +VCCSA
J20 M38 RH202 1 @ 2 0_0402_1% VCCSA_SENSE <62>
J21 VCCIO18 VCCSA_SENSE M37 VSSSA_SENSE_R RH470 1 @ 2 0_0402_1%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <62>
J26 RH469 1 2 100_0402_1%
J27 VCCIO20 H14
VCCIO21 VCCIO_SENSE J14
12 OF 13 VSSIO_SENSE
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
CFL-H_BGA1440 3. RC15, RC16 should be placed within 2 inches (50.8 mm) of CPU
@

B
VCCIO_SENSE <73> B
VSSIO_SENSE <73>

Backside cap Backside cap

+VCCIO

VDDQ_DDR VDDQ_DDR

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1

CH102

CH103

CH104

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1
2 2 2 1 1 1 1 1 1 1 1 1 1 1

CH129

CH130

CH131

CH132

CH118

CH121

CH124

CH120

CH119

CH122

CH123

CH125

CH126

CH127

CH128
2 2 2 2
2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P11-CPU(5/7) PWR,VDDR,VSA,VIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 11 of 76
5 4 3 2 1
 5 4 3 2 1

+VCCGT
GT +VCCGT
55000mA(Hexa Core GT2)
CFL-H
UH1K
AT14 BD35
AT31 VCCGT1 VCCGT80 BD36
AT32 VCCGT2 VCCGT81 BE31
AT33 VCCGT3 VCCGT82 BE32
AT34 VCCGT4 VCCGT83 BE33
D AT35 VCCGT5 VCCGT84 BE34 D
AT36 VCCGT6 VCCGT85 BE35
AT37 VCCGT7 VCCGT86 BE36
AT38 VCCGT8 VCCGT87 BE37
AU14 VCCGT9 VCCGT88 BE38
AU29 VCCGT10 VCCGT89 BF13
AU30 VCCGT11 VCCGT90 BF14
AU31 VCCGT12 VCCGT91 BF29
AU32 VCCGT13 VCCGT92 BF30
AU35 VCCGT14 VCCGT93 BF31
AU36 VCCGT15 VCCGT94 BF32
AU37 VCCGT16 VCCGT95 BF35
AU38 VCCGT17 VCCGT96 BF36
AV29 VCCGT18 VCCGT97 BF37
AV30 VCCGT19 VCCGT98 BF38
AV31 VCCGT20 VCCGT99 BG29
AV32 VCCGT21 VCCGT100 BG30
AV33 VCCGT22 VCCGT101 BG31
AV34 VCCGT23 VCCGT102 BG32
AV35 VCCGT24 VCCGT103 BG33
AV36 VCCGT25 VCCGT104 BG34
AW14 VCCGT26 VCCGT105 BG35
AW31 VCCGT27 VCCGT106 BG36
AW32 VCCGT28 VCCGT107 BH33
AW33 VCCGT29 VCCGT108 BH34
AW34 VCCGT30 VCCGT109 BH35
AW35 VCCGT31 VCCGT110 BH36
AW36 VCCGT32 VCCGT111 BH37
AW37 VCCGT33 VCCGT112 BH38
AW38 VCCGT34 VCCGT113 BJ16
AY29 VCCGT35 VCCGT114 BJ17
AY30 VCCGT36 VCCGT115 BJ19
C AY31 VCCGT37 VCCGT116 BJ20 C
AY32 VCCGT38 VCCGT117 BJ21
AY35 VCCGT39 VCCGT118 BJ23
AY36 VCCGT40 VCCGT119 BJ24
AY37 VCCGT41 VCCGT120 BJ26
AY38 VCCGT42 VCCGT121 BJ27
BA13 VCCGT43 VCCGT122 BJ37
BA14 VCCGT44 VCCGT123 BJ38
BA29 VCCGT45 VCCGT124 BK16
BA30 VCCGT46 VCCGT125 BK17
BA31 VCCGT47 VCCGT126 BK19
BA32 VCCGT48 VCCGT127 BK20
BA33 VCCGT49 VCCGT128 BK21
BA34 VCCGT50 VCCGT129 BK23
BA35 VCCGT51 VCCGT130 BK24
BA36 VCCGT52 VCCGT131 BK26
BB13 VCCGT53 VCCGT132 BK27
BB14 VCCGT54 VCCGT133 BL15
BB31 VCCGT55 VCCGT134 BL16
BB32 VCCGT56 VCCGT135 BL17
BB33 VCCGT57 VCCGT136 BL23
BB34 VCCGT58 VCCGT137 BL24
BB35 VCCGT59 VCCGT138 BL25
BB36 VCCGT60 VCCGT139 BL26
BB37 VCCGT61 VCCGT140 BL27
BB38 VCCGT62 VCCGT141 BL28
BC29 VCCGT63 VCCGT142 BL36
BC30 VCCGT64 VCCGT143 BL37
BC31 VCCGT65 VCCGT144 BM15
BC32 VCCGT66 VCCGT145 BM16
BC35 VCCGT67 VCCGT146 BM17
BC36 VCCGT68 VCCGT147 BM36
B BC37 VCCGT69 VCCGT148 BM37 B
BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
BD14 VCCGT72 VCCGT151 BN17
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37 +VCCGT
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15

1
BR15 VCCGT160 VCCGT165 BT16
VCCGT161 VCCGT166 RH203
BR16 BT17
BR17 VCCGT162 VCCGT167 BT37 100_0402_1%
VCCGT163 VCCGT168
2
AH37 VSSGT_SENSE_R RH204 1 @ 2 0_0402_1%
11 OF VSSGT_SENSE
13 VCCGT_SENSE_R VSSGT_SENSE <62>
AH38 RH471 1 @ 2 0_0402_1% VCCGT_SENSE <62>
VCCGT_SENSE
CFL-H_BGA1440
@
1

RH472
100_0402_1%

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2

2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC12, RC13 should be placed within 2 inches (50.8 mm) of CPU
A A

Security Classification Compal Secret Data Compal Electronics,TitleInc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P12-CPU(6/7) PWR,VGT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 12 of 76
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

CFL-H CFL-H CFL-H

UH1F UH1G UH1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BN7 VSS_325 VSS_409 F17
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP12 VSS_326 VSS_410 F19
D A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP14 VSS_327 VSS_411 F2 D
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP18 VSS_328 VSS_412 F21
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP21 VSS_329 VSS_413 F23
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP24 VSS_330 VSS_414 F25
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP25 VSS_331 VSS_415 F27
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP26 VSS_332 VSS_416 F29
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP29 VSS_333 VSS_417 F3
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP33 VSS_334 VSS_418 F31
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR34 VSS_345 VSS_429 G20
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR36 VSS_346 VSS_430 G22
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BR7 VSS_347 VSS_431 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT14 VSS_349 VSS_433 G26
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT18 VSS_350 VSS_434 G28
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18
C AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22 C
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C25 VSS_364 VSS_448 J18
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C27 VSS_365 VSS_449 J22
AF2 VSS_42 VSS_123 AR36 BE4 VSS_204 VSS_285 BM25 C29 VSS_366 VSS_450 J25
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C31 VSS_367 VSS_451 J32
AF4 VSS_44 VSS_125 AR38 BE6 VSS_206 VSS_287 BM27 C37 VSS_368 VSS_452 J33
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D16 VSS_375 VSS_459 K2
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D18 VSS_376 VSS_460 K3
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D28 VSS_381 VSS_465 K8
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D3 VSS_382 VSS_466 K9
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E34 VSS_387 VSS_471 M12
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11
B AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12 B
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 N9 VSS_400 VSS_B3 B37
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 VSS_162 VSS_243 VSS_324 N1 VSS_405 VSS_BT36 BT4
CFL-H_BGA1440 CFL-H_BGA1440 F11 VSS_406 VSS_BT4 C2
F13 VSS_4078 OF 13
VSS_C2 D38
@ @ VSS_408 VSS_D38
CFL-H_BGA1440
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P13-CPU(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 13 of 76
5 4 3 2 1
 5 4 3 2 1

<8> DDR_A_D[0..63]
<8> DDR_A_MA[0..13] JDIMM1
+1.2V_DDR JP?
<8> DDR_A_DQS#[0..7] +1.2V_DDR
<8> DDR_A_DQS[0..7]
1 2
DDR_A_D5 3 VSS1 VSS2 4 DDR_A_D4
Layout Note: Layout Note: DQ5 DQ4
5 6
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D1 7 VSS3 VSS4 8 DDR_A_D0
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17 VSS8 DQ6 18
+2.5V_MEM +0.6VS 19 DQ7 VSS9 20 DDR_A_D2
DDR_A_D3 21 VSS10 DQ2 22
Layout Note: DQ3 VSS11 DDR_A_D12
23 24
Place near JDIMM1.255 DDR_A_D13 25 VSS12 DQ12 26
DQ13 VSS13 DDR_A_D8

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
D 27 28 D
DDR_A_D9 VSS14 DQ8
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
29 30
1U_0402_6.3V6K DQ9 VSS15 DDR_A_DQS#1

1U_0402_6.3V6K
1 1 1 1 31 32
VSS16 DQS1_c DDR_A_DQS1

CD12

CD13

CD14

CD15
1 1 1 1 33 34
DM1_n/DBI_n DQS1_t
CD3

CD4
35 36
DDR_A_D15 VSS17 VSS18 DDR_A_D14
CD9

CD10

37 38
2 2 2 2 +3VS 39 DQ15 DQ14 40
2 2 2 2 DDR_A_D10 41 VSS19 VSS20 42 DDR_A_D11
43 DQ10 DQ11 44
DDR_A_D21 45 VSS21 VSS22 46 DDR_A_D20
47 DQ21 DQ20 48
DDR_A_D17 VSS23 VSS24 DDR_A_D16

.1U_0402_16V7K
49 50
51 DQ17 DQ16 52
1 1 DDR_A_DQS#2 VSS25 VSS26

CD16
53 54
CD17 DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
2.2U_0402_6.3V6M 57 DQS2_t VSS27 58 DDR_A_D22
2 2 DDR_A_D23 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D18
DDR_A_D19 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D28
DDR_A_D29 67 VSS32 DQ28 68
Layout Note: DQ29 VSS33 DDR_A_D24
69 70
Place near JDIMM1 DDR_A_D25 71 VSS34 DQ24 72
DQ25 VSS35

73 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
+1.2V_DDR 77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D30 79 VSS37 VSS38 80 DDR_A_D31
81 DQ30 DQ31 82
DDR_A_D26 83 VSS39 VSS40 84 DDR_A_D27
DQ26 DQ27
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

85 86
87 VSS41 VSS42 88
1 1 1 1 1 1 1 1 CB5/NC CB4/NC
CD1

CD2

CD75

CD74

CD77

CD76

CD79

CD78

89 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
2 2 2 2 2 2 2 2 95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C 103 CB2/NC VSS49 104 C
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108
DDR_CKE0_DIMMA VSS52 RESET_n DDR_CKE1_DIMMA DDR4_DRAMRST# <14,15>
109 110
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
111 112
+1.2V_DDR DDR_A_BG1 VDD1 VDD2

.1U_0402_16V7K
113 114
<8> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <8>
115 116 1 @
<8> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <8>

CD3326
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
A9 A7 2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

123 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
1 DDR_A_MA6 A8 A5 DDR_A_MA4
1 1 1 1 1 1 1 1 127 128
+ CD11 129 A6 A4 130
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
CD5

CD6

CD7

CD8

CD70

CD71

CD72

CD73

220U_D7_2VM_R6M 131 132

DDR_A_MA1 133 A3 A2 134 All VREF traces should
2 2 2 2 2 2 2 2 2 135 A1 EVENT_n/NF 136
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
have 10 mil trace width
137 138
<8> M_CLK_DDR0 M_CLK_DDR#0 CK0_t CK1_t/NF M_CLK_DDR#1 M_CLK_DDR1 <8>
139 140
<8> M_CLK_DDR#0 CK0_c CK1_c/NF M_CLK_DDR#1 <8>
141 142
DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
<8> DDR_A_PAR DDR_A_BS1 PARITY A0 DDR_A_MA10
145 146
<8> DDR_A_BS1 BA1 A10/AP
147 148
DDR_CS0_DIMMA# 149 VDD13 VDD14 150 DDR_A_BS0
<8> DDR_CS0_DIMMA# DDR_A_WE# CS0_n BA0 DDR_A_RAS# DDR_A_BS0 <8>
151 152
<8> DDR_A_WE# WE_n/A14 RAS_n/A16 DDR_A_RAS# <8>
153 154
M_ODT0 155 VDD15 VDD16 156 DDR_A_CAS#
<8> M_ODT0 DDR_CS1_DIMMA# ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_CAS# <8>
<8> DDR_CS1_DIMMA#
157 158
159 CS1_n A13 160
M_ODT1 161 VDD17 VDD18 162 +V_DDR_REFA
<8> M_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFA
163 164
165 VDD19 VREFCA 166 DIMM_CHA_SA2 20mil
167 C1, CS3_n,NC SA2 168
DDR_A_D37 VSS53 VSS54 DDR_A_D36

.1U_0402_16V7K
169 170
171 DQ37 DQ36 172
DDR_A_D33 VSS55 VSS56 DDR_A_D32 1

CD18
173 174
175 DQ33 DQ32 176
+1.2V_DDR DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180
+1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_A_D39
B +3VS +3VS +3VS DDR_A_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_A_D35
DDR_A_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D45
VSS64 DQ45
1

DDR_A_D44 191 192

DQ44 VSS65
1

RD35 193 194 DDR_A_D41

RD1 RD2 RD3 470_0402_1% DDR_A_D40 195 VSS66 DQ41 196
@ @ @ 197 DQ40 VSS67 198 DDR_A_DQS#5
0_0402_5% 0_0402_5% 0_0402_5% VSS68 DQS5_c DDR_A_DQS5
199 200
+1.2V_DDR
2

201 DM5_n/DBI5_n DQS5_t 202

2

DDR_A_D46 203 VSS69 VSS70 204 DDR_A_D47

DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2 DDR4_DRAMRST#RD31 1 @ 20_0402_1% 205 DQ46 DQ47 206
<14,15> DDR4_DRAMRST# H_DRAMRST# <18> DDR_A_D42 VSS71 VSS72 DDR_A_D43
207 208
209 DQ42 DQ43 210
VSS73 VSS74
1

DDR_A_D52 DDR_A_D53
.1U_0402_16V7K

211 212
RD28 RD29 RD30 @ 213 DQ52 DQ53 214
1 DDR_A_D49 VSS75 VSS76 DDR_A_D48
CD69

0_0402_1% 0_0402_1% 0_0402_1% 215 216

@ @ @ 217 DQ49 DQ48 218
DDR_A_DQS#6 219 VSS77 VSS78 220
+1.2V_DDR
2

2 DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222

223 DQS6_t VSS79 224 DDR_A_D54
DDR_A_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D50
DDR_A_D51 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D60
DDR_A_D61 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D57
VREF traces should be at least 20 mils DDR_A_D56 237 VSS86 DQ57 238
wide with 20 mils spacing to other 239 DQ56
VSS88
VSS87
DQS7_c
240 DDR_A_DQS#7
DDR_A_DQS7
241 242
signals +1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
DDR_A_D62 245 VSS89 VSS90 246 DDR_A_D63
247 DQ62 DQ63 248
CPU Side +V_DDR_REFA_R +1.2V_DDR
DDR_A_D58

PCH_SMBCLK
249
251
VSS91
DQ58
VSS93
VSS92
DQ59
VSS94
250
252
DDR_A_D59

PCH_SMBDATA
253 254
<6,15,18,44> PCH_SMBCLK SCL SDA DIMM_CHA_SA0 PCH_SMBDATA <6,15,18,44>
255 256
+3VS VDDSPD SA0
257 258
DIMM Side +2.5V_MEM VPP1 VTT +0.6VS
1

259 260 DIMM_CHA_SA1

20mil RH206 261 VPP2 SA1 262
A 1K_0402_1% GND1 GND2 A

+V_DDR_REFA
2

RH484 1 2 2_0402_1% +V_DDR_REFA BELLW_SD-80886-1021 CONN@

20mil
1
1

CH101 RH209
0.022U_0402_25V7K 1K_0402_1%
2
1

Security Classification Compal Secret Data Compal Electronics, Inc.

2

RH211
24.9_0402_1% Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

WWW.AliSaler.Com
P14-DDR4 DIMMA
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 14 of 76
5 4 3 2 1
 5 4 3 2 1

JDIMM2
+1.2V_DDR JP?
<8> DDR_B_D[0..63] +1.2V_DDR
<8> DDR_B_MA[0..13]
1 2
<8> DDR_B_DQS#[0..7] DDR_B_D5 VSS1 VSS2 DDR_B_D4
3 4
<8> DDR_B_DQS[0..7] DQ5 DQ4
Layout Note: Layout Note: 5 6
DDR_B_D1 7 VSS3 VSS4 8 DDR_B_D0
Place near JDIMM1.258 Place near JDIMM2.257,259 9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D6
DDR_B_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D2
DDR_B_D3 21 VSS10 DQ2 22
+0.6VS +2.5V_MEM 23 DQ3 VSS11 24 DDR_B_D12
DDR_B_D13 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_B_D8 D
DDR_B_D9 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
VSS16 DQS1_c DDR_B_DQS1
1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
Layout Note: 33 34
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 Place near JDIMM2.255 DDR_B_D15 VSS17 VSS18 DDR_B_D14
CD32

CD30

CD31
37 38
DQ15 DQ14
CD90

CD89

CD88

CD27

CD28
39 40
DDR_B_D10 41 VSS19 VSS20 42 DDR_B_D11
2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
DDR_B_D21 45 VSS21 VSS22 46 DDR_B_D20
47 DQ21 DQ20 48
DDR_B_D17 49 VSS23 VSS24 50 DDR_B_D16
+3VS 51 DQ17 DQ16 52
DDR_B_DQS#2 53 VSS25 VSS26 54
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D22
DDR_B_D23 59 VSS28 DQ22 60
DQ23 VSS29 DDR_B_D18

.1U_0402_16V7K
61 62
DDR_B_D19 63 VSS30 DQ18 64
1 1 DQ19 VSS31 DDR_B_D28

CD34
65 66
CD35 DDR_B_D29 67 VSS32 DQ28 68
2.2U_0402_6.3V6M 69 DQ29 VSS33 70 DDR_B_D24
2 2 DDR_B_D25 71 VSS34 DQ24 72
DQ25 VSS35
Layout Note: DDR_B_DQS#3
73 74
Place near JDIMMB 75 VSS36 DQS3_c 76 DDR_B_DQS3
77 DM3_n/DBI3_n DQS3_t 78
DDR_B_D30 79 VSS37 VSS38 80 DDR_B_D31
81 DQ30 DQ31 82
DDR_B_D26 83 VSS39 VSS40 84 DDR_B_D27
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
+1.2V_DDR 93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
VSS48 CB6/NC
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

101 102
C 103 CB2/NC VSS49 104 C
1 1 1 1 1 1 1 1 VSS50 CB7/NC
CD19

CD20

CD21

CD22

CD83

CD81

CD80

CD82

105 106
107 CB3/NC VSS51 108
DDR_CKE2_DIMMB VSS52 RESET_n DDR_CKE3_DIMMB DDR4_DRAMRST# <14>
109 110
2 2 2 2 2 2 2 2 <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
111 112
DDR_B_BG1 VDD1 VDD2

.1U_0402_16V7K
113 114
<8> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8>
115 116 1 @
<8> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <8>

CD3327
117 118
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
123 A9 A7 124 2
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
+1.2V_DDR DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134 All VREF traces should
135 A1 EVENT_n/NF 136
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
have 10 mil trace width
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

137 138
<8> M_CLK_DDR2 M_CLK_DDR#2 CK0_t CK1_t/NF M_CLK_DDR#3 M_CLK_DDR3 <8>
1 139 140
<8> M_CLK_DDR#2 CK0_c CK1_c/NF M_CLK_DDR#3 <8>
1 1 1 1 1 1 1 1 141 142
+ CD33 DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
<8> DDR_B_PAR DDR_B_BS1 PARITY A0 DDR_B_MA10
CD23

CD24

CD25

CD26

CD87

CD85

CD84

CD86

220U_D7_2VM_R6M 145 146

<8> DDR_B_BS1 BA1 A10/AP
147 148
2 2 2 2 2 2 2 2 2 DDR_CS2_DIMMB# 149 VDD13 VDD14 150 DDR_B_BS0
<8> DDR_CS2_DIMMB# DDR_B_WE# CS0_n BA0 DDR_B_RAS# DDR_B_BS0 <8>
151 152
<8> DDR_B_WE# WE_n/A14 RAS_n/A16 DDR_B_RAS# <8>
153 154
M_ODT2 155 VDD15 VDD16 156 DDR_B_CAS#
<8> M_ODT2 DDR_CS3_DIMMB# ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_CAS# <8>
<8> DDR_CS3_DIMMB#
157 158
159 CS1_n A13 160 +V_DDR_REFB
M_ODT3 161 VDD17 VDD18 162
<8> M_ODT3
163 ODT1 C0/CS2_n/NC 164 +V_DDR_REFB 20mil
165 VDD19 VREFCA 166 DIMM_CHB_SA2
167 C1, CS3_n,NC SA2 168
DDR_B_D37 VSS53 VSS54 DDR_B_D36

.1U_0402_16V7K
169 170
171 DQ37 DQ36 172
DDR_B_D33 VSS55 VSS56 DDR_B_D32 1

CD29
173 174
175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS57 VSS58 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180
+1.2V_DDR 2
181 DQS4_t VSS59 182 DDR_B_D39
B +3VS +3VS +3VS DDR_B_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_B_D35
DDR_B_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D45
DDR_B_D44 191 VSS64 DQ45 192
DQ44 VSS65
1

193 194 DDR_B_D41

RD4 RD5 RD6 DDR_B_D40 195 VSS66 DQ41 196
@ @ 197 DQ40 VSS67 198 DDR_B_DQS#5
0_0402_5% 0_0402_1% 0_0402_5% VSS68 DQS5_c DDR_B_DQS5
@ 199 200
+1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
2

DDR_B_D46 203 VSS69 VSS70 204 DDR_B_D47

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2 205 DQ46 DQ47 206
DDR_B_D42 207 VSS71 VSS72 208 DDR_B_D43
209 DQ42 DQ43 210
VSS73 VSS74
1

DDR_B_D52 211 212 DDR_B_D53

RD38 RD39 RD40 213 DQ52 DQ53 214
@ DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
0_0402_1% 0_0402_5% 0_0402_1% DQ49 DQ48
@ @ 217 218
DDR_B_DQS#6 219 VSS77 VSS78 220
+1.2V_DDR
2

DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222

223 DQS6_t VSS79 224 DDR_B_D54
DDR_B_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D50
DDR_B_D51 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D60
DDR_B_D61 233 VSS84 DQ60 234
VREF traces should be at least 20 mils 235 DQ61 VSS85 236 DDR_B_D57
wide with 20 mils spacing to other DDR_B_D56 237 VSS86
DQ56
DQ57
VSS87
238
DDR_B_DQS#7
239 240
signals 241 VSS88 DQS7_c 242 DDR_B_DQS7
+1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
+V_DDR_REFB_R DDR_B_D62 245 VSS89 VSS90 246 DDR_B_D63
+1.2V_DDR 247 DQ62 DQ63 248
DDR_B_D58 249 VSS91 VSS92 250 DDR_B_D59
251 DQ58 DQ59 252
VSS93 VSS94
1

PCH_SMBCLK 253 254 PCH_SMBDATA

<6,14,18,44> PCH_SMBCLK SCL SDA DIMM_CHB_SA0 PCH_SMBDATA <6,14,18,44>
RH207 255 256
+3VS VDDSPD SA0
1K_0402_1% +2.5V_MEM
257 258 +0.6VS
259 VPP1 VTT 260 DIMM_CHB_SA1
20mil +V_DDR_REFB 261 VPP2 SA1 262
2

A GND1 GND2 A
RH485 1 2 2_0402_1% +V_DDR_REFB
20mil
1

1 BELLW_SD-80886-1021
RH210 CONN@
CH100 1K_0402_1%
0.022U_0402_25V7K
2
2
1

RH212
24.9_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P15-DDR4 DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 15 of 76
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
CNP-H
UH2C
AR2 G36 TBT_CIO_PLUG_EVENT# 1 @ 2
<42> CLINK_CLK CL_CLK PCIE9_RXN PCIE_PRX_DTX_N09 <43>
AT5 F36 RH5889 10K_0201_5%
<42> CLINK_DATA CL_DATA PCIE9_RXP PCIE_PRX_DTX_P09 <43>
<42> CLINK_RST# AU4 C34 PCIE_PTX_DRX_N09 <43>
CL_RST# PCIE9_TXN D34 M2280_PCIE_SATA# 1 2
PCH_GPP_K8_BALL PCIE9_TXP PCIE_PTX_DRX_P09 <43>
@ PAD~D T91 P48 RH508 10K_0201_5%
@ PAD~D T92 PCH_GPP_K9_BALL V47 GPP_K8 HDD_DET# 1 2
V48 GPP_K9 K37
SSD
PCIE_PRX_DTX_N10 <43> RH513 10K_0201_5%
W47 GPP_K10 PCIE10_RXN J37
GPP_K11 PCIE10_RXP PCIE_PRX_DTX_P10 <43>
C35
PCIE10_TXN PCIE_PTX_DRX_N10 <43>
L47 B35 PCIE_PTX_DRX_P10 <43>
D
@ PAD~D T94 PCH_GPP_K2_BALL L46 GPP_K0 PCIE10_TXP D
U48 GPP_K1 F44
GPP_K2 PCIE15_RXN/SATA2_RXN SATA_PRX_DTX_N2 <44>
U47 E45 SATA_PRX_DTX_P2 <44> HDD
N48 GPP_K3 PCIE15_RXP/SATA2_RXP B40
GPP_K4 PCIE_15_SATA_2_TXN SATA_PTX_DRX_N2 <44>
N47 C40 SATA_PTX_DRX_P2 <44>
P47 GPP_K5 PCIE15_TXP/SATA2_TXP
R46 GPP_K6 L41 SATAGP0 RH5844 1 2 10K_0201_5%
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41 SATAGP3 RH5845 1 2 10K_0201_5%
<43> PCIE_PTX_DRX_P11
B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<43> PCIE_PTX_DRX_N11
SSD <43> PCIE_PRX_DTX_P11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP SATAGP4 RH5846 1 2 10K_0201_5%
G38 PCIE11_RXP/SATA0A_RXP K43
<43> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN PCIE_PRX_TTX_N17 <35>
K44 PCIE_PRX_TTX_P17 <35> SATAGP5 RH5847 1 2 10K_0201_5%
BIOS_REC AR42 PCIE17_RXP/SATA4_RXP A42
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN PCIE_PTX_TRX_N17 <35>
AR48 B42 PCIE_PTX_TRX_P17 <35> SATAGP6 RH5848 1 2 10K_0201_5%
RH5895 1 @ 2 0_0201_5% DTH_PDB_R AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP
<39> DTH_PDB PANEL_BKEN_PCH GPP_F13/SATA_SDATAOUT0 TS_DETECT#
AU46 P41 Thunderbolt RH5849 1 @ 2 10K_0201_5%
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE_PRX_TTX_N18 <35>
R40 PCIE_PRX_TTX_P18 <35>
C39 PCIE18_RXP/SATA5_RXP C42
PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_TRX_N18 <35>
D39 D42 PCIE_PTX_TRX_P18 <35>
D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
C47 PCIE14_RXN/SATA1B_RXN AK48 SATALED# A00_4P_0528: Add RH5894 to connect HDMI_HPLUG to SATAGP0
PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# +3VS
B38 AH41 SATAGP0 RH5894 1 @ 2 0_0201_5%
PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 HDMI_HPLUG <40>
C38 AJ43 M2280_PCIE_SATA# <43>
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 HDD_DET# BIOS_REC 1 2
PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 HDD_DET# <44>
C46 AN47 SATAGP3 RH5840 10K_0201_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 SATAGP4
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATAGP5 CAM_CBL_DET# 1 2
<43> SATA_PTX_DRX_P1A PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5
SSD <43> SATA_PTX_DRX_N1A D38 AM47 SATAGP6 RH511 10K_0201_5%
J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48 TS_DETECT#
<43> SATA_PRX_DTX_P1A PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7 TS_DETECT# <34>
H42 SATALED# 1 2
<43> SATA_PRX_DTX_N1A PCIE12_RXN/SATA1A_RXN AU48 BIA_PWM_PCH <7,34> RH512 10K_0201_5%
B44 GPP_F21/EDP_BKLTCTL AV46
<35> PCIE_PTX_TRX_P20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PANEL_BKEN_PCH <34>
A44 AV44 ENVDD_PCH <32>
<35> PCIE_PTX_TRX_N20 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN
<35> PCIE_PRX_TTX_P20 R37
R35 PCIE20_RXP/SATA7_RXP AD3 H_THERMTRIP# RH191 1 2 620_0402_5%
<35> PCIE_PRX_TTX_N20 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI H_THERMTRIP#_R <9,48>
C D43 AF2 RH539 1 2 13_0402_5% H_PECI <9,48> C
<35> PCIE_PTX_TRX_P19 C44 PCIE19_TXP/SATA6_TXP PECI AF3 H_PM_SYNC RH189 1 2 30_0402_5% PCH_PECI RH5836 1 @ 2 10K_0402_5%
Thunderbolt <35> PCIE_PTX_TRX_N19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PM_SYNC_R <9>
N42 AG5 PLTRST_CPU# <6,9>
<35> PCIE_PRX_TTX_P19 M44 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# AE2
<35> PCIE_PRX_TTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN <9>
CNP-H_BGA874 Rev1.0

+3VS
AUD_PWR_EN RH569 1 2 100K_0201_5%
CNP-H
UH2E
AL13 DDI1_DDPB_CTRLCLK
GPP_I5/DDPB_CTRLCLK DDI1_DDPB_CTRLDAT DDI1_DDPB_CTRLCLK <35>
AR8
PCH_DP1_HPD GPP_I6/DDPB_CTRLDATA DDI2_DDPC_CTRLCLK DDI1_DDPB_CTRLDAT <35>
<35> PCH_DP1_HPD AT6 AN13 DDI2_DDPC_CTRLCLK <35>
DP1/DP2 from Alpine Ridge PCH_DP2_HPD AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10 DDI2_DDPC_CTRLDAT AUD_PWR_EN RH568 1 @ 2 100K_0201_5%
<35> PCH_DP2_HPD PCH_DP3_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA DDI3_DDPD_CTRLCLK DDI2_DDPC_CTRLDAT <35>
<39> PCH_DP3_HPD AP9 AL9
DP3 from DP to HDMI Converter AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3 DDI3_DDPD_CTRLDAT
(UM1/PS175B2) GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40
GPP_F23/DDPF_CTRLDATA AT49 T2 PAD~D @
GPP_F22/DDPF_CTRLCLK
AP41 GPP_J9 RH5890 1 2 100K_0201_5%
GPP_F14/PS_ON# PROC_DETECT# <9>
AN6
<34> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
M45 PCH_GPP_K23_BALL T4 PAD~D @
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47 PCH_GPP_H23_BALL T8 PAD~D @
GPP_H23/TIME_SYNC0 +3VS
CNP-H_BGA874 Rev1.0

@ RP1
B DDI2_DDPC_CTRLCLK 1 8 B
DDI2_DDPC_CTRLDAT 2 7
DDI1_DDPB_CTRLCLK 3 6
DDI1_DDPB_CTRLDAT 4 5

2.2K_0804_8P4R_5%
CNP-H DDI3_DDPD_CTRLCLK 2.2K_0201_5% 1 2 RH1145
UH2M DDI3_DDPD_CTRLDAT 2.2K_0201_5% 1 2 RH1146
CAM_CBL_DET# AW13 BD4
<34> CAM_CBL_DET# GPP_G0/SD_CMD CNV_WR_CLKN
BE9 BE3
<23> GC6_EVENT# TBT_CIO_PLUG_EVENT# GPP_G1/SD_DATA0 CNV_WR_CLKP
<35> TBT_CIO_PLUG_EVENT# BF8
BF9 GPP_G2/SD_DATA1 BB3
<23,31,48> GPU_GC6_FB_EN GPP_G3/SD_DATA2 CNV_WR_D0N
BG8 BB4
HOST_SD_WP# BE8 GPP_G4/SD_DATA3 CNV_WR_D0P BA3
<50> HOST_SD_WP# AUD_PWR_EN BD8 GPP_G5/SD_CD# CNV_WR_D1N BA2 +3VS
<51,53> AUD_PWR_EN GPP_G6/SD_CLK CNV_WR_D1P
AV13
GPP_G7/SD_WP BC5
AP3 CNV_WT_CLKN BB6 HOST_SD_WP# 10K_0402_5% 2 1 RH563
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
AN4 GPP_I12/M2_SKT2_CFG1 BE6
AM7 GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N BD7
PAD~D @ GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6
PCH Strap PIN
T4949 CNV_WT_D1N
AV6 BF6
CPU_C10_GATE# RH5835 1 2 0_0402_5% CPU_VCCIO_PWR_GATE# AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P BA1
<33,73> CPU_C10_GATE#
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH108 1 2 100_0201_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 PCIE_RCOMPP BE5 SD_1P8_RCOMP RH5832 1 2 200_0201_1%
GPP_J4 AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_3P3_RCOMP RH5833 1 2 200_0201_1%
AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
GPP_J6 BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 BE1 GPPJ_RCOMP RH5834 1 2 200_0201_1%
AV3 GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82 BE2
AW2 GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD Y35 PMRSVD2 T4963 PAD~D @
GPP_J9/CNV_MFUART2_TXD RSVD2 Y36 PMRSVD3 T4962 PAD~D @
RSVD3
A A
BC1 PMRSVD1 T4961 PAD~D @
+1.8V_PCH 13 OF 13 RSVD1 AL35 PCH_TP_BALL T4947 PAD~D @
TP
CNP-H_BGA874 Rev1.0
RH5853 1 2 10K_0201_5% GPP_J4
@
RH5854 1 2 20K_0201_5% GPP_J6

RH5855 1 @ 2 10K_0201_5% GPP_J9

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P16-PCH (1/7) SATA,DDC,PCIE,CNV

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 16 of 76
5 4 3 2 1
 5 4 3 2 1

+3VS
RP2

RTC CRYSTAL
4 5 CLKREQ_PCIE#3
3 6 CLKREQ_PCIE#4 CNP-H
2 7 CLKREQ_PCIE#5 UH2G
1 8 CLKREQ_PCIE#6 BE33 PCH_RTCX1
GPP_A16/CLKOUT_48
10K_0804_8P4R_5% D7 Y3 RH70 1 2 10M_0402_5% PCH_RTCX2
<9> CPU_24MHZ_P CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# PCH_XDP_CLK_N <6>
C6 Y4 YH1
<9> CPU_24MHZ_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P PCH_XDP_CLK_P <6>
32.768KHZ_X1A000141000300
+3VS B8 B6
<9> PCH_CPU_BCLK_P CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <9>
<9> PCH_CPU_BCLK_N C8 A6 PCH_CPU_PCIBCLK_P <9> 1 2
CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P
RH548 1 @ 2 10K_0402_5% CLKREQ_PCIE#0 XTAL24_OUT U9 AJ6
RH549 1 2 10K_0402_5% SRCCLKREQ1# XTAL24_IN U10 XTAL_OUT CLKOUT_PCIE_N0 AJ7
RH550 1 @ 2 10K_0402_5% SRCCLKREQ2# XTAL_IN CLKOUT_PCIE_P0 Max Crystal
RH551 1 2 10K_0402_5% CLKREQ_PCIE#7 RH71 1 2 60.4_0402_1% XCLK_BIASREF T3 AH9 1
ESR = 50k Ohm. 1
D XCLK_BIASREF CLKOUT_PCIE_N1 AH10 D
PCH_RTCX1 BA49 CLKOUT_PCIE_P1 CH45 CH46
XCLK_BIASREF PCH_RTCX2 RTCX1
BA48 AE14 10P_0201_50V8J 10P_0201_50V8J
+3VS Trace Width/Space: 15mil /15 mil RTCX2 CLKOUT_PCIE_N2 AE15 2 2
Max Trace Length: 1000 mil CLKREQ_PCIE#0 BF31 CLKOUT_PCIE_P2
RP22@ SRCCLKREQ1# BE31 GPP_B5/SRCCLKREQ0# AE6
<35> SRCCLKREQ1# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_N3 <42>
4 5 SRCCLKREQ9# SRCCLKREQ2# AR32 AE7 NGFF - WLAN
CLKREQ_PCIE#3 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 <42>
3 6 SRCCLKREQ15# NGFF - WLAN <42> CLKREQ_PCIE#3 BB30
2 7 SRCCLKREQ8# CLKREQ_PCIE#4 BA30 GPP_B8/SRCCLKREQ3# AC2
Card Reader <50> CLKREQ_PCIE#4 CLKREQ_PCIE#5 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_N4 <50>
1 8 SRCCLKREQ10# Thunderbolt <35> CLKREQ_PCIE#5 AN29 AC3 CLK_PCIE_P4 <50> Card Reader
CLKREQ_PCIE#6 AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4
NGFF - SSD <43> CLKREQ_PCIE#6 CLKREQ_PCIE#7 GPP_H0/SRCCLKREQ6#
10K_0804_8P4R_5% GPU - ( N17P-GX ; N18P-Q1<23>
) AC48 AB2
CLKREQ_PCIE#7 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CLK_PCIE_N5 <35>
SRCCLKREQ8# AE41 AB3 CLK_PCIE_P5 <35> Thunderbolt
SRCCLKREQ9# AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 USB_PWR_EN RH544 1 2 10K_0402_5%
SRCCLKREQ10# AC41 GPP_H3/SRCCLKREQ9# W4
+3VS GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 CLK_PCIE_N6 <43>
SRCCLKREQ11# AC39 W3 NGFF - SSD
GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 CLK_PCIE_P6 <43>
SRCCLKREQ12# AE39
RP23@ SRCCLKREQ13# AB48 GPP_H6/SRCCLKREQ12# W7
GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 CLK_PCIE_N7 <23>
4 5 SRCCLKREQ11# SRCCLKREQ14# AC44 W6 GPU - ( N17P-GX ; N18P-Q1 )
GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 CLK_PCIE_P7 <23>
3 6 SRCCLKREQ13# SRCCLKREQ15# AC43
2 7 SRCCLKREQ14# GPP_H9/SRCCLKREQ15# AC14
1 8 SRCCLKREQ12# V2 CLKOUT_PCIE_N8 AC15
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
10K_0804_8P4R_5% CLKOUT_PCIE_P15 U2 XTAL24_IN_R RA96 1 2 33_0201_5% XTAL24_IN
T2 CLKOUT_PCIE_N9 U3
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
CLKOUT_PCIE_P14 AC9 RH72 1 2 1M_0201_5% XTAL24_OUT_R RA97 1 2 33_0201_5% XTAL24_OUT
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9 YH2
AC7 CLKOUT_PCIE_N11 AE11 1 3
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11 2 4
+3V_PCH CLKOUT_PCIE_P12 7 OF 13 R6 CLKIN_XTAL T4952 PAD~D @
CLKIN_XTAL 24MHZ_12PF_8Y24000034

1
CNP-H_BGA874 Rev1.0
1 1
@
RH5850 CH47 CH48
C RH5860 1 @ 2 100K_0402_5% PCH_SPI_SI 10K_0201_5% 15P_0201_50V8J 15P_0201_50V8J C
2 2

2
+3V_PCH

+3V_PCH SIO_EXT_SMI#_R RH110 1 2 10K_0201_5%

RH5881 1 @ 2 4.7K_0201_5% GPP_H12

+3VS
RH42 1 2 100K_0402_5% GPP_H15
CNP-H
RH74 1 @ 2 4.7K_0201_5% PCH_SPI_CS#0 UH2A
@ PAD~D T17 PCH_GPP_A11_BALL BE36 AV29 PCH_PLTRST# TOUCH_SCREEN_PD# RH510 1 2 10K_0402_5%
RH75 1 2 100K_0201_5% PCH_SPI_WP# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST#
TOUCHPAD_INTR# RH547 1 2 10K_0402_5%
RH78 1 2 100K_0201_5% PCH_SPI_HOLD# @ PAD~D T4950 PARSVD2 R15 Y47
@ PAD~D T4951 PARSVD1 R13 RSVD2 GPP_K16/GSXCLK Y46 EC_SLP_S0IX# RH535 1 2 10K_0402_5%
RSVD1 GPP_K12/GSXDOUT Y48
GPP_K13/GSXSLOAD W46
AL37 GPP_K14/GSXDIN AA45 PCH_PLTRST#
AN35 VSS GPP_K15/GSXSRESET#
TP @
PCH_SPI_SI AU41 AL47 BID_DIS CH3327
PCH_SPI_SO SPI0_MOSI GPP_E3/CPU_GP0 TOUCH_SCREEN_PD# BID_DIS <20,48>
BA45 AM45 TOUCH_SCREEN_PD# <34> 10P_0402_50V8J
PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TOUCHPAD_INTR#
PCH_SPI_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 EC_SLP_S0IX#
RH423 2 @ 1 100K_0201_5% 3.3V_mSATA_EN PCH_SPI_CS#1 AW48 SPI0_CLK GPP_B4/CPU_GP3
SPI0_CS1# AE44
PCH_SPI_WP# AY48 GPP_H18/SML4ALERT# AJ46
PCH_SPI_HOLD# BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15
<41> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT# DGPU_PWR_EN
AD48
GPP_H14/SML3DATA DGPU_PWR_EN <31>
BE19 AF47
BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 GPP_H12 +RTCVCC
SIO_EXT_SMI#_R BF18 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# AD47
<48> SIO_EXT_SMI#_R 3.3V_mSATA_EN GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA
BE18 AE48
B
RH5892 2 1 100K_0201_5% PCH_SPI_CLK PCH_RTD3_USB_PWR_EN BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK INTRUDER# RH531 1 2 1M_0201_5% B
<35> PCH_RTD3_USB_PWR_EN USB_PWR_EN GPP_D22/SPI1_IO3
BD17 1 OF 13 BB44 INTRUDER#
<45> USB_PWR_EN GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0

close to ROM @
RP4 +3VS
PCH_SPI_CLK_R 8 1 PCH_SPI_CLK
PCH_SPI_SI_R 7 2 PCH_SPI_SI
PCH_SPI_SO_R PCH_SPI_SO PCH_SPI_SI <6>
6 3
PCH_SPI_WP#_R 5 4 PCH_SPI_WP#
PCH_SPI_WP# <6> DGPU_PWR_EN RH537 1 2 10K_0402_5%
33_0804_8P4R_5%
DH1
TOUCHPAD_INTR# 2 1 PTP_INT# <41,48>
PCH_SPI_HOLD#_R RH576 1 2 33_0402_5% PCH_SPI_HOLD# RB751S40T1G_SOD523-2

+3V_PCH
PCH_SPI_CLK_TPM RH577 1 20_0402_1% PCH_SPI_CLK
<41> PCH_SPI_CLK_TPM PCH_SPI_SI_TPM
@
PCH_SPI_SI
Close PR313
RH578 1 @ 20_0402_1% RH586 1 @ 2 0_0201_5%
<41> PCH_SPI_SI_TPM PCH_SPI_SO_TPM RH579 PCH_SPI_SO
<41> PCH_SPI_SO_TPM 1 @ 20_0402_1% A00_4P_0525: remove DH2 ,add RH585 for flash ROM issue JSPI1
PCH_SPI_CS#1 1
PCH_SPI_SI 2 1
+3V_ROM DH2 1 2 RB751S40T1G_SOD523-2 +3V_PCH PCH_SPI_SO 3 2
PCH_SPI_CLK 4 3
@ PCH_SPI_CS#0 5 4
PCH_SPI_WP# 6 5
PCH_SPI_HOLD# 7 6
RH585 1 2 0_0603_5% 8 7
+3V_ROM 8
9
9

5
10 UH7
10

VCC
SPI ROM FOR ME ( 32MByte )
1 PCH_PLTRST#
11 4 IN1
<23,31,34,35,41,42,43,48,49,50>
GND1 PCH_PLTRST#_EC OUT
12 2

GND
GND2 IN2
A A

1
ACES_50521-01041-P01 MC74VHC1G08DFT2G_SC70-5
Follow Beaver Creek

3
UH8 CONN@ RH77
PCH_SPI_CS#0 1 8 100K_0402_5%
PCH_SPI_SO_R 2 CS# VCC 7 PCH_SPI_HOLD#_R

2
PCH_SPI_WP#_R 3 DO HOLD#_RESET# 6 PCH_SPI_CLK_R
4 WP# CLK 5 PCH_SPI_SI_R
GND DI

W25Q256JVEIQ_WSON8
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P17-PCH (2/7) CLK,SPI,PLTRST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 17 of 76
5 4 3 2 1
 5 4 3 2 1

HDA_SDO / I2S0_TXD
ME_FWP PCH has internal 20K PD.
+3VS_TS
FLASH DESCRIPTOR SECURITY OVERRIDE
+3V_PCH_DSW
1=Disable ME Protect (ME can be updated)
0=Enable ME Protect (ME cannot be updated) I2C2_IRQ_TS RH5891 1 2 100K_0201_5% PM_LANPHY_ENABLE RH5842 1 @ 2 10K_0402_5%
PCH_PCIE_WAKE# RH453 1 2 1K_0402_5%
PCH_BATLOW# RH515 1 2 8.2K_0402_5%
HDA_SDIN0 HDA_SDOUT
AC_PRESENT RH533 1 2 8.2K_0402_5%

RP15 LAN_WAKE# RH545 1 2 10K_0201_5%

HDA_SYNC 1 1
<52> HDA_SYNC_AUDIO 8 1 EMI@ EMI@
D
7 2 HDA_SDOUT CD3324 CD3325 VRALERT# 4.7K_0402_5% 2 @ 1 RH5837 D
<52> HDA_SDOUT_AUDIO HDA_BITCLK
6 3 2P_0201_25V8B 2P_0201_25V8B
<52> HDA_BITCLK_AUDIO HDA_RST# 2 2
<52> I2S_RST_AUDIO# 5 4
+3V_PCH
33_0804_8P4R_5%

ME_SUS_PWR_ACK RH506 1 @ 2 1M_0402_5%

SYS_RESET# RH571 1 2 8.2K_0402_5%

+RTCVCC

RH83 1 2 20K_0201_5% PCH_SRTCRST# CNP-H

UH2D
HDA_BITCLK BD11 BF36 +3VS
HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
1

RH96 1 @ 2 0_0201_5% HDA_SDIN0 BE11 AV32 CLKRUN#

<52> HDA_SDIN0_AUDIO HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
CH52 BF12
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 PM_LANPHY_ENABLE CLKRUN# RH85 1 @ 2 8.2K_0402_5%
1U_0402_6.3V6K
2

HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
HDA_RST# BE10 BD42 SIO_SLP_WLAN#
BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# SIO_SLP_WLAN# <32,48>
BE12 HDA_SDI1/I2S1_RXD BB46
+RTCVCC I2S1_TXD/SNDW2_DATA DRAM_RESET# H_DRAMRST# <14> +3V_PCH
BD12 BE32 VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
RH84 1 2 20K_0201_5% PCH_RTCRST# Close to PCH GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29 TS_I2C_RST#
AUD_AZA_CPU_SDO_R GPP_B0/GSPI0_CS1# TS_I2C_RST# <34>
RH146 1 2 30_0201_1% AM2 R47 SPKR 4.7K_0402_5% 2 @ 1 RH82
<7> AUD_AZA_CPU_SDO AUD_AZA_CPU_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE I2C2_IRQ_TS
close to BOT AN3 AP29 I2C2_IRQ_TS <34>
<7> AUD_AZA_CPU_SDI_R HDACPU_SDI GPP_B11/I2S_MCLK
1

RH147 1 2 30_0201_1% AUD_AZA_CPU_SCLK_R AM3 AU3 SYS_PWROK

<7> AUD_AZA_CPU_SCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <6,48>
CH53 CLRP1
SHORT PADS AV18 BB47 PCH_PCIE_WAKE#
1U_0402_6.3V6K PCH_PCIE_WAKE# <35,48> Top Swap Override (internal PD)
2

@ PAD~D T121 PCH_GPP_D7_BALL AW18 GPP_D8/I2S2_SCLK WAKE# BE40 SIO_SLP_A#

GPP_D7/I2S2_RXD GPD6/SLP_A# PCH_SLP_LAN# SIO_SLP_A# <48,51>
BA17 BF40 HIGH ENABLE
BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28 T20 PAD~D @
+3V_PCH PCH_DMIC_DAT_R RA102 1 2 33_0402_5% PCH_DMIC_DAT BF15 GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# BF42
SIO_SLP_S0# <33,41,51> LOW(DEFAULT) DISABLE
<51> PCH_DMIC_DAT_R PCH_DMIC_CLK_R PCH_DMIC_CLK GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# SIO_SLP_S4# SIO_SLP_S3# <31,33,35,48,51>
<51> PCH_DMIC_CLK_R RA103 1 2 33_0402_5% BD16 BE42
SIO_SLP_S4# <33,48,51>
DGPU_PWROK AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# BC42
<23,71> DGPU_PWROK KB_DET# GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# SIO_SLP_S5# <48,51>
C AW15 C
1 2 MEM_SMBCLK <51> KB_DET# GPP_D17/DMIC_CLK1/SNDW3_CLK BE45
RH458 1K_0201_5% SUSCLK <42,43>
RH459 1 2 1K_0201_5% MEM_SMBDATA GPD8/SUSCLK BF44 PCH_BATLOW#
RH460 1 2 1K_0201_5% SML1_SMBCLK GPD0/BATLOW# BE35 SUSACK#_R 0_0201_5% 2 @ 1 RH5872
SML1_SMBDAT PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK_R 0_0201_5% SUSACK# <48> +3V_PCH
RH461 1 2 1K_0201_5% BE47 BC37 2 @ 1 RH5873
SML0_SMBCLK <51> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK ME_SUS_PWR_ACK <48>
RH501 1 2 1K_0201_1% BD46
RH502 1 2 1K_0201_1% SML0_SMBDATA SRTCRST#
RH557 2 1 10K_0402_5% KB_DET# PCH_PWROK AY42 BG44 LAN_WAKE#
PCH_RSMRST#_R PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT LAN_WAKE# <48> PCH_SMB_ALERT# 4.7K_0402_5%
<6,48> PCH_RSMRST#_EC RH133 1 @ 2 0_0402_1% BA47 BG42
AC_PRESENT <48>
2 @ 1 RH505
+3VS RH5859 1 NDS@ 2 0_0402_5% RSMRST# GPD1/ACPRESENT BD39
SLP_SUS# SIO_SLP_SUS# <20,32,48>
BE46 SIO_PWRBTN# <6,48>
RH309 1 2 0_0402_5% PCH_DPWROK_R AW41 GPD3/PWRBTN# AU2 SYS_RESET#
RH463 1 2 1K_0201_5% PCH_SMBCLK <48> PCH_DPWROK_EC PCH_SMB_ALERT# BE25 DSW_PWROK SYS_RESET# AW29 SPKR
SYS_RESET# <6,51> TLS CONFIDENTIALITY
PCH_SMBDATA MEM_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR SPKR <52>
RH462 1 2 1K_0201_5% BE26 AE3
RH516 1 2 10K_0201_5% DGPU_PWROK MEM_SMBDATA BF26 GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <9> HIGH vPRO
SML0ALERT# BF24 GPP_C1/SMBDATA AL3 PCH_ITP_PMODE LOW(DEFAULT) non-vPRO
SML0_SMBCLK GPP_C5/SML0ALERT# ITP_PMODE PCH_JTAGX PCH_ITP_PMODE <6>
BF25 AH4
SML0_SMBDATA GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TMS PCH_JTAGX <6>
BE24 AJ4 PCH_JTAG_TMS <6>
RH91 1 @ 2 100K_0201_5% SYS_PWROK SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 PCH_JTAG_TDO
SML1_SMBCLK GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO <6>
BF27 AH2
<48> SML1_SMBCLK SML1_SMBDAT GPP_C6/SML1CLK 4 OF 13 PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI <6>
<48> SML1_SMBDAT BE27 AJ3 PCH_JTAG_TCK <6>
GPP_C7/SML1DATA PCH_JTAG_TCK
CNP-H_BGA874 Rev1.0
+3V_PCH
@
RH5841 1 2 10K_0201_5% PCH_RSMRST#_R

SML0ALERT# 4.7K_0402_5% 2 1 RH503

RH401 1 2 100K_0201_5% PCH_DPWROK_R

EC interface
HIGH ESPI
LOW(DEFAULT) LPC

B B

RH1152 1 2 100K_0201_5% SIO_SLP_A# +3V_PCH

RZ1150 1 2 100K_0201_5% SIO_SLP_S3# SML1ALERT# 150K_0402_5% 2 1 RH504

RZ1151 1 2 100K_0201_5% SIO_SLP_S4# PCHHOT# ( IntelR DCI-OOB )

HIGH Enable
LOW(DEFAULT) Disable

+3VS Reserve for EMI

A00_4P_0507: From SE00001KKM0 change to SE00000FW80

EMC@ CH50 1 2 8.2P_0201_25V8D HDA_BITCLK

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and PCH to DDR, XDP, FFS
allow the entire region of the SPI flash to be updated using @ CH51 1 2 10P_0201_25V8 HDA_SDOUT
+3VS
FPT. +3V_PCH
QH4A Reserve for RF please close to UH1
2

5
A00_4P_0517: remove debug part DMN65D8LDW-7_SOT363-6 UH14
1

VCC
RH536 MEM_SMBCLK 6 1 PCH_SMBCLK 1
PCH_SMBCLK <6,14,15,44> <62> IMVP_VR_PG IN1 PCH_PWROK
@ 1K_0201_5% 4
OUT
5

GND
<48> RUNPWROK IN2
SW4
2

A
MEM_SMBDATA 3 4 PCH_SMBDATA A
+3V_PCH_ME_SW PCH_SMBDATA <6,14,15,44>

1
1

3
HDA_SDOUT 1K_0201_5% 2 1 RH454 ME_EN 2 MC74VHC1G08DFT2G_SC70-5 RH529
3 @ QH4B 100K_0201_5%
0_0201_5% 2 1 RH487 DMN65D8LDW-7_SOT363-6
4 G

2
5
<48> ME_FWP G
SSAL120100_3P

ME_FWP PCH has internal 20K PD. Security Classification Compal Secret Data Compal Electronics, Inc.
FLASH DESCRIPTOR SECURITY OVERRIDE Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short P18-PCH (3/7) PM,HDA,SMB,JTAG

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
posit i on) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 18 of 76
5 4 3 2 1
 5 4 3 2 1

CNP-H
UH2B
K34 J3 USB Conn 1 (Right side)
<7> DMI_CTX_PRX_N0 DMI0_RXN USB2N_1 USB20_N1 <45>
<7> DMI_CTX_PRX_P0 J35 J2 USB20_P1 <45>
C33 DMI0_RXP USB2P_1 N13
<7> DMI_CRX_PTX_N0
B33 DMI0_TXN USB2N_2 N15
USB20_N2 <45> USB Conn 2 (Left side)
D <7> DMI_CRX_PTX_P0 DMI0_TXP USB2P_2 USB20_P2 <45> D
G33 K4
<7> DMI_CTX_PRX_N1 DMI1_RXN USB2N_3
F34 K3
<7> DMI_CTX_PRX_P1 DMI1_RXP USB2P_3
<7> DMI_CRX_PTX_N1 C32 M10 USB20_N4 <42>
B32 DMI1_TXN USB2N_4 L9 Mini Card(WLAN)
<7> DMI_CRX_PTX_P1 DMI1_TXP USB2P_4 USB20_P4 <42>
<7> DMI_CTX_PRX_N2 K32 M1 USB20_N5 <37>
<7> DMI_CTX_PRX_P2
J32 DMI2_RXN USB2N_5 L2
USB20_P5 <37>
reserve for TI_PD
C31 DMI2_RXP USB2P_5 K7
<7> DMI_CRX_PTX_N2 DMI2_TXN USB2N_6
<7> DMI_CRX_PTX_P2 B31 K6
G30 DMI2_TXP USB2P_6 L4
<7> DMI_CTX_PRX_N3
F30 DMI3_RXN USB2N_7 L3
USB20_N7 <49> Finger Print model
<7> DMI_CTX_PRX_P3 DMI3_RXP USB2P_7 USB20_P7 <49>
C29 G4
<7> DMI_CRX_PTX_N3 DMI3_TXN USB2N_8
B29 G5
<7> DMI_CRX_PTX_P3 DMI3_TXP USB2P_8
A25 M6 USB20_N9 <34> Touch Screen
B25 RSVD USB2N_9 N8
RSVD USB2P_9 USB20_P9 <34>
P24 H3
R24 RSVD USB2N_10 H2
C26 RSVD USB2P_10 R10
B26 RSVD USB2N_11 P9
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
USB20_N12 <34> RGB Camera
RSVD USB2P_12 USB20_P12 <34>
B27 N3
C27 RSVD USB2N_13 N2 +3V_PCH
L26 RSVD USB2P_13 E5
M26 RSVD USB2N_14 F6 USB_OC3# RH555 1 2 10K_0201_5%
D29 RSVD USB2P_14 USB_OC2# RH554 1 2 10K_0201_5%
E28 RSVD AH36 USB_OC0# USB_OC1# RH553 1 2 10K_0201_5%
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <45> USB_OC0#
K29 AL40 RH552 1 2 10K_0201_5%
RSVD GPP_E10/USB2_OC1# USB_OC2# USB_OC1# <45>
M29 AJ44
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3#
G17 GPP_E12/USB2_OC3# AV47 USB_OC4#
<42> PCIE_PRX_DTX_N1 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# USB_OC5#
F16 AR35
NGFF <42> PCIE_PRX_DTX_P1
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37 USB_OC6#
<42> PCIE_PTX_DRX_N1 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# USB_OC7# +3V_PCH
<42> PCIE_PTX_DRX_P1 B17 AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7# RP8
PCIE2_RXN/USB31_8_RXN USB2_COMP RH109 USB_OC5#
P21 F4 1 2 113_0402_1% 4 5
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE RH580 1 @ 2 0_0201_5% USB_OC4# 3 6
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 PBRSVD1 T4964 PAD~D @ USB_OC6# 2 7
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 RH581 1 @ 2 0_0201_5% USB_OC7# 1 8
C C
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 3.3V_CAM_EN# 10K_0804_8P4R_5%
PCIE3_TXN/USB31_9_TXN GPD7 3.3V_CAM_EN# <34>
C19
N18 PCIE3_TXP/USB31_9_TXP G45
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46
D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
<50> PCIE_PRX_DTX_N5 PCIE5_RXN PCIE23_TXP
G20 G49
CARD_READER <50>
<50>
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5 B21 PCIE5_RXP PCIE23_TXN W44 Xtal input
A22 PCIE5_TXN PCIE23_RXP W43
<50> PCIE_PTX_DRX_P5 PCIE5_TXP PCIE23_RXN
K21 H48
J21 PCIE6_RXN PCIE22_TXP H47 HIGH(DEFAULT) dif f er ent ia
PCIE6_RXP PCIE22_TXN
D21
C21 PCIE6_TXN PCIE22_RXP
U41
U40
LOW single-end
B23 PCIE6_TXP PCIE22_RXN F46
C23 PCIE7_TXP PCIE21_TXP G47 0628
J24 PCIE7_TXN PCIE21_TXN R44 CFL CRB rev0.5
L24 PCIE7_RXP PCIE21_RXP T43 Xtal input
PCIE7_RXN PCIE21_RXN High : differential
F24 Low : single-end
G24 PCIE8_RXN CNL- PCH EDS rev0.5
B24 PCIE8_RXP External pull-up is required. Recommend 100K if pulled
C24 PCIE8_TXN 2 OF 13 up to 3.3V
PCIE8_TXP
CNP-H_BGA874 Rev1.0

@
+3.3V_1.8V_ESPI

SIO_RCIN# RH518 1 210K_0402_5%

CNP-H
UH2F +3.3V_1.8V_ESPI
F9 BB39 ESPI_IO0_R RC5831 1 2 15_0201_1%
<46> USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <48,49>
USB Conn JUSB2 (Bottom Right Side) F7 AW37 RC5832 1 2 15_0201_1%
<46> USB3_PTX_DRX_P1 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 <48,49> ESPI_ALERT#
<46> USB3_PRX_DTX_N1 D11 AV37 RC5833 1 2 15_0201_1% ESPI_IO2 <48,49> RH1943 1 2 8.2K_0402_1%
B
C11 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 BA38 ESPI_IO3_R RC5834 1 2 15_0201_1%
B
<46> USB3_PRX_DTX_P1 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <48,49>

<47> USB3_PTX_DRX_N2 C3
D4 USB31_2_TXN BE38 ESPI_CS# ESPI_RESET# RH5838 1 @ 2 10K_0402_5%
USB Conn JUSB1 (Bottom Left Side) <47> USB3_PTX_DRX_P2
B9 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# AW35 IRQ_SERIRQ RH5882 1 @ 2 0_0201_5%
ESPI_CS# <48,49>
<47> USB3_PRX_DTX_N2 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_ALERT#_R ESPI_ALERT# <48>
C9 BA36 RH5883 1 2 0_0201_5%
<47> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# SIO_RCIN#
BE39
GPP_A0/RCIN#/ESPI_ALERT1# ESPI_RESET#_R SIO_RCIN# <48> ESPI_RESET#
C17 BF38 RH5839 1 2 0_0201_5% ESPI_RESET# <48>
C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#
G14 USB31_6_TXP BB36 ESPI_CLK RH168 1 2 15_0201_1%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 ESPI_CLK_5105
PCI_CLK_LPC1_R <48,49>
F14 BB34 RH428 1 @ 2 22_0201_1%
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1 T4945 PAD~D @
B15 USB31_5_TXN T48 TBT_PWR_EN T5990 PAD~D @
J13 USB31_5_TXP GPP_K19/SMI# T47 ESPI_CLK_5105
K13 USB31_5_RXN GPP_K18/NMI#
USB31_5_RXP
1
G12 AH40
USB31_3_TXP GPP_E6/SATA_DEVSLP2 HDD_DEVSLP <44>
F11 AH35 M2280_DEVSLP <43> @ CH198
C10 USB31_3_TXN GPP_E5/SATA_DEVSLP1 AL48
USB31_3_RXP GPP_E4/SATA_DEVSLP0 15P_0402_50V8J
B10 AP47 2
USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47 RF Reserved.
J15 USB31_4_TXN GPP_F6/SATA_DEVSLP4 AP48 LCD_DBC +3VS
USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
LCD_DBC <34>
K16
USB31_4_RXN
CNP-H_BGA874 Rev1.0
LCD_DBC RH527 1 @ 2 10K_0402_5%
@

RH528 1 2 10K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P19-PCH (4/7) DMI,PCIE,USB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 19 of 76
5 4 3 2 1
 5 4 3 2 1

CNP-H
UH2K
BBS_BIT6 BA26 BA20 +3VS
+3VS BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20
<32> PCH_3.3V_TS_EN SIO_EXT_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK DCI_CLK DGPU_HOLD_RST# <23,31>
AU26 BB16
SIO_EXT_SCI# <48> SIO_EXT_SCI# HDD_FALL_INT GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO DCI_DATA T5991 PAD~D @
RH383 1 2 10K_0402_5% AW26 AN18
1 2 49.9K_0402_1% UART2_TXD <44> HDD_FALL_INT GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI T5992 PAD~D @
RH561
RH562 1 2 49.9K_0402_1% UART2_RXD NRB_BIT BE30 BF14 BID_GPU
BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 BID_BC
<41> TPM_PIRQ# GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BF29 BF17
MEDIACARD_IRQ# BB26 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17
<50> MEDIACARD_IRQ# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
BB24
D <49> SBIOS_TX PCH_PLTRST#_EC_AR GPP_C9/UART0A_TXD SPK_DET# D
BE23 RH572 1 2 100K_0402_5%
<35> PCH_PLTRST#_EC_AR PCH_GPP_C11 AP24 GPP_C8/UART0A_RXD
@ PAD~D T4988 PCH_GPP_C10 GPP_C11/UART0A_CTS#
BA24
@ PAD~D T4989 GPP_C10/UART0A_RTS# AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
@ PAD~D T6002 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
AW24
<20> CPU_ID GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AP21 AH47
<35> RTD3_CIO_PWR_EN SIO_EXT_WAKE# GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24 AH48
<48> SIO_EXT_WAKE# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
+3V_PCH SPK_DET# AV21
<48,51> SPK_DET# GPP_C23/UART2_CTS#
AW21
UART2_TXD BE20 GPP_C22/UART2_RTS# AV34
RH119 1 2 4.7K_0402_5% I2C1_SCK_TP UART2_RXD BD20 GPP_C21/UART2_TXD GPP_A23/ISH_GP5 AW32
RH120 1 2 4.7K_0402_5% I2C1_SDA_TP GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C1_SCK_TP BE21 GPP_A21/ISH_GP3 BE34
<41> I2C1_SCK_TP I2C1_SDA_TP GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
BF21 BD34
SIO_EXT_WAKE# <41> I2C1_SDA_TP I2C0_SCK_TS GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 PCH_GPP_A18
RH523 1 2 10K_0402_5% BC22 BF35
<34> I2C0_SCK_TS I2C0_SDA_TS GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 T124 PAD~D @
<34> I2C0_SDA_TS BF23 BD38
GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 +3V_PCH
<35> TBT_FORCE_PWR BE15
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
<44> FFS_INT2 GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874 Rev1.0

MEDIACARD_IRQ# RH546 1 2 10K_0402_5%

RH564 RH566 RH5858

+3V_PCH

RH130 1 @ 2 4.7K_0402_5% BBS_BIT6

100K_0402_5% 100K_0402_5% 100K_0201_5%
UMA@ UMAP@ UMA@

C RH567 Boot BIOS Strap Bit (internal PD) C

RH567 RH5858 HIGH LPC

LOW(DEFAULT) SPI
100K_0402_5%
UMAX@
100K_0402_5% 100K_0201_5%
+3V_PCH +3V_PCH +3V_PCH N17PG0@ N17PG0@

RH567 RH5857
+3V_PCH
1

RH564 @ RH566 @ RH5857 RH524 1 @ 2 4.7K_0402_5% NRB_BIT

100K_0402_5% 100K_0402_5% @ 100K_0201_5%

100K_0402_5% 100K_0201_5%
2

N17PG1@ N17PG1@ NO REBOOT mode (internal PD)

BID_DIS BID_BC BID_GPU RH566 RH5858
BID_DIS <17,48> HIGH ENABLE
LOW(DEFAULT) DISABLE
1

RH565 DIS@ RH567 @ RH5858

100K_0402_5% 100K_0402_5% @ 100K_0201_5%
100K_0402_5% 100K_0201_5%
N18PQ1@ N18PQ1@
2

RH566 RH5857

100K_0402_5% 100K_0201_5%
N18PQ3@ N18PQ3@
B B

SIO_SLP_SUS# 0_0201_5% 2 1 RH5871 PCH_PRIM_EN

VCCDSW_EN_GPIO <18,32,48> SIO_SLP_SUS# PCH_PRIM_EN <33,60,70>

+3V_PCH_DSW +3VALW 0_0201_5% 2 1 RH5869 2 1 VCCDSW_EN_Q 0_0201_5% 2 NDS@1 RH5870

<48> VCCDSW_EN
DI16 RB751S40T1G_SOD523-2
NDS@
0_0402_5% 2 @ 1 RH5864

DI15 1 2 RB751S40T1G_SOD523-2
QH1 <33,48,59> ALWON
LP2301ALT1G_SOT23-3 NDS@

0_0402_5% 2 1 RH5865+3V_PCH_DSW_RR 1 3
D

+3V_PCH
G
2

1
1

R5832
RH5875 4PHASE@ 499K_0402_1% RH5867
100K_0402_5% 100K_0402_5%
2
2

1
2

CPU_ID
CPU_ID <20>
RH5868
49.9K_0402_1%
1

RH5876 3PHASE@
1

100K_0402_5% QE20
A A
1

D L2N7002WT1G_SC-70-3
2

2 VCCDSW_EN_GPIO
G
S
3

SYSTEM ID 3 (VR)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
HIGH =4PHASE P20-PCH (5/7) I2C,GPIO
LOW =3PHASE

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 20 of 76
5 4 3 2 1
 5 4 3 2 1

+1VALW +1V_PCH
CNP-H
@ PJP1302 +1V_PCH +1V_PCH_CLK5 +1V_PCH_PRIM UH2H +3V_PCH
1 2 5.95A AA22 AW9 0.182A
AA23 VCCPRIM_1P051 VCCPRIM_3P32
AB20 VCCPRIM_1P052 BF47
PAD-OPEN 3x3m +DCPRTC
+1VALW +1V_PCH_PRIM 1 2 AB22 VCCPRIM_1P053 DCPRTC1 BG47
VCCPRIM_1P054 DCPRTC2

0.1U_0201_6.3V6K
LH4 BLM15PX221SN1D_2P AB23 +3V_PCH +3V_USB2
@ PJP1303 AB27 VCCPRIM_1P055 V23 0.095A
VCCPRIM_1P056 VCCPRIM_3P35 1

CH3331
1 2 AB28 +3V_PCH +3V_PCH_SPI
AB30 VCCPRIM_1P057 AN44 0.042A
AD20 VCCPRIM_1P058 VCCSPI
PAD-OPEN 3x3m
AD23 VCCPRIM_1P059 BC49 2
VCCPRIM_1P0510 VCCRTC1 +RTCVCC
AD27 BD49
+1V_PCH +1V_MPHY_MPHYPLL AD28 VCCPRIM_1P0511 VCCRTC2 +3V_PCH +3V_PCH_PRIM
AD30 VCCPRIM_1P0512 AN21 0.195A +3V_PCH +3V_PHVLDO
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 0.97A
AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7
D
1 2 +1V_MPHY +1V_PCH AF30 VCCPRIM_1P0517 VCCPRIM_3P34 +3V_PCH +3V_1.8V_PGPPHK D

LH3 BLM15PX221SN1D_2P VCCPRIM_1P0518 AC35 0.262A

6.66A U26 VCCPGPPHK1 AC36 +3V_PCH +3V_1.8V_PGPPEF
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
V27 VCCPRIM_1P0525 VCCPGPPEF2 +3V_PCH +3V_1.8V_PGPPD
V28 VCCPRIM_1P0526 AN24 0.14A
+1V_PCH +1V_PCH_AZPLL V30 VCCPRIM_1P0527 VCCPGPPD AN26
+VCCPRIM_FUSE_1P05 +1V_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.334A
+1V_PCH VCCPRIM_1P0529 VCCPGPPBC2 +3.3V_1.8V_ESPI
0.0012A AD31 AN32 0.101A
1 2 VCCPRIM_1P0514 VCCPGPPA +3V_PCH +3V_PCH_PRIM
LH2 BLM15PX221SN1D_2P RH5856 1 2 0_0402_5% +1V_PCH_CNVI 0.2A AE17 AT44 0.106A +3V_PCH_DSW +3V_PCH_DSW
+1V_PCH_USBPLL VCCPRIM_1P0515 VCCPRIM_3P31 BE48 0.113A
+1V_PCH 0.42A W22 VCCDSW_3P31 BE49
1 1 VCCDUSB_1P051 VCCDSW_3P32
EMI@ EMI@ W23 +3V_PCH_AZIO
CH3323 CH3322 +1V_VCCDSW VCCDUSB_1P052 BB14 0.00767A +1.8V_PCH_I_LDO +1.8V_PCH +1.8V_PRIM
2P_0201_25V8B 2P_0201_25V8B BG45 VCCHDA AG19 0.766A RE321 1 2 0_0201_1%
2 2 +VCCCLPLLEBB_1P05 +1V_PCH BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15
+1V_PCH_AZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PCH +1.8V_PCH_LDO
+1V_MPHY_MPHYPLL +1V_MPHY_MPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A +1.8V_PCH_LDO RH5880 1 @ 2 0_0402_5%
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82 +1V_PCH +1V_PCH
+1V_PCH_CLK5 +1V_PCH_CLK5 VCCAMPHYPLL_1P053 AG31 0.193A +1V_PCH +1V_PCH
0.00428A P2 VCCPRIM_1P0520 AF31 0.0859A +1.25V_LDOSRAM
+VCCA_SRC_1P05 +1V_PCH P3 VCCA_XTAL_1P051 VCCPRIM_1P0519 AK22 T5003 PAD~D @
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
W20 VCCA_SRC_1P051 VCCPRIM_1P242 +1.25V_DPHY_MAR
+VCCA_BCLKPLL2_1P05 +1V_PCH VCCA_SRC_1P052 AJ22 T5004 PAD~D @
0.0198A C1 VCCDPHY_1P241 AJ23
+VCCA_OC_1P05 +1V_PCH C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5
0.0085A V19 VCCAPLL_1P055 VCCDPHY_1P243
+VCCA_BCLKPLL2_1P05 +1V_PCH VCCA_BCLK_1P05 K47 VCCMPHY_SENSE T4943 PAD~D @
0.021A B1 VCCMPHY_SENSE K46 VSSMPHY_SENSE T4944 PAD~D @
B2 VCCAPLL_1P051 VSSMPHY_SENSE
C C
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0

@ +3V_PCH +3V_PCH_AZIO

+1V_PCH_AZPLL 1 2
LH1 BLM15PX221SN1D_2P
Close to ball name +1.25V_DPHY_MAR
+1.25V_LDOSRAM +1.25V_DPHY_MAR 1 1
D1, E1
0.1U_0201_10V6K

+3.3V_1.8V_PGPPA EMI@ EMI@

1 CH203 1uF 0402 capacitor RH5879 1 2 0_0402_5% CH3321 CH3320

4.7U_0402_6.3V6M
CH203

1 2P_0201_25V8B 2P_0201_25V8B
+3.3V_1.8V_ESPI 2 2

CA131
2
+1.8V_PCH 2
RH599 1 2 0_0402_5% RH597 1 2 0_0402_5%

20170717 DB review change

+RTCVCC +1V_PCH
+3V_1.8V_PGPPEF
+1V_PCH_PRIM +3V_PCH_AZIO 20170614 +1V_PCH_CLK5
+1V_VCCDSW Close to ball name
+3V_PHVLDO +1V_PCH_CLK5 AE35 , AE36
0613 0613 intel review 0613 Intel review Close ball name P2 , P3
Close to ball name +VCCA_BCLKPLL2_1P05 Close to net name Close to ball name 1x 0.1uF 0402 3mm

0.1U_0201_10V6K
Close to ball name BC49, BD49 To add 1x 1uF 0603, 3mm (placeholder)
Intel review +1V_PCH_PRIM BB14
1U_0201_10V6M

BG45, BG46 Close to ball name AY8, BB7

1U_0402_10V6K

1x 0.1uF 0402, 3mm

1U_0201_10V6M

CH200
1 Close to ball name 1uF 0402 capacitor 1 1uF 0402 capacitor
1

1x 1uF 0402
1U_0201_10V6M

0.1U_0201_10V6K

CH207

1U_0201_10V6M
1 1x 1uF 0402, 5mm B1, B2, B3, C1, C2 +3V_PCH
+3V_PCH
CH176
CH3329

22U_0402_6.3V6M

22U_0402_6.3V6M
1 1 1 1 1
B 1uF 0402 capacitor B
CH80

CH70

CH179
2

2 2

CH177

CH178
2 @
2 2 2 2 2

1U_0201_10V6M

0.1U_0201_10V6K
1
1

CH187

CH192
@
2
2

+1.8V_PCH +1V_MPHY_MPHYPLL 20170717 DB review change

+1V_PCH +1V_PCH_PRIM
+1V_MPHY 20170613
20170614 Intel review Close to ball name +1V_MPHY_MPHYPLL
To add 1x 1uF, 0402 U26,U29,V25, Intel review Close to ball name
on +1.8V_PCH. AF31, AG31, AD31, AA22, 20170614 +3V_1.8V_PGPPD
1U_0201_10V6M

V27,V28,V30,V31 To change close ball name. +3V_PCH_DSW Close to ball name

1 1x 1uF 0402, 3mm Close to ball name AA23, AB20, AB22, AB23,
1U_0402_10V6K

Intel review AN24

CH205

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1x 22uF 0805, 5mm C49,D49,E49 AB27, AB28, AB30, AD20,

1
1U_0201_10V6M

1 1 1 AD23, AD27, AD28, AD30, To add 1x 0.1uF 0402, 3mm 1x 0.1uF 0402 3mm
CH206

1x 1uF 0402, 3mm

CH181

CH182
22U_0402_6.3V6M

1U_0201_10V6M

2 1 1
AF23, AF27, AF30, AE17, 3mm Close to ball name BE48, BE49 (placeholder)
CH180

2
CH184

CH183

2 2 2 +3V_PCH +3V_PCH +3VS +3V_PCH

2 2

0.1U_0201_10V6K

1U_0201_10V6M
0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1

CH82

CH188
CH204

CH191
@
2 2 2 2

+1.8V_PCH +3V_PCH +3V_PCH +1V_PCH

+1.8V_PRIM +3V_1.8V_PGPPEF
A
Close to ball name Close to ball name +3V_1.8V_PGPPHK 0619 A

AG19, AG20, AR15, AN15, BB11 AE35, AE36 Close to ball name +1V_PCH_USBPLL
1x 4.7uF 0603, 3mm 1x 0.1uF 0402, 3mm AC35, AC36 EMI require 100nF
CH92
4.7U_0402_6.3V6M

0.1U_0201_10V6K

1 Option 1: Internal LDO 1 (placeholder) 1x 0.1uF 0402 3mm Close to W22,W23 for EMI require
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1x 1uF 0402, 3mm (placeholder)

CH190

0.1U_0201_10V6K

0.1U_0201_10V6K

1 1 1 1
Option 2: External VRM
CH201

CH202

2 2
CH189

CH3324

2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P21-PCH (6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 21 of 76
5 4 3 2 1
 5 4 3 2 1

CNP-H CNP-H
UH2I UH2L
A2 AL12
A28 VSS VSS AL17 BG3 M24
A3 VSS VSS AL21 BG33 VSS VSS M32
A33 VSS VSS AL24 BG37 VSS VSS M34
A37 VSS VSS AL26 BG4 VSS VSS M49
A4 VSS VSS AL29 BG48 VSS VSS M5
D A45 VSS VSS AL33 C12 VSS VSS N12 D
A46 VSS VSS AL38 C25 VSS VSS N16
A47 VSS VSS AM1 C30 VSS VSS N34
A48 VSS VSS AM18 C4 VSS VSS N35
A5 VSS VSS AM32 C48 VSS VSS N37
A8 VSS VSS AM49 C5 VSS VSS N38
AA19 VSS VSS AN12 D12 VSS VSS P26
AA20 VSS VSS AN16 D16 VSS VSS P29
AA25 VSS VSS AN34 D17 VSS VSS P4
AA27 VSS VSS AN38 D30 VSS VSS P46
AA28 VSS VSS AP4 D33 VSS VSS R12
AA30 VSS VSS AP46 D8 VSS VSS R16
AA31 VSS VSS AR12 E10 VSS VSS R26
AA49 VSS VSS AR16 E13 VSS VSS R29
AA5 VSS VSS AR34 E15 VSS VSS R3
AB19 VSS VSS AR38 E17 VSS VSS R34
AB25 VSS VSS AT1 E19 VSS VSS R38 CNP-H
AB31 VSS VSS AT16 E22 VSS VSS R4 UH2J
AC12 VSS VSS AT18 E24 VSS VSS T17 Y14 PJRSVD7 T4953 PAD~D @
AC17 VSS VSS AT21 E26 VSS VSS T18 RSVD7 Y15 PJRSVD8 T4954 PAD~D @
AC33 VSS VSS AT24 E31 VSS VSS T32 RSVD8 U37 PJRSVD6 T4955 PAD~D @
AC38 VSS VSS AT26 E33 VSS VSS T4 RSVD6 U35 PJRSVD5 T4956 PAD~D @
AC4 VSS VSS AT29 E35 VSS VSS T49 RSVD5
AC46 VSS VSS AT32 E40 VSS VSS T5 N32 PJRSVD3 T4957 PAD~D @
AD1 VSS VSS AT34 E42 VSS VSS T7 RSVD3 R32 PJRSVD4 T4958 PAD~D @
AD19 VSS VSS AT45 E8 VSS VSS U12 RSVD4
AD2 VSS VSS AV11 F41 VSS VSS U15 AH15 PJRSVD2 T4959 PAD~D @
AD22 VSS VSS AV39 F43 VSS VSS U17 RSVD2 AH14 PJRSVD1 T4960 PAD~D @
AD25 VSS VSS AW10 F47 VSS VSS U21 RSVD1
AD49 VSS VSS AW4 G44 VSS VSS U24
AE12 VSS VSS AW40 G6 VSS VSS U33
AE33 VSS VSS AW46 H8 VSS VSS U38 AL2
C VSS VSS VSS VSS PREQ# XDP_PREQ# <6,9> C
AE38 B47 J10 V20 AM5
VSS VSS VSS VSS PRDY# XDP_PRDY# <6,9>
AE4 B48 J26 V22 AM4
VSS VSS VSS VSS CPU_TRST# CPU_XDP_TRST# <6,9>
AE46 B49 J29 V4 AK3
VSS VSS VSS VSS TRIGGER_OUT PCH_TRIGGER <9>
AF22 BA12 J4 V46 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGGER <9>
AF25 BA14 J40 W25
AF28 VSS VSS BA44 J46 VSS VSS W27 10 OF 13
AG1 VSS VSS BA5 J47 VSS VSS W28 CNP-H_BGA874 Rev1.0
AG22 VSS VSS BA6 J48 VSS VSS W30
VSS VSS VSS VSS @
AG23 BB41 J9 Y10
AG25 VSS VSS BB43 K11 VSS VSS Y12
AG27 VSS VSS BB9 K39 VSS VSS Y17
AG28 VSS VSS BC10 M16 VSS VSS Y33
AG30 VSS VSS BC13 M18 VSS VSS Y38
AG49 VSS VSS BC15 M21 VSS 12 OF 13 VSS Y9
AH12 VSS VSS BC19 VSS VSS
AH17 VSS VSS BC24 CNP-H_BGA874 Rev1.0
AH33 VSS VSS BC26
VSS VSS @
AH38 BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
AJ27 VSS VSS BC8
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
B AK4 VSS VSS BG25 B
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P22-PCH (7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev

WWW.AliSaler.Com
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 22 of 76
5 4 3 2 1
 5 4 3 2 1

+1.8V_GFX_AON
PEG_HTX_C_GRX_P[0..15]
UV18A @
<7> PEG_HTX_C_GRX_P[0..15]
PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P0 AN12 GC6_EVENT#_D
Part 1 of 7 RV551 1 DIS@ 2 10K_0402_5%
<7> PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_N0 AM12 PEX_RX0 P6 GPU_GPIO0 NVVDD_PWM_VID GPU_PSI
RV1095 1 DIS@ 20_0201_5% RV552 1 DIS@ 2 10K_0402_5%
PEG_GTX_C_HRX_P[0..15] PEG_HTX_C_GRX_P1 AN14 PEX_RX0_N GPIO0 M3 GPU_GC6_FB_EN_GPU NVVDD_PWM_VID <68>
<7> PEG_GTX_C_HRX_P[0..15] PEG_HTX_C_GRX_N1 AM14 PEX_RX1 GPIO1 L6 GC6_EVENT#_D GPU_GC6_FB_EN_GPU <31> GPU_LEVEL
DV14 RV554 1 DIS@ 2 100K_0402_5%
PEG_GTX_C_HRX_N[0..15] PEG_HTX_C_GRX_P2 AP14 PEX_RX1_N GPIO2 P5 GPU_GPIO3 20_0201_5% NVVDDS_PWM_VID GC6_EVENT#_D GC6_EVENT#
RV1098 1 DIS@ 2 1 GC6_EVENT# <16>
<7> PEG_GTX_C_HRX_N[0..15] PEG_HTX_C_GRX_N2 AP15 PEX_RX2 GPIO3 P7 1V8_MAIN_EN NVVDDS_PWM_VID <69> SYS_PEX_RST_MON#
1V8_MAIN_EN <31,68> RV557 1 DIS@ 2 10K_0402_5%
PEG_HTX_C_GRX_P3 AN15 PEX_RX2_N GPIO4 L7 FRM_LCK RB751S40T1G_SOD523-2
PEG_HTX_C_GRX_N3 AM15 PEX_RX3 GPIO5 M7 GPU_PSI 1V8_MAIN_EN RV562 1 DIS@ 2 10K_0402_5%
PEG_HTX_C_GRX_P4 PEX_RX3_N GPIO6 LCD_BL_PWM GPU_PSI <68,69> DIS@ GPU_PEX_RST_HOLD# RV563 1 DIS@
AN17 N8 2 10K_0402_5%
PEG_GTX_C_HRX_P0 CV818 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P0 PEG_HTX_C_GRX_N4 AM17 PEX_RX4 GPIO7 L3 GPU_GPIO8 RV1086 1 DIS@ 2 0_0402_5% MEM_VDD_CTL DV15 FRM_LCK RV564 1 DIS@ 2 10K_0402_5%
PEG_GTX_C_HRX_N0 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N0 PEG_HTX_C_GRX_P5 AP17 PEX_RX4_N GPIO8 M2 THERMAL_ALERT# MEM_VDD_CTL <71> GPU_LEVEL 2 1GPU_PWR_LEVEL
CV819
PEG_HTX_C_GRX_N5 AP18 PEX_RX5 GPIO9 L1 MEM_VREF GPU_PWR_LEVEL <48>
D PEG_GTX_C_HRX_P1 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P1 PEG_HTX_C_GRX_P6 AN18 PEX_RX5_N GPIO10 M5 LCD_VDD MEM_VREF <28,29> GPU_GC6_FB_EN_GPU RV566 1 DIS@ 2 10K_0402_5% D
CV820 RB751S40T1G_SOD523-2
PEG_GTX_C_HRX_N1 CV821 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N1 PEG_HTX_C_GRX_N6 AM18 PEX_RX6 GPIO11 N3 GPU_LEVEL MEM_VREF RV567 1 DIS@ 2 100K_0402_5%

GPIO
PEG_HTX_C_GRX_P7 PEX_RX6_N GPIO12 LCD_BLEN DIS@
AN20 M4
PEG_GTX_C_HRX_P2 CV822 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P2 PEG_HTX_C_GRX_N7 AM20 PEX_RX7 GPIO13 N4 HPD_IFPA
PEG_GTX_C_HRX_N2 CV823 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N2 PEG_HTX_C_GRX_P8 AP20 PEX_RX7_N GPIO14 P2 HPD_IFPB T4973 PAD~D@
PEG_HTX_C_GRX_N8 AP21 PEX_RX8 GPIO15 R8 SYS_PEX_RST_MON# T4974 PAD~D@ +1.8V_GFX_AON
PEG_GTX_C_HRX_P3 CV824 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P3 PEG_HTX_C_GRX_P9 AN21 PEX_RX8_N GPIO16 M6 HPD_IFPD
PEG_GTX_C_HRX_N3 CV825 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N3 PEG_HTX_C_GRX_N9 AM21 PEX_RX9 GPIO17 R1 HPD_IFPE T4975 PAD~D@
PEG_HTX_C_GRX_P10 AN23 PEX_RX9_N GPIO18 P3 3D VISION/STEREO T4976 PAD~D@ +1.8V_GFX_AON +3VS
PEG_GTX_C_HRX_P4 CV826 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P4 PEG_HTX_C_GRX_N10 AM23 PEX_RX10 GPIO19 P4 GC5_MODE T4977 PAD~D@
PEX_RX10_N GPIO20

1
PEG_GTX_C_HRX_N4 CV827 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N4 PEG_HTX_C_GRX_P11 AP23 P1 GPU_GPIO21 T210 PAD~D@ DIS@
PEG_HTX_C_GRX_N11 AP24 PEX_RX11 GPIO21 P8 GPU_GPIO22 RV1112
PEX_RX11_N GPIO22

2
PEG_GTX_C_HRX_P5 CV828 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P5 PEG_HTX_C_GRX_P12 AN24 T8 GPU_PEX_RST_HOLD# T4978 PAD~D@ 1.8K_0402_5% DIS@
PEG_GTX_C_HRX_N5 CV829 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N5 PEG_HTX_C_GRX_N12 AM24 PEX_RX12 GPIO23 L2 HPD_IFPF RV1133 I2CB_SCL RV570 1 DIS@ 2 1.8K_0402_5%
PEG_HTX_C_GRX_P13 AN26 PEX_RX12_N GPIO24 R4 GPU_GPIO25 T4979 PAD~D@ 100K_0402_5% I2CB_SDA RV571 1 DIS@ 2 1.8K_0402_5%

2
PEG_GTX_C_HRX_P6 CV830 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P6 PEG_HTX_C_GRX_N13 AM26 PEX_RX13 GPIO25 R5 GPU_GPIO26 T4995 PAD~D@
PEG_GTX_C_HRX_N6 CV831 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N6 PEG_HTX_C_GRX_P14 AP26 PEX_RX13_N GPIO26 U3 HPD_IFPC T4996 PAD~D@ VGA_EDID_CLK RV572 1 DIS@ 2 1.8K_0402_5%

1
PEX_RX14 GPIO27

2
PEG_HTX_C_GRX_N14 VGA_EDID_DATA

G
AP27 T4980 PAD~D@ DIS@ RV573 1 DIS@ 2 1.8K_0402_5%
PEG_GTX_C_HRX_P7 CV832 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P7 PEG_HTX_C_GRX_P15 AN27 PEX_RX14_N QV98
PEG_GTX_C_HRX_N7 CV833 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N7 PEG_HTX_C_GRX_N15 AM27 PEX_RX15 GPU_GC6_FB_EN_GPU 3 1
PEX_RX15_N GPU_GC6_FB_EN <16,31,48>

D
PEG_GTX_C_HRX_P8 CV834 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P8 +1.8V_GFX_AON
PEG_GTX_C_HRX_N8 CV835 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N8 PEG_GTX_HRX_P0 AK14 BSS138W 1N SOT-323-3
PEG_GTX_HRX_N0 AJ14 PEX_TX0 AK9 THERMAL_ALERT# RV553 1 DIS@ 2 10K_0402_5%
PEG_GTX_C_HRX_P9 CV836 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P9 PEG_GTX_HRX_P1 AH14 PEX_TX0_N RES AL10 GC5_MODE RV1839 1 DIS@ 2 10K_0402_5%
PEG_GTX_C_HRX_N9 CV837 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N9 PEG_GTX_HRX_N1 AG14 PEX_TX1 RES AL9 +1.8V_GFX_AON LCD_BL_PWM RV1834 1 @ 2 100K_0402_5%
PEG_GTX_HRX_P2 AK15 PEX_TX1_N RES
PEG_GTX_C_HRX_P10 CV838 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P10 PEG_GTX_HRX_N2 AJ15 PEX_TX2 AM9 RV1084 1 @ 2 0_0402_5% LCD_BLEN RV1838 1 DIS@ 2 100K_0402_5%

RES
PEX_TX2_N RES

1
PEG_GTX_C_HRX_N10 CV839 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N10 PEG_GTX_HRX_P3 AL16 AN9 DIS@ LCD_VDD RV1837 1 DIS@ 2 100K_0402_5%

PCI EXPRESS
PEG_GTX_HRX_N3 AK16 PEX_TX3 RES RV1842 +1.8V_GFX_AON
PEG_GTX_C_HRX_P11 CV840 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P11 PEG_GTX_HRX_P4 AK17 PEX_TX3_N AG10 10K_0402_5% DIS@ MEM_VDD_CTL RV1836 1 @ 2 10K_0402_5%
PEG_GTX_C_HRX_N11 CV841 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N11 PEG_GTX_HRX_N4 AJ17 PEX_TX4 RES AP9 UV29 NVVDDS_PWM_VID RV1835 1 @ 2 100K_0402_5%
PEX_TX4_N RES

5
C PEG_GTX_HRX_P5 AH17 AP8 GPU_GPIO21 RV1840 1 DIS@ 2 100K_0402_5% C

2
PEG_GTX_C_HRX_P12 CV842 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P12 PEG_GTX_HRX_N5 AG17 PEX_TX5 RES DGPU_PEX_RST# 1 LCD_BL_PWM RV1841 1 2 100K_0402_5%

P
PEG_GTX_C_HRX_N12 PEG_GTX_HRX_N12 PEG_GTX_HRX_P6 PEX_TX5_N <23,31> DGPU_PEX_RST# B
CV843 2 1 0.22U_0201_6.3V6M DIS@ AK18 4
PEG_GTX_HRX_N6 AJ18 PEX_TX6 GPU_GC6_FB_EN_GPU# 2 O
PEX_TX6_N A

G
PEG_GTX_C_HRX_P13 CV844 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P13 PEG_GTX_HRX_P7 AL19 D
DIS@
PEG_GTX_C_HRX_N13 CV845 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N13 PEG_GTX_HRX_N7 AK19 PEX_TX7 GPU_GC6_FB_EN_GPU 2 QV105 TC7SZ08FU_SSOP5

3
PEG_GTX_HRX_P8 AK20 PEX_TX7_N G
PEG_GTX_C_HRX_P14 PEG_GTX_HRX_P14 PEG_GTX_HRX_N8 PEX_TX8 BSS138W 1N SOT-323-3
CV846 2 1 0.22U_0201_6.3V6M DIS@ AJ20 S

3
PEG_GTX_C_HRX_N14 CV847 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N14 PEG_GTX_HRX_P9 AH20 PEX_TX8_N R7 I2CB_SCL
PEX_TX9 I2CB_SCL

2
PEG_GTX_HRX_N9 I2CB_SDA

G
AG20 R6 DIS@
PEG_GTX_C_HRX_P15 CV848 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_P15 PEG_GTX_HRX_P10 AK21 PEX_TX9_N I2CB_SDA QV91
PEG_GTX_C_HRX_N15 2 1 0.22U_0201_6.3V6M DIS@ PEG_GTX_HRX_N15 PEG_GTX_HRX_N10 AJ21 PEX_TX10 R2 VGA_EDID_CLK RV1082 1 DIS@ 2 0_0402_5% THERMATRIP_GPU#_R 3 1 RV1083 1 DIS@ 2 0_0402_5%

I2C
CV849 <24,31> THERMATRIP_GPU#
PEG_GTX_HRX_P11 AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA THERMTRIP1# <31,48>

D
PEG_GTX_HRX_N11 AK22 PEX_TX11 I2CC_SDA
PEG_GTX_HRX_P12 AK23 PEX_TX11_N T4 EC_SMB_CK2_PX BSS138W 1N SOT-323-3
PEG_GTX_HRX_N12 AJ23 PEX_TX12 I2CS_SCL T3 EC_SMB_DA2_PX
PEG_GTX_HRX_P13 AH23 PEX_TX12_N I2CS_SDA
PEG_GTX_HRX_N13 AG23 PEX_TX13
PEG_GTX_HRX_P14 AK24 PEX_TX13_N
PEG_GTX_HRX_N14 AJ24 PEX_TX14 +1.8V_GFX_AON
PEG_GTX_HRX_P15 AL25 PEX_TX14_N
PEG_GTX_HRX_N15 AK25 PEX_TX15
PEX_TX15_N GPCPLL_AVDD
H26 W=40mils +GPCPLL_AVDD
+GPCPLL_AVDD <26>
DIS@
XS_PLLVDD
AD8 W=40mils +XS_PLLVDD
+XS_PLLVDD <26>
RV1131 1 DIS@ 2 0_0402_5% DGPU_PEX_RST# DV13

1
AJ11 DIS@ DIS@ 2
NC
SP_PLLVDD
AE8 W=40mils +SP_PLLVDD
+SP_PLLVDD <26>
RV326 RV325
ALL_GPWRGD
<23,67> 1VS_GFX_PG
AL13 1.8K_0402_5% 1.8K_0402_5% RV1132 1 @ 2 0_0402_5% 1
<17>
<17>
CLK_PCIE_P7
CLK_PCIE_N7 CLKREQ_PCIE#7_GPU
AK13 PEX_REFCLK
PEX_REFCLK_N VID_PLLVDD
AD7 W=40mils +VID_PLLVDD
+VID_PLLVDD <26> GPU_GC6_FB_EN_GPU 3
FBVDD_EN <31,71>
AK12

2
PEX_CLKREQ_N

1
100K_0402_5%
CLK
PEX_TSTCLK_OUT

RV550
DIS@
@ PAD~D T4991 AJ26 H3 XTALIN BAT54CW-7-F_SOT323-3
NC XTAL_IN

2
@ PAD~D T4992 PEX_TSTCLK_OUT# AK26 H2 XTAL_OUT DMN63D8LDW-7_SOT363-6
B NC XTAL_OUT DIS@ B
DGPU_PEX_RST# RV577 1 DIS@ 2 0_0402_5% DGPU_PEX_RST#_R AJ12 J4 XTALOUT RV581 1 DIS@ 2 10K_0402_5% EC_SMB_CK2_PX QV21A 1 6
<23,31> DGPU_PEX_RST#

2
1 DIS@ 2 2.49K_0402_1% PEX_TERMP AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN RV579 1 DIS@ 2 10K_0402_5% GPU_SMBCLK <48>
RV578
PEX_TERMP XTAL_SSIN

5
DMN63D8LDW-7_SOT363-6
DIS@
N17P-GT_BGA908 EC_SMB_DA2_PX QV21B 4 3
GPU_SMBDAT <48>

RV1833 1 @ 2 10M_0402_5%

+1.8V_GFX_AON DIS@
+1.8V_GFX_AON YV1
RV580
1 DIS@ 2 XTALIN 1 3 XTAL_OUT
1@ 1 3

1
CV853 1 1
10K_0402_5% 0.1U_0402_10V7K DIS@ NC NC DIS@
DIS@ CV857 27MHZ_10PF_XRCGB27M000F2P18R0 CV858
DIS@ 2 RV591 12P_0201_50V8J 2 4 15P_0201_50V8J
5

UV19 ALL_GPWRGD RV590 2 DIS@ 1 10K_0402_5% 10K_0402_5% 2 2

2
1 RV587
G VCC

<20,31> DGPU_HOLD_RST# B SYS_PEX_RST_MON#_L DGPU_PEX_RST# DGPU_PEX_RST#

4 1 DIS@ 2
2 Y DGPU_PEX_RST# <23,31>
<17,31,34,35,41,42,43,48,49,50> PCH_PLTRST#_EC A 0_0402_5%
1
100K_0402_5%

TC7SZ08FU_SSOP5
3

2
RV589
DIS@

DIS@

G
+1.8V_GFX_AON QV103
A 1 3 BSS138W 1N SOT-323-3 CLKREQ_PCIE#7_GPU GPU_PWR_LEVEL A
<17> CLKREQ_PCIE#7
DIS@
Low Low Performace

S
2

UV20
5

1 High High Performace

P

<23,67> 1VS_GFX_PG B 4 ALL_GPWRGD

2 O
<18,71> DGPU_PWROK A
G

TC7SZ08FU_SSOP5 Security Classification Compal Secret Data Compal Electronics, Inc.

GC6 2.1 funct i on
3

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P23-N17P_PCIE/DAC/GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 23 of 76
5 4 3 2 1
 5 4 3 2 1

UV18D @

Part 4 of 7
AM6
AN6 IFPA_L3
AP3 IFPA_L3_N AC6
D
AN3 IFPA_L2 NC AJ28 D
AN5 IFPA_L2_N NC AJ4
AM5 IFPA_L1 NC AJ5
AL6 IFPA_L1_N NC AL11
AK6 IFPA_L0 NC C15
AJ6 IFPA_L0_N NC

NC
D19
AH6 IFPA_AUX_SCL NC D20
IFPA_AUX_SDA_N NC D23
NC D26
AJ9 NC
AH9 IFPB_L3
AP6 IFPB_L3_N V32
AP5 IFPB_L2 NC
AM7 IFPB_L2_N
IFPB_L1 trace width: 16mils
AL7
AN8 IFPB_L1_N differential voltage sensing.
AM8 IFPB_L0 differential signal routing.
AK8 IFPB_L0_N
AL8 IFPB_AUX_SCL
IFPB_AUX_SDA_N L4
VDD_SENSE VCCSENSE_VGA <68>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5
IFPC_L1 GND_SENSE VSSSENSE_VGA <68>
AJ2
AH3 IFPC_L1_N

TMDS
AH4 IFPC_L2
AG5 IFPC_L2_N
AG4 IFPC_L3
IFPC_L3_N
C
TEST C

AM1 AK11 TESTMODE

AM2 IFPD_L0 NVJTAG_SEL
IFPD_L0_N

1
AM3 AM10 GPU_JTAG_TCK PAD~D T201 @
AM4 IFPD_L1 JTAG_TCK AM11 GPU_JTAG_TDI PAD~D T202 @ DIS@
AL3 IFPD_L1_N JTAG_TDI AP12 GPU_JTAG_TDO PAD~D T203 @ RV592
AL4 IFPD_L2 JTAG_TDO AP11 GPU_JTAG_TMS PAD~D T204 @ 10K_0402_5%
AK4 IFPD_L2_N JTAG_TMS AN11 GPU_JTAG_TRST# RV593 1 DIS@ 2 10K_0402_5%

2
AK5 IFPD_L3 JTAG_TRST_N
IFPD_L3_N

AD2
AD3 IFPE_L0
AD1 IFPE_L0_N
AC1 IFPE_L1 SERIAL
AC2 IFPE_L1_N H6 ROM_CS PAD~D T205 @
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SI ROM_SCLK <30>
AC4 H5
IFPE_L3 ROM_SI ROM_SO ROM_SI <30>
AC5 H7
IFPE_L3_N ROM_SO ROM_SO <30>
+1.8V_GFX_AON
AE3
AE4 IFPF_L0
IFPF_L0_N

2
AF4 DIS@
AF5 IFPF_L1 RV594
AD4 IFPF_L1_N GENERAL 10K_0402_5%
AD5 IFPF_L2 E1
AG1 IFPF_L2_N BUFRST_N

1
AF1 IFPF_L3 M1
B IFPF_L3_N OVERT THERMATRIP_GPU# <23,31> B

AG3
AG2 IFPC_AUX_SCL
IFPC_AUX_SDA_N J2 STRAP0
STRAP0 STRAP0 <30>
J7 STRAP1
STRAP1 STRAP1 <30>
AK3 J6 STRAP2
IFPD_AUX_SCL STRAP2 STRAP2 <30>
AK2 J5 STRAP3
IFPD_AUX_SDA_N STRAP3 STRAP3 <30>
J3 STRAP4
STRAP4 STRAP4 <30>
J1 STRAP5
STRAP5 STRAP5 <30>
AB3
AB4 IFPE_AUX_SCL
IFPE_AUX_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 IFPF_AUX_SCL
IFPF_AUX_SDA_N

N17P-GT_BGA908

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P24-N17P_eDP/HDMI/mDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-G341P
WWW.AliSaler.Com
5 4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 2
Date: Wednesday, June 06, 2018
1
Sheet 24 of 76
 5 4 3 2 1

+1VS_GFX
Under GPU Near GPU 3A

10U_0603_6.3V6M

22U_0603_6.3V6M
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 1 1 2 1

CV865

CV866

CV859

CV860

CV867

CV861

CV868
UV18E @

CV869
+1.35VSDGPU Part 5 of 7
11A Near GPU 2 2 2 2 2 2 1 2
AA27 AG19
AA30 FBVDDQ_0 PEX_DVDD_0 AG21
FBVDDQ_1 PEX_DVDD_1 DIS@ DIS@ DIS@ DIS@

22U_0603_6.3V6M

22U_0402_6.3V6M

22U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AB27 AG22 DIS@ DIS@ DIS@ DIS@
AB33 FBVDDQ_2 PEX_DVDD_2 AG24
1 1 1 1 1 2 2 FBVDDQ_3 PEX_DVDD_3

CV871

CV864

CV873
AC27 AH21
FBVDDQ_4 PEX_DVDD_4

CV870

CV862

CV863

CV872
AD27 AH25
D AE27 FBVDDQ_5 PEX_DVDD_5 +1.8V_GFX_RUN_R RV1068 1 DIS@ 2 0_0603_5% D
2 2 2 2 2 1 1 AF27 FBVDDQ_6
FBVDDQ_7
Under GPU Near GPU +1.8V_GFX_RUN
1A
AG27 AG13
B13 FBVDDQ_8 PEX_HVDD_0 AG15
FBVDDQ_9 PEX_HVDD_1

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
DIS@ B19 AG16
FBVDDQ_11 PEX_HVDD_2

CV881
E13 AG18 1 1 1 1 1 1 2 2 1
FBVDDQ_12 PEX_HVDD_3

CV874

CV875

CV876

CV877

CV878

CV879

CV880
E19 AG25
FBVDDQ_14 PEX_HVDD_4

CV882
H10 AH15
H11 FBVDDQ_15 PEX_HVDD_5 AH18
H12 FBVDDQ_16 PEX_HVDD_6 AH26 2 2 2 2 2 2 1 1 2
+1.35VSDGPU H13 FBVDDQ_17 PEX_HVDD_7 AH27
Under GPU(below 150mils) H14 FBVDDQ_18
FBVDDQ_19
PEX_HVDD_8
PEX_HVDD_9
AJ27 DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@
H18 AK27 DIS@ DIS@
H19 FBVDDQ_22 PEX_HVDD_10 AL27
FBVDDQ_23 PEX_HVDD_11
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
H20 AM28

POWER
H21 FBVDDQ_24 PEX_HVDD_12 AN28 +1.8V_GFX_AON
2 2 1 1 1 1 1 1 FBVDDQ_25 PEX_HVDD_13
CV883

CV884

CV885

CV886

CV887

CV888

CV889

CV890
H22
H23 FBVDDQ_26 +1.8V_GFX_RUN Under GPU.J8/K8 Near GPU.J8/K8
1 1 2 2 2 2 2 2
H24 FBVDDQ_27
FBVDDQ_28 +PEX_PLL_HVDD
Near GPU
H8 AH12 RV597 1 DIS@ 2 0_0603_5%
FBVDDQ_29 PEX_PLL_HVDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
H9
FBVDDQ_30

0.1U_0402_10V7K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ L27 DIS@ 1 1 1 1
DIS@ DIS@ FBVDDQ_31

CV892

CV893

CV894

CV895
M27 1
FBVDDQ_32 +PEX_SVDD_3V3

CV891
N27 AG12
P27 FBVDDQ_33 NC T4993 PAD~D@
R27 FBVDDQ_34 2 2 2 2

+1.35VSDGPU
T27 FBVDDQ_35
FBVDDQ_36
150mA
+PEX_PLL_VDD
2
T30 AG26 DIS@
Under GPU(below 150mils) T33 FBVDDQ_37
FBVDDQ_38
NC
+1.8V_GFX_AON
T4994 PAD~D@ DIS@ DIS@ DIS@
Y27
FBVDDQ_43
+1.8V_GFX_RUN
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
J8
1V8_AON K8
2 2 1 1 1 1 1 1 1V8_AON Under GPU Near GPU
CV896

CV897

CV898

CV899

CV900

CV901

CV902

CV903
L8
B16 VDD18 M8
C
E16 FBVDDQ VDD18 C
1 1 2 2 2 2 2 2 FBVDDQ

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
H15
H16 FBVDDQ
FBVDDQ 1 1 1 1

CV904

CV905

CV906

CV907
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ V27 AH8
DIS@ DIS@ W27 FBVDDQ IFPAB_PLLVDD AJ8
W30 FBVDDQ IFPAB_RSET
W33 FBVDDQ 2 2 2 2
FBVDDQ AF7
IFPCD_PLLVDD AF8
IFPCD_RSET DIS@ DIS@ DIS@ DIS@

AB8
IFPEF_PLVDD AD6
<71> FBVDDQ_SENSE
W=10mils F1
FBVDDQ_SENSE
IFPEF_RSET

+1.35VSDGPU F2 AG8
PROBE_FB_GND IFP_IOVDD AG9
IFP_IOVDD
RV600 1 DIS@ 2 40.2_0402_1% J27 AF6
FB_CAL_PD_VDDQ IFP_IOVDD AG6
CALIBRATION PIN GDDR5 IFP_IOVDD
RV601 1 DIS@ 2 40.2_0402_1% H27 AC7
FB_CAL_x_PD_VDDQ 40.2 ohm FB_CAL_PU_GND IFP_IOVDD AC8
IFP_IOVDD
FB_CAL_x_PU_GND 40.2 ohm RV602 1 DIS@ 2 60.4_0402_1% H25
FB_CAL_TERM_GND AG7
FB_CAL_xTERM_GND 60.4 ohm NC AN2
NC
Place near balls
N17P-GT_BGA908

B B

GPU Power Up Sequence GPU GC6 Entry Sequence GPU GC6 Exit Sequence GPU Power Down Sequence
+1.8V_GFX_AON FB_CKE Normal Self-Refresh Self-Refresh Normal +GPU_CORE_VDDS

1V8_MAIN_EN
PXE_Link Active XXX XXX Detect Train +GPU_CORE

+1.8V_GFX_RUN
DGPU_PEX_RST# all other power rails
+GPU_CORE

GPU_GC6_FB_EN
+GPU_CORE_VDDS

+1VS_GFX 1V8_MAIN_EN 40us < T1 < 4ms

+1.35V_GPU
ALL_GPWRGD
T1 < 4ms
A A

The ramp time for any rail must be more than 40us and less than 2ms. GPU_EVENT# 1us < T0

The entire entry/exit sequence must complete within 200 ms.

Security Classification
2017/06/21
Compal Secret Data Compal Electronics, Inc.
Issued Date Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P25-N17P_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 25 of 76
5 4 3 2 1
 5 4 3 2 1

UV18F @

Part 6 of 7
A2 D2
+GPU_CORE AA17 GND_0 GND_100 D31
47A +GPU_CORE UV18G @ AA18 GND_1
GND_2
GND_101
GND_102
D33
AA20 E10
AA22 GND_3 GND_103 E22
AA14 Part 7 of 7 V17 AB12 GND_4 GND_104 E25
AA21 VDD_1 VDD_56 V20 AB14 GND_5 GND_105 E5
AB13 VDD_4 VDD_58 V22 AB16 GND_6 GND_106 E7
AB15 VDD_6 VDD_59 W12 AB19 GND_7 GND_107 F28
AB17 VDD_7 VDD_60 W16 AB2 GND_8 GND_108 F7
AB18 VDD_8 VDD_62 W19 AB21 GND_9 GND_109 G10
AB20 VDD_9 VDD_63 W23 A33 GND_10 GND_110 G13
AB22 VDD_10 VDD_65 Y13 AB23 GND_11 GND_111 G16
D
AC12 VDD_11 VDD_66 Y15 AB28 GND_12 GND_112 G19 D
AC16 VDD_12 VDD_67 Y17 AB30 GND_13 GND_113 G2
AC19 VDD_14 VDD_68 Y18 AB32 GND_14 GND_114 G22
AC23 VDD_15 VDD_69 Y20 AB5 GND_15 GND_115 G25
M12 VDD_17 VDD_70 Y22 AB7 GND_16 GND_116 G28
M16 VDD_18 VDD_71 AC13 GND_17 GND_117 G3
M19 VDD_20 AC15 GND_18 GND_118 G30
M23 VDD_21 AC17 GND_19 GND_119 G32
N13 VDD_23
VDD_24 VDDS_SENSE
U1 W=10mils VDDS_SENSE_VGA <69>
AC18 GND_20
GND_21
GND_120
GND_121
G33
N15 U2 AA13 G5
VDD_25 GNDS_SENSE GNDS_SENSE_VGA <69> GND_22 GND_122
N17 AC20 G7
N18 VDD_26 +GPU_CORE AC22 GND_23 GND_123 K2
N20 VDD_27 AE2 GND_24 GND_124 K28
N22 VDD_28 U4 AE28 GND_25 GND_125 K30

POWER
P14 VDD_29 XVDD_4 U5 AE30 GND_26 GND_126 K32
P21 VDD_31 XVDD_5 U6 AE32 GND_27 GND_127 K33
R13 VDD_34 XVDD_6 U7 AE33 GND_28 GND_128 K5
R15 VDD_36 XVDD_7 U8 AE5 GND_29 GND_129 K7
R17 VDD_37 XVDD_8 AE7 GND_30 GND_130 M13
R18 VDD_38 AH10 GND_31 GND_131 M15
R20 VDD_39 V1 AA15 GND_32 GND_132 M17
R22 VDD_40 XVDD_9 V2 AH13 GND_33 GND_133 M18
T12 VDD_41 XVDD_10 V3 AH16 GND_34 GND_134 M20
T16 VDD_42 XVDD_11 V4 AH19 GND_35 GND_135 M22
T19 VDD_44 XVDD_12 V5 AH2 GND_36 GND_136 N12
T23 VDD_45 XVDD_13 V6 AH22 GND_37 GND_137 N14
U13 VDD_47 XVDD_14 V7 AH24 GND_38 GND_138 N16
U15 VDD_48 XVDD_15 V8 AH28 GND_39 GND_139 N19
U18 VDD_49 XVDD_16 AH29 GND_40 GND_140 N2
U20 VDD_51 AH30 GND_41 GND_141 N21
U22 VDD_52 W2 AH32 GND_42 GND_142 N23
V13 VDD_53 XVDD_17 W3 AH33 GND_43 GND_143 N28

GND
V15 VDD_54 XVDD_18 W4 AH5 GND_44 GND_144 N30
VDD_55 XVDD_19 W5 AH7 GND_45 GND_145 N32
19A +GPU_CORE_VDDS XVDD_20
XVDD_21
W7 AJ7 GND_46
GND_47
GND_146
GND_147
N33
W8 AK10 N5
XVDD_22 AK7 GND_48 GND_148 N7
AA12 AL12 GND_49 GND_149 P13
C C
AA16 VDDS Y1 AL14 GND_50 GND_150 P15
AA19 VDDS NC Y2 AL15 GND_51 GND_151 P17
AA23 VDDS NC Y3 AL17 GND_52 GND_152 P18
AC14 VDDS NC Y4 AL18 GND_53 GND_153 P20
AC21 VDDS XVDD_23 Y5 AL2 GND_54 GND_154 P22
M14 VDDS XVDD_24 Y6 AL20 GND_55 GND_155 R12
M21 VDDS XVDD_25 Y7 AL21 GND_56 GND_156 R14
P12 VDDS XVDD_26 Y8 AL23 GND_57 GND_157 R16
P16 VDDS XVDD_27 AL24 GND_58 GND_158 R19
P19 VDDS AL26 GND_59 GND_159 R21
P23 VDDS AA1 AL28 GND_60 GND_160 R23
T14 VDDS NC AA2 AL30 GND_61 GND_161 T13
T21 VDDS NC AA3 AL32 GND_62 GND_162 T15
U17 VDDS NC AA4 AL33 GND_63 GND_163 T17
V18 VDDS NC AA5 AL5 GND_64 GND_164 T18
W14 VDDS NC AA6 AM13 GND_65 GND_165 T2
W21 VDDS NC AA7 AM16 GND_66 GND_166 T20
VDDS NC AA8 AM19 GND_67 GND_167 T22
NC AM22 GND_68 GND_168 AG11
AM25 GND_69 GND_169 T28
AN1 GND_70 GND_170 T32
N17P-GT_BGA908 AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
+1.8V_PLLVDD AN22 GND_75 GND_175 U16
+GPCPLL_AVDD
Under +1.8V_PLLVDD
AN25 GND_76
GND_77
GND_176
GND_177
U19
RV574 1 DIS@ 2 0_0402_5% AN30 U21
<23> +GPCPLL_AVDD
Under
+XS_PLLVDD
AN34 GND_78
GND_79
GND_178
GND_179
U23
<23> +XS_PLLVDD RV575 1 DIS@ 2 0_0402_5% AN4 V12
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

AN7 GND_80 GND_180 V14

1 1 1 GND_81 GND_181
AP2 V16
0.1U_0402_10V7K

AP33 GND_82 GND_182 V19

CV850
CV1051

CV1050

1 GND_83 GND_183
B1 V21
CV851

2 2 2 B10 GND_84 GND_184 V23

B22 GND_85 GND_185 W13
2 B25 GND_86 GND_186 W15
B DIS@ DIS@ DIS@ B28 GND_87 GND_187 W17 B

DIS@ B31 GND_88 GND_188 W18

B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
+1.8V_PLLVDD C22 GND_95 GND_195 Y19
+VID_PLLVDD
Under +1.8V_PLLVDD
C25 GND_96
GND_97
GND_196
GND_197
Y21
RV582 1 DIS@ 2 0_0402_5% C28 Y23
<23> +VID_PLLVDD
Under
+SP_PLLVDD
C7 GND_98
GND_99
GND_198
GND_199
AH11
<23> +SP_PLLVDD RV576 1 DIS@ 2 0_0402_5% C16
0.1U_0402_10V7K

GND_OPT W32
1 GND_OPT
CV854

0.1U_0402_10V7K

1
CV852

2 N17P-GT_BGA908

DIS@ 2

DIS@

+1.8V_PLLVDD +1.8V_GFX_RUN

Near LV23 1 DIS@ 2 PBY160808T-300Y-N_2P

30 ohm
10U_0402_6.3V6M

22U_0402_6.3V6M

1 1
CV855

(ESR=0.03) Bead
CV856

2 2
DIS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P26-N17P_VGA CORE/GND

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 26 of 76
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63]
<28> FBA_D[0..63]
FBC_D[0..63]
<29> FBC_D[0..63]
UV18B @ PU for X32 mode
PU for X32 mode
Part 2 of 7 UV18C @
FBA_D0 L28 U30 FBA_CS#_L
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_MA3_BA3_L FBA_CS#_L <28>
Part 3 of 7
FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_MA2_BA0_L FBA_MA3_BA3_L <28> FBC_D0 G9 D13 FBC_CS#_L
FBA_D3 M28 FBA_D2 FBA_CMD2 R34 FBA_MA4_BA2_L FBA_MA2_BA0_L <28> FBC_D1 E9 FBB_D0 FBB_CMD0 E14 FBC_MA3_BA3_L FBC_CS#_L <29>
FBA_D4 N31 FBA_D3 FBA_CMD3 R33 FBA_MA5_BA1_L FBA_MA4_BA2_L <28> FBC_D2 G8 FBB_D1 FBB_CMD1 F14 FBC_MA2_BA0_L FBC_MA3_BA3_L <29>
FBA_D5 P29 FBA_D4 FBA_CMD4 U32 FBA_WE#_L FBA_MA5_BA1_L <28> +1.35VSDGPU FBC_D3 F9 FBB_D2 FBB_CMD2 A12 FBC_MA4_BA2_L FBC_MA2_BA0_L <29>
D FBA_D6 R29 FBA_D5 FBA_CMD5 U33 FBA_MA7_MA8_L FBA_WE#_L <28> FBC_D4 F11 FBB_D3 FBB_CMD3 B12 FBC_MA5_BA1_L FBC_MA4_BA2_L <29> D
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_MA6_MA11_L FBA_MA7_MA8_L <28> FBC_D5 G11 FBB_D4 FBB_CMD4 C14 FBC_WE#_L FBC_MA5_BA1_L <29> +1.35VSDGPU
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <28> FBB_D5 FBB_CMD5 FBC_WE#_L <29>

1
FBA_D8 J28 V28 FBA_ABI#_L DIS@ FBC_D6 F12 B14 FBC_MA7_MA8_L
FBA_D9 H29 FBA_D8 FBA_CMD8 V29 FBA_MA12_RFU_L FBA_ABI#_L <28> FBC_D7 G12 FBB_D6 FBB_CMD6 G15 FBC_MA6_MA11_L FBC_MA7_MA8_L <29>
RV605
FBA_D9 FBA_CMD9 FBA_MA12_RFU_L <28> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <29>

1
FBA_D10 J29 V30 FBA_MA0_MA10_L FBC_D8 G6 F15 FBC_ABI#_L DIS@
FBA_D11 FBA_D10 FBA_CMD10 FBA_MA1_MA9_L FBA_MA0_MA10_L <28> 10K_0402_5% FBC_D9 FBB_D8 FBB_CMD8 FBC_MA12_RFU_L FBC_ABI#_L <29>
H28 U34 F5 E15 RV606
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_RAS#_L FBA_MA1_MA9_L <28> FBC_D10 E6 FBB_D9 FBB_CMD9 D15 FBC_MA0_MA10_L FBC_MA12_RFU_L <29>
10K_0402_5%

2
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_RST#_L FBA_RAS#_L <28> FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1_MA9_L FBC_MA0_MA10_L <29>
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CKE_L FBA_RST#_L <28> FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_RAS#_L FBC_MA1_MA9_L <29>

2
FBA_D15 F30 FBA_D14 FBA_CMD14 Y32 FBA_CAS#_L FBA_CKE_L <28> FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_RST#_L FBC_RAS#_L <29>
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS#_H FBA_CAS#_L <28> FBC_D14 E2 FBB_D13 FBB_CMD13 B15 FBC_CKE_L FBC_RST#_L <29>
FBA_D17 D32 FBA_D16 FBA_CMD16 AA29 FBA_MA3_BA3_H FBA_CS#_H <28> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#_L FBC_CKE_L <29>
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H <28> FBC_D16 C2 FBB_D15 FBB_CMD15 D18 FBC_CS#_H FBC_CAS#_L <29>
FBA_D19 C33 FBA_D18 FBA_CMD18 AC34 FBA_MA4_BA2_H FBA_MA2_BA0_H <28> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_MA3_BA3_H FBC_CS#_H <29>
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA5_BA1_H FBA_MA4_BA2_H <28> FBC_D18 D3 FBB_D17 FBB_CMD17 F18 FBC_MA2_BA0_H FBC_MA3_BA3_H <29>
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_WE#_H FBA_MA5_BA1_H <28> +1.35VSDGPU FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H <29>
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA7_MA8_H FBA_WE#_H <28> FBC_D20 B3 FBB_D19 FBB_CMD19 B20 FBC_MA5_BA1_H FBC_MA4_BA2_H <29>
FBA_D23 H32 FBA_D22 FBA_CMD22 Y28 FBA_MA6_MA11_H FBA_MA7_MA8_H <28> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_WE#_H FBC_MA5_BA1_H <29> +1.35VSDGPU
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <28> FBB_D21 FBB_CMD21 FBC_WE#_H <29>

1
FBA_D24 P34 Y29 FBA_ABI#_H DIS@ FBC_D22 B5 B18 FBC_MA7_MA8_H
FBA_D25 P32 FBA_D24 FBA_CMD24 W31 FBA_MA12_RFU_H FBA_ABI#_H <28> FBC_D23 C5 FBB_D22 FBB_CMD22 G18 FBC_MA6_MA11_H FBC_MA7_MA8_H <29>
RV607
FBA_D25 FBA_CMD25 FBA_MA12_RFU_H <28> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <29>

1
FBA_D26 P31 Y30 FBA_MA0_MA10_H FBC_D24 A11 G17 FBC_ABI#_H DIS@
FBA_D27 FBA_D26 FBA_CMD26 FBA_MA1_MA9_H FBA_MA0_MA10_H <28> 10K_0402_5% FBC_D25 FBB_D24 FBB_CMD24 FBC_MA12_RFU_H FBC_ABI#_H <29>
P33 AA34 C11 F17 RV608
FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_RAS#_H FBA_MA1_MA9_H <28> FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_MA0_MA10_H FBC_MA12_RFU_H <29>
10K_0402_5%

2
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_RST#_H FBA_RAS#_H <28> FBC_D27 B11 FBB_D26 FBB_CMD26 A18 FBC_MA1_MA9_H FBC_MA0_MA10_H <29>
FBA_D30 FBA_D29 FBA_CMD29 FBA_CKE_H FBA_RST#_H <28> FBC_D28 FBB_D27 FBB_CMD27 FBC_RAS#_H FBC_MA1_MA9_H <29>

MEMORY INTERFACE B
L32 Y33 D8 D17

2
FBA_D31 L33 FBA_D30 FBA_CMD30 V31 FBA_CAS#_H FBA_CKE_H <28> FBC_D29 A8 FBB_D28 FBB_CMD28 A17 FBC_RST#_H FBC_RAS#_H <29>
FBA_D32 AG28 FBA_D31 FBA_CMD31 R28 FBA_CAS#_H <28> FBC_D30 C8 FBB_D29 FBB_CMD29 B17 FBC_CKE_H FBC_RST#_H <29>
FBA_D33 AF29 FBA_D32 FBA_CMD32 AC28 FBC_D31 B8 FBB_D30 FBB_CMD30 E17 FBC_CAS#_H FBC_CKE_H <29>
FBA_D34 FBA_D33 FBA_CMD33 FBC_D32 FBB_D31 FBB_CMD31 FBC_CAS#_H <29>

MEMORY INTERFACE
AG29 R32 F24 G14
FBA_D35 AF28 FBA_D34 FBA_CMD34 AC32 FBC_D33 G23 FBB_D32 FBB_CMD32 G20
FBA_D36 AD30 FBA_D35 FBA_CMD35 FBC_D34 E24 FBB_D33 FBB_CMD33 C12
FBA_D37 AD29 FBA_D36 FBC_D35 G24 FBB_D34 FBB_CMD34 C20
C FBA_D38 AC29 FBA_D37 FBC_D36 D21 FBB_D35 FBB_CMD35 C
FBA_D39 AD28 FBA_D38 FBC_D37 E21 FBB_D36
FBA_D40 AJ29 FBA_D39 FBC_D38 G21 FBB_D37
FBA_D41 AK29 FBA_D40 FBC_D39 F21 FBB_D38
FBA_D42 AJ30 FBA_D41 FBC_D40 G27 FBB_D39
FBA_D43 AK28 FBA_D42 FBC_D41 D27 FBB_D40
FBA_D44 AM29 FBA_D43 FBC_D42 G26 FBB_D41
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D43 E27 FBB_D42
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 <28> FBC_D44 E29 FBB_D43
FBA_D47 AM30 FBA_D46 FBA_CLK0_N AB31 FBA_CLK1 FBA_CLK0# <28> FBC_D45 F29 FBB_D44 D12 FBC_CLK0
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 <28> FBC_D46 E30 FBB_D45 FBB_CLK0 E12 FBC_CLK0# FBC_CLK0 <29>
FBA_D49 AN32 FBA_D48 FBA_CLK1_N FBA_CLK1# <28> FBC_D47 D30 FBB_D46 FBB_CLK0_N E20 FBC_CLK1 FBC_CLK0# <29>
FBC_CLK1 <29>
A

FBA_D50 AP30 FBA_D49 FBC_D48 A32 FBB_D47 FBB_CLK1 F20 FBC_CLK1#

FBA_D51 AP32 FBA_D50 FBC_D49 C31 FBB_D48 FBB_CLK1_N FBC_CLK1# <29>
FBA_D52 AM33 FBA_D51 K31 FBA_WCK0 FBC_D50 C32 FBB_D49
FBA_D53 AL31 FBA_D52 FBA_WCK01 L30 FBA_WCK0_N FBA_WCK0 <28> FBC_D51 B32 FBB_D50
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK1 FBA_WCK0_N <28> FBC_D52 D29 FBB_D51 F8 FBC_WCK0
FBA_D55 AK32 FBA_D54 FBA_WCK23 J34 FBA_WCK1_N FBA_WCK1 <28> FBC_D53 A29 FBB_D52 FBB_WCK01 E8 FBC_WCK0_N FBC_WCK0 <29>
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK2 FBA_WCK1_N <28> FBC_D54 C29 FBB_D53 FBB_WCK01_N A5 FBC_WCK1 FBC_WCK0_N <29>
FBA_D57 AD32 FBA_D56 FBA_WCK45 AG31 FBA_WCK2_N FBA_WCK2 <28> FBC_D55 B29 FBB_D54 FBB_WCK23 A6 FBC_WCK1_N FBC_WCK1 <29>
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK3 FBA_WCK2_N <28> FBC_D56 B21 FBB_D55 FBB_WCK23_N D24 FBC_WCK2 FBC_WCK1_N <29>
FBA_D59 AD33 FBA_D58 FBA_WCK67 AK34 FBA_WCK3_N FBA_WCK3 <28> FBC_D57 C23 FBB_D56 FBB_WCK45 D25 FBC_WCK2_N FBC_WCK2 <29>
FBA_D60 AF31 FBA_D59 FBA_WCK67_N FBA_WCK3_N <28> FBC_D58 A21 FBB_D57 FBB_WCK45_N B27 FBC_WCK3 FBC_WCK2_N <29>
FBA_D61 AG34 FBA_D60 FBC_D59 C21 FBB_D58 FBB_WCK67 C27 FBC_WCK3_N FBC_WCK3 <29>
FBA_D62 AG32 FBA_D61 FBC_D60 B24 FBB_D59 FBB_WCK67_N FBC_WCK3_N <29>
FBA_D63 AG33 FBA_D62 J30 FBC_D61 C24 FBB_D60
FBA_D63 FBA_WCKB01 J31 FBC_D62 B26 FBB_D61
FBA_DBI0# P30 FBA_WCKB01_N J32 FBC_D63 C26 FBB_D62 D6
<28> FBA_DBI0# FBA_DBI1# FBA_DQM0 FBA_WCKB23 FBB_D63 FBB_WCKB01
F31 J33 D7
<28> FBA_DBI1# FBA_DBI2# FBA_DQM1 FBA_WCKB23_N FBC_DBI0# FBB_WCKB01_N
F34 AH31 E11 C6
<28> FBA_DBI2# FBA_DBI3# FBA_DQM2 FBA_WCKB45 <29> FBC_DBI0# FBC_DBI1# FBB_DQM0 FBB_WCKB23
M32 AJ31 E3 B6
<28> FBA_DBI3# FBA_DBI4# FBA_DQM3 FBA_WCKB45_N <29> FBC_DBI1# FBC_DBI2# FBB_DQM1 FBB_WCKB23_N
AD31 AJ32 A3 F26
<28> FBA_DBI4# FBA_DBI5# FBA_DQM4 FBA_WCKB67 <29> FBC_DBI2# FBC_DBI3# FBB_DQM2 FBB_WCKB45
B AL29 AJ33 C9 E26 B
<28> FBA_DBI5# FBA_DBI6# FBA_DQM5 FBA_WCKB67_N <29> FBC_DBI3# FBC_DBI4# FBB_DQM3 FBB_WCKB45_N
AM32 F23 A26
<28> FBA_DBI6# FBA_DBI7# FBA_DQM6 <29> FBC_DBI4# FBC_DBI5# FBB_DQM4 FBB_WCKB67
AF34 F27 A27
<28> FBA_DBI7# FBA_DQM7 <29> FBC_DBI5# FBC_DBI6# FBB_DQM5 FBB_WCKB67_N
C30
FBA_EDC0 +FB_PLLAVDD <29> FBC_DBI6# FBC_DBI7# FBB_DQM6
M31 A24
FBA_EDC1 FBA_DQS_WP0 <29> FBC_DBI7# FBB_DQM7
G31
<28> FBA_EDC[7..0] FBA_EDC2
FBA_EDC3
E33 FBA_DQS_WP1
FBA_DQS_WP2
50mA FBC_EDC0
FBC_EDC1
D10
FBB_DQS_WP0
M33 D5
FBA_EDC4 AE31 FBA_DQS_WP3 K27 CV921 1DIS@ 2 0.1U_0402_10V7K +FB_PLLAVDD FBC_EDC2 C3 FBB_DQS_WP1
FBA_EDC5 AK30 FBA_DQS_WP4 FB_REFPLL_AVDD <29> FBC_EDC[7..0] FBC_EDC3 B9 FBB_DQS_WP2
FBA_EDC6 AN33 FBA_DQS_WP5 FBC_EDC4 E23 FBB_DQS_WP3 H17
FBA_EDC7 FBA_DQS_WP6 Place close to ball +1.8V_GFX_RUN FBC_EDC5 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD

0.1U_0402_10V7K
AF33 E28
FBA_DQS_WP7 FBC_EDC6 FBB_DQS_WP5

CV922
U27 LV24 1 DIS@ 2 PBY160808T-300Y-N_2P B30 1
FBA_PLL_AVDD FBC_EDC7 FBB_DQS_WP6 120mA
22U_0603_6.3V6M
0.1U_0402_10V7K

M30 A23
FBA_DQS_RN0 120mA FBB_DQS_WP7
CV923

CV924

H30 1 1
E34 FBA_DQS_RN1
FBA_DQS_RN2
300mA D9
FBB_DQS_RN0 2
M34 H31 E4
AF30 FBA_DQS_RN3 FB_VREF B2 FBB_DQS_RN1
AK31 FBA_DQS_RN4 2 2 A9 FBB_DQS_RN2
AM34 FBA_DQS_RN5 D22 FBB_DQS_RN3 DIS@
AF32 FBA_DQS_RN6 D28 FBB_DQS_RN4
FBA_DQS_RN7 DIS@ DIS@ A30 FBB_DQS_RN5
FBB_DQS_RN6
Place close to ball
B23
Place close to ball FBB_DQS_RN7
N17P-GT_BGA908 Place close to BGA
N17P-GT_BGA908

FBA_RST#_L FBC_RST#_L
A FBA_RST#_H FBC_RST#_H A
1

DIS@ DIS@ DIS@ DIS@

RV613 RV614 RV615 RV616
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P27-N17P_MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 27 of 76
5 4 3 2 1
 5 4 3 2 1

Memory Part i t i on A- L ower 32 bi t MF=0 MF=1

UV23 UV24
FBA_D[0..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
<27> FBA_D[0..63]
FBA_EDC[7..0] A4 FBA_D0 A4 FBA_D56
<27> FBA_EDC[7..0] FBA_EDC0 DQ24 DQ0 FBA_D1 FBA_EDC7 DQ24 DQ0 FBA_D57
C2 A2 C2 A2
FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 FBA_EDC6 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4 FBA_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60
EDC3 EDC0 DQ28 DQ4 FBA_D5 BYTE0 EDC3 EDC0 DQ28 DQ4 FBA_D61 BYTE7
E2 E2
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D62
FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
<27> FBA_DBI0# FBA_DBI1# DBI0# DBI3# DQ31 DQ7 FBA_D8 <27> FBA_DBI7# FBA_DBI6# DBI0# DBI3# DQ31 DQ7 FBA_D48
D13 A11 D13 A11
<27> FBA_DBI1# FBA_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9 <27> FBA_DBI6# FBA_DBI5# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D49
<27> FBA_DBI2# FBA_DBI3# DBI2# DBI1# DQ17 DQ9 FBA_D10 <27> FBA_DBI5# FBA_DBI4# DBI2# DBI1# DQ17 DQ9 FBA_D50
P2 B11 P2 B11
D <27> FBA_DBI3# DBI3# DBI0# DQ18 DQ10 FBA_D11 <27> FBA_DBI4# DBI3# DBI0# DQ18 DQ10 FBA_D51 D
B13 BYTE1 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12 FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D52
<27> FBA_CLK0 FBA_CLK0# CK DQ20 DQ12 FBA_D13 <27> FBA_CLK1 FBA_CLK1# CK DQ20 DQ12 FBA_D53 BYTE6
J11 E13 J11 E13
<27> FBA_CLK0# FBA_CKE_L J3 CK# DQ21 DQ13 F11 FBA_D14 <27> FBA_CLK1# FBA_CKE_H J3 CK# DQ21 DQ13 F11 FBA_D54
<27> FBA_CKE_L CKE# DQ22 DQ14 FBA_D15 <27> FBA_CKE_H CKE# DQ22 DQ14 FBA_D55
F13 F13
DQ23 DQ15 U11 FBA_D16 DQ23 DQ15 U11 FBA_D40
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
<27> FBA_MA2_BA0_L FBA_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18 <27> FBA_MA4_BA2_H FBA_MA3_BA3_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D42
K10 T11 K10 T11
<27> FBA_MA5_BA1_L FBA_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19 <27> FBA_MA3_BA3_H FBA_MA2_BA0_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D43
<27> FBA_MA4_BA2_L FBA_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20 BYTE2 <27> FBA_MA2_BA0_H FBA_MA5_BA1_H BA2/A4 BA0/A2 DQ11 DQ19 FBA_D44
H10 N11 H10 N11 BYTE5
<27> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBA_D21 <27> FBA_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBA_D45
N13 N13
DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D46
FBA_MA7_MA8_L K4 DQ14 DQ22 M13 FBA_D23 FBA_MA0_MA10_H K4 DQ14 DQ22 M13 FBA_D47
<27> FBA_MA7_MA8_L FBA_MA1_MA9_L H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D24 <27> FBA_MA0_MA10_H FBA_MA6_MA11_H H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D32
<27> FBA_MA1_MA9_L FBA_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBA_D25 <27> FBA_MA6_MA11_H FBA_MA7_MA8_H A9/A1 A11/A6 DQ0 DQ24 FBA_D33
H4 U2 H4 U2
<27> FBA_MA0_MA10_L FBA_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBA_D26 <27> FBA_MA7_MA8_H FBA_MA1_MA9_H A10/A0 A8/A7 DQ1 DQ25 FBA_D34
K5 T4 K5 T4
<27> FBA_MA6_MA11_L FBA_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D27 <27> FBA_MA1_MA9_H FBA_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D35
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBA_D28 BYTE3 <27> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBA_D36 BYTE4
N4 N4
A5 DQ4 DQ28 N2 FBA_D29 A5 DQ4 DQ28 N2 FBA_D37
U5 VPP/NC DQ5 DQ29 M4 FBA_D30 +1.35VSDGPU U5 VPP/NC DQ5 DQ29 M4 FBA_D38
RV617 2 DIS@ 1 1K_0402_1% VPP/NC DQ6 DQ30 M2 FBA_D31 RV618 2 DIS@ 1 1K_0402_1% VPP/NC DQ6 DQ30 M2 FBA_D39
DQ7 DQ31 DQ7 DQ31
GPU_MF_BALL_A J1 +1.35VSDGPU Remove 0321 GPU_MF_BALL_B J1 +1.35VSDGPU
J10 MF J10 MF
RV619 2 DIS@ 1 121_0402_1% GPU_ZQ_BALL_A J13 SEN B1 RV620 2 DIS@ 1 121_0402_1% GPU_ZQ_BALL_B J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
FBA_ABI#_L J4 VDDQ M1 FBA_ABI#_H J4 VDDQ M1
<27> FBA_ABI#_L FBA_RAS#_L G3 ABI# VDDQ P1 <27> FBA_ABI#_H FBA_CAS#_H G3 ABI# VDDQ P1
<27> FBA_RAS#_L FBA_CS#_L RAS# CAS# VDDQ <27> FBA_CAS#_H FBA_WE#_H RAS# CAS# VDDQ
G12 T1 G12 T1
FBA_CLK0 <27> FBA_CS#_L FBA_CAS#_L CS# WE# VDDQ <27> FBA_WE#_H FBA_RAS#_H CS# WE# VDDQ
L3 G2 L3 G2
<27> FBA_CAS#_L FBA_WE#_L L12 CAS# RAS# VDDQ L2 <27> FBA_RAS#_H FBA_CS#_H L12 CAS# RAS# VDDQ L2
FBA_CLK0# <27> FBA_WE#_L WE# CS# VDDQ <27> FBA_CS#_H WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
VDDQ VDDQ
1

DIS@ DIS@ FBA_WCK0_N D5 H3 FBA_WCK3_N D5 H3

<27> FBA_WCK0_N FBA_WCK0 D4 WCK01# WCK23# VDDQ K3 <27> FBA_WCK3_N FBA_WCK3 D4 WCK01# WCK23# VDDQ K3
RV621 RV622
<27> FBA_WCK0 WCK01 WCK23 VDDQ <27> FBA_WCK3 WCK01 WCK23 VDDQ
C 40.2_0201_1% 40.2_0201_1% M3 M3 C
FBA_WCK1_N P5 VDDQ P3 FBA_WCK2_N P5 VDDQ P3
<27> FBA_WCK1_N FBA_WCK1 WCK23# WCK01# VDDQ <27> FBA_WCK2_N FBA_WCK2 WCK23# WCK01# VDDQ
P4 T3 P4 T3
<27> FBA_WCK1 <27> FBA_WCK2
2

WCK23 WCK01 VDDQ E5 WCK23 WCK01 VDDQ E5

VDDQ N5 VDDQ N5
@ TV3 GPU_VREFD_BALL_A A10 VDDQ E10 @ TV4 GPU_VREFD_BALL_B A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
1 +FBA_VREFC0 VREFD VDDQ +FBA_VREFC0 VREFD VDDQ
DIS@ J14 B12 J14 B12
CV925 VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
0.01U_0201_16V7K VDDQ VDDQ
2 H12 H12

820P_0402_25V7
FBA_RST#_L J2 VDDQ K12 FBA_RST#_H J2 VDDQ K12
<27> FBA_RST#_L RESET# VDDQ 1 <27> FBA_RST#_H RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12

CV926
VDDQ T12 VDDQ T12
MEM_VREF levels +1.35VSDGPU VDDQ G13 2 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
70% of rail Terminat i on Enabl e K1 VSS VDDQ B14 DIS@ K1 VSS VDDQ B14
VSS VDDQ VSS VDDQ
1

DIS@ B5 D14 B5 D14

50% of rail Terminat i on Disabl e RV623 G5 VSS VDDQ F14 G5 VSS VDDQ F14
549_0402_1% L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
RV624 VSS VDDQ VSS VDDQ
B10 T14 B10 T14
2

1 DIS@ 2 +FBA_VREFC0 D10 VSS VDDQ D10 VSS VDDQ

931_0402_1% G10 VSS G10 VSS
W=16mils L10 VSS A1 FBA_CLK1 L10 VSS A1
820P_0402_25V7

VSS VSSQ VSS VSSQ

1

DIS@ P10 C1 P10 C1

CV927

1 VSS VSSQ FBA_CLK1# VSS VSSQ

RV625 T10 E1 T10 E1
1.33K_0402_1% H14 VSS VSSQ N1 H14 VSS VSSQ N1
K14 VSS VSSQ R1 K14 VSS VSSQ R1
VSS VSSQ VSS VSSQ

1
2 +1.35VSDGPU U1 DIS@ DIS@ +1.35VSDGPU U1
2

VSSQ H2 RV626 RV627 VSSQ H2

G1 VSSQ K2 40.2_0201_1% 40.2_0201_1% G1 VSSQ K2
DIS@ VDD VSSQ VDD VSSQ
L1 A3 L1 A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3

2
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
B
C10 VDD VSSQ U3 C10 VDD VSSQ U3 B
VDD VSSQ 1 VDD VSSQ
R10 C4 DIS@ R10 C4
D11 VDD VSSQ R4 CV928 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
VDD VSSQ 0.01U_0201_16V7K VDD VSSQ
L11 M5 2 L11 M5
+FBA_VREFC0_R P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 +1.35VSDGPU VSSQ C12
VSSQ Under DRAM VSSQ
1

D E12 E12
2 VSSQ N12 VSSQ N12
<23,29> MEM_VREF VSSQ R12 VSSQ R12
G DIS@
QV101 170-BALL VSSQ U12 170-BALL VSSQ U12
S
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
3

BSS138W 1N SOT-323-3 VSSQ H13 VSSQ H13

VSSQ 1 1 1 1 1 1 1 1 VSSQ
SGRAM GDDR5 K13 SGRAM GDDR5 K13
CV929

CV930

CV931

CV932

CV933

CV934

CV935

CV936
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 2 2 2 2 2 2 2 2 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VSSQ
U14 U14
VSSQ VSSQ
@ K4G80325FB-HC03_FBGA170~D @ K4G80325FB-HC03_FBGA170~D
+1.35VSDGPU
Around DRAM Close to DRAM +1.35VSDGPU
Around DRAM Close to DRAM
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV937

CV938

CV939

CV940

CV941

CV942

CV943

CV944

CV945

CV946

CV947

CV948

CV949

CV950

CV951

CV952

CV953

CV954

CV955

CV956

CV957

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV958

CV959

CV960

CV961

CV962

CV963

CV964

CV965

CV966

CV967

CV968

CV969

CV970

CV971

CV972

CV973

CV974

CV975

CV976

CV977

CV978
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
A DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ A
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

+1.35VSDGPU
Under DRAM
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1
CV979

CV980

CV981

CV982

CV983

CV984

CV985

CV986

2 2 2 2 2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ P28-N17P_GDDR5_A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 28 of 76
5 4 3 2 1
 5 4 3 2 1

Memory Part i t i on A- L ower 32 bi t UV25 MF=0 UV26 MF=1

MF=0 MF=1 MF=1 MF=0
FBC_D[0..63] MF=0 MF=1 MF=1 MF=0
<27> FBC_D[0..63] A4 FBC_D56
FBC_EDC[7..0] A4 FBC_D0 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<27> FBC_EDC[7..0] FBC_EDC0 DQ24 DQ0 FBC_D1 FBC_EDC6 EDC0 EDC3 DQ25 DQ1 FBC_D58
C2 A2 C13 B4
FBC_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D60
FBC_EDC3 EDC2 EDC1 DQ27 DQ3 FBC_D4 BYTE0 EDC3 EDC0 DQ28 DQ4 FBC_D61 BYTE7
R2 E4 E2
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 DQ29 DQ5 F4 FBC_D62
DQ29 DQ5 F4 FBC_D6 FBC_DBI7# D2 DQ30 DQ6 F2 FBC_D63
FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7 <27> FBC_DBI7# FBC_DBI6# D13 DBI0# DBI3# DQ31 DQ7 A11 FBC_D48
<27> FBC_DBI0# FBC_DBI1# DBI0# DBI3# DQ31 DQ7 FBC_D8 <27> FBC_DBI6# FBC_DBI5# DBI1# DBI2# DQ16 DQ8 FBC_D49
D13 A11 P13 A13
<27> FBC_DBI1# FBC_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_D9 <27> FBC_DBI5# FBC_DBI4# P2 DBI2# DBI1# DQ17 DQ9 B11 FBC_D50
<27> FBC_DBI2# FBC_DBI3# DBI2# DBI1# DQ17 DQ9 FBC_D10 <27> FBC_DBI4# DBI3# DBI0# DQ18 DQ10 FBC_D51
P2 B11 B13
D <27> FBC_DBI3# DBI3# DBI0# DQ18 DQ10 FBC_D11 FBC_CLK1 DQ19 DQ11 FBC_D52 D
B13 BYTE1 J12 E11 BYTE6
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_D12 <27> FBC_CLK1 FBC_CLK1# J11 CK DQ20 DQ12 E13 FBC_D53
<27> FBC_CLK0 FBC_CLK0# CK DQ20 DQ12 FBC_D13 <27> FBC_CLK1# FBC_CKE_H CK# DQ21 DQ13 FBC_D54
J11 E13 J3 F11
<27> FBC_CLK0# FBC_CKE_L J3 CK# DQ21 DQ13 F11 FBC_D14 <27> FBC_CKE_H CKE# DQ22 DQ14 F13 FBC_D55
<27> FBC_CKE_L CKE# DQ22 DQ14 FBC_D15 DQ23 DQ15 FBC_D40
F13 U11
DQ23 DQ15 U11 FBC_D16 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
FBC_MA2_BA0_L H11 DQ8 DQ16 U13 FBC_D17 <27> FBC_MA4_BA2_H FBC_MA3_BA3_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D42
<27> FBC_MA2_BA0_L FBC_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBC_D18 <27> FBC_MA3_BA3_H FBC_MA2_BA0_H BA1/A5 BA3/A3 DQ10 DQ18 FBC_D43
K10 T11 K11 T13
<27> FBC_MA5_BA1_L FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 <27> FBC_MA2_BA0_H FBC_MA5_BA1_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBC_D44
<27> FBC_MA4_BA2_L FBC_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBC_D20 <27> FBC_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBC_D45 BYTE5
H10 N11 BYTE2 N13
<27> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBC_D21 DQ13 DQ21 FBC_D46
N13 M11
DQ13 DQ21 M11 FBC_D22 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
FBC_CLK0 FBC_MA7_MA8_L DQ14 DQ22 FBC_D23 <27> FBC_MA0_MA10_H FBC_MA6_MA11_H A8/A7 A10/A0 DQ15 DQ23 FBC_D32
K4 M13 H5 U4
<27> FBC_MA7_MA8_L FBC_MA1_MA9_L H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBC_D24 <27> FBC_MA6_MA11_H FBC_MA7_MA8_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D33
FBC_CLK0# <27> FBC_MA1_MA9_L FBC_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBC_D25 <27> FBC_MA7_MA8_H FBC_MA1_MA9_H A10/A0 A8/A7 DQ1 DQ25 FBC_D34
H4 U2 K5 T4
<27> FBC_MA0_MA10_L FBC_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBC_D26 <27> FBC_MA1_MA9_H FBC_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBC_D35
K5 T4 J5 T2 BYTE4
<27> FBC_MA6_MA11_L FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_D27 <27> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 N4 FBC_D36
<27> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 BYTE3 DQ4 DQ28
1

DIS@ DIS@ N4 FBC_D28 A5 N2 FBC_D37

RV628 RV629 A5 DQ4 DQ28 N2 FBC_D29 +1.35VSDGPU U5 VPP/NC DQ5 DQ29 M4 FBC_D38
40.2_0201_1% 40.2_0201_1% U5 VPP/NC DQ5 DQ29 M4 FBC_D30 RV630 2 DIS@ 1 1K_0201_1% VPP/NC DQ6 DQ30 M2 FBC_D39
RV631 2 DIS@ 1 1K_0402_1% VPP/NC DQ6 DQ30 M2 FBC_D31 DQ7 DQ31
DQ7 DQ31 GPU_MF_BALL_D J1 +1.35VSDGPU
2

GPU_MF_BALL_C J1 +1.35VSDGPU J10 MF

J10 MF RV632 2 DIS@ 1 121_0402_1% GPU_ZQ_BALL_D J13 SEN B1
RV633 2 DIS@ 1 121_0402_1% GPU_ZQ_BALL_C J13 SEN B1 ZQ VDDQ D1
ZQ VDDQ D1 VDDQ F1
1 VDDQ FBC_ABI#_H VDDQ
DIS@ F1 J4 M1
FBC_ABI#_L VDDQ <27> FBC_ABI#_H FBC_CAS#_H ABI# VDDQ
CV987 J4 M1 G3 P1
<27> FBC_ABI#_L FBC_RAS#_L G3 ABI# VDDQ P1 <27> FBC_CAS#_H FBC_WE#_H G12 RAS# CAS# VDDQ T1
0.01U_0201_16V7K <27> FBC_RAS#_L RAS# CAS# VDDQ <27> FBC_WE#_H CS# WE# VDDQ
2 FBC_CS#_L G12 T1 FBC_RAS#_H L3 G2
<27> FBC_CS#_L FBC_CAS#_L CS# WE# VDDQ <27> FBC_RAS#_H FBC_CS#_H CAS# RAS# VDDQ
L3 G2 L12 L2
<27> FBC_CAS#_L FBC_WE#_L L12 CAS# RAS# VDDQ L2 <27> FBC_CS#_H WE# CS# VDDQ B3
<27> FBC_WE#_L WE# CS# VDDQ VDDQ
B3 D3
VDDQ D3 VDDQ F3
VDDQ F3 FBC_WCK3_N D5 VDDQ H3
FBC_WCK0_N VDDQ <27> FBC_WCK3_N FBC_WCK3 WCK01# WCK23# VDDQ
D5 H3 D4 K3
<27> FBC_WCK0_N FBC_WCK0 D4 WCK01# WCK23# VDDQ K3 <27> FBC_WCK3 WCK01 WCK23 VDDQ M3
<27> FBC_WCK0 WCK01 WCK23 VDDQ FBC_WCK2_N VDDQ
C M3 P5 P3 C
FBC_WCK1_N P5 VDDQ P3 <27> FBC_WCK2_N FBC_WCK2 P4 WCK23# WCK01# VDDQ T3
<27> FBC_WCK1_N FBC_WCK1 WCK23# WCK01# VDDQ <27> FBC_WCK2 WCK23 WCK01 VDDQ
P4 T3 E5
<27> FBC_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 @ TV5 GPU_VREFD_BALL_D A10 VDDQ E10
@ TV6 GPU_VREFD_BALL_C A10 VDDQ E10 U10 VREFD VDDQ N10
U10 VREFD VDDQ N10 +FBC_VREFC1 J14 VREFD VDDQ B12
+FBC_VREFC1 J14 VREFD VDDQ B12 VREFC VDDQ D12
VREFC VDDQ D12 VDDQ F12

820P_0402_25V7
VDDQ F12 VDDQ H12
VDDQ 1 FBC_RST#_H VDDQ
H12 J2 K12
FBC_RST#_L J2 VDDQ K12 <27> FBC_RST#_H RESET# VDDQ M12

CV988
<27> FBC_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 2 VDDQ T12
VDDQ T12 VDDQ G13
MEM_VREF levels VDDQ G13 DIS@ H1 VDDQ L13
H1 VDDQ L13 K1 VSS VDDQ B14
70% of rail Terminat i on Enabl e +1.35VSDGPU K1 VSS VDDQ B14 B5 VSS VDDQ D14
B5 VSS VDDQ D14 G5 VSS VDDQ F14
50% of rail Terminat i on Disabl e G5 VSS VDDQ F14 L5 VSS VDDQ M14
VSS VDDQ VSS VDDQ
1

DIS@ L5 M14 T5 P14

RV634 T5 VSS VDDQ P14 B10 VSS VDDQ T14
549_0402_1% B10 VSS VDDQ T14 D10 VSS VDDQ
D10 VSS VDDQ G10 VSS
RV635 G10 VSS L10 VSS A1
2

1 DIS@ 2 +FBC_VREFC1 L10 VSS A1 FBC_CLK1 P10 VSS VSSQ C1

931_0402_1% P10 VSS VSSQ C1 T10 VSS VSSQ E1
W=16mils T10 VSS VSSQ E1 FBC_CLK1# H14 VSS VSSQ N1
820P_0402_25V7

VSS VSSQ VSS VSSQ

1

DIS@ H14 N1 K14 R1

CV989

1 VSS VSSQ VSS VSSQ

RV636 K14 R1 +1.35VSDGPU U1
VSS VSSQ VSSQ

1
1.33K_0402_1% +1.35VSDGPU U1 DIS@ DIS@ H2
VSSQ H2 RV637 RV638 G1 VSSQ K2
2 G1 VSSQ K2 40.2_0201_1% 40.2_0201_1% L1 VDD VSSQ A3
2

L1 VDD VSSQ A3 G4 VDD VSSQ C3

G4 VDD VSSQ C3 L4 VDD VSSQ E3
DIS@

2
L4 VDD VSSQ E3 C5 VDD VSSQ N3
C5 VDD VSSQ N3 R5 VDD VSSQ R3
R5 VDD VSSQ R3 C10 VDD VSSQ U3
B
C10 VDD VSSQ U3 R10 VDD VSSQ C4 B
VDD VSSQ 1 VDD VSSQ
R10 C4 DIS@ D11 R4
D11 VDD VSSQ R4 CV990 G11 VDD VSSQ F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
VDD VSSQ 0.01U_0201_16V7K VDD VSSQ
L11 M5 2 P11 F10
P11 VDD VSSQ F10 G14 VDD VSSQ M10
G14 VDD VSSQ M10 L14 VDD VSSQ C11
L14 VDD VSSQ C11 VDD VSSQ R11
+FBC_VREFC1_R VDD VSSQ R11 VSSQ A12
VSSQ A12 VSSQ C12
VSSQ C12 +1.35VSDGPU VSSQ E12
VSSQ
VSSQ
E12 Under DRAM VSSQ
VSSQ
N12
N12 R12
DIS@ VSSQ R12 170-BALL VSSQ U12
VSSQ VSSQ
1

D U12 H13
QV102 170-BALL
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<23,28> MEM_VREF VSSQ 1 1 1 1 1 1 1 1 VSSQ
G SGRAM GDDR5 K13 A14

CV991

CV992

CV993

CV994

CV995

CV996

CV997

CV998
VSSQ A14 VSSQ C14
S
3

BSS138W 1N SOT-323-3 VSSQ C14 VSSQ E14

VSSQ E14 2 2 2 2 2 2 2 2 VSSQ N14
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VSSQ
U14
VSSQ @ K4G80325FB-HC03_FBGA170~D
@ K4G80325FB-HC03_FBGA170~D
+1.35VSDGPU
Around DRAM Close to DRAM +1.35VSDGPU
Around DRAM Close to DRAM
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV999

CV1000

CV1001

CV1002

CV1003

CV1004

CV1005

CV1006

CV1007

CV1008

CV1009

CV1010

CV1011

CV1012

CV1013

CV1014

CV1015

CV1016

CV1017

CV1018

CV1019

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV1020

CV1021

CV1022

CV1023

CV1024

CV1025

CV1026

CV1027

CV1028

CV1029

CV1030

CV1031

CV1032

CV1033

CV1034

CV1035

CV1036

CV1037

CV1038

CV1039

CV1040
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
A DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ A
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

+1.35VSDGPU
Under DRAM
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1
CV1041

CV1042

CV1043

CV1044

CV1045

CV1046

CV1047

CV1048

2 2 2 2 2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P29-N17P_GDDR5_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 29 of 76
5 4 3 2 1
 5 4 3 2 1

SMB_ALT_ADDR State DEVID_SEL State PCIE_CFG State VGA_DEVICE State

Low Single GPU Low Original Device Low Normal signal swing Low 3D Device
+1.8V_GFX_AON
High Dual GPU High ID
Re-brand Device ID High Reduce the signal High VGA Device
amplitude

1
DIS@
RV1080
0_0402_5%

2
2

2
DIS@ DIS@ DIS@
RV639 RV640 RV641
D D
100K_0402_5% 100K_0402_5% 100K_0402_5%

1
ROM_SI
<24> ROM_SI ROM_SO
<24> ROM_SO ROM_SCLK
<24> ROM_SCLK

2
@ @ DIS@
RV642 RV643 RV644
100K_0402_5% 100K_0402_5% 100K_0402_5%

1
+1.8V_GFX_AON
2

2
@ @ @ @ @ @
RV645 RV646 RV647 RV648 RV649 RV650
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
1

1
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3
C <24> STRAP4 STRAP4 C
<24> STRAP5 STRAP5
2

2
@ @ @ DIS@ DIS@ DIS@
RV651 RV652 RV653 RV654 RV655 RV656
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P30-N17P_MISC

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 30 of 76
5 4 3 2 1
 5 4 3 2 1

+1.8V_3.3V_GFX_RUN Discharge
follow Fireload +5VALW
+1.8V_GFX_AON

+3VALW +1.35VSDGPU

1
DIS@
RV11

1
+1.8V_GFX_RUN DIS@ DIS@ DIS@ 100_0402_5%
UZ24 DIS@ RV12 RV8 RV657
+1.8V_GFX_AON 100K_0402_5% 10_0402_1% 100K_0402_5%

2
1 8
VIN VOUT

DMN63D8LDW-7_SOT363-6
2 7

2
VIN VOUT @ DIS@ DIS@
1

3
1V8_MAIN_RUN_EN 3 6 CZ98 1 2 2200P_0402_25V7K CZ99 QV3B
D EN CT 0.1U_0402_10V6K D
4 5 DIS@ DIS@ DIS@
+5VALW VBIAS GND DGPU_PWR_EN# 2 RV399
1 DIS@ 9 2 QZ6B QZ6A 1 DGPU_PWR_EN#_R 5
GND

6
CV817 DMN63D8LDW-7_SOT363-6 DMN63D8LDW-7_SOT363-6
0.1U_0402_10V7K APE8937GN2_DFN8_2X2 10K_0402_5%

4
6

0.1U_0402_10V7K
DIS@ DIS@
2 RZ106 5 2 DMN63D8LDW-7_SOT363-6 QV3A
<23,31,71> FBVDD_EN 1

CV499
0_0402_5%
1 2 1V8_AON_EN 2

1
@ DV16 2 DIS@

1
1V8_MAIN_EN 2
<23,31,68> 1V8_MAIN_EN
DIS@
1 1V8_MAIN_RUN_EN 2 1 DA57 1V8_AON_EN
RB751S40T1G_SOD523-2
3
<31,68> GPU_CORE_PG
BAT54CW-7-F_SOT323-3
+1.8VALW to +1.8V_3.3V_GFX_AON
+3VALW +GPU_CORE_VDDS +1VS_GFX
+1.8V_GFX_AON +3VALW +1.8V_GFX_RUN
+1.8VALW UZ30 DIS@ +3VALW +GPU_CORE

1
DIS@

1
1 8 RV103 DIS@ DIS@ DIS@ DIS@
VIN VOUT

1
2 7 100K_0402_5% RV1808 RV112 DIS@ DIS@ RV111 RV1811
VIN VOUT DIS@ 10_0402_1% 10_0402_1% RV1809 RV1810 100K_0402_5% 100_0402_5%
1V8_AON_EN 1 DIS@ 2 3 6 CZ2155 1 2 100P_0402_25V8K 100K_0402_5% 10_0402_1%

2
RZ1964 0_0402_5% EN CT

2
4 5
+5VALW

2
VBIAS GND 9
GND

DMN63D8LDW-7 2N SOT363-6

DMN63D8LDW-7 2N SOT363-6
C DIS@ C

L2N7002WT1G_SC-70-3

DMN63D8LDW-7 2N SOT363-6
APE8937GN2_DFN8_2X2 DIS@ DIS@ QZ17A

3
QZ14A DIS@ DIS@ QZ15A DMN63D8LDW-7 2N SOT363-6 DIS@

3
+3V_PCH DMN63D8LDW-7 2N SOT363-6 QZ14B QZ18 DMN63D8LDW-7 2N SOT363-6 DIS@ QZ17B

1
D
QZ15B
DIS@ 5 2 1V8_MAIN_RUN_EN 2 5
5

UZ31 2 G 2 5
<31,67,69> NVVDDS_EN <31,68> NVVDD_EN
S
VCC

4
1
<17> DGPU_PWR_EN

4
IN1 4 1V8_AON_EN
2 OUT
GND

0.01UF_0402_25V7K

<18,33,35,48,51> SIO_SLP_S3# IN2

1

@ DIS@
1

CV920 RV1350
1M_0402_5%
3

MC74VHC1G08DFT2G_SC70-5
2

NVVDDS Enable +1.8V_GFX_AON

NVVDD Enable
DIS@
CV917 DIS@
0.1U_0402_10V7K RB751S40T1G_SOD523-2 2 1 DA56
1 2

DIS@
A00_4P_0524 : From SE00000G880 to SE102104K00 RV1130
B DIS@ derating issue 10K_0402_5% B
5

UV28 1 2 1V8_MAIN_EN
<31,68> NVVDD_EN
1 RH5893 1 DIS@ 2 0_0201_5%
G VCC

B 1V8_MAIN_EN <23,31,68>
<31,67,69> NVVDDS_EN RV1807 1 DIS@ 2 0_0402_5% 4 DIS@
Y

1
2 CV919
A GPU_CORE_PG <31,68>
1

@ DIS@ 0.01UF_0402_25V7K
1

CV918 RV1128 TC7SZ08FU_SSOP5

3

2
0.01UF_0402_25V7K 1M_0402_5%
2

@
U33
+1.8V_GFX_AON
RV658 1 DIS@ 2 0_0603_5% +3VS_VDD 1 20
+3VS VDD PEX_VDD_EN PEX_VDD_EN <67>

0.1U_0402_10V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
2 19 1 1 1
NC FBVDDQ_EN FBVDD_EN <23,31,71>

CV794

CV796

CV798
<23,24> THERMATRIP_GPU# 3 18
OVERT# NVVDD1_EN NVVDD_EN <31,68>
4 +3VS_VDD 2 2 2
<23,48> THERMTRIP1# GPU_OVERT# 17
NVVDD2_EN NVVDDS_EN <31,67,69>
<67,69> GPU_CORE_VDDS_PG 5
NVVDD2_PGOOD DIS@ DIS@
DIS@
0.1U_0402_25V6

<23> GPU_GC6_FB_EN_GPU 6 16
GPU_GC6_FB_EN 1V8_MAIN_EN
1

GPU_GC6_FB_EN 7
<16,23,48> GPU_GC6_FB_EN GC6_FB_EN
CE3323

15
A 8 3V3_SYS_EN A
<17,23,34,35,41,42,43,48,49,50> PCH_PLTRST#_EC
2

PCH_PLTRST#
Under GPU Near GPU
14
1V8_AON_EN
9 13 A01_4P_0315:Del net name
<20,23> DGPU_HOLD_RST# DGPU_HOLD_RST# GPIO4_1V8_MAIN_EN U33.16:1V8_MAIN_RUN_EN
U33.14:1V8_AON_EN
12 U33.13:1V8_MAIN_EN
10 DGPU_PWR_EN U33.12:DGPU_PWR_EN
<23> DGPU_PEX_RST# DGPU_PEX_RST# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
10K_0402_5%2 @ 1 RV1844GPU_GC6_FB_EN 11
GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P31-DC/DC-VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
SLG4U41821VTR_STQFN20_2X3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 31 of 76
5 4 3 2 1
 A B C D E

+3VALW
+5VALW to +5VS WLAN Load Switch UN3
+3VS_WLAN +3VS_WLAN +3VS_WLAN
C267
+3VALW to +3VS +5VALW 1U_0402_6.3V6K

0.1U_0201_10V6K
UZ1 1495mA 1 2 1 8 1
1 14 2 VIN VOUT 7
+5VALW VIN1 VOUT1 +5VS VIN VOUT 1

1
C280

100P_0201_50V8J
EMI@ C1031

68P_0402_50V8J
EMI@ C1033
2 13
VIN1 VOUT1 WLAN_PWR_EN 3 6 1 2
RUN_ON_EC 3 12 +5VS_CT1 CZ4 1 2 470P_0603_50V7K EN CT @ 2
<33,48> RUN_ON_EC

2
ON1 CT1 4 5 CN22 2
4 11 VBIAS GND 9 2200P_0402_25V7K
+5VALW VBIAS GND GND
RUN_ON_EC 5 10 +3VS_CT2 CZ6 1 2 470P_0603_50V7K
ON2 CT2 APE8937GN2_DFN8_2X2
6 9 +3VALW
+3VALW VIN2 VOUT2 +3VS
7 8
VIN2 VOUT2
2041mA

2
15
1 GPAD RE275
1

RZ43 1 2 100K_0402_5% RUN_ON_EC EM5209VF_DFN14_3X2 10K_0402_5%

1
SLP_WLAN#_GATE RZ1141 1 @ 2 0_0402_5%
<48> SLP_WLAN#_GATE

2
G
Close UZ4 Close UZ4 QR105 DN3
1 3 SIO_SLP_WLAN#_R 2
+5VALW +3VALW <18,48> SIO_SLP_WLAN#
+5VS +3VS

S
1 WLAN_PWR_EN
L2N7002WT1G_SC-70-3
1 1 1 1 3
<48> AUX_EN_WOWL

2
@ CZ11 @ CZ12 CZ8 CZ9 RZ1149 1 2 100K_0402_5% SIO_SLP_WLAN# BAT54CW-7-F_SOT323-3~D RN33
1U_0603_10V6K 1U_0603_10V6K 10U_0603_6.3V6M 10U_0603_6.3V6M 100K_0402_5%
2 2 2 2 RZ1142 1 @ 2 0_0402_5%

1
+3VALW
Touch Screen Load Switch & Card Reader +3VALW to +3V_PCH
0.01_0603_1% 2 @ 1 RH5866

+3VALW +3V_PCH
CZ18 UZ4
1U_0402_6.3V6K
+3VALW +3VS_TS +3VS_TS 2 1 1 8 +3V_PCH_BR RZ18 1 @ 2 0_0603_5%
CZ26 UZ5 2 VIN VOUT 7
1U_0402_6.3V6K VIN VOUT
2 1 1 8 RZ1133 1 2 0_0402_5% PCH_ALW_ON_R 3 6 +3V_PCH_CT CZ20 1 2 2200P_0402_25V7K
VIN VOUT 1 <18,20,32,48> SIO_SLP_SUS# EN CT
2 7
VIN VOUT CZ29 4 5
2 +5VALW 2
PCH_3.3V_TS_EN 3 6 1 2 VBIAS GND 9 +3V_PCH
<20> PCH_3.3V_TS_EN EN CT 0.1U_0402_10V7K GND
2
4 5 2200P_0402_25V7K
+5VALW VBIAS GND APE8937GN2_DFN8_2X2
9 CZ31@ 1
GND
RZ46 1 2 100K_0402_5% PCH_ALW_ON_R CZ19
APE8937GN2_DFN8_2X2
0.1U_0402_10V7K
RZ39 2 1 100K_0402_5% PCH_3.3V_TS_EN 2

HDD, SSD Load Switch

UZ33 +5VS_HDD
+3VS +3VS_CR
1 8
+5VALW VIN VOUT
RZ28 1 @ 2 0_0603_5% 2 7
VIN VOUT
RUN_ON_EC 3 6 CZ37 1 2 470P_0603_50V7K
EN CT
4 5
+5VALW VBIAS GND 9
GND

eDP & Camera Load Switch APE8937GN2_DFN8_2X2

+3VALW
RZ1956 1 @ 2 0_0402_5%
+3VALW +EDPVDD
1U_0201_10V6M

+EDPVDD
1 UZ32
+3VALW +3VALW +3.3VDX_SSD
CZ2157

1U_0201_10V6M

UZ8 1
CZ41

5 1 1 8
IN OUT VIN VOUT

5
2 UZ6 2 7
3
2 RUN_ON_EC 1 VIN VOUT 3

P
GND 2 INB 4 SSD_EN 3 6 CZ39 1 2 470P_0603_50V7K
ENVDD 4 3 SSD_SCP_PWR_EN 2 O EN CT
EN OC <48> SSD_SCP_PWR_EN INA

G
4 5
+3VALW VBIAS GND
MC74VHC1G32DFT2G_SC70-5~D 9

3
SY6288C20AAC_SOT23-5 GND

APE8937GN2_DFN8_2X2

DV7
BAT54CW-7-F_SOT323-3~D +5VS_HDD +3.3VDX_SSD
2
<48> LCD_VCC_TEST_EN
1 ENVDD RZ40 1 2 100K_0402_5% 1 1
SSD_SCP_PWR_EN RZ1958 1 2 100K_0402_5%
3 CZ45 CZ46
<16> ENVDD_PCH
0.1U_0402_10V7K 0.1U_0402_10V7K
2 2

+VCCST Load Switch +1VALW

+VCCST

+1.8VALW to +1.8V_PCH UZ15

1
2 VIN1
+1.8VALW +1.8V_PCH VIN2
+5VALW 7 6
VIN thermal VOUT
1
RH1957 1 @ 2 0.01_0603_1% 3
VBIAS CZ28
1
1U_0402_6.3V6K

0.1U_0402_25V6
1

4 5
CZ96

@ CZ97

2000mA +1.8V_PCH ON GND 2

0.1U_0402_10V7K

4 +1.8VALW UZ29 4
2

2 TPS22961DNYR_WSON8
1 8 4.4mohm/6A
2 VIN VOUT 7
VIN VOUT
1
TR=12.5us@Vin=1.05V
<18,20,32,48> SIO_SLP_SUS# RZ1952 1 2 0_0402_5% 3 6 CZ105 1 2 2200P_0402_25V7K CZ106 <33> SUS_ON_EC_ST
EN CT 0.1U_0402_10V6K
+5VALW 4 5
VBIAS GND 9 2
1 GND
CZ1501
0.1U_0402_10V7K APE8937GN2_DFN8_2X2
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P32-DC/DC SYSTEM

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 32 of 76
A B C D E
 5 4 3 2 1

+3V_PCH

5
UZ20 RZ1951 1 NDS@ 2 2.2K_0402_5% PCH_PRIM_EN
<20,48,59> ALWON PCH_PRIM_EN <20,60,70>

VCC
1
<32,48> RUN_ON_EC

4.7U_0603_6.3V6M
IN1 4 RUN_ON_EC_GATE RZ58 1 @ 2 0_0201_5%
OUT RUN_ON_P <61,73>

1
SIO_SLP_S3# 2

@ CZ2154
GND
<18,31,35,48,51> SIO_SLP_S3# IN2

2
RZ50

3
MC74VHC1G08DFT2G_SC70-5 100K_0201_5%

2
D D

RZ59 1 @ 2 0_0402_5%
0_0402_5% 2 1 RT5839 1.8V_PRIM_PWRGD_OK
<60,70> 1.8V_PRIM_PWRGD 1.8V_PRIM_PWRGD_OK <48>

<60> +1VALW_PG 0_0402_5% 2 1 RT5840

+3V_PCH +VCCSTG Load Switch +1VALW

5

UZ21 UZ9
1
VCC

1 2 VIN1
<48> IMVP_VR_ON IN1 VIN2 +VCCSTG
4 RZ60 1 @ 2 0_0402_1%
SIO_SLP_S3# 2 OUT +5VALW 7 6
GND

IN2 VIN thermal VOUT

3
VBIAS

1
+3V_PCH
1
3

1
1U_0402_6.3V6K

0.1U_0402_10V7K
@ CZ86
MC74VHC1G08DFT2G_SC70-5 4 5 CZ82
ON GND +VCCSTG

CZ88
0.1U_0402_10V7K

2
5
UZ12
@

2
2 TPS22961DNYR_WSON8

VCC
1
IN1 4
4.4mohm/6A 1
SIO_SLP_S0# RZ61 1 @ 2 0_0402_5% 2 OUT VR_ON <33,62> TR=12.5us@Vin=1.05V CZ47

GND
<18,41,51> SIO_SLP_S0# IN2
0.1U_0402_10V7K
1

1
VCCSTG_EN RZ1153 1 2 0_0402_5% VCCSTG_EN_R 2
RZ86 RZ71

3
100K_0402_5% @ MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
C @ C
2

2
+1.8V_PCH

5
UZ26
RUN_ON_P 1

G VCC
B 4 VCCSTG_EN
RZ1953 1 2 0_0201_1% 2 Y
<16,73> CPU_C10_GATE# A
RZ91 1 @ 2 0_0402_1% TC7SZ08FU_SSOP5 RZ1965 1 @ 2 0_0402_5%
VCCIO_EN

3
+3VALW

SUS_ON_EC_P <53,72>
@
5

UZ23
VCC

+3VALW 1
IN1 4
2 OUT SUS_ON_EC_ST <32>
GND

<48> PCH_ALW_ON IN2

5

UZ22

+VCCPLL_OC Load Switch

VCC

1 1
<48> SUS_ON_EC_R
3

IN1 4 MC74VHC1G08DFT2G_SC70-5 CZ588

2 OUT @ 0.1U_0402_10V6K
GND

<18,48,51> SIO_SLP_S4# IN2 +1.2V_DDR

B 2 B
UZ16
1 +1.2V_VCCPLL_OC
3

MC74VHC1G08DFT2G_SC70-5 2 VIN1
VIN2
DZ59 1 2 7 6
RB751S40T1G_SOD523-2 +5VALW VIN thermal VOUT
3
RZ1954 1 @ 2 0_0402_5% RZ1966 1 2 100K_0402_5% VBIAS +1.2V_VCCPLL_OC
1.2V_DDR_EN <61> VCCSTG_EN RZ72 1 2 0_0402_5% 4 5
ON GND
1

1
RZ87 1 TPS22961DNYR_WSON8
100K_0402_5% CZ2156 CZ49
0.1U_0402_10V6K 0.1U_0402_10V7K
2
2

<48> VCCST_PWRGD RZ1957 1 @ 2 0_0402_5%

+3V_PCH RZ1955 1 2 0_0402_5%

<33,62> VR_ON
+3VALW

RZ82 1 @ 2 0_0402_5%
1

RZ84 +3V_PCH
100K_0402_5%
2

1
5

@ UZ19 UE7
A A
VCC

1
Vcc

<61> +1.2V_DDR_PG IN1 H_VCCST_PWRGD_GATE H_VCCST_PWRGD

NC

4 2 4
SIO_SLP_S4# OUT A Y H_VCCST_PWRGD <6,9>
RZ81 1 2 0_0402_5% 2
GND

IN2
G

MC74VHC1G08DFT2G_SC70-5 74AUP1G07SE-7_SOT353-5
3
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P33-DC/DC/S0iX/CS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 33 of 76
5 4 3 2 1
 5 4 3 2 1

LCD backlight PWR CTRL eDP & CCD(RGB) Conn.

DV1 +EDPVDD
2
<48> PANEL_BKEN_EC
1 DISPOFF#
+INV_PWR_SRC

10U_0603_6.3V6M
B+

1
3
60mil <16> PANEL_BKEN_PCH
RV107 1 1

CV157
BAT54CW-7-F_SOT323-3~D 10K_0402_5%
CV156
QV11 8.2P_0402_50V8D @

2
SI3457BDV-T1-E3_TSOP6~D 2 2
DV2

D
6 2
60mil

S
<7,16> BIA_PWM_PCH
4 5
2 1 INV_PWM
1

1
3

G
1 <48> BIA_PWM_EC_R
RV119 1

3
D D
CV168 270K_0402_5% BAT54CW-7-F_SOT323-3~D RV109
1000P_0402_50V7K CV169 4.7K_0402_5%
2 0.1U_0402_25V6

2
2

1
RV120
47K_0402_5%
RV135 2 1 220K_0402_5% EN_INVPWR RV520 1 @ 2 0_0201_5% EDP_TXP0_R

2
EDP_TXP0_C

1
D
<7> EDP_TXP0 CV158 1 2 0.1U_0201_10V6K JEDP1
EN_INVPWR 2 QV12
<48> EN_INVPWR
G L2N7002WT1G_SC-70-3 +INV_PWR_SRC 40 41
EDP_TXN0_C CONNTST MGND1
S <7> EDP_TXN0 CV159 1 2 0.1U_0201_10V6K
W=60mils 39 42

3
38 LCD_VDD MGND2 43
37 LCD_VDD MGND3 44
RV521 1 @ 2 0_0201_5% EDP_TXN0_R RV110 1 @ 2 0_0402_1% 36 V_EDID MGND4 45
<48> LCD_TST BIST MGND5
35 46
34 EDID_CLK MGND6
RV522 1 @ 2 0_0201_5% EDP_TXP1_R 33 EDID_DATA
USB20_P12_R 32 LVDS_A0-
USB20_N12_R 31 LVDS_A0+
CV160 1 2 0.1U_0201_10V6K EDP_TXP1_C 30 LVDS_A1-
<7> EDP_TXP1 LVDS_A1+
<16> CAM_CBL_DET# 29
28 LVDS_A2-
CV161 1 2 0.1U_0201_10V6K EDP_TXN1_C RV1843 1 2 0_0201_5% LCD_DBC_R 27 LVDS_A2+
<7> EDP_TXN1 <19> LCD_DBC @
+3VS_TS @ PAD~D T5995 EDP_PANEL_DAT 26 GND

Touch Screen Conn. RV523 1 @ 2 0_0201_5% EDP_TXN1_R

INV_PWM
DISPOFF#
EDP_HPD_S
25
24
LVDS_A_CLK-
LVDS_A_CLK+
GND
+3VS_TS +3VS_CAM 23
22 LVDS_B0-
2 0_0201_5% EDP_TXP2_R LVDS_B0+
1

RV524 1 @ +EDPVDD 21
LVDS_B1-
AZ5B25-01F_DFN0603P2Y2

D18 W=60mils 20
LVDS_B1+
10U_0402_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

19
CV162 1 2 0.1U_0201_10V6K EDP_TXP2_C @ PAD~D T5994 EDP_PANEL_CLK 18 LVDS_B2-
EMC@

1 1 1 <7> EDP_TXP2 LVDS_B2+

C3005

C3004

C3003

17
EDP_AUXP_R 16 GND
CV163 1 2 0.1U_0201_10V6K EDP_TXN2_C EDP_AUXN_R 15 LCD_B_CLK-
2 2 2 <7> EDP_TXN2 LCD_B_CLK+
14
2

EDP_TXP0_R 13 VR_GND
RV525 1 @ 2 0_0201_5% EDP_TXN2_R EDP_TXN0_R 12 VR_GND
11 VR_GND
EDP_TXP1_R 10 CONNTST_GND
EDP_TXN1_R 9 PWM
RV526 1 @ 2 0_0201_5% EDP_TXP3_R 8 DISP_ON/OFF#
EDP_TXP2_R 7 NC
CONN@ EDP_TXN2_R VR_SRC
C 6 C
ACES_50208-00601-P01 CV164 1 2 0.1U_0201_10V6K EDP_TXP3_C 5 VR_SRC
<7> EDP_TXP3 EDP_TXP3_R VR_SRC
LI1 8 4
1 2 USB20_P9_R 7 GND EDP_TXN3_R 3 BREATH_WHITE_LED
<19> USB20_P9 GND EDP_TXN3_C BATT_YELLOW_LED
6 CV165 1 2 0.1U_0201_10V6K 2
USB20_P9_R 6 <7> EDP_TXN3 BATT_WHITE_LED
5 1
4 3 USB20_N9_R +3VS_TS USB20_N9_R 4 5 GND
<19> USB20_N9
3 4 RV527 1 @ 2 0_0201_5% EDP_TXN3_R
MCM1012B900F06BP_4P 1 2 2 3 ACES_59003-04006-001
<17,34> TOUCH_SCREEN_PD# 2
EMC@ DI1 RB751S40T1G_SOD523-2 1 CONN@
@ 1
2

JTS
DI3
AZ5125-02S.R7G_SOT23-3

RV528 1 @ 2 0_0201_5% EDP_AUXN_R

CV166 1 2 0.1U_0201_10V6K EDP_AUXN_C

<7> EDP_AUXN

CV167 1 2 0.1U_0201_10V6K EDP_AUXP_C

<7> EDP_AUXP
1

RV529 1 @ 2 0_0201_5% EDP_AUXP_R

EMC@
MCM1012B900F06BP_4P
USB20_P12 4 3 USB20_P12_R
<19> USB20_P12 EDP_HPD_S
RV113 1 @ 2 0_0201_5%
<16> EDP_HPD
USB20_N12 USB20_N12_R

1
1 2
<19> USB20_N12
LV22 RV114
100K_0402_5%

2
EMC@
DV12
USB20_P12_R 1 4
D1+ D2+
2 5
GND VCC +3VS
USB20_N12_R 3 6
D2- D1- +3VS +3VS_CAM
IP4220CZ6_SC-74-6
B +3VS_CAM_R B

D
3 1 RZ37 1 @ 2 0_0603_5%

1
+3VS_TS QZ9 DMG2301U-7_SOT23-3

G
2
CZ43
RC183 1 2 499_0402_1% I2C0_SDA_TS
I2C0_SCK_TS 0.1U_0402_10V7K
RC184 1 2 499_0402_1% 2

3.3V_CAM_EN#
3.3V_CAM_EN# <19>
RC5835 1 2 100K_0402_5% TS_DETECT#

+3VALW
+3VS_TS

3.3V_CAM_EN# RZ38 1 2 100K_0402_5%

JTS1
1
I2C0_SDA_TS RR42 1 2 0_0201_5% I2C0_SDA_TS_R 2 1
<20> I2C0_SDA_TS I2C0_SCK_TS I2C0_SCK_TS_R 2
<20> I2C0_SCK_TS RR45 1 2 0_0201_5% 3
I2C2_IRQ_TS RR41 1 2 0_0201_5% I2C0_IRQ_TS_R 4 3 +3VS_CAM +3VS_CAM
<18> I2C2_IRQ_TS PCH_PLTRST#_EC 4
<17,23,31,35,41,42,43,48,49,50> PCH_PLTRST#_EC RR43 1 @ 2 0_0201_5% 5
TOUCH_SCREEN_PD# 6 5
<17,34> TOUCH_SCREEN_PD# TS_DETECT# 6
<18> TS_I2C_RST# RR44 1 2 0_0201_5%
<16> TS_DETECT#
7 1
8 7
8 1 1
CZ44
1

9 CV183 CV184 1U_0402_6.3V6K

GND 2
AZ5B25-01F_DFN0603P2Y2

D74 10 .1U_0402_16V7K 8.2P_0402_50V8D

GND 2 2
ACES_50208-00801-003
EMC@

CONN@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 2027/06/21 Title
Deciphered Date

WWW.AliSaler.Com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P34-eDP/CCD/TS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 34 of 76
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
+3VA_TBT_LC

PCH_PLTRST#_EC_AR 100K_0201_5% 2 @ 1 RT5857

1
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
RT6

RT7

RT8

RT9
UT1A
CT176 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_TRX_P17 Y23 V23 PCIE_PRX_C_TTX_P17 CT179 2 1 0.22U_0201_6.3V6M
<16> PCIE_PTX_TRX_P17 PCIE_PTX_C_TRX_N17 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_TTX_P17 <16>
CT177 2 1 0.22U_0201_6.3V6M Y22 V22 PCIE_PRX_C_TTX_N17 CT181 2 1 0.22U_0201_6.3V6M
<16> PCIE_PTX_TRX_N17 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_TTX_N17 <16>
2

2
CT175 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_TRX_P18 T23 P23 PCIE_PRX_C_TTX_P18 CT178 2 1 0.22U_0201_6.3V6M

PCIe GEN3
TBT_JTAG_TDI <16> PCIE_PTX_TRX_P18 PCIE_PTX_C_TRX_N18 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_TTX_P18 <16>
T196 @ PAD~D CT174 2 1 0.22U_0201_6.3V6M T22 P22 PCIE_PRX_C_TTX_N18 CT180 2 1 0.22U_0201_6.3V6M
TBT_JTAG_TMS <16> PCIE_PTX_TRX_N18 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_TTX_N18 <16>
T197 @ PAD~D
TBT_JTAG_TCK T198 @ PAD~D CT6 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_TRX_P19 M23 K23 PCIE_PRX_C_TTX_P19 CT5 2 1 0.22U_0201_6.3V6M
TBT_JTAG_TDO <16> PCIE_PTX_TRX_P19 PCIE_PTX_C_TRX_N19 PCIE_RX2_P PCIE_TX2_P PCIE_PRX_TTX_P19 <16>
T199 @ PAD~D CT8 2 1 0.22U_0201_6.3V6M M22 K22 PCIE_PRX_C_TTX_N19 CT7 2 1 0.22U_0201_6.3V6M
<16> PCIE_PTX_TRX_N19 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_TTX_N19 <16>
CT2 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_TRX_P20 H23 F23 PCIE_PRX_C_TTX_P20 CT1 2 1 0.22U_0201_6.3V6M
<16> PCIE_PTX_TRX_P20 PCIE_PTX_C_TRX_N20 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_TTX_P20 <16>
<16> PCIE_PTX_TRX_N20 CT4 2 1 0.22U_0201_6.3V6M H22 F22 PCIE_PRX_C_TTX_N20 CT3 2 1 0.22U_0201_6.3V6M PCIE_PRX_TTX_N20 <16>
D PCIE_RX3_N PCIE_TX3_N D
V19 L4 PCH_TBT_PERST# 0_0201_5% 2 1 RT435
+3V_TBT <17> CLK_PCIE_P5 PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_EC <17,23,31,34,41,42,43,48,49,50>
<17> CLK_PCIE_N5 T19
RT5845 1 @ 2 0_0201_5% CLKREQ_PCIE#5_AR AC5 PCIE_REFCLK_100_IN_N N16 TBT_PCIE_RBIAS 1 2 0_0201_5% 2 @ 1 RT5855 PCH_PLTRST#_EC_AR
<17> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS PCH_PLTRST#_EC_AR <20>
RT1 3.01K_0402_1%
RT202 1 @ 2 10K_0201_5% TBT_POC_RST# CT17 2 1 0.1U_0201_6.3V6K CPU_DP1_P0_C AB7 R2
<7> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P
<7> CPU_DP1_N0 CT18 2 1 0.1U_0201_6.3V6K AC7 R1
RT21 1 @ 2 10K_0201_5% CLKREQ_PCIE#5 DPSNK0_ML0_N DPSRC_ML0_N
CT19 2 1 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2
<7> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P
CT20 2 1 0.1U_0201_6.3V6K AC9 N1

SOURCE PORT 0
TBT_DDC_CLK <7> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N
RT33 1 2 100K_0201_5%

SINK PORT 0
RT34 1 2 100K_0201_5% TBT_DDC_DATA CT21 2 1 0.1U_0201_6.3V6K CPU_DP1_P2_C AB11 L2
<7> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P
<7> CPU_DP1_N2 CT22 2 1 0.1U_0201_6.3V6K AC11 L1
DPSNK0_ML2_N DPSRC_ML2_N
CT23 2 1 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2
TBT_SRC_CFG1 <7> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P
RT107 1 2 1M_0201_1%
<7> CPU_DP1_N3 CT24 2 1 0.1U_0201_6.3V6K AC13 J1
DPSNK0_ML3_N DPSRC_ML3_N
CT25 2 1 0.1U_0201_6.3V6K CPU_DP1_AUXP_C Y11 W19
<7> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
<7> CPU_DP1_AUXN CT26 2 1 0.1U_0201_6.3V6K W11 Y19
DPSNK0_AUX_N DPSRC_AUX_N
PCH_DP1_HPD AA2 G1 TB_HDMI_HPLUG RT1134 1 2 1M_0402_5%
<16> PCH_DP1_HPD DPSNK0_HPD DPSRC_HPD
DDI1_DDPB_CTRLCLK Y5 N6 DPSRC_RBIAS RT2 1 2 14K_0402_1%
<16> DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLDAT DPSNK0_DDC_CLK DPSRC_RBIAS
R4
<16> DDI1_DDPB_CTRLDAT DPSNK0_DDC_DATA TBT_I2C_DATA
U1 TBT_I2C_DATA <37>
CT29 2 1 0.1U_0201_6.3V6K CPU_DP2_P0_C AB15 GPIO_0 U2 TBT_I2C_CLK
<7> CPU_DP2_P0 CPU_DP2_N0_C DPSNK1_ML0_P GPIO_1 TBT_ROM_WP# TBT_I2C_CLK <37>
CT30 2 1 0.1U_0201_6.3V6K AC15 V1 0_0201_5% 2 1 RT5849

LC GPIO
+3VA_TBT <7> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT PCIE_WAKE# <42,43,48>
V2 0_0201_5% 2 @ 1 RT5843 PCH_PCIE_WAKE# <18,48>
CT31 2 1 0.1U_0201_6.3V6K CPU_DP2_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE# 0_0201_5% 2 @ 1 RT5856
<7> CPU_DP2_P1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# SRCCLKREQ1# <17>
<7> CPU_DP2_N1 CT32 2 1 0.1U_0201_6.3V6K AC17 W2 TBT_CIO_PLUG_EVENT# <16>
DPSNK1_ML1_N GPIO_5 Y1 TBT_DDC_DATA
CT33 2 1 0.1U_0201_6.3V6K CPU_DP2_P2_C AB19 GPIO_6 Y2 TBT_DDC_CLK

SINK PORT 1
TBT_DDC_CLK <7> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1
RT5848 1 @ 2 2.2K_0201_5% <7> CPU_DP2_N2 CT34 2 1 0.1U_0201_6.3V6K AC19 AA1
RT5847 1 @ 2 2.2K_0201_5% TBT_DDC_DATA DPSNK1_ML2_N GPIO_8 J4 TBTA_I2C_INT#
CPU_DP2_P3_C POC_GPIO_0 TBTB_I2C_INT# TBTA_I2C_INT# <37>
CT35 2 1 0.1U_0201_6.3V6K AB21 E2

POC GPIO
TBT_I2C_DATA <7> CPU_DP2_P3 CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN TBTB_I2C_INT# <37>
RT35 1 2 2.2K_0201_5% CT36 2 1 0.1U_0201_6.3V6K AC21 D4 RT5841 2 @ 1 0_0201_5% PCH_RTD3_USB_PWR_EN
TBT_I2C_CLK <7> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR_R PCH_RTD3_USB_PWR_EN <17>
RT36 1 2 2.2K_0201_5% H4 RT5846 2 @ 1 0_0201_5%
TBT_PCIE_WAKE# CPU_DP2_AUXP_C POC_GPIO_3 TBT_BATLOW# TBT_FORCE_PWR <20>
C RT22 1 @ 2 10K_0201_5% <7> CPU_DP2_AUXP CT108 2 1 0.1U_0201_6.3V6K Y12 F2 C
RT23 1 2 10K_0201_5% TBT_CIO_PLUG_EVENT# CT107 2 1 0.1U_0201_6.3V6K CPU_DP2_AUXN_C W12 DPSNK1_AUX_P POC_GPIO_4 D2 SIO_SLP_S3#_AR RT433 2 @ 1 0_0201_5%
TBT_BATLOW# <7> CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_AR SIO_SLP_S3# <18,31,33,48,51>
RT25 1 2 10K_0201_5% F1 RT5842 1 2 0_0201_5% RTD3_CIO_PWR_EN <20>
PCH_DP2_HPD Y6 POC_GPIO_6
<16> PCH_DP2_HPD DPSNK1_HPD TBT_TEST_EN
E1 100_0201_1% 2 1 RT3
RT39 1 @ 2 10K_0201_5% RTD3_CIO_PWR_EN DDI2_DDPC_CTRLCLK Y8 TEST_EN

Misc
<16> DDI2_DDPC_CTRLCLK DDI2_DDPC_CTRLDAT DPSNK1_DDC_CLK TBT_TEST_PWRG 100_0201_1% 2
N4 AB5 1 RT4
<16> DDI2_DDPC_CTRLDAT DPSNK1_DDC_DATA TEST_PWR_GOOD
2 1 Y18 F4 TBT_POC_RST# RB751S40T1G_SOD523-2 2 @ 1 DT29
DPSNK_RBIAS RESET_N TBTA_RESET_N <37>
RT5 14K_0402_1% RT244 2 @ 1 0_0201_5% TBT_RESET_N_EC <37,48>
TBT_JTAG_TDI Y4 D22 XTAL_25_IN_R RA98 1 2 33_0201_5% XTAL_25_IN
RT37 1 2 100K_0201_5% TBT_TMU_CLK_OUT TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT_R RA99 1 2 33_0201_5% XTAL_25_OUT
RT38 1 2 100K_0201_5% TBT_FORCE_PWR TBT_JTAG_TCK T4 TMS XTAL_25_OUT
TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI
RTD3_USB_PWR_EN TDO MISC EE_DI TBT_ROM_DO
RT40 1 2 10K_0201_5% AC4
RT41 1 2 100K_0201_5% PCH_DP1_HPD TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS#
RT42 1 2 100K_0201_5% PCH_DP2_HPD 1 2 TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK
TBTA_HPD RSENSE EE_CLK 1 1
RT43 1 2 100K_0201_5% RT10 4.75K_0402_0.5%
RT44 1 2 1M_0201_1% TBT_LSTX RT5832 1 @ 2 0_0201_5% TBT_USB3_RX1_P_R A15 B7 CT44 CT43
TBT_LSRX <38> TBT_USB3_RX1_P TBT_USB3_RX1_N_R PA_RX1_P PB_RX1_P
RT45 1 2 1M_0201_1% RT5833 1 @ 2 0_0201_5% B15 A7 27P_0201_25V8 27P_0201_25V8
TBTB_LSTX <38> TBT_USB3_RX1_N PA_RX1_N PB_RX1_N 2 2
RT207 1 2 1M_0201_1%
RT208 1 2 1M_0201_1% TBTB_LSRX CT37 2 1 0.22U_0201_6.3V6M TBT_USB3_TX1_P_C A17 A9
TBTB_HPD <38> TBT_USB3_TX1_P TBT_USB3_TX1_N_C PA_TX1_P PB_TX1_P
RT209 1 2 100K_0201_5% <38> TBT_USB3_TX1_N CT38 2 1 0.22U_0201_6.3V6M B17 B9
PA_TX1_N PB_TX1_N
RT58501 2 100K_0201_5% RTD3_CIO_PWR_EN CT39 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_P_C A19 A11
<38> TBT_USB3_TX0_P TBT_USB3_TX0_N_C PA_TX0_P PB_TX0_P
<38> TBT_USB3_TX0_N CT40 2 1 0.22U_0201_6.3V6M B19 B11
PA_TX0_N PB_TX0_N

TBT PORTS
RT5834 1 @ 2 0_0201_5% TBT_USB3_RX0_P_R B21 A13
<38> TBT_USB3_RX0_P TBT_USB3_RX0_N_R PA_RX0_P PB_RX0_P
RT5835 1 @ 2 0_0201_5% A21 B13

Port A

PORT B
<38> TBT_USB3_RX0_N PA_RX0_N PB_RX0_N
CT41 2 1 0.1U_0201_6.3V6K TBTA_AUX_P_C Y15 Y16 YT1
<37> TBTA_AUX_P TBTA_AUX_N_C PA_DPSRC_AUX_P PB_DPSRC_AUX_P
<37> TBTA_AUX_N CT42 2 1 0.1U_0201_6.3V6K W15 W16
+3V_TBT_SPI PA_DPSRC_AUX_N PB_DPSRC_AUX_N XTAL_25_IN 1 3 XTAL_25_OUT
+3VA_TBT_LC E20 E19 1 3
<37> TBT_USB2_D+ PA_USB2_D_P PB_USB2_D_P NC NC
D20 D19
@ <37> TBT_USB2_D- PA_USB2_D_N PB_USB2_D_N
RT242 1 2 0_0402_5% 25MHZ_20PF_XRCGB25M000F2P18R0
TBT_LSTX A5 B4 TBTB_LSTX 2 4
<37> TBT_LSTX TBT_LSRX PA_LS_G1 PB_LS_G1 TBTB_LSRX

POC
VCC3V3_FLASH

POC
<37> TBT_LSRX A4 B5
B TBTA_HPD M4 PA_LS_G2 PB_LS_G2 G2 TBTB_HPD B
<37> TBTA_HPD PA_LS_G3 PB_LS_G3
RT243 1 @ 2 0_0402_1%
RT12 2 1 499_0201_1% H19 F19 RT164 2 1 499_0201_1%
PA_USB2_RBIAS PB_USB2_RBIAS
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC

ALPINE-RIDGE_BGA337

+3V_TBT_SPI +3V_TBT_SPI
0.1U_0201_6.3V6K
1

1
RT15 RT18 RT16 RT17
CT47

2.2K_0201_5%

2.2K_0201_5%
3.3K_0201_1%

3.3K_0201_1%

2
2

A A
UT2
8 1 TBT_ROM_CS#
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP#
TBT_ROM_DI 5 CLK WP#(IO2) 4
9 DI(IO0) GND
thermal pad
W25Q80DVZPIG_WSON8

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P35-AR_TBT (1/2) DP / PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 35 of 76
5 4 3 2 1
 5 4 3 2 1

+VCC0V9_DP +3VA_TBT

+3V_TBT +3VA_TBT +3V_TBT

+3VA_TBT_LC
+3V_TBT_S0
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 RT46 2 @ 1 0_0603_5%

1U_0201_6.3V6M

1U_0201_6.3V6M
CT62

CT63

CT64

CT65

CT66

CT67

CT68

1U_0201_6.3V6M
1 1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
2 2 2 2 2 2 2 1 1 1 1 1

CT50
+3VALW

CT143

CT53

CT54

CT55

CT56
CT52
2 2
RT113 1 @ 2 0_0603_5% 2 2 2 2 2
+VCC0V9_DP

R13
R6

H9
UT1B

F8
D D
L8 A2

VCC3P3_S0
VCC3P3_LC

VCC3P3_SX

VCC3P3A
+VCC0V9_PCIE +VCC0V9_USB L11 VCC0P9_DP VCC3P3_SVR A3
L12 VCC0P9_DP VCC3P3_SVR B3
M8 VCC0P9_DP VCC3P3_SVR
T11 VCC0P9_DP
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
+3VS +3V_TBT T12 VCC0P9_DP L9 VCC0V9_SVR
1 1 1 1 1 1 1 VCC0P9_DP VCC0P9_SVR
L6 M9

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
VCC0P9_ANA_DPSRC VCC0P9_SVR
CT80

CT71

CT72

CT81

CT82

CT93

CT94
M6 E12 1 1 1 1 1 1 1
V11 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA E13
2 2 2 2 2 2 2 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA

CT83

CT84

CT74

CT85

CT86
CT142

CT141
0_0603_5% 2 @ 1 RT241 V12 F11
+VCC0V9_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE 0.6uH, 5A, 20m ohm by TB CRB
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND LT1 1 2 0.68UH_MLV-YT10NR68N-M1L_2.7A_30%
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2
+VCC0V9_CIO M18 VCC0P9_ANA_PCIE_2 SVR_IND D1 1 1 1

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
N18 VCC0P9_ANA_PCIE_2 SVR_IND

VCC
+VCC0V9_USB VCC0P9_ANA_PCIE_2

CT88

CT89

CT90
R15 A1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

R16 VCC0P9_USB SVR_VSS B1 2 2 2

1 1 1 VCC0P9_USB SVR_VSS B2
+VCC0V9_CIO SVR_VSS
CT101

CT102

CT103

R8
R9 VCC0P9_CIO
2 2 2 R11 VCC0P9_CIO
R12 VCC0P9_CIO F18 VCC0V9_LVR_OUT
VCC0P9_CIO VCC0P9_LVR H18

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
VCC_3V3_PCIE L16 VCC0P9_LVR J11
VCC_3V3_USB2 VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
+3V_TBT J16 H11

CT95

CT96

CT97

CT98
1U_0201_6.3V6M

1U_0201_6.3V6M
+3V_TBT_S0 VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
LT14 1 1
A6 V5
VSS_ANA VSS_ANA 2 2 2 2

CT99

CT100
1 2 A8 V6
A10 VSS_ANA VSS_ANA V8
LQM18PN1R0MFHD_2P 2 2 A12 VSS_ANA VSS_ANA V9
A14 VSS_ANA VSS_ANA V15
1U_0201_6.3V6M

C C
47U_0603_6.3V6M

47U_0603_6.3V6M

A16 VSS_ANA VSS_ANA V16

1 1 1 VSS_ANA VSS_ANA
A18 V20
CT164

CT165

VSS_ANA VSS_ANA
CT163

A20 W5
A22 VSS_ANA VSS_ANA W6
2 2 2 B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16

GND
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8 close to UT1 close to UT1
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12 VCC0V9_SVR TBT_SVR_IND
E23 VSS_ANA VSS_ANA AC14
VSS_ANA VSS_ANA

39P_0201_50V8J
EMC@ CT182

100P_0201_50V8J
EMC@ CT183

39P_0201_50V8J
EMC@ CT186

100P_0201_50V8J
EMC@ CT187
F9 AC16
F16 VSS_ANA VSS_ANA AC18
VSS_ANA VSS_ANA 1 1 1 1
F20 AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4 2 2 2 2
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
B
H15 VSS_ANA VSS F6 B
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15 close to UT1
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11 VCC0V9_LVR_OUT
K1 VSS_ANA VSS M12
VSS_ANA VSS

39P_0201_50V8J
EMC@ CT184

100P_0201_50V8J
EMC@ CT185
K2 N8
L5 VSS_ANA VSS N9
VSS_ANA VSS 1 1
L20 N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6 2 2
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18
N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
ALPINE-RIDGE_BGA337
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P36-AR_TBT (2/2) PWR / VSS

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 36 of 76
5 4 3 2 1
 5 4 3 2 1

+5VALW TBTA_LDO_BMC VCC3V3_TBT_SX VCC3V3_FLASH VCC1V8A_TBTA_LDO VCC1V8D_TBTA_LDO

1 1 1 1 1

1 1 1 1 CT144 CT145 CT146 CT151 CT152

CT147 CT148 CT149 CT150 2.2U_0402_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 2 2 2 2

2 2 2 2

D D

+5VALW +3VALW
+VBUS_1

1 1

1
CT188 CT189
4.7U_0603_25V6K 10U_0402_6.3V6M CT153
2 2 1U_0603_25V6

2
+3VA_TBT

RT167 1 2 10K_0201_5% TBTA_I2C_INT# UT4

RT1145 1 2 10K_0201_5% TBTB_I2C_INT#
TBTB_I2C_INT# <35>
A6 B10
VCC3V3_FLASH PP_HV PP_HV SENSEP
A7 A10
A8 PP_HV SENSEN
RT1092 1 2 0_0603_5% B7 PP_HV
RT168 1 2 3.3K_0201_1% PD_EE_CS# PP_HV B9 T191 PAD~D @
RT169 1 2 3.3K_0201_1% PD_EE_DO A11 HV_GATE1 A9 T192 PAD~D @ +VBUS_1
PD_EE_WP# +5VALW PP_5V0 HV_GATE2
RT170 1 2 3.3K_0201_1% C11
RT171 1 2 3.3K_0201_1% PD_HOLD# B11 PP_5V0
RT432 1 2 100K_0201_5% TBTA_AUX_N D11 PP_5V0 H11
RT431 1 2 100K_0201_5% TBTA_AUX_P PD_VDDIO_VIN_3V3 PP_5V0 VBUS J10
VBUS

3
EMI@ DT174
+3VALW RT1095 1 2 0_0402_5% H10 J11
PP_CABLE VBUS

1
BAT54LPS-7
K11
B1 VBUS CT157 DT10
VDDIO 1U_0603_25V6 AZ4024-02S_SOT23-3~D

2
H1 H2 VCC3V3_TBT_SX EMC@
VIN_3V3 VOUT_3V3 G1
VCC3V3_FLASH

1
LDO_3V3 K1
LDO_1V8A VCC1V8A_TBTA_LDO
RT5836 1 2 0_0201_5% TBT_I2C_DATA_R D1 A2
<35> TBT_I2C_DATA I2C_SDA1 LDO_1V8D VCC1V8D_TBTA_LDO
RT5837 1 2 0_0201_5% TBT_I2C_CLK_R D2 E1
<35> TBT_I2C_CLK I2C_SCL1 LDO_BMC TBTA_LDO_BMC
RT5838 1 2 0_0201_5% TBTA_I2C_INT#_R C1
C <35> TBTA_I2C_INT# I2C_IRQ1_N close to +VBUS_1 C

UPD_SMBDAT_R A5
UPD_SMBCLK_R B5 I2C_SDA2 CT160 1 2 220P_0402_50V7K
B6 I2C_SCL2 L9
<48> UPD1_ALERT# I2C_IRQ2_N C_CC1 TBTA_CC1 <38>
L10 TBTA_CC2 <38>
C_CC2 CT159 1 2 220P_0402_50V7K
PD_EE_CLK A3 K9
PD_EE_DI B4 SPI_CLK RPD_G1 K10
RT1144 1 2 0_0201_5% PD_EE_DO A4 SPI_MOSI RPD_G2
<19> USB20_P5 PD_EE_CS# SPI_MISO
<19> USB20_N5 RT1143 1 2 0_0201_5% B3
SPI_SS_N K6 0615 CHANGE NET NAME
C_USB_TP TBTA_TOP_P <38>
L6 TBTA_TOP_N <38>
RT1141 1 @ 2 0_0201_5% USB20_P5_R L5 C_USB_TN
<35> TBT_USB2_D+ USB20_N5_R USB_RP_P
<35> TBT_USB2_D- RT1142 1 @ 2 0_0201_5% K5
USB_RP_N K7
C_USB_BP TBTA_BOT_P <38>
L7
C_USB_BN TBTA_BOT_N <38>
<35> TBTA_AUX_P J1
J2 AUX_P
<35> TBTA_AUX_N AUX_N TBTA_PD_SBU1
K8 RT176 1 @ 2 0_0201_5%
C_SBU1 TBTA_PD_SBU2 TBTA_SBU1 <38>
L8 RT177 1 @ 2 0_0201_5% TBTA_SBU2 <38>
@ PAD~D T193 G4 C_SBU2
@ PAD~D T194 F4 SWD_CLK
SWD_DATA B2 T185 PAD~D @
GPIO0 C2 RT178 1 @ 2 0_0201_5%
GPIO1 EN_PD_HV_1 <57>
RT430 1 2 100K_0201_5% E2 D10 PD_GPIO2 RT437 1 2 1M_0201_1% +3VA_TBT
F2 UART_TX GPIO2 G11 RT5844 1 @ 2 0_0201_5%
UART_RX GPIO3 AC1_DISC# <57,58>
C10 RT181 1 @ 2 0_0201_5% TBTA_HPD <35>
TBT_LSTX L4 GPIO4 E10
<35> TBT_LSTX TBT_LSRX LSTX/R2P GPIO5
K4 G10
<35> TBT_LSRX LSRX/P2R GPIO6 D7 PD_PGPIO7 RT182 1 @ 2 0_0201_5% PWR_BTN_DOCK1#
RT226 1 2 10K_0201_5% PD_DEBUG_CTRL1 E4 GPIO7 H6 TBT_CONFIG
VCC3V3_FLASH PD_DEBUG_CTRL2 DEBUG_CTL1 GPIO8
RT227 1 2 10K_0201_5% D5
DEBUG_CTL2
RT184 1 @ 2 0_0201_5% TBTA_DEBUG1 L2 RT245 1 @ 2 0_0201_5%
<48> DOCK_TNY_SMB_CLK DEBUG1 TBT_RESET_N_EC <35,48>

1
<48> DOCK_TNY_SMB_DAT RT185 1 @ 2 0_0201_5% TBTA_DEBUG2 K2 E11 PD_PMRESET RT186 1 2 100K_0201_5%
DEBUG2 MRESET RT194
TBT_LSTX RT233 1 @ 20_0201_5% TBTA_DEBUG3_LSTX L3 F11 100K_0201_5%
B TBT_LSRX TBTA_DEBUG4_LSRX DEBUG3 RESET_N TBTA_RESET_N <35> B
RT232 1 @ 20_0201_5% K3
DEBUG4

2
G
F10 RT189 1 @ 2 0_0201_5%
VCC3V3_FLASH

2
F1 BUSPOWER_N
I2C_ADDR G2 PWR_BTN_DOCK1# 3 1 RT195 1 @ 2 0_0201_5%
R_OSC PWR_TB_DOCK# <48>
2

2
100K_0201_5%

100K_0201_5%

D
PD_SS
RT187

RT188

H7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

SS
1

QV89

1
@ 1 RT199 1 2 0_0201_5%
RT190 SN1703018ZQZR_BGA96 RT191 L2N7002WT1G_SC-70-3
1

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H8
L1
L11

0_0402_1%

15K_0402_0.1%
2

CT158 2

2
0.22U_0402_10V6K

TBTA_HRESET
1

the PD RST will keep low,

RT429
it will let PD work abnormal.[Ex. Type-c adapter plug in] 100K_0201_5%
TBTA_HRESET might be connected to
EC or PCH to allow TPS65982 FW load
2

VCC3V3_FLASH

1
RT1093
10K_0201_1%

2
TBT_CONFIG

1
VCC3V3_FLASH
RT183
100K_0201_1%
A MAIN : SA00003K820 A
2nd : SA00007P810 UT5

2
8 1 PD_EE_CS#
PD_HOLD# 7 VCC /CS 2 PD_EE_DO
PD_EE_CLK 6 /HOLD/IO3 DO/IO1 3 PD_EE_WP#
PD_EE_DI 5 CLK /WP/IO2 4
DI/IO0 GND
W25Q80DVZPIG_WSON8

Security Classification Compal Secret Data Compal Electronics, Inc.

UPD_SMBDAT_R Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
RT200 1 @ 2 0_0201_5%
<48> UPD_SMBDAT
UPD_SMBCLK_R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P37-PD CONTROLLER
<48> UPD_SMBCLK RT201 1 @ 2 0_0201_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 37 of 76
5 4 3 2 1
 5 4 3 2 1

D D
TBT_USB3_TX0_P 1 2 TBT_USB3_RX0_P 1 2
DT12 AZ5B75-01B.R7G_CSP0603P2Y2 DT20 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@
TBT_USB3_TX0_N 1 2 TBT_USB3_RX0_N 1 2
DT13 AZ5B75-01B.R7G_CSP0603P2Y2 DT21 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@
TBTA_CC1 1 2 TBTA_SBU2 1 2
DT14 AZ5B75-01B.R7G_CSP0603P2Y2 DT22 AZ5B75-01B.R7G_CSP0603P2Y2
CMMI21T-900Y-N_4P EMC@ EMC@
4 3 TBTA_BOT_C_N
<37> TBTA_BOT_N 4 3 TBTA_TOP_C_P TBTA_BOT_C_N
1 2 1 2
DT15 AZ5B75-01B.R7G_CSP0603P2Y2 DT23 AZ5B75-01B.R7G_CSP0603P2Y2
1 2 TBTA_BOT_C_P EMC@ EMC@
<37> TBTA_BOT_P 1 2
LT13 TBTA_TOP_C_N 1 2 TBTA_BOT_C_P 1 2
EMC@ DT16 AZ5B75-01B.R7G_CSP0603P2Y2 DT24 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@
TBTA_SBU1 1 2 TBTA_CC2 1 2
DT17 AZ5B75-01B.R7G_CSP0603P2Y2 DT25 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@
CMMI21T-900Y-N_4P
4 3 TBTA_TOP_C_P TBT_USB3_RX1_N 1 2 TBT_USB3_TX1_N 1 2
<37> TBTA_TOP_P 4 3 DT18 AZ5B75-01B.R7G_CSP0603P2Y2 DT26 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@
1 2 TBTA_TOP_C_N
<37> TBTA_TOP_N 1 2 TBT_USB3_RX1_P TBT_USB3_TX1_P
1 2 1 2
LT12 DT19 AZ5B75-01B.R7G_CSP0603P2Y2 DT27 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@ EMC@

C C

+VBUS_1 +VBUS_1

JUSBC1
+VBUS_1 A1 B12
GND GND
TBT_USB3_TX0_P A2 B11 TBT_USB3_RX0_P
<35> TBT_USB3_TX0_P TBT_USB3_TX0_N SSTXP1 SSRXP1 TBT_USB3_RX0_N TBT_USB3_RX0_P <35>
A3 B10
<35> TBT_USB3_TX0_N SSTXN1 SSRXN1 TBT_USB3_RX0_N <35>
CT120 1 2 0.47U_0402_25V6K A4 B9 CT122 1 2 0.47U_0402_25V6K
VBUS VBUS
1

TBTA_CC1 A5 B8 TBTA_SBU2
<37> TBTA_CC1 CC1 RFU2 TBTA_SBU2 <37>
DT28
TBTA_TOP_C_P A6 B7 TBTA_BOT_C_N
RB751S40T1G_SOD523-2 DP1 DN2
TBTA_TOP_C_N A7 B6 TBTA_BOT_C_P
DN1 DP2

Bottom
2

TBTA_SBU1 A8 B5 TBTA_CC2
B <37> TBTA_SBU1 RFU1 CC2 TBTA_CC2 <37> B

TOP
CT121 1 2 0.47U_0402_25V6K A9 B4 CT123 1 2 0.47U_0402_25V6K
VBUS VBUS
TBT_USB3_RX1_N A10 B3 TBT_USB3_TX1_N
<35> TBT_USB3_RX1_N TBT_USB3_RX1_P SSRXN2 SSTXN2 TBT_USB3_TX1_P TBT_USB3_TX1_N <35>
<35> TBT_USB3_RX1_P A11 B2 TBT_USB3_TX1_P <35>
SSRXP2 SSTXP2
A12 B1
GND GND

1 4
GND GND
2 3
GND GND

JAE_DX07S024XJ2
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P38-PD USB TYPE-C CONN.

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 38 of 76
5 4 3 2 1
 5 4 3 2 1

+1.2V_DDR +1.2V_DTH
+3VS_DTH +3VS_DTH +3VS +VDISPLAY_VCC
+1.2V_DTH
+5VS UZ25 900mA 2 DDC_CLK_HDMI
CZ101 RM15 1 @ 2 0_0603_5% RM1 1 2 2.2K_0402_5%
LM1 1 2 DTH_VDD33 1 8 0.1U_0201_10V6K DDC_DAT_HDMI RM2 1 2 2.2K_0402_5%
PBY160808T-301Y-N_2P 2 VIN VOUT 7
VIN VOUT 1
DTH_VDD12_ON

10U_0402_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
3 6 CZ100 1 2
EN CT
1 1 2 2 2 DTH_PDB

CM2

CM3

CM4

CM5
4 5 2200P_0201_25V7K RV561 1 @ 2 2.2K_0402_5%
CM1 VBIAS GND 9
0.47U_0201_6.3V6K GND
2 2 1 1 1
D
APE8937GN2_DFN8_2X2 D

PCH_DP3_HPD RM1145 2 1 100K_0201_5%

DTH_VDD12_ON <16,39> PCH_DP3_HPD
RM21 1 2 10K_0201_5%
UM1

DTH_VDD12 D6 G4 DTH_VDD33
F5 VDD12 VDD33 G2
+1.2V_DTH DTH_VDDA12 VDD12 VDD33 +3VS_DTH
F4 B2
VDDA12 VDD33
DTH_VDDTX12 G7 G8 DTH_VDD12_ON
G5 VDDTX12 VDD12_ON
VDDTX12

1
LM2 1 2 DTH_VDD12 B7
PBY160808T-301Y-N_2P DTH_VDDRX12 B5 VDDRX12 H8
VDDRX12 HDMID2P HDMI_TX_P2 <40>
B4 H7 HDMI_TX_N2 <40> RM6
VDDRX12 HDMID2N 10K_0201_5%
10U_0402_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0201_16V7
1 1 2 2 2 1 H6 HDMI_TX_P1 <40>

2
CPU_DP3_P0_C HDMID1P
CM9

CM10

CM11

CM12

CM13
CM6 2 1 0.1U_0201_6.3V6K A8 H5 HDMI_TX_N1 <40>
<7> CPU_DP3_P0 CPU_DP3_N0_C DRX0P HDMID1N
CM8 CM7 2 1 0.1U_0201_6.3V6K A7
<7> CPU_DP3_N0 DRX0N
0.47U_0201_6.3V6K H4 HDMI_TX_P0 <40>
2 2 1 1 1 2 CM14 2 1 0.1U_0201_6.3V6K CPU_DP3_P1_C A6 HDMID0P H3 DTH_RST#
<7> CPU_DP3_P1 CPU_DP3_N1_C DRX1P HDMID0N HDMI_TX_N0 <40>
<7> CPU_DP3_N1 CM15 2 1 0.1U_0201_6.3V6K A5
DRX1N H2
CPU_DP3_P2_C HDMICKP HDMI_CLKP <40>
<7> CPU_DP3_P2 CM16 2 1 0.1U_0201_6.3V6K A4 H1 HDMI_CLKN <40>
CM17 2 1 0.1U_0201_6.3V6K CPU_DP3_N2_C A3 DRX2P HDMICKN
<7> CPU_DP3_N2 DRX2N 1
F2 RM19 1 2 0_0402_5% CM41
CPU_DP3_P3_C HDMI_CEC HDMI_CEC <40>
<7> CPU_DP3_P3 CM18 2 1 0.1U_0201_6.3V6K A2 1U_0201_6.3V6M
CM19 2 1 0.1U_0201_6.3V6K CPU_DP3_N3_C A1 DRX3P E1
<7> CPU_DP3_N3 DRX3N DDC_SCL DDC_CLK_HDMI <40> 2
F1 DDC_DAT_HDMI <40>
CM45 2 1 0.1U_0201_6.3V6K CPU_DP3_AUXP_R CM20 2 1 0.1U_0201_6.3V6K CPU_DP3_AUXP_C C7 DDC_SDA
C +1.2V_DTH <7> CPU_DP3_AUXP CPU_DP3_AUXN_R CM21 2 CPU_DP3_AUXN_C AUXP HDMI_HPLUG DTH_PDB HDMI_HPLUG <40> C
<7> CPU_DP3_AUXN CM46 2 1 0.1U_0201_6.3V6K 1 0.1U_0201_6.3V6K C8 G1 RM27 1 @ 2 0_0402_5%
AUXN HDMI_HPD
RM25 1 2 68_0201_1% DTH_SPI_CS C1 B1 PCH_DP3_HPD_R RM3 1 2 1K_0402_5%
DTH_SPI_D_IN SPI_CS DP_HPD PCH_DP3_HPD <16,39>
RM26 1 2 68_0201_1% C2
LM3 1 2 DTH_VDDA12 DTH_SPI_D_OUT D1 SPI_D_IN
PBY160808T-301Y-N_2P DTH_SPI_CK_OUT D2 SPI_D_OUT C6 RM4 1 2 4.75K_0402_1% +3VS_DTH
DTH_SPI_WR_PROT E2 SPI_CK_OUT REXT C3 DTH_PDB RM5 1 2 10K_0201_5%
SPI_WR_PROT PDB DTH_RST#
10U_0402_10V6M

0.1U_0201_10V6K

0.01U_0201_16V7

B8
RESETB C5 A00_4P_0524 : EA Vlow issue (EQ)
1 1 2 1 TESTMODEB RM4 From 4.22K to 4.75K ohm
CM23

CM24

CM25

GPIO0 C4
CM22 D3 GPIO0
GIPIO1 DTH_PDB <16>
0.47U_0201_6.3V6K GPIO2 E3 F7
2 2 1 2 F3 GPIO2 NC
GPIO4 E7 CONFG1/GPIO3 G6
D7 CEC_EN/GPIO4 GND E5
HDMI_ID D8 I2C_ADDR/GPIO5 GND B3
<16> HDMI_ID HDMI_ID/GPIO6 GND G3
@ PAD~D T4936 DTH_CSCL E6 GND E4
@ PAD~D T4937 DTH_CSDA F6 CSCL GND D5
CSDA GND D4 +3VS_DTH
DTH_XTLI RM1031 2 33_0201_5% DTH_XTLI_R E8 GND B6
+1.2V_DTH DTH_XTLO RM1021 2 1K_0201_1% DTH_XTLO_R F8 XTLI GND A00_4P_0528: Remove RM23 for layout routing
XTLO RM14 1 2 4.7K_0201_5% DTH_CSCL

RM16 1 2 4.7K_0201_5% DTH_CSDA

LM4 1 2 DTH_VDDRX12

RM18

RM17
PBY160808T-301Y-N_2P
10U_0402_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0201_16V7

0.01U_0201_16V7

0.01U_0201_16V7

S IC PS175HDMBGA64GTR2-B2 TFBGA 64P

1
HDMI_ID
1 2 2 2 1 1 1
CM27

CM28

CM29

CM30

CM31

CM32

CM33

1
@ @

1
B CM26 B
0.47U_0201_6.3V6K 2 1 1 1 2 2 2 @

2
2 RM24
10K_0201_5%

4.7K_0201_5%

4.7K_0201_5%
2
+1.2V_DTH RM1834 1 @ 2 10M_0402_5% +3VS_DTH
YM1

LM5 1 2 DTH_VDDTX12 DTH_XTLI 1 3 DTH_XTLO

PBY160808T-301Y-N_2P 1 3

1
NC NC
+3VS_DTH
0.01U_0201_16V7
10U_0402_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0201_16V7

27MHZ_10PF_XRCGB27M000F2P18R0 RM7 RM10

2 4 4.7K_0201_5% 4.7K_0201_5%
1 1 2 2 1 1 1 1
CM34

CM35

CM38

CM50

CM39

CM43 CM44
CM37 15P_0402_50V8J 15P_0402_50V8J UM2

2
0.47U_0201_6.3V6K DTH_SPI_CS 1 8
2 2 1 1 2 2 2 2 DTH_SPI_D_IN 2 CS# VCC 7
DO HOLD#
1

DTH_SPI_WR_PROT 3 6 DTH_SPI_CK_OUT
RM20 4 WP# CLK 5 DTH_SPI_D_OUT
GND DI

1
@ 4.7K_0402_5%

1
0.1U_0201_10V6K
W25X20CLSNIG_SO8
RM28 2 RM9
2

10K_0201_5%

CM40
4.7K_0201_5%

2
RM11 1 @ 2 4.7K_0402_5% GPIO4

2
1
A RM12 1 @ 2 4.7K_0402_5% GPIO2 A

RM13 1 @ 2 4.7K_0402_5% GPIO0

Power On Configuration
GPIO2:Firmware initial address, internal pull-up~80K
0: Start from Bank 7 1: Start from Bank 3 (default)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
GPIO0 : Pre-emphasis setting; Intermal pull up
1:default, no pre-emphasis 0:pre-emphasis=2.5dB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P39-DP to HDMI Converter PS175
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
CEC_EN/GPIO4: For debug purpose DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 39 of 76
5 4 3 2 1
 5 4 3 2 1

HDMI change to CPU to PS185 to CONN Place between ESD and CM-Choke Place close to JHDMI1

@EMC@
HDMI_R_CLKN RV532 1 EMC@ 2 8.2_0201_1% HDMI_R_CLKN HDMI_R_CLKN DT175 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_CLKN

1
D RV539 D
150_0201_1%
@EMC@ @EMC@

2
HDMI_R_CLKP RV533 1 EMC@ 2 8.2_0201_1% HDMI_R_CLKP HDMI_R_CLKP DT176 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_CLKP

@EMC@
HDMI_R_TX_N0 RV534 1 EMC@ 2 8.2_0201_1% HDMI_R_TX_N0 HDMI_R_TX_N0 DT177 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_TX_N0

1
RV540
150_0201_1%
@EMC@ @EMC@

2
HDMI_R_TX_P0 RV535 1 EMC@ 2 8.2_0201_1% HDMI_R_TX_P0 HDMI_R_TX_P0 DT178 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_TX_P0

@EMC@
HDMI_R_TX_N1 RV536 1 EMC@ 2 8.2_0201_1% HDMI_R_TX_N1 HDMI_R_TX_N1 DT179 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_TX_N1

1
RV541
150_0201_1%
@EMC@ @EMC@

2
HDMI_R_TX_P1 RV537 1 EMC@ 2 8.2_0201_1% HDMI_R_TX_P1 HDMI_R_TX_P1 DT180 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_TX_P1
C C
@EMC@
HDMI_R_TX_N2 RV530 1 EMC@ 2 8.2_0201_1% HDMI_R_TX_P2 HDMI_R_TX_P2 DT182 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_TX_P2

1
RV538
150_0201_1%
@EMC@ @EMC@

2
HDMI_R_TX_P2 RV531 1 EMC@ 2 8.2_0201_1% HDMI_R_TX_N2 HDMI_R_TX_N2 DT181 1 2 AZ5B25-01F_DFN0603P2Y2
<39> HDMI_TX_N2

B B

HDMI DDC HDMI conn

+VDISPLAY_VCC
UV16
JHDMI1
+5VS HDMI_HPLUG 19
3
W=40mils <39> HDMI_HPLUG +VDISPLAY_VCC 18 HPD
OUT +5V

0.1U_0201_10V6K

10U_0402_6.3V6M
17
1 DDC_DAT_HDMI 16 DDC/CEC GND
IN 1 1 <39> DDC_DAT_HDMI DDC_CLK_HDMI SDA

CV178

CV179
<39> DDC_CLK_HDMI 15
2 HDMI_Reserved 14 SCL
GND HDMI_CEC 13 Reserved
2 2 <39> HDMI_CEC HDMI_R_CLKN CEC
12
11 CK-
AP2330W-7_SC59-3 HDMI_R_CLKP 10 CK_Shield
HDMI_R_TX_N0 9 CK+
8 D0-
HDMI_R_TX_P0 7 D0_Shield
HDMI_R_TX_N1 6 D0+
For EMI Reserve D1-
5
HDMI_R_TX_P1 4 D1_Shield 20
@ CV180 1 2 0.1U_0201_25V6K HDMI_HPLUG HDMI_R_TX_N2 3 D1+ GND1 21
2 D2- GND2 22
@ CV181 1 2 0.1U_0201_25V6K HDMI_Reserved HDMI_R_TX_P2 1 D2_Shield GND3 23
D2+ GND4
A @ CV182 1 2 0.1U_0201_25V6K HDMI_CEC ACON_HMRB9-AK120C A

CONN@
close to JHDMI

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P40-HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 40 of 76
5 4 3 2 1

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 5 4 3 2 1

+3VS +5VS +5VS +3VS

Power Button and LED PWM FAN

1
1

1
+3VALW RE100
10K_0201_5%
RE81 RE82

2
100K_0201_5% 10K_0201_5% JFAN1

1
1
<48> PWM_FAN1

2
RE104 1 @ 2 0_0603_5% 5VS_FAN1 2 1
RE3 2 1 3 2
<48> TACH_FAN1 4 3
300_0402_5% DE7 RB751S40T1G_SOD523-2
1 5 4

2
D CE66 6 G1 D
G2
0.01U_0402_16V7K
LED6 ACES_50224-00401-001
A00_4P_0517: remove debug part 1 2 2 CONN@
<48> BREATH_LED#
HT-F196BP5_WHITE

4 SW_BOT
3
PBTN_SW# <41,48,49,51>
+3VS +5VS +5VS +3VS

SW1 3

1
2 1 4
PBTN_SW# <41,48,49,51>
SKRBAAE010_4P

1
RE101
@ 10K_0201_5%
RE83 RE84

2
2 1 100K_0201_5% 10K_0201_5% JFAN2
1
<48> PWM_FAN2

2
SKRBAAE010_4P RE105 1 @ 2 0_0603_5% 5VS_FAN2 2 1
2 1 3 2
<48> TACH_FAN2 4 3
DE8 RB751S40T1G_SOD523-2
1 5 4
CE67 6 G1
G2
0.01U_0402_16V7K
ACES_50224-00401-001
2 CONN@

C power rail opt i on: TP Mpo wer r ail must sa me as +3. 3V_SPI ( SPI R O M
) C

Touch pad Nuvoton TPM +3VS

RE129 1 @ 2 0_0603_5% +3VS_TPM_VHIO

+3VALW +3VS_TP

UE6
+5VALW +3V_PCH
1 8 +3VALW +3VS_TPM_VSB
2 VIN VOUT 7
VIN VOUT CE65 RE141 1 @ 2 0_0603_5%
TP_PWR_EN 3 6 1 2 1 TPM@ 2 TPM_PIRQ#
<48> TP_PWR_EN EN CT 1
@ RE86 10K_0201_5%
4 5 2200P_0402_25V7K CE2
VBIAS GND 9 0.1U_0402_10V6K
GND 2
APE8937GN2_DFN8_2X2

RZ32 1 2 100K_0402_5% TP_PWR_EN +3VS_TPM_VSB

U32
1
+3VS_TP RE125 1 TPM@ 2 0_0201_1% SIO_SLP_S0#_TPM 29 VSB
<18,33,51> SIO_SLP_S0# SDA/GPIO0 +3VS_TPM_VHIO
30 8
+3VS_TP GPIO1/SCL VHIO 22
6 VHIO
GPIO3 2
RE113 1 TPM@ 2 33_0201_5% PCH_SPI_SO_TPM_R 24 NC 3
<17> PCH_SPI_SO_TPM MISO NC
RE7 RE114 1 TPM@ 2 33_0201_5% PCH_SPI_SI_TPM_R 21 5
<17> PCH_SPI_SI_TPM MOSI/GPIO7 NC
2

QE2A 1 2 2.4K_0402_5% TPM_PIRQ# 18 7

B <20> TPM_PIRQ# SPI_IRQ#/GPIO2 NC B
9
6 1 I2C1_SDA_TP_C NC 10
<20> I2C1_SDA_TP NC
RE115 1 TPM@ 2 33_0201_5% PCH_SPI_CLK_TPM_R 19 11
<17> PCH_SPI_CLK_TPM 1 2 0_0201_5% PCH_SPI_CS#2_R 20 SCLK NC 12
DMN65D8LDW-7_SOT363-6 <17> PCH_SPI_CS#2 RE133 @
17 SCS#/GPIO5 NC 14
<17,23,31,34,35,42,43,48,49,50> PCH_PLTRST#_EC RESET# NC
RE9 27 15
NC NC
5

1 2 2.4K_0402_5% 13 26
GPIO4/SINT# NC 25
3 4 I2C1_SCK_TP_C NC 28
<20> I2C1_SCK_TP 4 NC 31
QE2B PP/GPIO6 NC 32
DMN65D8LDW-7_SOT363-6 NC
16
GND 23
+3VS_TP +3VS_TP GND 33
PGND
NOTE:
Place 0.1 uF capacitors NPCT750JAAYX_QFN32_5X5
1

RE87 close to U32 pin8 and pin 22

+3VS_TPM_VHIO
100K_0402_5%
2
G

PTP_INT#_R +3VS_TP

10U_0603_6.3V6M
1 3 +3VS_TPM_VSB
<17,48> PTP_INT#

0.1U_0201_25V6K

0.1U_0201_25V6K

0.1U_0201_25V6K
D

10U_0603_6.3V6M
1 1 1 1

0.1U_0201_25V6K
QE13 JTP

CE85

CE84

CE75

CE76
1 1
L2N7002WT1G_SC-70-3 8 @EMI@ C135
I2C1_SDA_TP_C 8 PCH_SPI_CLK_TPM_R 2 2 2 2

CE11

CE83
7 10 2 1
I2C1_SCK_TP_C 6 7 G2 9 TPM@ TPM@ @ TPM@
5 6 G1 0.1U_0201_10V6K 2 2
A PTP_INT#_R 4 5 TPM@ TPM@ A
4 Reserve for EMI please close to U32
3
<48> PTP_DIS# 2 3
<48> DAT_TP_SIO 2
1
<48> CLK_TP_SIO 1
PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

1 1 ACES_51524-0080N-001
3

22P_0402_50V8J
CE80

22P_0402_50V8J
CE79

1 1 @ @

CE78
22P_0402_50V8J
CE77 EMC@
22P_0402_50V8J DE4
DE5
EMC@ 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
@ @ P41-FAN/TP/TPM/SW
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 41 of 76
5 4 3 2 1
 5 4 3 2 1

M.2 Slot-A Key-A (WLAN + BT)

+3VS_WLAN
CONCR_213AAAA32FA
JNGFF1
1 2 WLAN_WIGIG60GHZ_DIS#_R 2 1
USB20_P4_R 3 1 2 4 WLAN_WIGIG60GHZ_DIS# <48>
USB20_N4_R 3 4

.1U_0402_16V7K
5 6 DN1
7 5 6 RB751S40T1G_SOD523-2
7

22U_0603_6.3V6M
1 1 BT_RADIO_DIS#_R

CN2
2 1
BT_RADIO_DIS# <48>

CN1
8 DN2
9 8 10 2 2 RB751S40T1G_SOD523-2
11 9 10 12
D
13 11 12 14 D
15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22
23 21 22 24
Close to JNGFF
25 23 24 26
CN21 1 2 0.1U_0201_10V6K PCIE_PTX_C_DRX_P1 27 25 26 28
<19> PCIE_PTX_DRX_P1 PCIE_PTX_C_DRX_N1 27 28 CLINK_RST#
<19> PCIE_PTX_DRX_N1 CN20 1 2 0.1U_0201_10V6K 29 30
CLINK_RST# <16>
31 29 30 32 CLINK_DATA
31 32 CLINK_CLK CLINK_DATA <16>
33 34
<19> PCIE_PRX_DTX_P1 33 34 CLINK_CLK <16>
35 36
<19> PCIE_PRX_DTX_N1 35 36
37 38
39 37 38 40
<17> CLK_PCIE_P3 39 40 SUSCLK_R
<17> CLK_PCIE_N3 41 42 RN1 1 @ 2 0_0201_5% SUSCLK <18,43>
43 41 42 44
43 44 BT_RADIO_DIS#_R PCH_PLTRST#_EC <17,23,31,34,35,41,43,48,49,50>
45 46
<17> CLKREQ_PCIE#3 PCIE_WAKE# 45 46 WLAN_WIGIG60GHZ_DIS#_R
<35,43,48> PCIE_WAKE# 47 48
49 47 48 50
51 49 50 52
53 51 52 54
55 53 54 56
57 55 56 58
59 57 58 60 +3VS_WLAN
61 59 60 62
63 61 62 64
65 63 64 66
65 66

22U_0603_6.3V6M

.1U_0402_16V7K
67
67
1 1

CN6

CN7
69 68
GND GND

2 2
CONN@

C C
Reserve for EMI
Close to JNGFF
+3VS_WLAN +3VS_WLAN

1 1
@ CN8 @ CN9
.1U_0402_16V7K 1000P_0201_50V7K
2 2

EMC@
MCM1012B900F06BP_4P
4 3 USB20_P4_R
<19> USB20_P4

1 2 USB20_N4_R
<19> USB20_N4
LN1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P42-NGFF-WLAN/BT

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 42 of 76
5 4 3 2 1
 5 4 3 2 1

+3.3VDX_SSD

M.2 Slot-C Key-M (SSD)

RF Reserved.
JNGFF2 EMC@ EMC@

4.7U_0603_6.3V6K
CD36

.1U_0402_16V7K
CD38

0.01U_0402_16V7K
CD39

47P_0402_50V8J
CD40

15P_0402_50V8J
CD41
1 2 1 1 1 1 1
3 1 2 4
5 3 4 6
<16> PCIE_PRX_DTX_N09 5 6 SSD_SCP#_R
<16> PCIE_PRX_DTX_P09 7 8 RD101 1 2 0_0402_5%
9 7 8 10 SSD_SCP# <48> 2 2 2 2 2
CD43 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N09 11 9 10 12
<16> PCIE_PTX_DRX_N09 PCIE_PTX_C_DRX_P09 11 12
CD44 1 2 0.22U_0402_10V6K 13 14
<16> PCIE_PTX_DRX_P09 13 14
15 16
17 15 16 18
<16> PCIE_PRX_DTX_N10 17 18
19 20
<16> PCIE_PRX_DTX_P10 19 20
PCIe SSD 21 22
D
CD45 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N10 23 21 22 24 D
<16> PCIE_PTX_DRX_N10 PCIE_PTX_C_DRX_P10 23 24
CD46 1 2 0.22U_0402_10V6K 25 26
<16> PCIE_PTX_DRX_P10 25 26
27 28
29 27 28 30
<16> PCIE_PRX_DTX_N11 29 30
<16> PCIE_PRX_DTX_P11 31 32
33 31 32 34
CD53 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 35 33 34 36 RD7 2 @ 1 10K_0402_5%
<16> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 35 36 +3.3VDX_SSD
<16> PCIE_PTX_DRX_P11 CD51 1 2 0.22U_0402_10V6K 37 38
39 37 38 40 M2280_DEVSLP <19>
41 39 40 42
<16> SATA_PRX_DTX_P1A 41 42
43 44
<16> SATA_PRX_DTX_N1A 43 44
45 46
SATA SSD 1A CD37 1 2 0.22U_0402_10V6K SATA_PTX_C_DRX_N1A 47 45 46 48
<16> SATA_PTX_DRX_N1A SATA_PTX_C_DRX_P1A 47 48
CD42 1 2 0.22U_0402_10V6K 49 50
<16> SATA_PTX_DRX_P1A 49 50 PCH_PLTRST#_EC <17,23,31,34,35,41,42,48,49,50>
51 52 CLKREQ_PCIE#6 <17>
53 51 52 54 SSD_PCIE_WAKE# RD59 1 @ 2 0_0402_5%
<17> CLK_PCIE_N6 53 54 PCIE_WAKE# <35,42,48>
55 56
<17> CLK_PCIE_P6 55 56
57 58 RD8 1 2 10K_0402_5% +3.3VDX_SSD
57 58

59 60 SSD_SUSCLK RD9 1 @ 2 0_0402_5%

59 60 SUSCLK <18,42>
+3VS RD10 1 @ 2 10K_0402_5% 61 62
+3.3VDX_SSD
63 61 62 64
65 63 64 66
67 65 66
67

68 69
GND GND

CONCR_213MAAA32FA
CONN@
RD58 1 @ 2 0_0402_1%
<16> M2280_PCIE_SATA#
C C

SATA -> GND

PCIe -> OPEN

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P43-NGFF-SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 43 of 76
5 4 3 2 1
 5 4 3 2 1

HDD CONN
CONN@
JHDD
1
2 1
3 2
4 3
SATA_PTX_C_DRX_P2 5 4
SATA_PTX_C_DRX_N2 6 5
7 6
SATA_PRX_C_DTX_N2 8 7
SATA_PRX_C_DTX_P2 9 8
10 9
FFS_INT2_Q 11 10
D
12 11 D
<16> HDD_DET# 13 12
14 13
15 14
+5VS_HDD 15
RD100 1 2 0_0402_5% 16
<19> HDD_DEVSLP 16
17
18 17
19 18
20 19
21 20
22 GND
23 GND
24 GND
GND
J-L_UCNR2234B020-0

Place near HDD CONN (JHDD1)

+5VS_HDD

1 1 1 1
CS12 CS13 CS14 CS15
1000P_0402_50V7K .1U_0402_16V7K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 2 2 2

C C

CS17 1 2 0.01U_0201_16V7 SATA_PTX_C_DRX_P2

<16> SATA_PTX_DRX_P2 SATA_PTX_C_DRX_N2
CS18 1 2 0.01U_0201_16V7
<16> SATA_PTX_DRX_N2
CS19 1 2 0.01U_0201_16V7 SATA_PRX_C_DTX_P2
<16> SATA_PRX_DTX_P2 SATA_PRX_C_DTX_N2
CS20 1 2 0.01U_0201_16V7
<16> SATA_PRX_DTX_N2

BYPASS Circuit

Free Fall Sensor +5VS

1
RF2
+3VS_FFS 100K_0402_5%

+3VS

2
RF4 1 2 100K_0402_5% HDD_FALL_INT
FFS_INT2_Q

1
RF5 1 2 100K_0402_5% FFS_INT2
RF3
100K_0402_5%

3
2
QF1B
B B
5 DMN65D8LDW-7_SOT363-6

4
6
QF1A
FFS_INT2 2 DMN65D8LDW-7_SOT363-6

1
+3VS +3VS_FFS

RF1 1 @ 2 0_0603_5%

1 1
CF1 CF2
10U_0603_6.3V6M 0.1U_0402_25V6 UF1
2 2 LNG2DM
10 5
9 VDD_IO RES
VDD 12 HDD_FALL_INT
INT 1 FFS_INT2 HDD_FALL_INT <20>
3 11 FFS_INT2 <20>
PCH_SMBDATA 4 SDO/SA0 INT 2
<6,14,15,18> PCH_SMBDATA PCH_SMBCLK SDA/SDI/SDO
<6,14,15,18> PCH_SMBCLK 1 6
SCL/SPC GND 7
2 GND 8
CS GND
A A

LNG2DMTR_LGA12_2X2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P44-HDD / FFS

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-G341P 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 44 of 76
5 4 3 2 1
 5 4 3 2 1

USB Powershare
Device Control Pins CTL1 = 0 : Enable Power Share DCP mode in Suspend mode
Flow Line
Condition Suspend mode
CTL1 CTL2 CTL3 ILIM_SEL
CTL1 = 1 : Disable Power Share in Suspend mode (For Support USB wake)
0 1 1 X DCP AUTO
D D
ILIM_SEL = 0 : SDP mode (0.9A by ILIM_LO setting)
1 1 1 0 SDP
S0 mode
1 1 1 1 CDP ILIM_SEL = 1 : CDP mode (STATUS# trigger by ILIM_HI =2.2A)

+3VALW
USB3.1 / USB2.0 Port1 (Right Side)
RI30 1 2 100K_0402_5% ILIM_SEL_R
+5VALW
RI9 1 2 100K_0402_5% USB_R_CTL

RI10 1 2 100K_0402_5% USB_POWERSHARE_EN_R#

1
RI13 1 2 10K_0402_5% USB_POWERSHARE_VBUS_EN_R +3VALW CI2
0.1U_0402_25V6
CI22 2 +5V_CHGUSB_1
1 2

0.1U_0402_10V7K 2.1A
UI2

5
UI5 1 12
C USB_PWR_EN 1 USB_STATUS#_R 9 IN OUT 10 C

P
INB USB_PWR_EN_R STATUS# DP_IN CHR_USB20_P1 <47>
4 13 11
USB_POWERSHARE_VBUS_EN_R O <19> USB_OC0# ILIM_SEL_R FAULT# DM_IN CHR_USB20_N1 <47>
2 4 2
<48> USB_POWERSHARE_VBUS_EN_R INA ILIM_SEL DM_OUT USB20_N1 <19>

1
USB_PWR_EN_R 5 3
USB_POWERSHARE_EN_R# EN DP_OUT ILIM_LO1 RI11 USB20_P1 <19>
MC74VHC1G32DFT2G_SC70-5~D RI27 6 15 1 2 33K_0402_1%
<48> USB_POWERSHARE_EN_R#

3
7 CTL1 ILIM_LO 16 ILIM_HI1 1 2
1M_0402_5% CTL2 ILIM_HI
USB_R_CTL 8 14 RI12 22.1K_0402_1%
CTL3 GND 17

2
T-PAD

TPS2546RTER_QFN16_3X3

RI28 1 @ 2 0_0402_5%

+3VALW

ILIM_SEL_L
USB3.1 / USB2.0 Port2 (Left Side)
RI31 1 2 100K_0402_5%

RI4 1 2 100K_0402_5% USB_L_CTL +5VALW

RI5 1 2 100K_0402_5% USB_POWERSHARE_EN_L#

USB_POWERSHARE_VBUS_EN_L 1
RI8 1 2 10K_0402_5%
CI1 +5V_CHGUSB_2
0.1U_0402_25V6
+3VALW 2
2.1A
CI21 UI1
1 2 1 12
B USB_STATUS#_L 9 IN OUT 10 B
STATUS# DP_IN CHR_USB20_P2 <47>
0.1U_0402_10V7K 13 11
<19> USB_OC1# ILIM_SEL_L FAULT# DM_IN CHR_USB20_N2 <47>
4 2
ILIM_SEL DM_OUT USB20_N2 <19>
5

UI4 USB_PWR_EN_L 5 3
USB_PWR_EN USB_POWERSHARE_EN_L# 6 EN DP_OUT ILIM_LO3 RI6 USB20_P2 <19>
1 15 1 2 33K_0402_1%
P

<17> USB_PWR_EN INB USB_PWR_EN_L <48> USB_POWERSHARE_EN_L# CTL1 ILIM_LO ILIM_HI3

4 7 16 1 2
USB_POWERSHARE_VBUS_EN_L 2 O USB_L_CTL 8 CTL2 ILIM_HI 14 RI7 22.1K_0402_1%
<48> USB_POWERSHARE_VBUS_EN_L INA CTL3 GND
G

17
T-PAD
1

MC74VHC1G32DFT2G_SC70-5~D
3

RI26
1M_0402_5% TPS2546RTER_QFN16_3X3
2

DI12
2 ILIM_SEL_R RI32 1 @ 2 0_0402_1% USB_STATUS#_L

1
<48> USB_ILIM_SEL
3 ILIM_SEL_L RI33 1 @ 2 0_0402_1% USB_STATUS#_R

BAT54CW-7-F_SOT323-3~D

RI35 1 @ 2 0_0402_5% ILIM_SEL_R RI34 1 @ 2 0_0402_5% ILIM_SEL_L

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P45-USB Powershare
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 45 of 76
5 4 3 2 1
 5 4 3 2 1

+3V_PS8723
Equalizer control and program for channel A1&A2/B1&B2
A_EQ0 RI15 1 2 10K_0402_5% 3.3V tolerant. Internally pulled down at ~150KΩ
A_EQ1 [EQ1, EQ0] ==
@ RI16 1 2 0_0402_5% LL: equalization for channel loss up to 9.5dB (default)
LH: equalization for channel loss up to 13 dB
HL: equalization for channel loss up to 4.5dB
+3V_PS8723 HH: equalization for channel loss up to 7.5dB

B_EQ0 RI17 1 2 10K_0402_5%

D D
B_EQ1 @ RI18 1 2 0_0402_5%

+3V_PS8723
Programmable output de-emphasis level setting for channel A1&A2/B1&B2
A_DE0 @ RI19 1 2 4.7K_0402_5% 3.3V tolerant. Internally pulled down at ~150KΩ
A_DE1 [DE1, DE0] ==
@ RI20 1 2 4.7K_0402_5% LL: 3.5dB de-emphasis (default)
LH: No de-emphasis
+3V_PS8723 HL: 2.7dB de-emphasis
HH: 5.0dB de-emphasis
B_DE0 @ RI21 1 2 4.7K_0402_5%
B_DE1 @ RI22 1 2 4.7K_0402_5%

+3V_PS8723
LFPS swing adjust.
USB8723_test @ RI24 1 2 4.7K_0402_5% 3.3V tolerant. Internally pulled down at ~150KΩ .
TST ==
L: Normal LFPS swing (default)
H: Tune down LFPS swing

+3VALW +3V_PS8723

RI45 1 @ 2 0_0805_5% USB3.0 Re-driver PS8713_PD#

2
C C
+3VS +3V_PS8723 RI46
@ 10K_0402_5%
RI14 1 @ 2 0.01_0805_1%

1
PS8713_PD#_R
0.01U_0402_16V7K
0.1U_0402_10V7K

1
D
1 1 USB_DET#_R
@ QI10 2
USB_DET#_R <47,48>
UI3 L2N7002WT1G_SC-70-3 G
1 S
+3V_PS8723

3
2 2 13 VDD
CI3

CI4

VDD

A_EQ1 15 4 B_EQ1
A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 B_DE0
A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 B_EQ0
A_DE1 18 A_EQ0/NC B_EQ0/NC 6 B_DE1
A_DE1/NC B_DE1/NC
CI5 1 2 0.1U_0402_10V7K USB3_PTX_C_RD_DRX_P1 19 12
<19> USB3_PTX_DRX_P1 USB3_PTX_C_RD_DRX_N1 A_INp A_OUTp USB3_PTX_RD_DRX_P1 <47>
<19> USB3_PTX_DRX_N1 CI6 1 2 0.1U_0402_10V7K 20 11 USB3_PTX_RD_DRX_N1 <47>
A_INn A_OUTn

9 22 USB3_PRX_C_RD_DTX_P1 0.1U_0402_10V7K 2 1CI7

<47> USB3_PRX_RD_DTX_P1 B_INp B_OUTp USB3_PRX_C_RD_DTX_N1 USB3_PRX_DTX_P1 <19>
8 23 0.1U_0402_10V7K 2 1CI8
<47> USB3_PRX_RD_DTX_N1 B_INn B_OUTn USB3_PRX_DTX_N1 <19>

PS8713_PD# 0_0402_5% 2 @ 1 RI36 PIN5_PD# 5

4.99K_0402_1% 2 1 RI23 DPM_REXT 7 PD# 10
USB8723_test 14 REXT GND 21
0_0402_1% 2 @ 1 RI25 I2C_EN8723 24 TEST GND 25
I2C_EN GPAD
PS8713BTQFN24GTR2_TQFN24_4X4

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P46-USB3.1 retimer
WWW.AliSaler.Com
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 2
Size Document Number
Custom

Date: Wednesday, June 06, 2018

1
Sheet 46 of 76
Rev
1.0(A00)
 5 4 3 2 1

D D

C C

<45> CHR_USB20_N1
1
LI2
2 CHR_USB20_N1_R USB3.1 / USB2.0 Port1 (Left Side(BOT))
4 3 CHR_USB20_P1_R
<45> CHR_USB20_P1
MCM1012B900F06BP_4P +5V_CHGUSB_1
DI9 EMC@ JUSB2
EMC@ USB3_PRX_L_DTX_N11 USB3_PRX_L_DTX_N1 USB3_PTX_L_DRX_P1
1 10 9 9
SSTX+
1
USB3_PRX_L_DTX_P12 USB3_PRX_L_DTX_P1 USB3_PTX_L_DRX_N1 VBUS
2 9 8 8
SSTX-
CHR_USB20_P1_R 3
USB3_PTX_C_DRX_N1 2 0_0402_1% USB3_PTX_L_DRX_N1 USB3_PTX_L_DRX_N14 4 USB3_PTX_L_DRX_N1 D+

10U_0603_6.3V6M

0.1U_0402_25V6
1 2 RI37 1 @ 7 7 1 1 1 7
<46> USB3_PTX_RD_DRX_N1 CHR_USB20_N1_R GND

CI18
CI16 0.1U_0402_10V7K 2 11
USB3_PTX_L_DRX_P15 USB3_PTX_L_DRX_P1 USB3_PRX_L_DTX_P1 D- GND

CI19
5 6 6 CI17 6
SSRX+ GND
12
1 2 USB3_PTX_C_DRX_P1 RI38 1 @ 2 0_0402_1% USB3_PTX_L_DRX_P1 4 13
<46> USB3_PTX_RD_DRX_P1 47U_0805_6.3V6M GND GND
CI20 0.1U_0402_10V7K 3 3 2 2 2 USB3_PRX_L_DTX_N1 5 14
10 SSRX- GND
<46,48> USB_DET#_R Plug_DET

1
8 D123 D124
EMC@ EMC@ TAIWI_USB019-107CRL-TWD
CONN@
AZ1045-04F_DFN2510P10E-10-9

RI39 1 @ 2 0_0402_1% USB3_PRX_L_DTX_P1

<46> USB3_PRX_RD_DTX_P1
B AZ5B25-01F_DFN0603P2Y2 AZ5B25-01F_DFN0603P2Y2 B

2
RI40 1 @ 2 0_0402_1% USB3_PRX_L_DTX_N1
<46> USB3_PRX_RD_DTX_N1
Place close to JUSB2

LI5
<45> CHR_USB20_N2
1 2 CHR_USB20_N2_R
USB3.1 / USB2.0 Port2 (Right Side(BOT))
4 3 CHR_USB20_P2_R
<45> CHR_USB20_P2
MCM1012B900F06BP_4P +5V_CHGUSB_2
EMC@ JUSB1
USB3_PTX_C_DRX_P2 9
1 SSTX+
USB3_PTX_C_DRX_N2 VBUS

10U_0603_6.3V6M
8
CHR_USB20_P2_R 3 SSTX-
D+

0.1U_0402_25V6
1 1 1 7
DI7 CHR_USB20_N2_R GND

CI12
EMC@ 2 11
USB3_PRX_DTX_N2 USB3_PRX_DTX_P2 D- GND

CI13
1 1 10 9 CI11 6 12
<19> USB3_PRX_DTX_N2 SSRX+ GND
47U_0805_6.3V6M 4 13
2 2 8 USB3_PRX_DTX_P2 2 2 2 USB3_PRX_DTX_N2 5 GND GND 14
9
<19> USB3_PRX_DTX_P2 SSRX- GND
10
<48> USB_DET#_L Plug_DET

1
1 2 USB3_PTX_C_DRX_N2 4 4 7 7 USB3_PTX_C_DRX_N2 D125 D126
<19> USB3_PTX_DRX_N2
CI9 0.1U_0201_10V6K EMC@ EMC@ TAIWI_USB019-107CRL-TWD
1 2 USB3_PTX_C_DRX_P2 5 5 6 6 USB3_PTX_C_DRX_P2 CONN@
<19> USB3_PTX_DRX_P2
CI10 0.1U_0201_10V6K
3 3

A 8 A
AZ5B25-01F_DFN0603P2Y2 AZ5B25-01F_DFN0603P2Y2

2
AZ1045-04F_DFN2510P10E-10-9

Place close to JUSB1

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P47-USB3.1/USB2.0 conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 47 of 76
5 4 3 2 1
 A B C D E F G H

+3VS
+3VALW_5105
+3VLP

RE304 1 @ 2 0.01_0603_1% +RTC_CELL_VBAT

1
RP19
BC_DAT_ECE1117 1 8
+3VALW_5105 +RTCVCC_R @ RE137 @ RE136
TOUCHPAD_INTR#_EC 2 7
5.1K_0402_1% 5.1K_0402_1%
<48> TOUCHPAD_INTR#_EC
RE16 1 @ 2 0_0603_5% 3 6
RESET_IN#

2
0.1U_0402_25V6
RE145 1 2 100K_0402_5% BATBTN# 4 5

2
2 100K_0402_5% RESET_IN# AUDIO_AMP_SMBDAT

1
RE311 1 @ <48> AUDIO_AMP_SMBDAT 6 1
I2C0_SDA_DSP <51,52> 100K_0804_8P4R_5% +3VALW_5105

5
CE17
DMN65D8LDW-7_SOT363-6
SSD_SCP#
+3VALW RZ1136 1 @ 2 0_0603_5% RE307 1 @ 2 100K_0402_5%
AUDIO_AMP_SMBCLK HW_ACAVIN_NB_P

2
QE18A3 4 RE142 1 2 100K_0402_5%
+3VS_TP <48> AUDIO_AMP_SMBCLK I2C0_SCK_DSP <51,52>
DMN65D8LDW-7_SOT363-6
CLK_TP_SIO FPR_DET#
RE24 1 2 4.7K_0402_5% RE284 1 2 10K_0402_5%
RE26 1 2 4.7K_0402_5% DAT_TP_SIO +3VALW_5105 QE18B FPR_SCAN# RE283 1 2 10K_0402_5%
PCIE_WAKE#_R
RE19 1 2 10K_0402_5%
USBC_MCP23008_SMBDAT RE20 1 2 2.2K_0402_5%
USBC_MCP23008_SMBCLK
RH5884 1 2 1M_0402_5% ALWON RE21 1 2 2.2K_0402_5%
PBAT_CHARGER_SMBDAT RE22 1

10U_0603_6.3V6M

0.1U_0402_25V6
2 10K_0402_5%

1U_0402_6.3V6K

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
PCH_PLTRST#_EC PBAT_CHARGER_SMBCLK
RE31 1 @ 2 10K_0402_5% RE23 1 2 10K_0402_5%
LCD_TST

1
RE32 1 2 100K_0402_5% THERMTRIP1# RE25 1 2 10K_0402_5%
SYS_PWROK AUDIO_AMP_SMBDAT

CE23
CE22

CE24

CE25

CE26

CE27
1 RE33 1 2 1M_0402_5% UE3 RE94 1 2 2.2K_0402_5% 1
F2 RC_ID0 AUDIO_AMP_SMBCLK
T4982 PAD~D @ RE95 1 2 2.2K_0402_5%

2
+RTC_CELL_VBAT A2 GPIO033/RC_ID0 J10 GPU_ID UPD_SMBDAT RE293 1 2 2.2K_0402_5%
VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID GPU_ID <49> UPD_SMBCLK
J13 RE294 1 2 2.2K_0402_5%
GPIO036/RC_ID2/SPI0_MISO AUDIO_AMP_SMBDAT BOARD_ID <48> GPU_SMBDAT
B7 E7 AUDIO_AMP_SMBDAT <48> RE295 1 2 2.2K_0402_5%
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7 AUDIO_AMP_SMBCLK GPU_SMBCLK RE296 1 2 2.2K_0402_5%
+3VALW_5105 K2 GPIO004/SMB00_CLK/SPI0_MOSI AUDIO_AMP_SMBCLK <48> Audio + AMP SMB00
+3VALW_5105 RH5861 +3VALW_5105_VTR_PLL VREF_ADC G3 UPD1_ALERT#
RUNPWROK RUNPWROK <18> <37,48> UPD1_ALERT# RE99 1 2 10K_0402_5%
1 2 F1 GPIO057/VCC_PWRGD H5 SSD_SCP#
+3VALW_5105 VTR_PLL GPIO060/KBRST/48MHZ_OUT HOST_DEBUG_TX SSD_SCP# <43>

0.1U_0402_25V6

22U_0603_6.3V6M
G11 MSDATA RE27 1 2 10K_0402_5%
GPIO104/UART0_TX ME_FWP HOST_DEBUG_TX <49> SUS_ON_EC_R
H1 G12 RE30 1 2 100K_0402_5%
WLAN_WIGIG60GHZ_DIS# 100_0402_1% VTR_REG GPIO105/UART0_RX ME_SUS_PWR_ACK ME_FWP <18>

1
RE71 1 2 100K_0402_5% @ B13

0.1U_0402_25V6
BT_RADIO_DIS# GPIO127/A20M/UART0_CTS# UPD1_ALERT# ME_SUS_PWR_ACK <18>

CE18

CE19
RE72 1 2 100K_0402_5% G8 F10
SIO_SLP_SUS#_R VTR1 GPIO225/UART0_RTS# UPD1_ALERT# <37,48>

1
RE300 1 2 100K_0402_5%
+3VALW_5105
M9
PCIE_WAKE#_R

2
VTR2

CE20
NDS@ N5 N13
+1.8V_3.3V_ALW_VTR3 VTR3 GPIO025/TIN0/nEM_INT/UART_CLK SIO_SLP_S4#
N12
SIO_SLP_S4# <18,33,51>

2
PCH_DPWROK_EC F8 GPIO026/TIN1 M11 SIO_SLP_A#_R 2 1 RE290
<18> PCH_DPWROK_EC 0_0402_5% SIO_SLP_A# <18,51>
+VSS_PLL RUN_ON_EC E8 GPIO020 GPIO027/TIN2 H9 TP_PWR_EN
<32,33,48> RUN_ON_EC SIO_EXT_WAKE# GPIO045 GPIO030/TIN3 TP_PWR_EN <41> MSDATA_R
M12 0_0402_1% 1 @ 2 RE287 MSDATA
<20> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120 VGA_IDENTIFY MSDATA <49>
C2 L9 RE112 1 @ 2 0_0402_1%
<42> BT_RADIO_DIS# PBAT_PRES# GPIO166 GPIO017/GPTP-IN5 USB_ILIM_SEL BID_DIS <17,20> MSCLK_R
F9 M10 0_0402_1% 1 @ 2 RE288 MSCLK

POWER SW /LID CL <18,20,32> SIO_SLP_SUS# RE111 2 1 43K_0402_1%

<56,58> PBAT_PRES#

<33> PCH_ALW_ON
<18> AC_PRESENT
SIO_SLP_SUS#_R
PCH_ALW_ON
AC_PRESENT
N4
M8
K8
GPIO175
GPIO230
GPIO231
GPIO151/ICT4
GPIO152/GPTP-OUT3
N9

C11
SPK_DET#_EC

BREATH_LED#
RE139 2 @
USB_ILIM_SEL <45>
1 0_0402_1%

BREATH_LED# <41>
SPK_DET# <20,51>
MSCLK <49>

GPIO233 GPIO156/LED0 D10 BAT1_LED#

SML1_SMBDAT GPIO157/LED1 BAT2_LED# BAT1_LED# <51> Amber
+RTC_CELL_VBAT E11 D11 White
<18> SML1_SMBDAT SML1_SMBCLK GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 LCD_VCC_TEST_EN BAT2_LED# <51>
D8 E1
Connect PCH SMB03 <18> SML1_SMBCLK BATT_LED#_LV5 M13 GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <32>
<49> BATT_LED#_LV5 GPIO110/PS2_CLK2 FPR_SCAN#
1

SUSACK# K12 E5
<18> SUSACK# WLAN_WIGIG60GHZ_DIS# GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 FPR_DET# FPR_SCAN# <49>
RE34 HDA_I2S_SEL = Low ; HDA Mode L13 B3
<42> WLAN_WIGIG60GHZ_DIS# SIO_PWRBTN# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 VCCDSW_EN FPR_DET# <49>
100K_0402_5% HDA_I2S_SEL = High ; I2S Mode K11 M7
<6,18> SIO_PWRBTN# SLP_WLAN#_GATE_R GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 GPU_GC6_FB_EN VCCDSW_EN <20>
@ <32> SLP_WLAN#_GATE 0_0402_1% 2 @ 1 RE305 K10 M4
GPU_GC6_FB_EN <16,23,31>
2 1 RE110 LID_CL_SIO# N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PBAT_CHARGER_SMBDAT TBT_RESET_N_EC 100K_0402_5% 1 2 RZ41
<37> PWR_TB_DOCK# <48,49> LID_CL_SIO# PBAT_CHARGER_SMBDAT <56,58>
2

CLK_TP_SIO GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK

10K_0402_5% 0_0402_5% 2 @ 1 RE306 E10 N2
POWER_SW_IN# <33> VCCST_PWRGD <41> CLK_TP_SIO DAT_TP_SIO C12 GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 N10 USBC_MCP23008_SMBDAT PBAT_CHARGER_SMBCLK <56,58> PBAT and Charger SMB10
Touch Pad SMB02 <41> DAT_TP_SIO GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA A12 USBC_MCP23008_SMBCLK
2 1 RE36
<49> JTAG_TDI
JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 GPU_SMBDAT
GPU_SMBDAT <23>
EXPENDER and Dock_TINY SMB06
<41,49,51> PBTN_SW# JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 GPU_SMBCLK TOUCHPAD_INTR#_EC 0_0402_1% 2 1 RE138
1K_0402_5% @
<49> JTAG_TDO JTAG_CLK GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# UPD_SMBDAT GPU_SMBCLK <23> GPU SMB05 PTP_INT# <17,41>
1

C8 B4 UPD_SMBDAT <37>
<49> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD_SMBCLK
1

@ CE30 C5 C3
CE29 2.2U_0402_6.3V6M
<49> JTAG_TMS JTAG_RST# G13 GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD_SMBCLK <37> PD SMB04
<48> JTAG_RST#
2

JTAG_RST# J4 I_BATT_R
1U_0402_6.3V6K RE55 1 2 300_0402_5%
I_BATT <58>
2

TACH_FAN1 E3 GPIO200/ADC00 J5 I_SYS_R RE126 1 2 300_0402_5%

SHD_CLK SHD_CLK_R1 <41> TACH_FAN1 TACH_FAN2 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 PS_ID P_SYS <58,62>
R5831 1 @ 2 24.9_0402_1% T5999 PAD~D @ <41> TACH_FAN2
D1 J6
PS_ID <56>
LCD_TST M2 GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 G2 TOUCHPAD_INTR#_EC SIO_SLP_S3# 2 1 RUN_ON_EC
<34> LCD_TST TOUCHPAD_INTR#_EC <48> @ RUN_ON_EC <32,33,48>
PWM_FAN1 L10 GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 H2 T6004 PAD~D @ 0_0402_5% RE35
<41> PWM_FAN1 PWM_FAN2 GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POWERSHARE_VBUS_EN_L
L11 J2
<41> PWM_FAN2 PCH_RSMRST# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POWERSHARE_EN_L# USB_POWERSHARE_VBUS_EN_L <45>
<6,18> PCH_RSMRST#_EC 0_0402_5% 2 1 RT1136 M5 J3
USB_POWERSHARE_EN_L# <45>
SHD_CLK J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_POWERSHARE_EN_R#
+3VALW_5105 USB_POWERSHARE_EN_R# <45>
BIA_PWM_EC N1 GPIO056/PWM3/SHD_CLK GPIO207/ADC07 D3 AUX_EN_WOWL
<48> BIA_PWM_EC TBT_RESET_N_EC GPIO001/PWM4 GPIO210/ADC08 SUS_ON_EC AUX_EN_WOWL <32>
L8 D2
<35,37> TBT_RESET_N_EC HW_ACAVIN_NB_P GPIO002/PWM5 GPIO211/ADC09 BC_INT#_ECE1117 SUS_ON_EC <48>
<57,58> HW_ACAVIN_NB DI14 1 2 RB751S40T1G_SOD523-2 N6 E2
BC_INT#_ECE1117 <51>
PANEL_BKEN_EC GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_POWERSHARE_VBUS_EN_R
1
100K_0402_5%

2 J9 G5 2
<34> PANEL_BKEN_EC GPIO015/PWM7 GPIO213/ADC11 USB_POWERSHARE_VBUS_EN_R <45>
BEEP H11 F5 T6000 PAD~D @
BIA_PWM_EC <52> BEEP SIO_SLP_WLAN# GPIO035/PWM8/CTOUT1 GPIO214/ADC12 DCIN1_EN Connect Battery
RE41

RE122 1 @ 2 0_0402_1% D9 K4
<34> BIA_PWM_EC_R BIA_PWM_EC <48> <18,32> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 PCH_PCIE_WAKE# DCIN1_EN <57>
H12 L1
<58> AC_DIS BATT_LED#_LV2 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 LAN_WAKE# PCH_PCIE_WAKE# <18,35,48>
G10 L3
<49> BATT_LED#_LV2 LAN_WAKE# <18>
2

MSCLK_R H10 GPIO135/UART1_CTS# GPIO217/ADC15

MSDATA_R G9 GPIO170/TFDP_CLK/UART1_TX H8 SSD_SCP_PWR_EN
LID_CL_SIO# GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ SHD_IO0 SSD_SCP_PWR_EN <32>
1 2 J7 T5997 PAD~D @
<51> LID_SW_IN# LID_CL_SIO# <48,49> NB_MUTE# GPIO223/SHD_IO0 SHD_IO1 1.8V_PRIM_PWRGD_OK
10_0402_5% RE45 A4 L6 T5998 PAD~D @ 0_0402_5% 2 1 RT1139
<51,52> NB_MUTE# EN_INVPWR GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 1.8V_PRIM_PWRGD/SHD_IO2 1.8V_PRIM_PWRGD_OK <33>
1 B2 L7
<34> EN_INVPWR RESET_IN# GPIO023/GPTP-IN1 GPIO227/SHD_IO2 SHD_IO3 SIO_SLP_S4# SUS_ON_EC_R
C1 M6 T5996 PAD~D @ 2 @ 1
IMVP_VR_ON GPIO024/GPTP-IN2 GPIO016/GPTP-IN7/SHD_IO3/ICT3 SUS_ON_EC_R <33>
CE31 N7 0_0402_5% RE38
<33> IMVP_VR_ON SIO_SLP_S3# GPIO031/GPTP-OUT1
0.047U_0402_25V7K K9 D6 T4948 PAD~D @
2 <18,31,33,35,51> SIO_SLP_S3# SIO_SLP_S5# GPIO032/GPTP-OUT0 BGPO0 ACAV_IN SUS_ON_EC
N8 C7 0_0402_1% 2 @ 1 RE39
<18,51> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <58> <48> SUS_ON_EC
A5 ALWON
VBUS1_ECOK VCI_OUT POWER_SW_IN# ALWON <20,33,59>
F13 D5
<57> VBUS1_ECOK AC_DISC# GPIO121/PVT_IO0 GPIO163/VCI_IN0#
E13 B5 BATBTN#
<57> AC_DISC# VBUS2_ECOK GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# USB_DET_EC#_R BATBTN# <49>
C13 D4
<57> VBUS2_ECOK GPU_PWR_LEVEL GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# USB_DET_EC#_L USB_DET_EC#_R <48>
+RTC_CELL_VBAT E12 E4
SIO_EXT_SMI#_R SIO_EXT_SMI# <23> GPU_PWR_LEVEL GPIO126/PVT_IO3 GPIO000/VCI_IN3# USB_DET_EC#_L <48>
2 @ 1
<17> SIO_EXT_SMI#_R SIO_EXT_SMI# <48> RTCRST_ON
0_0402_5% RE285 F11
SIO_RCIN# LPC_PD# <51> RTCRST_ON BATT_LED#_LV1 GPIO122/BCM0_DAT/PVT_IO1 BATT_LED#_LV3
1
100K_0402_5%

2 @ 1 F12 C6
<19> SIO_RCIN# LPC_PD# <48> <49> BATT_LED#_LV1 BC_DAT_ECE1117 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 BATT_LED#_LV3 <49> USBC_MCP23008_SMBDAT
RE50

0_0402_5% RE286 D12 0_0402_1% 2 @ 1 RE108

<51> BC_DAT_ECE1117 BC_CLK_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT USBC_MCP23008_SMBCLK DOCK_TNY_SMB_DAT <37>
D13 F3 CE1501 10P_0402_50V8J 0_0402_1% 2 @ 1 RE109
<51> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT DOCK_TNY_SMB_CLK <37>
PTP_DIS# F4
<41> PTP_DIS#
2

2 1 1K_0402_5% +3VLP_EC B1 GPIO041/SYS_SHDN# J11 +PECI_VREF

+3VLP RE43 @ 0_0402_5%2 1 RE292
+VCCST
2 1 USB_DET_EC#_R SIO_EXT_SMI# K7 SYSPWR_PRES GPIO044/VREF_VTT K13 PECI_EC_R 1 2 33_0402_1%
USB_DET_EC#_R <48> <48> SIO_EXT_SMI# RE48
<46,47> USB_DET#_R LPC_PD# GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT BATT_LED#_LV4 H_PECI <9,16>

0.1U_0402_25V6
10K_0402_5% RE54 N3 J12 RE292/CE34 close to UE3
<48> LPC_PD# ESPI_RESET# GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N BATT_LED#_LV4 <49>
1U_0402_6.3V6K

K6 A8 CE32 1 2 2200P_0402_25V7K
<19> ESPI_RESET# ESPI_ALERT# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P pin J11 (GPIO044/VREF_VTT)
1

CE34
H7 A7
<19> ESPI_ALERT# PCH_PLTRST#_5105 GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N at least 250mils
CE38

CE37 RE44 K1 A10 CE33 1 2 2200P_0402_25V7K

ESPI_CLK_5105 G7 GPIO064/LRESET# DN2_DP2A A9 REM_DIODE2_P +3VALW_5105
1U_0402_6.3V6K 100K_0402_5%
<19,49> ESPI_CLK_5105
2

2
ESPI_CS# H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE3_N CE35 1 2 2200P_0402_25V7K
@ <19,49> ESPI_CS# ESPI_IO0 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE3_P
K5 B8
<19,49> ESPI_IO0
2

ESPI_IO1 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N

8.2K_0402_5%
L4 A11 CE36 1 2 2200P_0402_25V7K
<19,49> ESPI_IO1 ESPI_IO2 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P

1
G6 B10
SIO_EXT_SCI# SIO_EXT_SCI#_R <19,49> ESPI_IO2 ESPI_IO3 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP

RE66
2 @ 1 L5 C10
<20> SIO_EXT_SCI# SIO_EXT_SCI#_R <48> <19,49> ESPI_IO3 GPIO073/LAD3/ESPI_IO3 VIN VSET_5085
0_0402_5% RE291 @ PAD~D T6003 L2 C9
SIO_EXT_SCI#_R M1 GPIO067/CLKRUN# VSET B11 I_ADP
<48> SIO_EXT_SCI#_R SYS_PWROK_R GPIO100/nEC_SCI VCP I_ADP <58>
+RTC_CELL_VBAT 0_0402_5% 2 1 RE303 G4 H3 THERMTRIP2#

VSS_ANALOG
<6,18> SYS_PWROK

2
DCIN2_EN L12 GPIO106/PWROK GPIO103/THERMTRIP2# B12 THERMTRIP1#
<57> DCIN2_EN GPIO107/nSMI THERMTRIP1# H_PROCHOT#_EC THERMTRIP1# <23,31>
H13 RE96 1 2 100_0402_5%

VSS_ADC
H_PROCHOT# <9,58,62>

VSS_PLL
MEC_XTAL1 GPIO160/PWM11/PROCHOT#
1

VR_CAP
100K_0402_5%

A1 THERMTRIP2#
MEC_XTAL2 1 0_0402_1% MEC_XTAL2_R MEC_XTAL2_R XTAL1
RE90

RE51 2 @ A3

VSS1

VSS2

VSS3
XTAL2 +VCCST
PECI_EC_R I_BATT_R I_SYS_R

0.1U_0402_25V6
1
MEC5105K_D2_TN_TR_WFBGA_169P @ C
2

A6

A13

E6

H4

J1

C4

G1

47P_0402_50V8J
CE39
1 1 1 1 2 2
USB_DET_EC#_L

CE52
2 1 RE69 2.2K_0402_5% B
<47> USB_DET#_L USB_DET_EC#_L <48>

+VR_CAP
10K_0402_5% RE89 C3320 C3321 E

3
1U_0402_6.3V6K

2200P_0402_50V7K 2200P_0402_50V7K

+VSS_PLL
QE10

2
1

3 2 2 2 MMBT3904WH_SOT323-3 3
15mil
CE70

CE71
1U_0402_6.3V6K
2

@ <9,16> H_THERMTRIP#_R

0602 review D net name THSEL_STRAP

Place near UE5

1
CE40
1U_0603_10V6K
1: Channel 1 will provide Thermistor Readings

2
REM_DIODE1_P
PCIE_WAKE# <35,42,43>
ESR <2ohms QE7 0: Channel 1 will provide Diode Readings

100P_0402_50V8J

1
MMBT3904WH_SOT323-3

100P_0402_50V8J
E C

2
@ CE45
+3VALW_5105 2
B
2
PCIE_WAKE#_R 1 RE322 PCH_PCIE_WAKE#

@ CE69
0_0402_5% 2 1 RE323 0_0402_5% 2 @ B
PCH_PCIE_WAKE# <18,35,48>

1
C E MMBT3904WH_SOT323-3

3
1
100K_0402_5%

QE15 REM_DIODE1_N
RE59

Place QE7 For FAN1 Place QE15 For OTP

Place to BOT
2

REM_DIODE2_P
JTAG_RST# VSET_5085
JTAG_RST# <48> QE5

100P_0402_50V8J

1
MMBT3904WH_SOT323-3

@ CE46

100P_0402_50V8J

0.1U_0402_25V6
E C
1

1
@ CE47
2
B
2

1
1U_0402_6.3V6K

B RE58
1

2
1
@SHORT PADS~D
JTAG1 @

100_0402_1%

CE41
C E MMBT3904WH_SOT323-3 1.33K_0402_1%

3
1

@ RE61

QE6
32 KHz Clock

2
+1.8V_3.3V_ALW_VTR3 REM_DIODE2_N
CE44

2
2

YE1
Place QE5 close to BOT Place QE6 close to BOT
2

MEC_XTAL1 MEC_XTAL2 Skin1 Skin2

2

1 2 RZ1148 1 @ 2 0_0603_5%
1 2 +1.8VALW
0.1U_0201_10V6K
2

1 1 1
C3319

32.768KHZ_9PF_9H03200033
CE42 CE43 Rest=1.33K , Tp=93 degree C
10P_0402_50V8J 12P_0201_50V8J REM_DIODE3_P
2 2 2
QE8

100P_0402_50V8J

1
MMBT3904WH_SOT323-3

@ CE49

100P_0402_50V8J
E C

1
@ CE68
2
B
2
B

2
C E MMBT3904WH_SOT323-3

3
A00_4P_0517: Change 1K for Pilot
+3VALW
QE11 REM_DIODE3_N
Setting for Thermal Design
Place QE8 close to Place QE11 close to Alpine Thermal diode mapping
10K_0402_5%

4 +3VALW_5105 +3VALW_5105 4
RE67 CE51 REV PHASE JDIMM Ridge
1

REM_DIODE4_P
RE52

+3VALW 5085 Channel Locat i on 5085 Channel Locat i on

240K 4700p X00 EVT QE12
1

+3VALW

100P_0402_50V8J

100P_0402_50V8J
2

1
MMBT3904WH_SOT323-3
100K_0402_5%

RE68
E C
130K 4700p X01 PRE DVT DP1A/DN1A FAN1 DP1/DN1 OTP
2
1

2
+1.8V_3.3V_ALW_VTR3
@ CE72

@CE50
RE67 10K_0402_5% RUNPWROK 2
B
2
RE56

@ B
62K 4700p X02 DVT1 1K_0402_5%
1
C E MMBT3904WH_SOT323-3
DP2A/DN2A Skin1 DP2/DN2 Skin2
2

3
2

33K 4700p X03 DVT2 QE9

1

BOARD_ID ME_FWP REM_DIODE4_N

3

<48> BOARD_ID RE183

2

RUN_ON#
5

UE5
8.2K 4700p A00 10K_0402_5%
QE4B Place QE12 For SSD Place QE9 close to
DP3A/DN3A JDIMM DP3/DN3 AR
2

5
Vcc

DMN65D8LDW-7_SOT363-6
4.3K 4700p X00_4P FAN2
1

PCH_PLTRST#_5105
1

NC

CE51 2 4
<17,23,31,34,35,41,42,43,49,50> PCH_PLTRST#_EC A Y DP4A/DN4A SSD DP4/DN4 FAN2
6

4700P_0402_25V7K RE70
2K 4700p X01_4P DVT2
4
G

10K_0402_5%
2

QE4A
1K 4700p A00_4P Pilot RUN_ON_EC 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1

74AUP1G07SE-7_SOT353-5 DMN65D8LDW-7_SOT363-6
3

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

WWW.AliSaler.Com
P48-EC_MEC 5105
1

BOARD_ID rise time is measured from 5%~68%. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 48 of 76
A B C D E F G H
 5 4 3 2 1

JDEG
+EC_DEBUG_VCC +3VALW_5105
JLPDE RE312 , RE313 ,
RE60 +3VS RE314 , RE315 ,
2 1 JLPDE1 RE316 , RE317 ,

10K_0804_8P4R_5%
1
1 close to BOT
49.9_0402_1% 2
2

8
7
6
5
+3VALW_5105 3
3 ESPI_IO0 <19,48>
4
+EC_DEBUG_VCC 4 ESPI_IO1 <19,48>

RP20
5 ESPI_IO2 <19,48>
5 6
6 ESPI_IO3 <19,48>

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

100K_0402_5%
7
ESPI_CS# <19,48>

1
2
3
4
JDEG1 @ 7 8 PCH_PLTRST#_EC_R RT1135 1 @ 2 0_0402_5% PCH_PLTRST#_EC
8 PCH_PLTRST#_EC <17,23,31,34,35,41,42,43,48,50>

RE63

RE64

RE298

RE65
1 9
1 2 JTAG_TDI 9 10 ESPI_CLK_5105_JLPDE RE313 1 @ 2 0_0201_5%
D 2 JTAG_TMS JTAG_TDI <48> 10 ESPI_CLK_5105 <19,48> D
3
JTAG_TMS <48>

2
3 4 JTAG_CLK
4 JTAG_TDO JTAG_CLK <48>
5 JTAG_TDO <48> 11
5 6 MSCLK GND1 12
6 MSCLK <48,49> GND2
7 MSDATA MSDATA <48,49>
7 8 HOST_DEBUG_TX
8 DEBUG_TX HOST_DEBUG_TX <48,49>
9 ACES_50521-01041-P01
9 10 CONN@
10

11 0_0402_5% 2 @ 1 RE297
GND1 <20> SBIOS_TX
12
GND2 HOST_DEBUG_TX <48,49>

MSDATA <48,49>
ACES_50521-01041-P01
CONN@ MSCLK <48,49>
+3VALW_5105
0_0402_5% 2 1 RE299 ESPI_CLK_5105_JLPDE RE301CE3319 REV

EMC@ RE62
1

1
10_0402_5%
240K 4700p i3 CPU/UMA RE301
@ 10K_0402_5%
130K 4700p UMA
62K 4700p N17P-G0

2
4.7P_0402_50V8C
EMC@ CE48
GPU_ID
33K 4700p N17P-G1 <48> GPU_ID

1
8.2K 4700p N18P-Q1

1
Place close pin CE3319
4700P_0402_25V7K
G7 4.3K 4700p N18P-Q3

2
EMI depop location
2K 4700p
1K 4700p
C C

Bat t er y Gauge LE D
BATT LED Power Button
+5VALW
PBTN_SW# +3VALW

3 SW2 1
<48> BATBTN#
2

2
DL1 LED5

2
AZ5125-02S.R7G_SOT23-3 4 2

G
27-21-T3D-CP1Q2B16Y-3C_WHITE

2
EMC@ QH3A
NTC311-EA1T-A160T_4P LED4
27-21-T3D-CP1Q2B16Y-3C_WHITE

2
1 6 BAT_LED#_LV5_D RL1 1 2 820_0402_5% BAT_LED#_LV5

S
<48> BATT_LED#_LV5

D
LED3
2N7002KDW_SOT363-6 27-21-T3D-CP1Q2B16Y-3C_WHITE
1

1
5

2
G
QH3B LED2
27-21-T3D-CP1Q2B16Y-3C_WHITE

2
4 3 BAT_LED#_LV4_D RL2 1 2 820_0402_5% BAT_LED#_LV4 LED1

S
<48> BATT_LED#_LV4

D
27-21-T3D-CP1Q2B16Y-3C_WHITE

1
2N7002KDW_SOT363-6

2
G
QH5A

1
1 6 BAT_LED#_LV3_D RL3 1 2 820_0402_5% BAT_LED#_LV3

S
<48> BATT_LED#_LV3

D
5
2N7002KDW_SOT363-6

G
QH5B
B B

4 3 BAT_LED#_LV2_D RL4 1 2 820_0402_5% BAT_LED#_LV2

<48> BATT_LED#_LV2 S

D
2N7002KDW_SOT363-6
2
G

3 1 BAT_LED#_LV1_D RL5 1 2 820_0402_5% BAT_LED#_LV1

<48> BATT_LED#_LV1
S

Q4
L2N7002WT1G_SC-70-3
EC GPIO set to OD output

Finger Print circuit <19> USB20_P7 1

CMMI21T-900Y-N_4P
1 2
2 USB20_FP_P7_CONN

R5841 1 @ 2 0_0201_5% LID_FPR#

+3VS_FP_R USB20_FP_N7_CONN <48> LID_CL_SIO#
4 3
RZ1960 1 @ 2 0_0603_5%
( Fingerprint Reader ) <19> USB20_N7 4 3
+3VALW CONN@
Current capability: 3.3V 150mA ML17 EMC@
ACES_50521-00841-P01
10
R281 +3VS_FP +3VS_FP 9 GND
+3VS_FP PBTN_SW#_R GND
2.2U_0402_6.3V6M

2 1 8
LID_FPR# PBTN_SW#_R 8
0.1U_0201_10V6K

1 7
USB20_FP_N7_CONN 7
C1079

0438.500WR 0.5A 32V UL/CSA 1 6

6
2

USB20_FP_P7_CONN
C1080

5
G

RE255 1 20_0402_5% FGND 4 5

2 PBTN_SW# 1 3 PBTN_SW#_R LID_FPR# 3 4
<41,48,51> PBTN_SW# 3
1

2 D324 D323 RE273 1 2 0_0402_5% FPR_GPIO_SCAN# 2

D

<48> FPR_SCAN# FPR_GPIO_DET# 2

Q6 EMC@ EMC@ <48> FPR_DET# RE274 1 2 0_0402_5% 1
L2N7002WT1G_SC-70-3 1
JFP
A
USB20_FP_P7_CONN A
FPR_GPIO_DET#
USB20_FP_N7_CONN FPR_GPIO_SCAN#
AZ5B75-01B.R7G_CSP0603P2Y2

AZ5B75-01B.R7G_CSP0603P2Y2
AZ5B75-01B.R7G_CSP0603P2Y2

AZ5B75-01B.R7G_CSP0603P2Y2

AZ5B25-01F_DFN0603P2Y2 AZ5B25-01F_DFN0603P2Y2
2

2
1

1
EMC@ DI13

EMC@ DI17

EMC@ MD3

EMC@ MD4

Close to JFP Fingerprint Reader CONN

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title
P49-BAT LED/BUZZER/FP
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 49 of 76
5 4 3 2 1
 5 4 3 2 1

Card Reader +3VS_CR

Pin11, Pin12 trace fixed width is 40 mils.

Pin27 trace fixed width is 30mils.
Pin10, pin14, pin18 trace fixed width is 20 mils.

0.1U_0201_10V6K

10U_0603_6.3V6M

0.1U_0201_10V6K
Pin 9 trace fixed width is 12 mils.

4.7U_0402_6.3V6M
Trace routing length < 200mils. 1 1 1

1
CR1

CR4
Close to pin27 (3V3_AUX)

CR12
Via size: Pad>=28 mils, Finished hole>=16 mils.

CR11
2
2 2 2

D D

27
11
UR1
+ODR_PWR

3V3_IN
3V3aux
1 12
<17,23,31,34,35,41,42,43,48,49> PCH_PLTRST#_EC PERST# CARD_3V3 DV33_18
2 18 1 2
<17> CLKREQ_PCIE#4 CLK_REQ# DV33_18 CR3 1U_0402_6.3V6K
Close to JCR
5
<17> CLK_PCIE_P4 REFCLKP SD_RCLK_M_R SD_RCLK_M
<17> CLK_PCIE_N4 6 15 RR2 1 @ 2 0_0402_1% JCR
REFCLKN SP1 16 SD_RCLK_P_R RR3 1 @ 2 0_0402_1% SD_RCLK_P +ODR_PWR
CR7 1 2 0.1U_0402_10V7K PCIE_PTX_C_DRX_P5 3 RTS5242 SP2 17 SD_CLK_R RR4 1 @ 2 0_0402_1% SD_CLK SD_D2 1
<19> PCIE_PTX_DRX_P5 PCIE_PTX_C_DRX_N5 HSIP SP3 SD_CMD_R SD_CMD SD_D3 DAT2
CR9 1 2 0.1U_0402_10V7K 4 19 RR5 1 @ 2 0_0402_1% 2
<19> PCIE_PTX_DRX_N5 PCIE_PRX_C_DTX_P5 HSIN SP4 SD_D3_R SD_D3 SD_CMD CD/DAT3/RSV
CR10 1 2 0.1U_0402_10V7K 7 20 RR7 1 @ 2 0_0402_1% 3
<19> PCIE_PRX_DTX_P5 PCIE_PRX_C_DTX_N5 HSOP SP5 SD_D2_R SD_D2 CMD
<19> PCIE_PRX_DTX_N5 CR13 1 2 0.1U_0402_10V7K 8 21 RR8 1 @ 2 0_0402_1% 4
HSON SP6 29 SP7_SDWP 5 VSS1
SP7 1 SD_CLK VDD/VDD1
RR10 1 @ 2 0_0201_5% 6
<20> MEDIACARD_IRQ# CD_WAKE# CLK

10U_0603_6.3V6M

0.1U_0201_10V6K
RR1 1 @ 2 10K_0201_5% 32 CR8 7
+3VS_CR
31 WAKE# Close to UR1 10P_0201_50V8J
SD_CD# 8 VSS2
SD_CD# 30 MS_INS# 2 EMC@ SD_RCLK_P 9 CARD DETECT
SD_CD# 1 DAT0/RCLK+/DAT

1
SD_RCLK_M

CR14

CR15
10
22 SD_LN1_P +SD_VDD2 SP7_SDWP_C 11 DAT1/RCLK-
SD_LN1_P 23 SD_LN1_M 12 WRITE PROTEC

2
10 SD_LN1_M 2 SD_LN0_P 13 VSS3
+SD_VDD2 DV12S 14 AV12 26 SD_LN0_P SD_LN0_M 14 D0+
DV12S SD_LN0_P 25 SD_LN0_M 15 D0-
13 SD_LN0_M 16 VSS4
SD_VDD2 24 SD_REG2 EMC@ CR16 1 2 1U_0402_6.3V6K SD_LN1_M 17 VDD2 20

E-PAD
SDREG2 SD_LN1_P D1- GND

4.7U_0603_6.3V6K

0.1U_0402_10V7K
1 2 RREF 9 28 1 2 18 21
RREF GPIO +3VS_CR D1+ GND
RR6 6.2K_0402_1% RR9 10K_0201_5% 1 1 19 22
VSS5 GND 23
GND

CR17

CR18
RTS5242-GR_QFN32_4X4

33
2 2 T-SOL_156-1051902601
If GPIO not use for LED function,
C CONN@ C
must be pull-high (Layout guide)
DV12S
4.7U_0603_6.3V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

1 1 1
CR6

CR2

CR5

Close to pin10 (AV12)

2 2 2 For GPIO control SD_WP
L2N7002WT1G_SC-70-3
QR1

SP7_SDWP 1 3 SP7_SDWP_C

S
G
2
<16> HOST_SD_WP#

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P50-Card Reader

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 50 of 76
5 4 3 2 1
 5 4 3 2 1

AUDIO Board Conn. Keyboard Controller board + DMIC

JAUDIO

1 2
1 2 AUD_PWR_EN <16,53>
<48,52> I2C0_SDA_DSP 3 4 +3VALW RZ1138 1 @ 2 0_0603_5%
3 4 NB_MUTE# <48,52>
5 6
<48,52> I2C0_SCK_DSP 5 6 SPK_DET# <20,48>
7 8
7 8 HP_JD# <52,53>
9 10
<52> I2S_BCLK 11 9 10 12 JKB
<52> I2S_MCLK 11 12
13 14 +5VALW 1
<52> I2S_LRCK 13 14 1
15 16 2
<52> I2S_IN 15 16 +5VS +3VALW_KB 2
17 18 3
<52> I2S_OUT 17 18 3
19 20 +3VS 4
21 19 20 22 5 4
23 21 22 24 <18> KB_DET# 6 5
D 23 24 <48> BC_INT#_ECE1117 6 D
25 26 <48> BC_DAT_ECE1117 7
27 25 26 28 8 7
27 28 <48> BC_CLK_ECE1117 8
29 30 9
+3VS_AUDIO 29 30 B+ White <48> BAT2_LED#
10 9
31 32 DMIC_DAT_CODEC Amber <48> BAT1_LED#
RE117 1 @ 2 0_0402_1% DMIC_DAT_CODEC_C 11 10
G1 G2 <51,52> DMIC_DAT_CODEC DMIC_CLK_CODEC DMIC_CLK_CODEC_C 11
33 34 <51,52> DMIC_CLK_CODEC RE116 1 @ 2 0_0402_1% 12
33 G3 G4 34 13 12
G5 G6 13

4.7P_0402_50V8C
@

4.7P_0402_50V8C
@

4.7P_0402_50V8C
@

4.7P_0402_50V8C
@
14
15 14
15 16
GND

1
ACES_88028-3010M 17
GND

CE81

CE82

CE73

CE74
CONN@
E-T_6710K-Y15M-31L

2
CONN@

PCH_DMIC_DAT_R RE309 1 @ 2 0_0402_5% DMIC_DAT_CODEC_C

<18> PCH_DMIC_DAT_R PCH_DMIC_CLK_R DMIC_CLK_CODEC_C
RE310 1 @ 2 0_0402_5%
Lid Switch <18> PCH_DMIC_CLK_R

27P_0402_50V8J

27P_0402_50V8J
+3VALW

1
CE3321

CE3322
2

2
UE2
APX8132AI-TRG SOT-23 3P

2 3 LID_SW_IN# DMIC_DAT_CODEC
<51,52> DMIC_DAT_CODEC
GND

VDD VOUT LID_SW_IN# <48> DMIC_CLK_CODEC

<51,52> DMIC_CLK_CODEC
1 1
1

CE15 CE16
0.1U_0201_10V6K 10P_0201_50V8J
2 2 APS CONN

3
C JAPS C
1
+3V_PCH 1 TVNST52302AB0_SOT523-3
2
<18,31,33,35,48> SIO_SLP_S3# 2 DE9
3
+3VALW 3
4
<18,48> SIO_SLP_S5# 4
5 EMC@
<18,33,48> SIO_SLP_S4#

1
6 5
<18,48> SIO_SLP_A# 6
+3VALW 7
8 7
9 8
<18,51> PCH_RTCRST# 9
10
11 10
<41,48,49> PBTN_SW# 11
12
RTC Battery With Charge Function JRTC
<6,18> SYS_RESET#
13
14
12
13
14
+RTCBATT +RTCBATT 1 15
2 1 <18,33,41> SIO_SLP_S0# 16 15
2 17 16
+RTCBATT 18 17
3 19 18
4 G1 20 GND
G2 GND
2

E&T_3806K-F02N-03R CONN@
RH67 CONN@ ACES_50506-01841-P01
1.3K_0402_5%
1

W=20mils
+3VLP

RH590
D322 W=20mils W=20mils
2 1 +3VLP_P 2 1
+RTCVCC_R
RB751S40T1G_SOD523-2 200_0201_1% 1
1

B B
EMC@
CH44 CH196
0.1U_0201_10V6K 15P_0201_50V8J
2

RF Reserved.

Default: OD EC drives GPIOs to LOW to turn off power to VCCRTC.

+RTCVCC +RTCVCC_R

follow Intel Keep old RTC

QRTC RT1133 1 2 0_0402_5% PCH_RTCRST#_R
LP2301ALT1G_SOT23-3 <18,51> PCH_RTCRST#
@
1 3
D

1
D
1 RTCRST_ON
1U_0402_6.3V6K~D

QR104 2
G

RTCRST_ON <48,51>
2
1

D321 L2N7002WT1G_SC-70-3 G
C3

R276 RB751S40T1G_SOD523-2 S
3
2 10K_0201_5% 2 1
@

2
RE143
2

100K_0402_5%
A A
1
1

D R3
@
2RTCRST_ON_R 1 2
RTCRST_ON <48,51>
G
QRTC1 S
3

1M_0402_5%~D
0.1U_0201_10V6K

DMN65D8LW-7_SOT323-3
1
22P_0201_25V8

100K_0201_1%

1
1

R277

C4
C2

Security Classification Compal Secret Data Compal Electronics, Inc.

2

@ 2
2

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P51-CONN/Lid/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 51 of 76
5 4 3 2 1
 5 4 3 2 1

HD Audio Codec
+AVDD1 +5VS_AUDIO
For EMI For EMI
3mA 10mil 3mA 10mil BLM21PG600SN1D_0805~D LA2
2 @ 1 1 2 2 1
+3VS_AUDIO +DVDDIO +3VS_AUDIO +DVDD
LA4
RA18 1 1 BLM15BB220SN1D_2P 1

CA7
0_0603_5%

CA39

CA40
1 1

10U_0402_6.3V6M
4.7U_0402_6.3V6M

0.1U_0201_6.3V6K

CA78

CA32
4.7U_0402_6.3V6M

0.1U_0201_6.3V6K
2 2
CA39,CA40 close 2
with UA1.19 2 2

D D

AGND
LA1
BLM15PX600SN1D_2P
2 1
50mil +5VS_AUDIO_PVDD2
+5VS_AUDIO
CA32,CA78 close
1 1 1 1 with UA1.7
+AVDD1
CA1

CA2

CA3

CA4
10U_0402_6.3V6M

10U_0402_6.3V6M
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
2 2 2 2

1 1

CA5

CA6
10U_0402_6.3V6M
0.1U_0201_6.3V6K
LA3
BLM15PX600SN1D_2P 2 2
2 1
50mil +5VS_AUDIO_PVDD1
+5VS_AUDIO +AVDD2
1 1 1 1 RA2
+1.8VS_AUDIO
CA8

CA9

0_0603_5%
CA10

CA11
+DVDDIO
10U_0402_6.3V6M

10U_0402_6.3V6M
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

+DVDD AGND 2 @ 1
2 2 2 2
1 1 1 1

CA12

CA13

CA17

CA14
10U_0402_6.3V6M

10U_0402_6.3V6M
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
57

19

46

51

45

24
Beep sound

7
UA1 2 2 2 2

PVDD1

PVDD2

AVDD1

CPVDD/AVDD2
T-PAD

DVDD

DVDD-IO
23 MONO_IN
11 PCBEEP RA4
<48,51> I2C0_SDA_DSP I2C DATA 25 CA15 1 2 2.2U_0402_6.3V6K 200K_0201_1%
CA120 1 2 22P_0201_25V8 12 CBN2 AGND AGND 1 2 1 2 MONO_IN
<48,51> I2C0_SCK_DSP I2C CLK CODE_CBP2 <48> BEEP
C 26 CA16 0.1U_0201_6.3V6K C
13 CBP2
<18> HDA_BITCLK_AUDIO AUDIOLINK: BCLK/IBCLK 27 CA18 1 2 2.2U_0402_6.3V6K
14 CBP1 RA7
<18> HDA_SYNC_AUDIO AUDIOLINK:SYNC/LRCK 28 CODE_CBN1 200K_0201_1%
RA93 1 @ 2 0_0402_5%~D I2S_RST_AUDIO#_R 15 CBN1 1 2 MONO_IN_R
<18> I2S_RST_AUDIO# AUDIOLINK:RESETB/MCLK <18> SPKR
39
Mic1-VrefO-R/AGPO-1 MIC1-VREFO_R <53>

1
RA6 1 2 33_0201_5% I2S_SDIN0_AUDIO_R 16
<18> HDA_SDIN0_AUDIO AUDIOLINK:SDATA-IN/DOUT 1
38 RA57
Mic1-VrefO-L/AGPP-0 MIC1-VREFO_L <53>
17 10K_0201_5% CA19
<18> HDA_SDOUT_AUDIO AUDIOLINK:SDATA-OUT/DIN 100P_0201_25V8J
37 Sleeve <53>
DMIC_CLK_CODEC 53 Mic1-R/Sleeve 2
<51,52> DMIC_CLK_CODEC

2
DMIC-CLK1 36
DMIC_DAT_CODEC Mic1-L/Ring2 Ring2 <53>
<51,52> DMIC_DAT_CODEC 54
DMIC-DATA1 35
Line1-L LINE1_L <53>
1 34 Close to UA2 Pin2
<51> I2S_LRCK GPIO_9/I2S_LRCK Line1-R LINE1_R <53>
2
3 GPIO_1/DMIC_CLK2/SPDIF_O/I2S_In JD 33
<51> I2S_OUT GPIO_6/I2S_Out HP_Out-R HPOUT_R <53>
4
5 GPIO_2/DMIC DATA2/I2S_Out JD 32
<51> I2S_IN GPIO_5/I2S_In HP_Out-L HPOUT_L <53>
8
55 I2S_Out JD/Mic JD 40
<51> I2S_MCLK GPIO_8/I2S-MCLK/SPDIF_IN LINE1-VREFO LINE1-VREFO <53>
56
<51> I2S_BCLK GPIO_7/I2S-BCLK CODE_MIC1_CAP
41
52 MIC1-CAP
<48,51> NB_MUTE# EAPD+PD#/GPIO_11 44 LDO1_CAP
47 LDO1-CAP
SPK-OUT-LP
RA12 1 @ 2 48 21 CODE_VREF1
+DVDD SPK-OUT-LN VREF1
Codec
1

10K_0201_5% 49 22 LDO2_CAP
RA68 SPK-OUT-RN LDO2-cap
@ 10K_0201_5% 50 43 CODE_VREF
SPK-OUT-RP VREF
HP_LINE1_JD 9
Analog 29 CA20 1 2 2.2U_0402_6.3V6K
2

HP JD/Line JD CPVPP
LDO3_CAP
Pin20~45
18 30
B LDO3_cap CPVREF B

1 1 1 @ 2 VDD33STB 10 31 CA21 1 2 2.2U_0402_6.3V6K

+3VALW VD33STB CPVEE
0_0402_5%
CA77

CA130
4.7U_0402_6.3V6M

0.1U_0201_6.3V6K

RA100 HD_SOC_SEL 6 42
HD-SOC SEL AVSS1
2 2 1 2
Digital 20
1 1 1 1 1 1 1 1

CA24

CA25

CA26

CA27

CA28

CA29

CA30

CA31
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
+RTCVCC_R

2.2U_0402_6.3V6M

4.7U_0402_6.3V6M
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
AVSS2
0_0402_5% Pin1~19, 46~56
RA101
2 2 2 2 2 2 2 2

ALC3266-CG_QFN56_7X7

AGND AGND AGND AGND AGND AGND

RA95 1 @ 2 0_0402_5%

RA94 1 @ 2 0_0402_1%

JACK DETECTION NETWORK MODE SELECT RA17,CA37 CA35,CA36 close Close to UA1 RA73 2 @ 1 0_0603_5%
Close UA1 Pin15 UA1 Pin53,Pin54
A00_4P_0507: From SE00001KKM0 change to SE00000FW80
+3VS_AUDIO HDA_SDOUT_AUDIO HDA_SYNC_AUDIO HDA_BITCLK_AUDIO
+DVDD DMIC_CLK_CODEC
<51,52> DMIC_CLK_CODEC 1 1 1
A RA13 +DVDD 1 2 HD_SOC_SEL 1 EMC@ CA33 RA74 2 @ 1 0_0603_5% A
100K_0201_1% RA15 100K_0201_1% EMC@ CA38 EMC@ CA34 8.2P_0201_25V8D
1

1 2 HP_LINE1_JD EMC@ CA35 10P_0201_50V8J 10P_0201_50V8J

RA14 RA17 @ 10P_0201_50V8J 2 2 2
200K_0201_1% 4.7K_0201_5% 2
<51,53> HP_JD# 1 2 GND AGND
1 1 @ 2 HD_SOC_SEL <51,52> DMIC_DAT_CODEC
DMIC_DAT_CODEC
2

RA16 100K_0201_1% 1
@ CA23 I2S_RST_AUDIO#
0.1U_0201_6.3V6K EMC@ CA36
2 10P_0201_50V8J
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
CA37 EMC@ 2017/06/21 2027/06/21 Title
10P_0201_50V8J Issued Date Deciphered Date
HD_SOC_SEL = Low ; SOC Mode 2 P52-ALC3266
HD_SOC_SEL = High ; HDA Mode

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Reserved for EMI Reserved for EMI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 52 of 76
5 4 3 2 1
 5 4 3 2 1

+1.8VALW To +1.8VS_AUDIO +5VALW and +3VALW To +5VS_AUDIO and +3VS_AUDIO

UA4
1 14
+5VALW VIN1 VOUT1 +5VS_AUDIO
2 13
D VIN1 VOUT1 D
3 12 CA124 1 2 470P_0201_25V7K
<16,51,53> AUD_PWR_EN ON1 CT1
+1.8VALW +1.8VALW 4 11
+5VALW VBIAS GND
UA3 5 10 CA125 1 2 1000P_0201_16V7K
ON2 CT2
1 8 6 9
1U_0201_6.3V6M

2 VIN VOUT 7
+1.8VS_AUDIO +3VALW
7 VIN2 VOUT2 8
+3VS_AUDIO
1 VIN VOUT VIN2 VOUT2
CA121

3 6 CZ104 1 2 15

1U_0201_6.3V6M
<16,51,53> AUD_PWR_EN EN CT GPAD
@ 1
2 4 5 2200P_0402_25V7K EM5209VF_DFN14_3X2
+3VALW VBIAS GND

CA122
9
GND
2
APE8937GN2_DFN8_2X2

Close UA4 Close UA4

+5VALW +3VALW +5VS_AUDIO +3VS_AUDIO

1U_0201_6.3V6M

1U_0201_6.3V6M
1 @ 1 @ 1 1

CA128

CA129
10U_0402_6.3V6M

10U_0402_6.3V6M
CA126

CA127
2 2 2 2

C C

Universal Audio Jack

+3VS_AUDIO

1 2
<52,53> MIC1-VREFO_R
RA19 2.2K_0402_5%~D 1 1

1
AGND
CA41 CA42 RA82
1 @ 2 680P_0402_50V7K 680P_0402_50V7K @ 100K_0201_5%
RA20 2.2K_0402_5%~D EMC@ 2 2 EMC@
1 2
<52> MIC1-VREFO_L

2
RA21 2.2K_0402_5%~D
40mil JHP1
1.2V DDR dischager
<52> Ring2 Ring2 LA5 1 2 EMC@
BLM15AX700SN1D_2P
Ring2_L 3
1
HPOUT_L RA52 1 2 2.4_0402_5% HPOUT_L_R1 LA6 1 2 EMC@ HPOUT_D_L_C +1.2V_DDR
<52> HPOUT_L
BLM15AX700SN1D_2P
5
B+

2
6 JACK_PLUG#
R5843
HPOUT_R RA51 1 2 2.4_0402_5% HPOUT_R_R2 LA7 1 2 EMC@ HPOUT_D_R_C 2
<52> HPOUT_R 33_0402_1%

1
BLM15AX700SN1D_2P
LA8 1 2 EMC@ Sleeve_L 4 7
<52> Sleeve

1
BLM15AX700SN1D_2P R5842
B
Sleeve 200K_0402_1% DMN66D0LDW-7_SOT363-6 B

40mil

3
YUQIU_PJ567-F07J1BE-C
5
D

CONN@
G

AGND S

4
DMN66D0LDW-7_SOT363-6
1

Q5A
AZ5123-01F.R7G_DFN1006P2X2

AZ5123-01F.R7G_DFN1006P2X2

AZ5123-01F.R7G_DFN1006P2X2

AZ5123-01F.R7G_DFN1006P2X2

AZ5123-01F.R7G_DFN1006P2X2
DA5 EMC@

DA2 EMC@

DA9 EMC@

DA4 EMC@

DA3 EMC@

1 1

6
CA44 CA43
680P_0402_50V7K 680P_0402_50V7K 2
D
G
2 2 <33,72> SUS_ON_EC_P
EMC@ EMC@ S
2

1
Q5B

AGND

<51,52> HP_JD#

1 @ 2 HPOUT_L
<52,53> MIC1-VREFO_R
RA75 4.7K_0402_5%~D

1 @ 2 HPOUT_R
RA27 4.7K_0402_5%~D
DA7
A A
2 1 1 2
RA28 4.7K_0402_5%~D
RB751S40T1G_SOD523-2
<52> LINE1-VREFO RB751S40T1G_SOD523-2
2 1 1 2
RA29 4.7K_0402_5%~D
DA14

CA45 1 2 10U_0402_6.3V6M LINE1_R_C RA30 1 2 1K_0402_5%~D HPOUT_L

<52> LINE1_L
LINE1_L_C HPOUT_R
Security Classification Compal Secret Data Compal Electronics, Inc.
CA119 1 2 10U_0402_6.3V6M RA31 1 2 1K_0402_5%~D 2017/06/21 2027/06/21 Title
<52> LINE1_R Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P53-Audio_Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G341P
Date: Wednesday, June 06, 2018 Sheet 53 of 76
5 4 3 2 1
 5 4 3 2 1

D D

Screw Hole
@ H9 @ H37 @ H38 @ H39 @ H40
H_2P5 H_3P2 H_3P2 H_2P5 H_2P5
CPU x 4 GPU x 2 H_2P5 H_3P2 H_3P2 H_2P5 H_2P5

1
@ H16 @ H5
H_3P9 H_3P9
H_3P9 H_3P9 @ H12 @ H41 @ H42 @ H43 @ H47

1
H_6P0N H_2P8 H_2P8 H_2P3 H_6P0N
H_6P0N H_2P8 H_2P8 H_2P3 H_6P0N

1
@ H45 @ H46
H_3P9 H_3P9
H_3P9 H_3P9 @ H17

1
H_2P1X2P5N @ H59 @ H49 @ H48
C H_2P1X2P5N H_2P9X2P1N H_2P3 H_4P1 C

1
X03_1222: for peel off issue, H_2P9X2P1N H_2P3 H_4P1

1
change footprint to CLIP_C6-PM

@ H50
CLIP_C6-PM
CLIP_C6-PM

1
NGFF x 2
@ H1 @ H2
H_2P3 H_2P3
H_2P3 H_2P3

1
EMI shilding clip x 3 @ H10 @ H11
H_2P5 H_2P1N
H_2P5 H_2P1N

1
@ H55 @ H54
CLIP_C5P5-npm CLIP_C5P5-npm
CLIP_C5P5-npm CLIP_C5P5-npm

1
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
B B
@ H23 @ H24 @ H25 FD1 FD2 FD3 FD4
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1

1
FD5 FD6
@ FIDUCAL @ FIDUCAL

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P54-Screws

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 54 of 76
5 4 3 2 1
 5 4 3 2 1

B+
+5VALW
NVDC +3VALW TDC:5.5A
DC IN power path CHARGER +5VALW TDC:11.3A +3VALW
(ISL88738) TPS51285B
D P58 D

Type-C PCH_1V TDC:6A +1VALW

Battery
(3S) SY8288RAC
P60

+1.2V_DDR
+1.2V TDC:8.2A
+0.6VS TDC:0.5A +0.6VS
G5616A

For discrete
VCCIO_0.95V TDC: 3.9A +VCCIO
NB681A
C C

+GPU_CORE +1.8ALWP TDC: 2A

VGA_CORE TDC: 40A +1.8ALWP
RT8816B (SY8286RAC)
P70

+GPU_CORE_VDDS
VGA_CORE TDC: 16A
RT8816B
+VCC_CORE TDC: 80A +VCC_CORE
NCP81215

+1.35VSDGPU
+1.35VSDGPU TDC: 11A
RT8812AGQW-GP
B
+VCC_GT TDC: 25A +VCCGT B

+1VS_GFX TDC: 1.1A +1VSDGPU

(SY8286RAC)
P67 +VCC_SA TDC: 10A +VCCSA

@ : Nopop Component
@DIS@ : Nopop Component
DIS@: POP for discrete GPU SKU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P55-Power Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 06, 2018 Sheet 55 of 74
5 4 3 2 1
 A B C D

+3VALW

CONN@ ADP100 +DC_IN

ACES_50290-00701-001
1
1

1
2

EMC@ PC114
@ PR100

0.1U_0402_25V6
2
0_0402_5%

1
3 PR102 1 2 PR101

0.1U_0402_25V6
3

EMC@ PC115
33_0402_5% 2.2K_0402_5%
4 PSID 1 2 PQ100

2
4 FDV301N-G_SOT23-3
5
5
1 3

S
D
6 PS_ID <48>

AZ5125-01H.R7G_SOD523-2
1
6 1

1
7 +5VALW
7

G
PD100
PR104

2
1
10K_0402_5%
HCB2012KF-121T50_0805

PR103 PSID-2 1 2

0.1U_0402_25V6
1

1
1 2 100K_0402_5%

EMC@ PC106
HCB2012KF-121T50_0805
EMC@ PL105

PL106

BLM15AG102SN1D_2P

1
EMC@ PL104

EMC@
C
2 PSID-1 2 PQ101
EMC@

B MMBT3904W H_SOT323-3
2

1
E

3
PR105
15K_0402_5%

place near connect

2
VBATT EMC@ PL107 BATT++
HCB2012KF-121T50_0805
1 2
PL108
HCB2012KF-121T50_0805
1 2
1

1
0.01UF_0402_25V7K
100P_0402_50V8J

100P_0402_50V8J
1000P_0402_50V7K

EMC@
1

1
PC108

PC109

PC110

PD101 PD102
PC107

TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
2 2
2

EMC@ EMC@
2

3
EMC@
EMC@

EMC@
EMC@

PBAT_CHARGER_SMBCLK <48,58>
CONN@ BAT100
ACES_50290-01201-P01
1 PBAT_CHARGER_SMBDAT <48,58>
1 2
2 3 PBAT_PRES# <48,58>
3 4
4 5 1 2 PR111 PR112
5 6 PR106 1 2100_0402_5% 100_0402_5% 10K_0402_5%
6 7 PR108 100_0402_5% 1 2 1 2
7 +3VALW
8
8 9
9 10
10 11
11 12
12

Battery
3 (3S2P) 97W 3

(3S1P) 56W
JIMBTY battery connector
SMAR T
Battery:
01.BAT+
02.BAT+
03.BAT+
04.BAT+
05.CLK_SMB
06.DAT_S MB
07.BATT_PRS
08.SYS_PR S
09. GN D
10. GN D
11. GN D
12. GN D

4 4

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, P56-PWR_DCIN / BATT CONN / OTP

WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
Smart Adapter circuit (39.1) LA-F541P 0.1(X00)

Date: W ednesday, June 06, 2018 Sheet 56 of 74

A B C D
 5 4 3 2 1

PVT_10
PD200
S SCH DIO 5A 100V 15UA 0.88V TO227-3
D 2 D
DC_IN+ Source 3
1
+DC_IN
S1 S2 +SDC_IN
PQ200 +DC_IN_SS PQ201
AON7409_DFN8-5 AON7409_DFN8-5
DCIN_AC_Detector 1 1
+SDC_IN
2 2

0.022U_0603_50V7K

1
3 5 5 3
PR200

PC202
PR201

499K_0402_1%
1
300K_0402_5%

1
0.022U_0603_50V7K

3
S

2
2
G
+3V_VC PR202
+DC_IN

100K_0402_5%

10U_0805_25V6K

2
PC201
@ PC200 +3V_VC 1M_0402_5%

1
D
0.01U_0402_25V7K~D +3V_VC

1
PC203
1 2 PR204
+3V_VC

PR203
PQ202 100K_0402_5%

PR205

DMN65D8LDW-7_SOT363-6
49.9K_0402_1%
2

1
AO3409_SOT23-3
PR207 PVT_01 PR206
1.8M_0402_1% 100K_0402_5%
1

6
1 2

1
PR208 PVT_01 @ PR210

2
PQ203A
1K_0402_1% PR209 0_0402_5%
240K_0402_1%

DMN65D8LW-7_SOT323-3
1M_0402_5% 2 1 2
102K_0402_1%
1

PC204 @ PR213
2

1
PR211

2 1 D
+3V_VC 0_0402_5%

1
PQ204
PR212

2 1 2

DMN65D8LDW-7_SOT363-6
0.1U_0402_10V7K G
PU200A PVT_01 S

DMN65D8LW-7_SOT323-3
2

3
LM393DGKR_VSSOP8 @ PR214 PU201 VBUS2_ECOK <48,57> PVT_01

5
3 0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
P

3
(>17.6V) + 1 1 2 1 D

P
O HW_ACAVIN_NB <48,57,58> <48,57,58> HW_ACAVIN_NB B

PQ205
2 4 1 2 2 @ PR218
G

- O

PQ203B
1 2 2 G 0_0402_5%
1200P_0402_50V7K
100P_0402_50V8J~D

220P_0402_50V8J~D
24K_0402_1%

G
A @ PR216 PR217 5 1 2
S AC_DISC# <48,57>
84.5K_0402_1%
1

3
@ PR215 0_0402_5% 100K_0402_5%
1

2
PR219

PC205

PC206

0_0402_5%
1

4
PR220

PC207

PVT_01 PVT_01
2

PQ206
2

@ PR221 DMN65D8LW-7_SOT323-3
2

0_0402_5%
1 2 3 1

D
<48> DCIN2_EN

PVT_01

G
100K_0402_5%
1

1 2

1
PR222
PR223 @
0_0402_5%
PR224

2
100K_0402_5%

2
+3VALW +3V_VC

PVT_10
PD201
S SCH DIO 5A 100V 15UA 0.88V TO227-3
C 2 C
1
3
@ PJP200
1 2
1 2
JUMP_43X118
EMI Part S4 S5
EMC@ PL200 PQ207 S3
HCB2012KF-121T50_0805 AON7409_DFN8-5 PQ208 +VBUS_DC_SS PQ209
1 2 1 AON7409_DFN8-5 AON7409_DFN8-5
+TBTA_Vbus_1 2 +AC_IN 1 1
1 2 5 3 2 2
+VBUS_1 3 5 5 3 +SDC_IN

1500P_0402_50V7K
0.47U_0603_25V6K
100P_0402_50V8J

1
PL201
EMC@
100K_0402_5%

499K_0402_1%

HCB2012KF-121T50_0805 PR225 PR226

1000P_0402_50V7K

1500P_0402_50V7K

499K_0402_1%
1

1
300K_0402_5% 300K_0402_5%

499K_0402_1%
1

1
EMC@ PC208

PR227

EMC@ PC209

3
PC211

PR229

PC212
S S
+3V_VC

2 PR230
2

2
PC210

PR228

2 2
G G
2

2
+3V_VC
2

2
D D
2

1
DVT1 PR232
PR231 100K_0402_5% PR233
1

100K_0402_5% 100K_0402_5%

49.9K_0402_1%
6 2

1
PQ210 PQ211

2
PR235
PR234 AO3409_SOT23-3 AO3409_SOT23-3 PVT_01 PR236
PC1209 can't over 1000P

49.9K_0402_1%
1
330K_0402_1% 100K_0402_5%
2

6
PR237
EN_PD_HV_1# PQ212A
2 DMN65D8LDW-7_SOT363-6 @ PR238

DMN65D8LDW-7_SOT363-6
3 2

2
PQ214A
PVT_01 0_0402_5%

3
2 1 2

2
PQ212B @ PR239 PQ213B
<37,57> EN_PD_HV_1 0_0402_5%

1
5 1 2 5
<48,57> VBUS1_ECOK
1

+3V_VC
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6

DMN65D8LDW-7_SOT363-6
PQ213A
S3 OVP
+TBTA_Vbus_1

4
2 PVT_01
@ PD202 PR240 PVT_01

3
RB751V-40_SOD323-2 49.9K_0402_1% PC213
160K_0402_1%
1

1
1 2 +3V_VC 0.1U_0402_10V7K PR242 @ PR241 PQ214B @ PR243
PR245 2 1 +3V_VC 0_0402_5% 100K_0402_5% 0_0402_5%

2
PR244

0_0402_5% 5 1 2
AC1_DISC# <37,57,58>
1 2 PR247 @ PR248 DMN65D8LDW-7_SOT363-6
2

2
1M_0402_5% 0_0402_5%
1

4
PR246 2 1 1 2
1

100K_0402_5% @ PR250 5 PU202

PR251 0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
DMN65D8LDW-7_SOT363-6
PQ215A

@ PR249 100K_0402_1% 1 2 1
P
<37,57> EN_PD_HV_1
1

330K_0402_1% +3V_VC 2 B 4
2

1 2 2 O
PVT_01 (From TI GPIO1)
2

PU203A A
8

LM393DGKR_VSSOP8 @ PR253 PQ215B @ PR252

3

3 0_0402_5% 0_0402_5%
P

1200P_0402_50V7K
100P_0402_50V8J

+ 1 1 2 5
0.01UF_0402_25V7K

2 O PVT_01
DMN65D8LDW-7_SOT363-6
100K_0402_1%

100K_0402_1%

100P_0402_50V8J
1

OVP is setting to 5.6V -

1

4
PC214

PC216
1

1
PR254

PR255

PC215

PC217

PVT_01
PQ217
2

@ PR256 DMN65D8LW-7_SOT323-3
2

0_0402_5%
2

1 2 3 1
S

<48> DCIN1_EN

PVT_01
G

100K_0402_5%
1

1 2
100K_0402_5%

PVT_01
6

PR259

PR258 @
PR257
@

@ PR260 PT202 0_0402_5%

DMN65D8LDW-7_SOT363-6
PQ216A

0_0402_5% PAD~D
LPS_PROTECT#
2

2 1 2
2

1
1

(From EC)
1

PR261
10K_0402_5% 1 2
EN_PD_HV_1 <37,57>
@ PR262
2

B +3VALW +3V_VC B
0_0402_5%

+3V_VC +3V_VC

3V LDO
2

@ PR265
PVT_01 100K_0402_5% @ PR267
@ PR268 100K_0402_5% +3V_VC
LDO_IN
1

0_0402_5% PQ222
1

1 2 PD203 @ PR289 S TR AO7401 1P SC70-3

<48,57> VBUS2_ECOK
RB520SM-30T2R_EMD2-2 PU204 0_0805_5% +3V_LDOP
2

1 2 2 1 1 5 1 2 1 3

S
<48,57> VBUS1_ECOK
PR270 +DC_IN VCC VOUT
CMOUT <58>
1U_0402_16V6K

@ PR269 100K_0402_5% 2 PR288

GND
DMN65D8LDW-7 2N SOT363-6

0_0402_5% PVT_01 1M_0201_1%

G
AC_DISC# <48,57>
1

2
@ PR272 PD204 PC220 3 4 1 2
PC223

10K_0402_1%
1

+3V_VC D RB520SM-30T2R_EMD2-2 1U_0603_25V6K NC EN

0_0402_5%
1
PQ220A

1 2 2 2 1 1 2 PC218
+VBUS_1
2

G 0.01U_0201_16V7
PR263

RT9069-33GB_SOT23-5
1500P_0402_50V7K
DMN65D8LDW-7 2N SOT363-6

DMN65D8LDW-7 2N SOT363-6

1 2
2

3
PQ220B

+3V_VC D D D PVT_01 S
1

5 2 5 PR276
2

PQ226
PQ221A

PC219

PR273 G G G 300K_0402_5% S TR AO7401 1P SC70-3 @ PR266

100K_0402_5% 1 2 0_0805_5%
2

1 3 1 2
+3V_VC
D

S
1U_0402_16V6K

S S S
+3VALW
1

DMN65D8LDW-7 2N SOT363-6
PQ221B

@
DMN65D8LW-7_SOT323-3
1
300K_0402_5%

PR274 PROCHOT#_ISL88738 <58>

1
DMN65D8LDW-7 2N SOT363-6

PC222

+3V_VC PR275 PVT_01

PR280

100K_0402_5%
G
6

2
PQ223A

@ PQ225

@ PR277 D D D 100K_0201_1%
DMN65D8LW-7_SOT323-3
1

0_0402_5% 2 D 2 5 1 2
<37,57> EN_PD_HV_1
2
DMN65D8LDW-7 2N SOT363-6

PQ224

1 2 G +3V_VC 2 G G
2

G S PQ219B
0_0201_5%
3

3
PQ223B

D S PR279 S S
PR290
1

1 2 5 RC delay 110ms 2N7002KDW_SOT363-6

0_0201_5%

<37,57,58> AC1_DISC# 100K_0402_5%

G
@PR295

@ PR278 PR282
1

0_0402_5% S 100K_0402_5%
4

PVT_01 @ PR283
1

0_0402_5% D PR271
6

1 2 2 PQ227A 0_0201_5% D
PVT_01 G DMN65D8LDW-7 2N SOT363-6 1 2 2 PQ219A
3

D <59> ALW_PWRGD_3V_5V G 2N7002KDW_SOT363-6

0.1U_0201_10V6K

1 2 5 S
<48,57,58> HW_ACAVIN_NB
1

1
PC221

G PQ227B S
1

@ PR284 DMN65D8LDW-7 2N SOT363-6

0_0402_5% S
4

1 2

@ PR285
0_0402_5%

A A

Title
P57-PWR_Switch
Si ze Document Number Rev
Custom LA-F541P 0.1(X00)

Dat e: Wednesday, June 06, 2018 Sheet 57 of 74

5 4 3 2 1
 A B C D

+PWR_SRC_AC
+SDC_IN
PR1900
0.01_1206_1% EMC@ PL1900
+CHG_SRC_20V
1UH +-20% 6.6A 5X5X3 MOLDING, A.3
1 4 2 1

1
1 1

2 3 @ PD1904
SMF4L22A SOD123FL-2

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
2

1
PC1900

PC1901

PC1902

PC1903

PC1904

PC1905

PC1906

PC1907

PC1908
Reserve for Acoustic

2
1

1
TVS diode

100U_D_20VM_R55M
PR1901 PR1902
1
2_0603_1% 2_0603_1%
Intersil suggested +
Low Noise SE00000X210 *7

PC1909
2

2
2
PC1910
4.7U_0402_6.3V6M
1 2 B+

1U 25V K X5R 0402

1U 25V K X5R 0402

1

1
PC1911

PC1912
2

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6
PC1923

PC1924
2

5
PC1913 PQ1902 PQ1900

2200P_0402_50V7K
1

1
+SDC_IN +SDC_IN

PC1914

PC1915

PC1916

PC1917

PC1918

PC1919

PC1920

PC1921

PC1922
@ PR1903 AON6380_DFN5X6-8-5 AON6380_DFN5X6-8-5 PQ1901
PD1900

@EMC@
0_0603_5% 0.22U_0603_25V7K

@EMC@
1
2 1 1 2 ADP_ISL88738
AON6314_DFN5x6-8

2
UG1_ISL88738 4 UG1_ISL88738 4
@ @ @ @
UG2_ISL88738

1
4
1

RB751V-40_SOD323-2 PVT_01 PR1905

PR1904 2.2_0603_5%
442K_0402_1%

3
2
1

3
2
1
2

1
2
3
2
Low Noise SE00000X210 2
2

ACIN_ISL88738

CSIP_ISL88738

CSIN_ISL88738

BOOT1_ISL88738

UG1_ISL88738

LX1_ISL88738

LG1_ISL88738
PD1902
LX1_ISL88738
1

B+ 2 1
1

PC1925 PR1906 PR1908

LX2_ISL88738
0.1U 25V K X5R 0402 100K_0402_5% 4.7_0402_5%
2 VDD_ISL88738
2

RB751V-40_SOD323-2 1
2

PR1907 PQ1903 Package: 11.5x 10 x 4

2

PU1900

5
16

15

14

13

12

11

10

33
1_0805_5%~D Idc=18A, Isat=36A

AON6314_DFN5x6-8
9
S IC ISL88738HRTZ-T TQFN 32P PWM
PC1926 1U_0603_25V6
DCR=2.9mohm (Typ.) 97Whr/(3*3.7)*1.5=12.8A VBATT

BOOT1

UGATE1

PHASE1

LGATE1
CSIN

PAD
ADP

CSIP

ASGATE
DCIN_ISL88738
1

1 2 PC1927 12.8*12.8*5m=0.82W
1U_0402_6.3V6K PQ1905
17 8 VDDP_ISL88738 2 1 LG1_ISL88738 4 4 LG2_ISL88738 PR1910
PL1901 AON7405_DFN8-5
DCIN VDDP 1 4 3S_BATT+ 1
2 1 VDD_ISL88738 18 7 LG2_ISL88738 1 2 2
VDD LGATE2
2

@ PR1912 0_0402_5% 2 3 3 5
1 2 ACIN_ISL88738 19 6 LX2_ISL88738

10U_0603_25V6M

10U_0603_25V6M
PC1928 PR1911 1UH_MMD-10DZ-1R0M-X1A_18A_20%

3
2
1

1
2
3
1U_0402_6.3V6K @ PR1909 0_0402_5% ACIN PHASE2 0.005_1206_1%
100K_0402_1% UG2_ISL88738

1
1 2 20 5

PC1930

PC1931
OTGEN/CMIN

4
@ PR1913 0_0402_5% OTGEN/CMIN UGATE2 PR1914 PC1929 PQ1904
ACAV_IN1 BOOT2_ISL88738
1

1
PR1915
1 2 21 4 2 1 2 1

@EMC@ PR1916

2200P_0402_50V7K
<48,56> PBAT_CHARGER_SMBDAT

2
SDA BOOT2

4700P_0402_25V7K
4.7_1206_5%

1
4.7_1206_5%
@ PR1917 0_0402_5% AON6380_DFN5X6-8-5

PC1932
1

1
PQ1906 1 2 22 3 2.2_0603_5% 0.22U_0603_25V7K

CHG_BGATE

PC1933
<48,56> PBAT_CHARGER_SMBCLK SCL VSYS
1

D
DMN65D8LW-7_SOT323-3 PR1918
CSOP_ISL88738
OTGPG/CMOUT

2
2 1 2 23 2

@EMC@
154K_0402_1% <9,48,62> H_PROCHOT#

SNUB_CHG2 2

2
PROCHOT# CSOP
AMON/BMON

<48> AC_DIS G
CSON_ISL88738
1

24 1
BATGONE

@ PR1919 0_0402_5% PVT_01

SNUB_CHG1
S <57> PROCHOT#_ISL88738
3

ACOK BGATE CSON @ PR1922

CMOP
PROG

PSYS

VBAT

@ PR1921 0_0402_5% 0_0402_5% Low Noise SE00000X210

1 2 ACOK_ISL88738 1 2
PR1920 B+
2

1M_0402_1% PVT_01 @ PR1923 PC1934

25

26

27

105K_0402_1% 28

29

30

31

32

@EMC@ PC1937
@EMC@ PC1936

680P_0402_50V7K
100K_0402_1% 10P_0402_50V8J

680P_0402_50V7K
1

1
PR1924 1 2 1 2 1 2
2 PR1925 1

<48,56> PBAT_PRES# 100K_0402_1%

1 2 @ PC1935 0.1U_0402_25V6
CHG_BGATE
VBAT1_ISL88738

2
1
PR1927 1K_0402_5%

3 PR1926 3

100K_0402_1%
1 2
+3VALW
@ PR1928 0_0402_5%
2

1 2
<57> CMOUT
PVT_01 COMP_ISL88738

1 2
0_0402_5%
1
@ PR1930

0_0402_5%
560P_0402_50V7K

@ PC1938 1U 25V K X5R 0402

1
0_0402_5%

10K_0402_5%
0.1U_0402_25V6
1

1 2
@ PC1939

0_0402_5%

1
PC1940
2

PC1942 PR1931 1_0402_1%

2

@ PR1929

PVT_01
0.012U_0402_16V7K

2
1
PC1941

1U_0402_25V6K PR1935 1_0402_1%

2

1 2
@ PR1933
2
@ PR1932

PR1934
2

PVT_01
1 2
@
PVT_01 P_SYS <48,62>
PC1943 0.22U_0402_25V6K

@ PR1936 +3V_VC
0_0402_5%
1 2

I_BATT <48>
PVT_01 PD1903 PC1944 I_ADP <48> VBATT
@ PR1937 BAT54CW_SOT323-3 0.1U_0402_10V7K
0_0402_5% 1 2 2 1
1 2 3 Close to EC ADP_I pin
<37,57> AC1_DISC#
1 2 PU1901 PR1938
2

@ PR1939 1PR1943 100K_0402_1% MC74VHC1G08DFT2G SC70 5P AND 100_0402_1%

5

0_0402_5% @ PR1940 @ PC1945

4
1 2 2 1 0_0402_5% 0.1U_0402_25V6
4
P

<48,57> HW_ACAVIN_NB <48> ACAV_IN

1

B 4 1 2
ACAV_IN1 1 2 2 Y
A
1
G

PVT_01
@ PR1941 0_0402_5% PR1942
3

100K_0402_1%
PVT_01
2

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P58-PWR_CHARGER(ISL88738)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P
Date: Wednesday, June 06, 2018 Sheet 58 of 74

A B C D

WWW.AliSaler.Com
 A B C D E

+3VLP

PVT_01

1
PR400 @
0_0402_5%

2
4.7U_0603_6.3V6M

1
PC400

2
1 1

@ PC401 @ PC402
100P_0402_50V8J 100P_0402_50V8J
B+ 1 2 1 2

160K_0402_1%
@EMC@ PL403 PR401
PR402
HCB2012KF-121T50_0805 71.5K_0402_1%
1 2 1 2 1 2

@EMC@ PL402 PR404

B++
HCB2012KF-121T50_0805 B++
PR403 102K_0402_1%
1 2 1 2 FB_3V FB_5V 1 2

@ PJP400 102K_0402_1%
JUMP_43X118

10U_0603_25V6M
1 2
PR406

2200P_0402_50V7K
1 2 1 2

0.1U_0402_25V6
1 2
100U_D_20VM_R55M

2200P_0402_50V7K

1
10U_0603_25V6M

PC409
PC407

PC408
1 PR405
0.1U_0402_25V6
15P_0402_50V8J

PQ400

5
PC405

21.5K_0402_1%
13.3K_0402_1%
1

5
+ AON7408L_DFN8-5
PC406
PC420

PC403

PC404

PQ401

2
AON6380_DFN5X6-8-5
PVT_01
2

2
@ PR408 4
<57> ALW_PWRGD_3V_5V

1
4 0_0402_5% PVT_01
3V/5VALW_EN 1 2 21 EMC@ EMC@
Package: 6.6x 7.3 x 3

CS2

VFB2

VREG3

VFB1

CS1
TP @ PR409
EMC@ EMC@ EMC@ Idc=6.5A, Isat=9.5A @ PR407 0_0402_5%

3
2
1
2 DCR=18mohm (Typ.) 1 0_0402_5% 6 20 1 2 3V/5VALW_EN 2
2
3
1 2 PVT_01 EN2 EN1
PR410
1 2 7 19 1 2
PL400
+3VALWP PR428 PGOOD VCLK PL401
3.3UH_PCMB063T-3R3MS_6.5A_20% 100K_0402_5% PU400 200_0402_1% 2.2UH_PCMB103T-2R2MS_13A_20% +5VALWP
1 2 LX_3V 8 18 LX_5V 1 2
+3VALWP SW2 TPS51285BRUKR_QFN20_3X3 SW1 PR412 PC411
PC410 PR411 2.2_0603_5% 0.1U_0603_50V7K
PQ402

1
1 2 BST1_3V 1 2 BST_3V 9 17 BST_5V 1 2 BST1_5V 1 2

4.7_1206_5%
VBST2 VBST1
1

AON7506_DFN3X3-8-5

PR414
R4=(Vo-2)/2*R5 EMC@ PR413 0.1U_0603_50V7K 2.2_0603_5% PQ403 EMC@
Valtage setting: Vo=3.4V

5
4.7_1206_5% UG_3V 10 16 UG_5V AON6796_DFN5X6-8-5
150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M
DRVH2 DRVH1

VREG5
1 1 1

DRVL2

DRVL1

2
2

VO1
VIN
+ 4 + +
PC412

PC456

PC413
SNUB_5V
SNUB_3V

11

12

13

14

15
2 2 2
LG_3V LG_5V

680P_0603_50V7K
1
2
3

.1U_0402_16V7K
1

1
PC416
@ PC415

3
2
1

PC417
PC414 .1U_0402_16V7K
1

EMC@ EMC@
2

2
680P_0603_50V7K @

2
2

3 3

4.7U_0603_6.3V6M
PVT_01

0.1U_0402_25V6
1
Package: 10.3 x 11.2 x 3.0

PC419
PC418
PR415 @
PR326 0_0402_5%
Idc=13A, Isat=16A
2.2K_0402_5% DCR=8mohm (Typ.)

2
1 2 3V/5VALW_EN
<20,33,48> ALWON 2
R1=(Vo-2)/2*R2
Valtage setting: Vo=5.14V
B++
4.7U_0603_6.3V6M
1

@ PC335

@ PJP402 @ PJP403
2

1 2 +3VALW 1 2
+3VALWP +5VALWP +5VALW
PAD-OPEN 4x4m PAD-OPEN 4x4m

3.3VALWP 5VALWP
TDC 5.5A TDC 11.3A
Peak Current 7.7A Peak Current 12.6A
OCP current 9.35A OCP current 19.2A
4 4

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

3V/5V controller(35.1), Support component(35.2) BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P59-PWR_3.3VALWP/5VALWP
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
0.1(X00)
LA-F541P
Date: Wednesday, June 06, 2018 Sheet 59 of 74
A B C D E
 5 4 3 2 1

D +1VSP D

TDC 6A
Peak Current 8.2A
OCP current 12A(fix)

+3VALW

B+_1V

1
PR500 Package: 4.9 x 5.2 x 3.0
100K_0402_5%
PVT_01 Idc=7A, Isat=11A
B+ EMC@ PL500
PU500
@ PR521 keep short pad, DCR=13mohm (Typ.)
HCB2012KF-121T50_0805 0_0402_5% snubber is for EMI only.

2
1 2 2 9 1 2 +1VALW_PG <33> PC502
IN PG 0.1U_0201_10V6K
10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

3 1 BST_1V 1 2 BST_1V_R 1 2
2200P_0402_50V7K

IN BS
1

1
@ PR501 PR502 PC504
PC500

PC501

PC503

PC513
PVT_01 4 6 LX_1V 0_0402_5% 4.7_1206_5% 680P_0603_50V7K
IN LX
2

2
@ PR1950 5 19 PVT_01 1 2SNB_1V 1 2 +1VSP +1VALW
0_0402_5% IN LX
EMC@

@EMC@
@EMC@

<20,33,70> PCH_PRIM_EN 1 2 7 20 PL501 @EMC@ @ PJP500

GND LX
8 14 1 2 1 2
GND FB 1 2
C C
@ PR503 18 17 LDO_3V 1UH_PCMB053T-1R0MS_7A_20% JUMP_43X118

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
GND VCC

1
0_0402_5% 1

90.9K_0402_1%

1
<33,70> 1.8V_PRIM_PWRGD 1 2 EN_1V 11 10

PR504

220P_0402_50V8J
EN NC PC505

PC507

PC508

PC509

PC510
PC506
13 12 2.2U_0201_6.3V6M
Rup

2
ILMT NC
1

@ PC511 2

2
PR505 0.1U_0402_25V6 15 16
1M_0201_5% +3VALW BYP NC
2

21
PAD
FB = 0.6V
2

EN :H>0.8V ; L<0.4V +3VALW

SY8288RAC_QFN20_3X3
1

VFB=0.6V

1
PC512
EN pin don't floating
1

1U_0402_6.3V6K PR507
Vout=0.6V* (1+Rup/Rdown)
2

If have pull down resistor at HW side, Rdown 121K_0402_1%

PR506
please delete PR601. 100K_0201_5%
Vout=1.05V

2
2

ILMT_1V
1

@ PR508
0_0201_5%
2

B B

The current limit is set to 6A, 8A or 12A when this pin

is pull low, floating or pull high

PWR.Plane.Regulator(35.25), Support component(35.26)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P60-PWR_PCH_1V(SY8288RAC)

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P
Date: Wednesday, June 06, 2018 Sheet 60 of 74
5 4 3 2 1
 5 4 3 2 1

B+

+1.2V_MEN_P
PL601 EMC@
HCB2012KF-121T50_0805
1 2

@PJP600
JUMP_43X118 @ PJP601
1 2 1.2V_B+ PC600 PR600 +VLDOIN_1.2V 2 1
D
1 2 +0.6VS D
0.22U_0603_16V7K 2.2_0603_5% +0.6VSP
1 2 1 2 BOOT_1.2V PAD-OPEN1x1m

2200P_0402_50V7K
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6
@ PJP602

1
DH_1.2V 1 2

PC615

PC601

PC602

PC603

PC604
PQ600
PAD-OPEN 3x3m
2

5
AON7406L_DFN8-5 SW _1.2V

10U_0603_25V6M

10U_0603_25V6M
1

1
PC605

PC606
16

17

18

19

20

2
4

DH

VLDOIN
LX

BST

VTT
21
PAD
+1.2V_MEN_P

EMC@ EMC@
DL_1.2V 15 1
+1.2V_DDR DL VTTGND

1
2
3
@ PJP603 PL600 14 2 +V_DDR_REF
1UH_PCMB063T-1R0MS_12A_20% PR601 PGND VTTSNS
PAD-OPEN 4x4m
2 1 1 2 7.87K_0402_1%
1 2 CS_1.2V 13 PU600 3
CS GND
PC607 G5616ARZ1U_TQFN20_3X3
1U_0603_10V6K
1 1 1 2 12 4
4.7_1206_5%

VPP VTTREF

5
PR603
PR602
330U_D1_2VY_R9M

+ 5.1_0603_5%
VDD_1.2V +1.2V_MEN_P
PC608

C 1 2 11 5 C
+5VALW VCC VDDQSNS

1
PC609
1 SNUB_1.2V 2

VDDQSET
.1U_0402_16V7K
EMC@

PGOOD
4 PC610

2
1U_0603_10V6K

TON

S5

S3
2
680P_0603_50V7K

1
2
3

10

6
PC611

+5VALW PR604
16.2K_0402_1%
2

PQ601 @ PR651 1.2V_FB 1 2

EMC@

0_0402_5%
AON7534_DFN3X3-8-5 1 2
<33> +1.2V_DDR_PG @ PC612
PVT_01 22P_0402_50V8J
PR609 1 2
1 2 +1.2V_PW ROK
+3VS PR605
Package: : 6.6 x 7.3 x 3.0 100K_0402_5% 1M_0402_1%
Idc=12A, Isat=15A @ PR606 @
1.2V_B+ 1 2
DCR=6.7mohm (Typ.) 0_0402_5%
1 2 S5_1.2V
<33> 1.2V_DDR_EN

1
PR607

1
PVT_01 @ PC613 27K_0402_1%
0.1U_0402_10V7K

2
PVT_01
B B
@ PR608
0_0402_5%
1 2
<9> SM_PG_CTRL

1
@ PR610
0_0402_5% @PC614
2 1 0.1U_0402_10V7K
<33,73> RUN_ON_P 2

FB sense trace

0.6Volt +/- 5%
1.2Volt +/- 5% TDC 0.5A
TDC 8.2A Peak Current 0.7A
Peak Current 15.4A OCP Current 0.85A
OCP current

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P61-PWR_+1.2V_MEN/+0.6V_DDR
DDR controller(35.3), Support component(35.4) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number Rev
0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P
Date: W ednesday, June 06, 2018 Sheet 61 of 74
5 4 3 2 1
 5 4 3 2 1

Place close to Choke in VCCSA first phase circuit

PR1100 PR1101
12K_0402_1% 7.5K_0603_1%
PC1100 PH1100 1 2 1 2 1 2 +VCCST

0.1U_0402_10V7K
<65> CSN_1PH SW_1PH <65>
2200P_0402_50V7K

1
1 2

PC1102
100K_0402_1%_TSM0B104F4251RZ

100_0402_1%
1

1
PVT_01 PR1103

499_0402_1%

45.3_0402_1%

45.3_0402_1%
1 2

PR1104

PR1105

PR1106

PR1107
@ PR1108 10_0402_1%

2
0_0402_5% PR1109 PC1101
1 2 1 2 VSN_1PH 0.01UF_0402_25V7K
<11> VSSSA_SENSE

2
@

2
2
2.55K_0402_1% 2 1 1 2 @
PC1103

1
CSP_1PH
1000P_0402_50V7K PR1111 PC1104 PC1105 PR1113

1
1.74K_0402_1% 3300P_0402_25V7K 1000P_0402_50V7K PR1112 100_0402_1%

1
PVT_01 1 2 1 2 VSP_1PH CSN_1PH_R PC1106 28K_0402_1% 81215_VR_HOT
1 2
<11> VCCSA_SENSE H_PROCHOT# <9,48,58>
PR1115 +3VS
D @ PR1110 2.21K_0402_1% PC1107 470P_0402_50V8J D

2
0_0402_5% 1 2 1 2 1000P_0402_50V7K 81215_SCLK 21
VR_SVID_CLK <9>
1 2 PR1116

IMON_1PH
PWM1_1PH/ICCMAX1 <65>

1
PC1108 PVT_01 49.9_0402_1%
1000P_0402_50V7K PR1119 81215_ALERT 1 2
VR_SVID_ALERT# <9>
9.31K_0402_1% PR1117 @ PR1118
1 2 10K_0402_1% PR1123 0_0402_5%
38.3K_0402_1% 81215_SDIO 1 2
VR_SVID_DATA <9>

2
PR1122 PC1109 PR1120 10_0402_1%
IMVP_VR_PG <18>
PVT_01 1.5K_0402_1% 0.015U_0402_25V7K 1 2
@ PR1124 1 2 1 2
0_0402_5% 81215_SCLK
1 2 VSP_4PH 81215_ALERT 1 2
<10> VCC_SENSE 81215_SDIO VR_ON <33>
1 2

2
@ PR1125
PC1111 PC1110 0_0402_5%
1000P_0402_50V7K PR1127 100P_0402_50V8J PVT_01

1
1.3K_0402_1% PVT_01
PVT_01 1 2 1 2 VSN_4PH VSN_1PH @ PR1130
<10> VSS_SENSE
0_0402_5%

ILIM_1PH
COMP_1PH
@ PR1126 1 2 VCCGT_SENSE <12>
0_0402_5% 1 2 VSP_1PH
PC1113

1
PC1112 1000P_0402_50V7K
2200P_0402_50V7K PR1131
1.37K_0402_1% PVT_01

2
1 2 1 2
VSSGT_SENSE <12>
PVT_11
@ PR1132
1 2 0_0402_5%
PC1115 PR1134 PC1116 PU1100

53

52
51
50
49
48
47
46
45
44
43
42
41
40
47P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J NCP81215DMNTXG_QFN52_6X6 PC1114
1 2 1 2 1 2 PR1135 2200P_0402_50V7K

TAB

VR_RDY

SCLK
ALERT#
SDIO
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH

PWM_1PH/ICCMAX_1PH
EN
26.1K_0402_1%
PR1136 PR1137 1 2 PR1138 PC1118 PC1119
3.65K_0402_1% 1K_0402_1% PR1139 49.9_0402_1% 470P_0402_50V8J 47P_0402_50V8J
1 2 1 2 1 2 30.1K_0402_1% 1 2 1 2 1 2
PC1120 VSP_4PH 1 39 81215_VR_HOT 1 2
PC1117 470P_0402_50V8J VSN_4PH 2 VSP_4PH VRHOT# 38 VSP_2PH PC1122 2 1 1 2 1 2
2200P_0402_50V7K 1 2 3 VSN_4PH VSP_2PH 37 VSN_2PH 470P_0402_50V8J PR1140 PR1141 PC1121
DIFFOUT_4PH 4 IMON_4PH VSN_2PH 36 1 2 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
FB_4PH 5 DIFFOUT_4PH IMON_2PH 35 DIFFOUT_2PH
C COMP_4PH FB_4PH DIFFOUT_2PH FB_2PH C
6 34
4PH@ PR11421 2 ILIM_4PH 7 COMP_4PH FB_2PH 33 COMP_2PH
Place close to Choke in VCORE CSCOMP_4PH ILIM_4PH COMP_2PH ILIM_2PH
30K_0402_1% 8 32 PR11431 2 13K_0402_1%
first phase circuit CSCOMP_4PH ILIM_2PH
1

CSSUM_4PH 9 31 CSCOMP_2PH
75K_0402_1%

1
10 CSSUM_4PH CSCOMP_2PH 30 CSSUM_2PH
PR1144

PH1101 PH1102

75K_0402_1%
1000P_0402_50V7K
180P_0402_50V8J

CSP1_4PH 11 CSREF_4PH CSSUM_2PH 29

PR1145
1000P_0402_50V7K
100P_0402_50V8J
CSP1_4PH CSREF_2PH
1

CSP2_4PH CSP1_2PH

PWM1_4PH/ICCMAX_4PH

PWM1_2PH/ICCMAX_2PH
12 28
PC1124

PC1125

220K_0402_5%_ERTJ0EV224J 220K_0402_5%_ERTJ0EV224J

PWM4_4PH/ROSC_MPH
CSP2_4PH CSP1_2PH

1
CSP3_4PH

PWM2_2PH/ROSC_1PH
13 27 2 1

PC1126

PC1127
PC1123
+5VS Place close to Choke in VCCGT first phase circuit
2

1 2

CSP3_4PH CSP2_2PH

TTSENSE_1PH/PSYS
PR1147
165K_0402_1%

1 2

2
PWM3_4PH/VBOOT

1
80.6K_0603_1% 0.1U_0402_25V7K PR1146

165K_0402_1%
PWM2_4PH/ADDR
1

2
1 2
PR1148

1K_0402_1% PC1128
<62,63> SW1_4PH

TTSENSE_2PH

PR1149
PR1150 0.1U_0402_25V7K

TSENSE_4PH

2
80.6K_0603_1% PR1151

CSP4_4PH
1 2 +5VS 57.6K_0603_1%
<62,63> SW2_4PH
2

PR1152 1 2
SW1_2PH <62,65>

2
DRON
VRMP
80.6K_0603_1%

VCC

2
1 2
<62,64> SW3_4PH
4PH@ PR1155 PR1153 3PH@
80.6K_0603_1% PR1154 1K_0402_1%

14
15
16
17
18
19
20
21
22
23
24
25
26
1 2 1K_0402_1%
<62,64> SW4_4PH
1 2 PC1129
Vcore_B+ P_SYS <48,58>

1
0.1U_0402_25V6 CSP4_4PH
CSREF_4PH PC1130 2 1 TSENSE_4PH PC1131
<63,64> CSREF_4PH
0.01U_0402_50V7K 0.1U_0402_25V6 PR1157
1 2 TSENSE_2PH 1 2 6.81K_0402_1%
CSREF_2PH <65>
1 2 1 2
PR1159 +5VALW 1 2
<63,64,65> DRON PWM2_2PH/ROSC1
6.98K_0402_1% PR1156 PR1158

1
1 2 CSP1_4PH 2.2_0603_5% 25.5K_0402_1%

1U_0603_10V6K
<62,63> SW1_4PH

PC1132

102K_0402_1%
2

1
2

4PH@ PR1161
PC1133 @ PR1160

4.3K_0402_1%

24.9K_0402_1%

97.6K_0402_1%

97.6K_0402_1%
PWM1_2PH/ICCMAX2 <65>

1
0.033U_0402_25V7K 1K_0402_1%
1

PR1162

PR1163

PR1164

PR1165
PR1166
6.98K_0402_1%
1

2
CSREF_4PH PR1161 PR1142 CSP1_2PH 1 2
<63> PWM1_4PH/ICCMAX4 SW1_2PH <62,65>
PR1167

2
6.98K_0402_1%
1 2 CSP2_4PH PC1134
<62,63> SW2_4PH <63> PWM2_4PH/ADDR
2

0.033U_0402_25V7K

1
2

@ PR1168
PC1135 CSREF_2PH
B 1K_0402_1% 75K_0402_1% 23.2K_0402_1% B
0.033U_0402_25V7K 3PH@ 3PH@
1

<64> PWM3_4PH/VBOOT
1

CSREF_4PH
PR1169
6.98K_0402_1%
CSP3_4PH <64> PWM4_4PH/ROSCM
1 2
<62,64> SW3_4PH
2
2

@ PR1170
PC1136 1K_0402_1%
0.033U_0402_25V7K
1

CSREF_4PH
TSENSE_4PH TSENSE_2PH
4PH@ PR1171
6.98K_0402_1%
1

1
1 2 CSP4_4PH PVT_01 PVT_01
<62,64> SW4_4PH
2

PR1172 @ PR1173 @
2

@ PR1174 0_0402_5% 0_0402_5%

PC1137 4PH@ 1K_0402_1% Place close to H-side,L-side MOS
0.033U_0402_25V7K Place close to H-side,L-side MOS in VCCGT first phase
1

1 2

1 2
in VCORE first phase
1

1
CSREF_4PH
PH1103 PH1104
PR1175 PR1176
220K_0402_5%_ERTJ0EV224J 8.45K_0402_1% 220K_0402_5%_ERTJ0EV224J 8.45K_0402_1%
2

A A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D NCP81215
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.0
LA-F601P
Date: Wednesday, June 06, 2018 Sheet 62 of 74
5 4 3 2 1
 5 4 3 2 1

B+ Vcore_B+

EMC@ PL1200
HCB2012KF-121T50_0805
1 2

EMC@ PL1201
HCB2012KF-121T50_0805
1 2

EMC@ PL1204
D HCB2012KF-121T50_0805 D
1 2

100U_D_20VM_R55M

2200P_0402_50V7K
10U_0805_25VAK
1 +5VS

PC1206
10U_0805_25VAK

1.5P_0402_50V8
0.1U_0402_25V7K
1

1
+

PC1203

PC1204
PC1202

PC1207
Vcore_B+

2
2

PC1205
1 2 PC1209
0.1U_0402_25V7K

2
EMC@ PR1200 2_0603_5% 2 1
EMC@ EMC@ PC1208
1U_0603_25V7K PC1210

1
PU1200 1 2 1 2
3 8
Package: 6.8 x 7.6 x 4.0
15 VCC VIN 9 PR1201 Idc=36A, Isat=45A
VCCD VIN 0.22U_0603_25V7K DCR=0.66mohm (Typ.)
10U_B3_25VM_R0.1

10U_B3_25VM_R0.1
3.9_0603_1%
1 1 17 5
THWN BOOT

1
16 7
+ + <62,63,64,65> DRON DISB# PHASE PL1202
PC1211

PC1214
PC1216 1
<62> PWM1_4PH/ICCMAX4 PWM
2.2U_0603_10V7K 2 11 CORE_SW1 1 4 +VCC_CORE

2
SMOD# SW 12
2 2 +5VS SW 2 3
4 PR1202
10 CGND 0.15UH_PCME064T-R15MS_36A_20% 10_0402_1%
@ 14 PGND 1 2
13 PGND 6 CSREF_4PH <62,63,64>
19 GL NC 18
GL AGND

1
C EMC@ C
PC1217
NCP302045MNTXG_PQFN33_5X5 2200P_0603_50V7K

2
SW1_4PH <62>

1
EMC@
PR1203
1_1206_5%

2
+5VS
Vcore_B+

PC1222
0.1U_0402_25V7K
2 1
B 1 2 B
2200P_0402_50V7K
10U_0805_25VAK

PC1225
10U_0805_25VAK

0.1U_0402_25V7K

PR1204 2_0603_5%

2
1

1
PC1223

PC1224

PC1226

PC1227
PC1228
1U_0603_25V7K
1
2

1 2 1 2
PU1201
3 8 PR1205
15 VCC VIN 9 3.9_0603_1% 0.22U_0603_25V7K
VCCD VIN
17 5
THWN BOOT
1

PC1229 16 7
<62,63,64,65> DRON DISB# PHASE PL1203
1
<62> PWM2_4PH/ADDR PWM
2.2U_0603_10V7K 2 11 CORE_SW2 1 4 +VCC_CORE
2

EMC@ EMC@ SMOD# SW 12

+5VS SW 2 3
4 PR1206
10 CGND 0.15UH_PCME064T-R15MS_36A_20% 10_0402_1%
PGND

1
14 EMC@ 1 2
13 PGND 6 PC1230 CSREF_4PH <62,63,64>
19 GL NC 18 2200P_0603_50V7K

2
GL AGND

NCP302045MNTXG_PQFN33_5X5

1
2200P_0402_50V7K
10U_0805_25VAK

EMC@
SW2_4PH <62>
PC1233
10U_0805_25VAK

0.1U_0402_25V7K

PR1207
1

1
PC1231

PC1232

PC1234

1_1206_5%
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

EMC@ EMC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCC_CORE_Phase1&2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F601P
Date: Wednesday, June 06, 2018 Sheet 63 of 74
5 4 3 2 1
 5 4 3 2 1

Vcore_B+

2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK
0.1U_0402_25V7K
1

1
PC1251 EMC@

PC1252 EMC@

PC1254

PC1256
2

2
+5VS

D PR1251 D

1 2
PC1258
0.1U_0402_25V7K
2_0603_5%

2
PC1257 1 2
1U_0603_25V7K PC1259

1
PU1251 1 2 1 2
3 8
15 VCC VIN 9 PR1252
VCCD VIN 3.9_0603_1% 0.22U_0603_25V7K
17 5
THWN BOOT

1
16 7
<62,63,64,65> DRON DISB# PHASE PL1251
PC1260 1
<62> PWM3_4PH/VBOOT PWM
2.2U_0603_10V7K 2 11 CORE_SW3 1 4 +VCC_CORE

2
SMOD# SW 12
+5VS SW 2 3
4 PR1253
10 CGND 0.15UH_PCME064T-R15MS_36A_20% 10_0402_1%
14 PGND 1 2
PGND CSREF_4PH <62,63,64>

1
13 6 EMC@
19 GL NC 18 PC1261
GL AGND 2200P_0603_50V7K

2
NCP302045MN_PQFN33_5X5
SW3_4PH <62>

1
C EMC@ C
PR1254
1_1206_5%

Vcore_B+

2
2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK
0.1U_0402_25V7K
1

1
PC1262 4PH@

PC1263 4PH@

PC1264

PC1265
+5VS 2

2
4PH@

4PH@
4PH@
PR1255
1 2

2_0603_5%
2

4PH@ PC1269
PC1268 4PH@ 0.1U_0402_25V7K
1U_0603_25V7K
1

1 2
4PH@
PC1270
4PH@
PU1252
1 2 1 2
3 8
15 VCC VIN 9 4PH@ PR1256
VCCD VIN 3.9_0603_1% 0.22U_0603_25V7K
B 17 5 B
THWN BOOT
1

16 7 4PH@
<62,63,64,65> DRON 1 DISB# PHASE PL1252
4PH@ PC1271
<62> PWM4_4PH/ROSCM PWM
2 11 CORE_SW4 1 4 +VCC_CORE
2

SMOD# SW 12
2.2U_0603_10V7K +5VS SW 2 3
4 4PH@ PR1257
10 CGND 0.15UH_PCME064T-R15MS_36A_20% 10_0402_1%
14 PGND 1 2
13 PGND 6 CSREF_4PH <62,63,64>
19 GL NC 18
GL AGND
1

4PH@
PC1272
NCP302045MN_PQFN33_5X5 2200P_0603_50V7K
2

SW4_4PH <62>
1

4PH@
PR1258
1_1206_5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCC_CORE_Phase3&4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F601P
Date: Wednesday, June 06, 2018 Sheet 64 of 74
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

GT_B+
B+ GT_B+

2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK
0.1U_0402_25V7K
1

1
PC1701 EMC@

PC1702 EMC@

PC1700

PC1703
EMC@ PL1700
HCB2012KF-121T50_0805

2
1 2
+5VS
EMC@ PL1701
HCB2012KF-121T50_0805
1 2 PC1704
D 0.1U_0402_25V7K D
PR1700
1 2 1 2

2_0603_5%

2
PC1705
1U_0603_25V7K PC1706

1
PU1700 1 2 1 2
3 8
15 VCC VIN 9 PR1701
VCCD VIN 3.9_0603_1% 0.22U_0603_25V7K Package: 6.8 x 7.6 x 4.0
17 5 Idc=36A, Isat=45A
THWN BOOT

1
<62,63,64,65> DRON
16
DISB# PHASE
7
PL1702
DCR=0.66mohm (Typ.)
PC1707 1
<62> PWM1_2PH/ICCMAX2
2 PWM 11 GT_SW1 1 4
2.2U_0603_10V7K

2
SMOD# SW
+5VS SW
12 +VCCGT
2 3
4 PR1702
10 CGND 0.15UH_PCME064T-R15MS_36A_20% 10_0402_1%
14 PGND 1 2
PGND CSREF_2PH <62>

1
13 6 EMC@
19 GL NC 18 PC1708
GL AGND 2200P_0603_50V7K

2
B+ SA_B+
NCP302045MN_PQFN33_5X5
SW1_2PH <62>
EMC@ PL1703

1
C HCB2012KF-121T50_0805 EMC@ C
1 2 PR1703
1_1206_5%

SA_B+

2
2200P_0402_50V7K

10U_0805_25VAK

10U_0805_25VAK
0.1U_0402_25V7K
1

1
PC1709 EMC@

PC1710 EMC@

PC1711

PC1712
+5VS 2

2
PR1704
1 2
PC1714
0.1U_0402_25V7K
2_0603_5%
2

PC1713 1 2
1U_0603_25V7K
1

PC1715
PU1701
1 2 1 2
3 8
Package: 5.7 x 5.4 x 3.0
15 VCC VIN 9 PR1705 Idc=12A, Isat=16A
VCCD VIN 3.9_0603_1% 0.22U_0603_25V7K DCR=6.2mohm (Typ.)
B 17 5 B
THWN BOOT
1

16 7
<62,63,64,65> DRON DISB# PHASE PL1704
PC1716 1
<62> PWM1_1PH/ICCMAX1 2 PWM 11 SA_SW 1 4
2

SMOD# SW
2.2U_0603_10V7K
SW
12
2 3
+VCCSA
4
10 CGND 0.47UH_MMD05CZR47M_12A_20%
14 PGND
13 PGND 6 CSN_1PH <62>
19 GL NC 18
GL AGND
1

EMC@
PC1717
NCP302045MN_PQFN33_5X5 2200P_0603_50V7K
2

SW_1PH <62>
1

EMC@
PR1706
1_1206_5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCC_GT/+VCC_SA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F601P
Date: Wednesday, June 06, 2018 Sheet 65 of 74
5 4 3 2 1
 A
B
C
D
1uF*24
22uF*40
220uF*1
470uF*2
+VCC_CORE

1uF*12
+VCCGT
22uF*32
470uF*2
+VCC_CORE

2 1 2 1 2 1

@
2 1

+VCCGT

5
5

2
1
+

PC2004 PC2105 PC2003

2 1 PC2029 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM PC2001
1U_0201_6.3V6M 2 1 2 1 470U_D2E_2.5VM_R6M

@
PC2083 2 1 2 1
2
1
+

1U_0201_6.3V6M PC2100 PC2010

2
1
+
2 1 2 1 PC2030 PC2005 22U_0603_6.3VAM 22U_0603_6.3VAM PC2002
2 1 PC2020 1U_0201_6.3V6M 1U_0201_6.3V6M 2 1 2 1 470U_D2E_2.5VM_R6M

@
PC2122 PC2021 2 1
PVT_02

330U_B2_2.5VM_R9M
PC2075 22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 PC2104 PC2012
2
1
+

1U_0201_6.3V6M 2 1 2 1 PC2031 22U_0603_6.3VAM 22U_0603_6.3VAM

2
1
+
1U_0201_6.3V6M PC2006 PC2011

@
2 1 PC2124 PC2022 PC2019 2 1 1U_0201_6.3V6M 2 1 2 1 220U_D7_2VM_R6M
22U_0603_6.3VAM 22U_0603_6.3VAM 470U_D2E_2.5VM_R6M
2
1
+

PC2074 2 1 2 1 PC2032 2 1 PC2108 PC2017

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM @ PC2028

@
PC2126 PC2024 2 1 PC2007 220U_D7_2VM_R6M
2 1 22U_0603_6.3VAM 22U_0603_6.3VAM 1U_0201_6.3V6M 2 1 2 1
2 1 2 1 PC2033
PC2076 1U_0201_6.3V6M 2 1 PC2110 PC2013

@
1U_0201_6.3V6M PC2128 PC2023 2 1 22U_0603_6.3VAM 22U_0603_6.3VAM
2 1 22U_0603_6.3VAM 22U_0603_6.3VAM PC2008 2 1 2 1
2 1 2 1 PC2034 1U_0201_6.3V6M
X6S low noise

PC2082 1U_0201_6.3V6M PC2109 PC2014

@
1U_0201_6.3V6M PC2125 PC2026 2 1 2 1 22U_0603_6.3VAM 22U_0603_6.3VAM
22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 2 1
2 1 2 1 2 1 PC2035 PC2009
1U_0201_6.3V6M 1U_0201_6.3V6M PC2106 PC2015

X6S low noise

@
PC2081 PC2127 PC2025 2 1 2 1 22U_0603_6.3VAM 22U_0603_6.3VAM
1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 2 1
2 1 2 1 PC2036 PC2047
2 1 1U_0201_6.3V6M 1U_0201_6.3V6M PC2102 PC2016

@
PC2123 PC2027 2 1 22U_0603_6.3VAM 22U_0603_6.3VAM
PC2080 22U_0603_6.3VAM 22U_0603_6.3VAM 2 1
1U_0201_6.3V6M 2 1 2 1 PC2037 2 1 2 1
1U_0201_6.3V6M PC2046

@
2 1 PC2120 PC2094 2 1 1U_0201_6.3V6M PC2111 PC2018
22U_0603_6.3VAM 22U_0603_6.3VAM 22U_0603_6.3VAM 22U_0603_6.3VAM
PC2079 2 1 2 1 PC2038 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M

@
PC2118 PC2092 2 1 PC2045 PC2103 PC2040
2 1 22U_0603_6.3VAM 22U_0603_6.3VAM 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM
2 1 2 1 PC2060
1U_0201_6.3V6M

WWW.AliSaler.Com
PC2077 @ 2 1 2 1 2 1
1U_0201_6.3V6M PC2121 PC2093 2 1
22U_0603_6.3VAM 22U_0603_6.3VAM PC2044 PC2107 PC2039
2 1 2 1 2 1 PC2067 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM
1U_0201_6.3V6M

4
4

PC2078 PC2119 PC2091 2 1 2 1 2 1 2 1

1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM
2 1 2 1 PC2061 PC2042 PC2101 PC2041
2 1 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM
@

PC2137 PC2138 2 1 2 1 2 1
PC2084 22U_0603_6.3VAM 22U_0603_6.3VAM 2 1
1U_0201_6.3V6M 2 1 2 1 PC2065 PC2096 PC2087
1U_0201_6.3V6M PC2043 22U_0603_6.3VAM 22U_0603_6.3VAM
@

2 1 PC2135 PC2131 2 1 1U_0201_6.3V6M

22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 2 1 2 1
PC2085 2 1 2 1 PC2064
1U_0201_6.3V6M 1U_0201_6.3V6M PC2059 PC2099 PC2090
@

PC2133 PC2129 2 1 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM

22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 2 1
2 1 2 1 PC2063 2 1
1U_0201_6.3V6M PC2097 PC2088
@

PC2136 PC2132 2 1 PC2058 22U_0603_6.3VAM 22U_0603_6.3VAM

22U_0603_6.3VAM 22U_0603_6.3VAM 1U_0201_6.3V6M
2 1 2 1 PC2069 2 1 2 1
1U_0201_6.3V6M 2 1
@

PC2134 PC2130 2 1 PC2098 PC2089

22U_0603_6.3VAM 22U_0603_6.3VAM PC2057 22U_0603_6.3VAM 22U_0603_6.3VAM
PC2062 1U_0201_6.3V6M
1U_0201_6.3V6M 2 1 2 1
@

2 1 2 1
PC2095 PC2086
PC2068 PC2050 22U_0603_6.3VAM 22U_0603_6.3VAM
1U_0201_6.3V6M 1U_0201_6.3V6M 2 1 2 1
+VCCSA
@

2 1
2 1 PC2117 PC2113
PC2066 22U_0603_6.3VAM 22U_0603_6.3VAM
1U_0201_6.3V6M PC2048
@

2 1 1U_0201_6.3V6M 2 1 2 1
2 1 2 1
PC2070 2 1 PC2116 PC2114
PC2139 PC2146 1U_0201_6.3V6M 22U_0603_6.3VAM 22U_0603_6.3VAM
@

22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 PC2049

2 1 2 1 1U_0201_6.3V6M 2 1 2 1
PC2073 2 1
PC2141 PC2148 1U_0201_6.3V6M PC2115 PC2112
@

22U_0603_6.3VAM 22U_0603_6.3VAM 2 1 PC2056 22U_0603_6.3VAM 22U_0603_6.3VAM

2 1 2 1 1U_0201_6.3V6M
PC2071
PC2143 PC2150 1U_0201_6.3V6M 2 1
@

22U_0603_6.3VAM 22U_0603_6.3VAM 2 1
2 1 2 1 PC2055

3
3

PC2072 1U_0201_6.3V6M
PC2145 PC2152 1U_0201_6.3V6M
22U_0603_6.3VAM 22U_0603_6.3VAM 2 1
2 1 2 1
PC2054
PC2142 PC2149 1U_0201_6.3V6M
22U_0603_6.3VAM 22U_0603_6.3VAM
2 1 2 1 2 1

PC2144 PC2151 PC2053

22U_0603_6.3VAM 22U_0603_6.3VAM 1U_0201_6.3V6M
2 1 2 1
2 1
PC2140 PC2147
22U_0603_6.3VAM 22U_0603_6.3VAM PC2051
2 1 2 1 1U_0201_6.3V6M

PC2000 PC2153 2 1
22U_0603_6.3VAM 22U_0603_6.3VAM
PVT_03

PC2052
1U_0201_6.3V6M
+VCCSA

Issued Date
22uF*16

Security Classification
2017/06/21

2
2

Compal Secret Data

Deciphered Date

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2027/06/21

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title

Date:
Document Number

LA-F541P
Wednesday, June 06, 2018

1
1

Sheet
66
of
Compal Electronics, Inc.

74
Rev
0.1(X00)
P65-PWR_PROCESSOR_DECOUPING
A
B
C
D
 5 4 3 2 1

for dGPU SKU

@DIS@ : Nopop Component +1.0VSP/1.05VSP
DIS@: POP for dGPU SKU TDC 1.1A
Peak Current 1.1A
OCP current 6A(fix)
+3VS

DIS@
B+_1VSP

1
D D
PR951 keep short pad,
100K_0402_5% PVT_01 snubber is for EMI only.
DIS_EMC@ DIS@ Package: 4.9 x 5.2 x 3.0
B+ PL900 PR952 @DIS@
HCB2012KF-121T50_0805
PU900
0_0402_5% Idc=7A, Isat=11A

2
1 2 2
IN PG
9 1 2 1VS_GFX_PG <23> DIS@ PC902 DCR=13mohm (Typ.)
0.1U_0201_10V6K

DIS@ 10U_0603_25V6M

DIS@ 10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1VSP 1 2 BST_1VSP_R 1 2 DIS_EMC@ DIS_EMC@

2200P_0402_50V7K
IN BS

1
@DIS@ PR900 PR901 PC904

PC901

PC900

PC903

PC913
4 6 LX_1VSP 0_0402_5% PVT_01 4.7_1206_5% 680P_0603_50V7K
IN LX

2
5 19 1 2SNB_1VSP 1 2 +1VS_GFX
IN LX

DIS_EMC@

@DIS_EMC@

@
7 20
GND LX
PJP900
8 14 1 2 2 1
PVT_01 PVT_01 GND FB
@DIS@ PR902 @DIS@ PR903 18 17 DIS@ PL901 PAD-OPEN1x1m

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
GND VCC

1
0_0402_5% 0_0402_5% 1UH_PCMB053T-1R0MS_7A_20%

100K_0402_1%
1

1
<31,69> NVVDDS_EN 1 2 1 2 11 10

PR904

220P_0402_50V8J
EN NC

PC907

PC908

PC909

PC910
PC905

PC906
13 12 2.2U_0402_6.3V6M Rup

DIS@ 2

2
1 ILMT NC

1
<31,69> GPU_CORE_VDDS_PG 1 2 @DIS@ PC911

DIS@
2
@DIS@ PR906 0.1U_0402_25V6 15 16
@DIS@ PR905 1M_0402_1% +3VALW BYP NC

DIS@

DIS@
0_0402_5% 2 21 FB = 0.6V
PAD

DIS@

DIS@

DIS@
2

+3VALW

1
SY8286RAC_QFN20_3X3

1
PR908
1 2 133K_0402_1%

1
<31> PEX_VDD_EN DIS@

2
@DIS@ PR907 @DIS@
Rdown

2
0_0402_5% PR909 DIS@ PC912
100K_0402_5%
EN :H>0.8V ; L<0.4V 2
ILMT_1VSP
1U_0402_6.3V6K
VFB=0.6V
EN pin don't floating
1

PVT_01
C
If have pull down resistor at HW side, PR910 @DIS@
Vout=0.6V* (1+Rup/Rdown) C

please delete PR601. 0_0402_5% For Vout=1.05V @Rup=100K (PN:SD034100380)

2

B B

A The current limit is set to 6A, 8A or 12A when this pin A

is pull low, floating or pull high

GPU other power_Regulatorr(43.7), Support component(43.8)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P67-PWR_+1.05VSDGPU(SY8286RAC)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P
Date: Wednesday, June 06, 2018 Sheet 67 of 74
5 4 3 2 1
 GPU_CORE (0.95V)
TDC 41A
for dGPU SKU +1.8V_GFX_AON Peak Current 94A
@DIS@ : Nopop Component OCP current 100A
DIS@: POP for dGPU SKU DCR 0.98mohm +/- 5%

1
DIS@
Ra PR1000
10K_0402_1%
MIN MAX
PR1001 DIS@
H/S Rds(on) : 4mohm , 5.2mohm

2
22.6K_0402_1%
1 2
GPU_PSI <23,69> L/S Rds(on) : 2.8mohm , 3.5mohm

1
@DIS@ DIS_EMC@
PR1002 PL1000
169K_0402_1% HCB2012KF-121T50_0805
+VGA_B+ 2 1
Rc

2
PL1001
HCB2012KF-121T50_0805
2 1 B+

10U_0805_25VAK

10U_0805_25VAK

0.1U_0402_25V7K

2200P_0402_50V7K
DIS@ PC1000

DIS_EMC@ PC1003
DIS_EMC@

DIS_EMC@ PC1004
DIS@ PC1001
NVVDD_EN <31>

1
PVT_01 DIS@ +GPU_CORE
@DIS@ PR1003 PQ1000 +GPU_CORE (place under GPU)

5
Vmax=1.3V 0_0402_5%

2
1 2 1 2 1V8_MAIN_EN <23,31>
Vmin=0.3V <23> NVVDD_PWM_VID
Vboot=0.8V @DIS@ PR1004
2.2K_0402_5% Package: 7x 7 x 4.0
DH1_NVVDD

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM
4
Idc=32A, Isat=55A

1
Enable 1.2V

1
DCR=0.98mohm (Typ.)

PC1016

PC1006

PC1007

PC1008

PC1009

PC1010

PC1011

PC1012

PC1013

PC1014
R2 Disable 0.55V
1

@DIS@ PC1015

2
DIS@ PR1005 0.22U_0402_25V6K DIS@ PL1002 +GPU_CORE

3
2
1

2
1

DIS@ PC1005 20.5K_0402_1% AON6354_N_DFN56-8-5

0.1U_0402_25V7K
R3 0.22UH_MMD-06DZIR22MEM2L_32A_20%
DIS@ PR1006 DIS@ PR1007 LX1_NVVDD 1 2
2

4.32K_0402_1% 6.19K_0402_1% DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1 2 1 2

1
309_0402_1% 16.5K_0402_1%

DIS_EMC@
PR1009
10_1206_5%
1

DIS@PR1011 DIS@ PR1008

DIS@ DIS@
R1

DH1_NVVDD
NVVDD_VID
.01U_0402_16V7K

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
NVVDD_EN

5
DIS@ PR1010 PQ1001 PQ1007
@DIS@ PC1017

1 1 1
1

R4 C 2.2_0603_5%
1

+ + +

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK
PC1019

PC1020

PC1021
2
DIS@ PC1018 BST1_NVVDD 1 2
REFADJ_NVVDD
2

1
4700P_0402_25V7K

PC1023

PC1025

PC1026

PC1027

PC1028

PC1029
2

DL1_NVVDD 4 DL1_NVVDD 4 2 2 2
1

DIS_EMC@
DIS@

PC1024

2
47P_0603_50V8J
5

1
PU1001 DIS@ PC1022
0.22U_0603_25V7K
R5
VID

PSI

EN

UGATE1

BOOT1

2
3
2
1

3
2
1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2

6 20 LX1_NVVDD +5VS DIS@ DIS@ DIS@

REFADJ PHASE1
AON6314_N_DFN56-8-5 AON6314_N_DFN56-8-5
REFIN_NVVDD 7 19 DL1_NVVDD DIS@ PR1012
REFIN LGATE1
2.2_0603_5%
VREF_NVVDD

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK
8 18 1 2
VREF PVCC

1
+VGA_B+

PC1031

PC1032

PC1037

PC1038

PC1039

PC1040

PC1035

PC1033

PC1034

PC1036
RT8816BGQW_WQFN20_3X3

1
DIS@ PR1014 DIS@ PR1013
412K_0402_1% 9 17 DL2_NVVDD DIS@ PC1030
20_0402_1%

2
1 2 1 2 TON LGATE2 2.2U_0402_6.3VAM
+VGA_B+

10U_0805_25VAK

10U_0805_25VAK

0.1U_0402_25V7K
DIS_EMC@ PC1045

DIS_EMC@ PC1046
LX2_NVVDD

2200P_0402_50V7K
OCSET/SS
0.1U_0402_25V7K

10 16
RGND PHASE2
1

UGATE2
DIS@ PC1041

DIS@ PC1042

DIS@ PC1043
PGOOD

BOOT2

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

1
VSNS

Fsw=370KHz
GND

1
DIS@
2

DIS@ DIS@ PC1047 PQ1002

2
5
PR1015 0.22U_0603_25V7K
21

11

12

13

DH2_NVVDD 14

15

2
2.2_0603_5%
BST2_NVVDD 1 2 +GPU_CORE (place near GPU) +GPU_CORE
NVVDD_PGOOD

DIS@ PR1016
100_0402_5% PVT_12 DH2_NVVDD 4
1 2
@DIS@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PVT_01 PR1017

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK

4.7U_0603_6.3VAK
@DIS@ PR1018 0_0402_5% DIS@ PL1003

3
2
1
0_0402_5% 1 2 GPU_CORE_PG <31> AON6354_N_DFN56-8-5

1
PC1049

PC1050
1 2 PVT_01 0.22UH_MMD-06DZIR22MEM2L_32A_20%

PC1048

PC1051

PC1052

PC1053
<24> VSSSENSE_VGA LX2_NVVDD
1 2 1 2
PR1019 +3VS

2
1

@DIS@ PC1054 10K_0402_5%

DIS_EMC@
PVT_01 100P_0402_50V8J DIS@ DIS@ DIS@

10_1206_5%
@DIS@ PR1021 PR1022 DIS@ PQ1008 7 x 7 x 4mm

PR1020
DIS@ DIS@
2

1
0_0402_5% 232K_0402_1% PQ1003 DIS@ DIS@ DIS@ DIS@

5
1 2 1 2
<24> VCCSENSE_VGA
DIS@ PR1023
100_0402_5% 1 2 PVT_12

2
1 2 DL2_NVVDD 4
+GPU_CORE DL2_NVVDD

DIS_EMC@
@DIS@ PC1055 4

47P_0603_50V8J
1
0.01U_0402_16V7K

PC1056

10U_0603_6.3VAM

10U_0603_6.3VAM

10U_0603_6.3VAM

10U_0603_6.3VAM

10U_0603_6.3VAM

10U_0603_6.3VAM

10U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM
3
2
1

2
AON6314_N_DFN56-8-5

3
2
1

1
PC1057

PC1058

PC1059

PC1060

PC1061

PC1062

PC1063

PC1064

PC1065

PC1066

PC1067

PC1068

PC1069

PC1070
AON6314_N_DFN56-8-5

2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

Under:
4.7U_0603_6.3VAK *16
1U_0402_6.3VAK *10

Near:
10U_0805_6.3V6M*7
22U_0805_6.3V6M *7
4.7U_0805_6.3V6K *6
330u*3

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title

P68-PWR-+GPU_CORE
VGA_CORE controller(43.1), Support component(43.2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
VGA_CORE Drivers (43.3), GPU Core Output CAP (43.9) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F541P 0.1(X00)

Date: Wednesday, June 06, 2018 Sheet 68 of 74

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WWW.AliSaler.Com
 +1.8V_GFX_AON
+GPU_CORE_VDDS
Ra TDC 12A
for dGPU SKU

1
@DIS@ : Nopop Component DIS@ PR1500 Peak Current 16A
10K_0402_1%
Rb OCP current 21A
DIS@: POP for dGPU SKU @DIS@
PR1501 DCR 0.98mohm +/- 5%

2
NVVDDS_PSI
0_0402_5%
1 2
GPU_PSI <23,68>
MIN MAX

1
PR1502 H/S Rds(on) : 3.7mohm , 4.5mohm
DIS@ 8.2K_0402_1% L/S Rds(on) : 1.5mohm , 1.9mohm
Rc

2
+NVVDDS_B+
DIS_EMC@ PL1501
HCB2012KF-121T50_0805
2 1

PVT_01 2 1 B+
@DIS@ PR1503

10U_0805_25VAK

10U_0805_25VAK

0.1U_0402_25V7K
Vmax=1.3V 0_0402_5% DIS_EMC@ PL1502

2200P_0402_50V7K
PC1510
1 2 HCB2012KF-121T50_0805

PC1511
Vmin=0.3V <23> NVVDDS_PWM_VID

PC1509

PC1505
Vboot=0.8V

1
+GPU_CORE_VDDS
NVVDDS_EN <31,67>
NVVDDS (place under GPU)

2
R2DIS@
1

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM
DIS@ DIS@

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK

1U_0402_6.3VAK
DIS@ PR1505
1

1
PC1502

PC1512

PC1503

PC1507

PC1513

PC1514

PC1508

PC1515

PC1504

PC1516
PC1501 20.5K_0402_1% DIS_EMC@ DIS_EMC@
0.1U_0402_25V7K
R3
DIS@ PR1508 PR1507 DIS@
2

2
4.32K_0402_1% 6.19K_0402_1% DIS@
1 2 1 2 PQ1500

5
309_0402_1% 16.5K_0402_1%

DH1_NVVDDS
1

NVVDDS_VID
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
R1 DIS@ DIS@ DIS@ DIS@
.01U_0402_16V7K
DIS@ PR1511 DIS@ PR1509

PC1518

PR1510
1

R4 C 2.2_0603_5%
1

PC1517 DIS@ BST1_NVVDDS 1 2 DH1_NVVDDS 4

REFADJ_NVVDDS
2

4700P_0402_25V7K
2
@DIS@

DIS@
1

1
DIS@ DIS@
5

1
PU1501 PC1519 DIS@ PL1500
+GPU_CORE_VDDS

3
2
1
0.22U_0603_25V7K AON6354_N_DFN56-8-5
R5
VID

PSI

EN

UGATE1

BOOT1

2
0.22UH_MMD-06DZIR22MEM2L_32A_20%
LX1_NVVDDS 1 2
2

6 20 LX1_NVVDDS
REFADJ PHASE1

1
REFIN_NVVDDS 7
REFIN LGATE1
19 DL1_NVVDDS DIS@ DIS@ PR1512 NVVDDS (place near GPU)

5
PR1513 PQ1501 10_1206_5% Package: 7x 7 x 4.0
VREF_NVVDDS 8 18 1
2.2_0603_5%
2 DIS_EMC@ Idc=32A, Isat=55A +GPU_CORE_VDDS
+5VS

2
VREF RT8816BGQW_WQFN20_3X3 PVCC DCR=0.98mohm (Typ.)

1
PR1514 PR1515
DL1_NVVDDS

1
20_0402_1% 412K_0402_1% 9 17 PC1520 4 PC1521
1 2 1 2 TON LGATE2 2.2U_0402_6.3VAM
+NVVDDS_B+ 47P_0603_50V8J

2
OCSET/SS
0.1U_0402_25V7K

DIS@ DIS@ 10 16 DIS@

RGND PHASE2

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
1

UGATE2

10U_0603_6.3VAM

10U_0603_6.3VAM

10U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM
PC1522

DIS_EMC@
PGOOD

BOOT2

1 1

3
2
1
VSNS

Fsw=370KHz 1 1 1
GND

1
PC1523

PC1524

PC1525

PC1526

PC1527

PC1528
+ +

PC1529

PC1530
2

AON6314_N_DFN56-8-5
21

11

12

13

14

15

2
2 2 2 2 2

PVT_12
NVVDDS_PGOOD

DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PR1516 DIS@ PR1522
100_0402_5% 10K_0402_5% DIS@ DIS@
1 2 1 2
+3VS
DIS@ PVT_01
PVT_01 @DIS@ PR1517 @DIS@ PR1518
0_0402_5% 0_0402_5% GPU_CORE_VDDS_PG <31,67> Under:
<26> GNDS_SENSE_VGA 1 2 1 2
4.7U_0603_6.3VAK *6
1U_0402_6.3VAK *4
1

@DIS@ PC1531
100P_0402_50V8J DIS@
PR1519
2

PVT_01 @DIS@ PR1520 71.5K_0402_1% Near:

0_0402_5% 1 2
1 2 10U_0603_6.3VAM *3
<26> VDDS_SENSE_VGA 22U_0603_6.3VAM *3
1 2 330u*2
+GPU_CORE_VDDS 1 2 @DIS@ PC1532
0.01U_0402_16V7K
PR1521
100_0402_5%
DIS@

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title

P69-PWR-+GPU_CORE_VDDS
VGA_CORE controller(43.1), Support component(43.2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
VGA_CORE Drivers (43.3), GPU Core Output CAP (43.9) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F541P 0.1(X00)

Date: Wednesday, June 06, 2018 Sheet 69 of 74

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
 5 4 3 2 1

+1.8VALW
TDC 2A
Peak Current 3A
OCP current 6A(fix)
+3VALW

1
B+_1.8VSP PR1643
100K_0402_5% keep short pad,
EMC@ PVT_01 snubber is for EMI only.
D B+ D
PL1600 PU1600
@ PR1651

2
HCB2012KF-121T50_0805 0_0402_5%
1 2 2 9 1 2 1.8V_PRIM_PWRGD <33,60>
IN PG PC1601

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1.8VSP 1 2 1 2 0.1U_0201_10V6K

2200P_0402_50V7K
IN BS

1
@ PR1600 PR1601 PC1604

EMC@ PC1600

@EMC@ PC1603

PC1602

PC1613
4 6 LX_1.8VSP 0_0402_5% PVT_01 4.7_1206_5% 680P_0603_50V7K
IN LX

2
5 19 1 2SNB_1.8VSP1 2
IN LX +1.8ALWP +1.8VALW
7 20 EMC@ EMC@
GND LX PL1601

@
PVT_14 PJP1600
8 14 1 2 1 2
GND FB 1 2
PVT_01 @ PR1602 18 17 JUMP_43X118

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM
GND VCC

1
0_0402_5% 1UH_AWP252012HF-1R0M-C1__3A_20%

100_0402_1%
1

1
1 2 11 10

PR1603
<20,33,60> PCH_PRIM_EN EN NC

1
PC1605

PC1607

PC1608

PC1609

PC1610
220P_0402_50V8J
13 12 2.2U_0402_6.3V6M FB = 0.6V

PC1606
2

2
ILMT NC
1

PC1611

2
PR1604 0.1U_0402_25V6 15 16
1M_0402_1% +3VALW BYP NC
2

@ 21
@ PAD
2

+3VALW SY8286RAC_QFN20_3X3 PR1605

1
1 2
PC1612
1

1U_0402_6.3V6K

2
49.9K_0402_1%
PR1606
Vout=0.6V* (1+Rup/Rdown)
@

100K_0402_5% Rup
2

ILMT_1.8VSP
EN :H>0.8V ; L<0.4V VFB=0.6V

1
1

PR1608
EN pin don't floating PVT_01 PR1607 @
Vout=0.95V
If have pull down resistor at HW side, 0_0402_5%
Rdown 24K_0402_1%

C please delete PR601. C

2
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2027/06/21 Title
2017/06/21 Deciphered Date
P70-PWR_ +1.8ALWP(SY8286RAC)

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P
Wednesday, June 06, 2018
Date: Sheet 70 of 74
5 4 3 2 1
 5 4 3 2 1

for dGPU SKU

@DIS@ : Nopop Component
DIS@: POP for dGPU SKU

1.35VS_VGAP
TDC=11A
D DIS_EMC@ Ipeak=20A D
PL777
HCB2012KF-121T50_0805
OCP=24A
+1.35VS_B+ 1 2 B+ Switching Frequency: 400kHz
+5VALW
TYP MAX
H/S Rds(on):6.8mohm ,8.6mohm

DIS_EMC@ PC701

1U_0402_25VAK

1000P_0402_50V7K
0.1U_0402_25V7K

PC704

PC705
10U_0603_16VAM

10U_0603_16VAM
2200P_0402_50V7K
L/S Rds(on):2.0mohm ,2.5mohm

1
DIS_EMC@ PC700

DIS@ PC702

DIS@ PC703
DIS@
PR700
2.2_0603_5%

2
DIS_EMC@

DIS_EMC@
1
PVT_06
RT8812_PVCC

1
DIS@ DIS@ PQ700

1
DIS@ PC707 PC706 AON6962_DFN5X6D-8-7 PVT_04
0.1U_0402_25V7K 2.2U_0402_6.3VAM
Package: 7x 7 x 3

D1

G1
Idc=13A, Isat=24A

2
DIS@ PL700
1 2PWR_VGA_CORE_TON_1 0.82UH_MMD-06CZ-R82M-V1L_13A_20% DCR=6.7mohm (Typ.)

18
PU700
PVT_05 D2/S1
7 1 2
+1.35VS_VGAP

PVCC
DIS@ PR701 DIS@ PR704

1
2.2_0201_1%

G2
383K_0402_1%

S2

S2

S2
2 1 2 1 PWR_VGA_CORE_TON 9 2 PWR_VGA_CORE_UGATE1
+1.35VS_B+ TON UGATE1 DIS@ PC708 PR702
PR706

6
+3VS DIS@ 0.22U_0603_25V7K 4.7_1206_5%
@DIS@

+3VS PR705 PWR_VGA_CORE_BOOT12 2.2_0603_5%

2 1 13 1 1PWR_VGA_CORE_BOOT1_1 2 1 @DIS_EMC@

1 2
PGOOD BOOT1
100K_0402_1% PC709
12K_0201_1%
1

FBVDD/Q_ENP 3 20 PWR_VGA_CORE_PHASE1 680P_0402_50V7K

<18,23> DGPU_PWROK EN PHASE1
DIS@ PR703

@DIS_EMC@

2
FBVDD_PSI 4 19 PWR_VGA_CORE_LGATE1
1

@DIS@PC710 PSI LGATE1

2

FBVDD_PSI PR709 0.1U_0402_25V6 2 1

0_0201_5% 9.76K_0402_1%
2
1

10K_0201_1%

1 2 5 14
PR708

DIS@ PR707
<23,31> FBVDD_EN VID UGATE2
DIS@

C C
8 15
2

VREF BOOT2
DIS@

7 16
PR710 REFIN PHASE2
10K_0201_1%
DIS@ 6 17
REFADJ LGATE2 PR711
2

10_0402_5%
PWR_VGA_CORE_SS 11 12 1 2 @ PJP701
SS VSNS
2200P_0402_50V7K

+1.35VS_VGAP 1 2 +1.35VSDGPU
1 2
DIS@

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
21 10 JUMP_43X118

22U_0603_6.3V6M
0.1U_0402_25V7K

GND RGND

150U_B2_6.3VM_R35M
PC716
1 @ PJP702

0.1U_0402_25V7K

.1U_0402_16V7K
1

2200P_0402_50V7K
1 2
DIS@PC712

PC715

PC721
PC711

1 1 1 1 1 1

22U_0603_6.3V6M
1

1
+ 1 2
DIS@ PR713

PC714
@DIS@

PC717

PC719

PC722

PC718
34.8K_0201_1%

52.3K_0201_1%

1
RT8812AGQW-GP DIS@ JUMP_43X118
DIS@ PR712

PC723

PC724
2

PC713 PR718
OPS

DIS_EMC@
2

2
47P_0402_50V8J 2 2 2 2 2 2 2
DIS@

DIS_EMC@
0_0201_5%
DIS@

DIS@
2

@DIS@

@DIS@
DIS@

DIS@

DIS@

DIS@
2
PVT_07
PVT_08
3

DIS@
DMN53D0LDW-7 2N SOT363-6
DIS@ PQ701B

<25> FBVDDQ_SENSE
1 2 5
+3VALW
DIS@ PR715
4
DMN53D0LDW-7 2N SOT363-6

10K_0402_5%
6

DIS@ PQ701A

@DIS@ PR717
0_0402_5%
1 2 2
<23> MEM_VDD_CTL
0.1U_0402_25V7K

PVT_01
1
PC725

B B
2
DIS@

PVT_09

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.35VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E994P
Date: Wednesday, June 06, 2018 Sheet 71 of 74
5 4 3 2 1
 A B C D

2.5V_MEM controller(35.13), Support component(35.14)

+2.5V_MEM
TDC 0.86A
1
Peak Current 1A 1

OCP Current 1.46A

VDD>Vo+1.5V

+5VALW
PC1804 PR1805
1U_0402_6.3V6K PU1800 0.01_0603_1%
2 1 10 1 1 2
9 VDD VOUT 2 +2.5V_MEM
+3VALW 8 VIN VOUT 3
Rup

22P_0402_50V8J
1
VIN VOUT 4

1
PC1801
7

22U_0603_6.3V6M
VIN ADJ/NC 5

1
6 1 2

PC1802
PR1803
2
EN PGOOD +3VALW 2

22U_0603_6.3V6M
21.5K_0402_1%

2
11

PC1803
PR1800

2
PAD 100K_0402_5%

2
RT9059GQW_WDFN10_3X3

PVT_01

1
@ PR1801
0_0402_5% PVT_01
+2.5VSP_ON

@
1 2
<33,53> SUS_ON_EC_P
@ PR1851
0_0402_5%
PT201
PAD~D
PR1804
10K_0402_1%
Rdown
0.1U_0402_16V7K 1 2 +2.5V_MEM_PG

2
1
@ PC1800
2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P72-PWR_+2.5V_MEM(RT9059GSP)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P
Date: Wednesday, June 06, 2018 Sheet 72 of 74
A B C D

WWW.AliSaler.Com
 5 4 3 2 1

+0.95VS_VCCIOP
+3VALW
TDC 3.9A
Peak Current 5.5 A
EMC@
Vin=9~13.5V OCP Current 6.6 A Fix by IC
PL801
TYP MAX

1
HCB2012KF-121T50_0805 @ PR818
B+ 1 2 100K_0402_5%

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
1

1
PC800

PC801

PC802

PC803

2
PR800 PR801 PC805
2.2_0603_5% PC804

2
@ PR802 1 2 1 2 1 2SNUB_1VS_VCCIO 1 2
D D

EMC@
0_0402_5%

@EMC@
1 2 0.1U_0402_25V6
CPU_C10_GATE# 4.7_0603_5% 470P_0402_50V7K
<16,33>
@EMC@ @EMC@
PVT_01
Package: 4.9 x 5.2 x 3.0
Idc=7A, Isat=11A

9
PVT_01 PU800 PL800 DCR=13mohm (Typ.)
1UH_PCMB053T-1R0MS_7A_20%

LP#

BST
MODE
@ PR803
0_0402_5%
EN_1VS_VCCIO
1
VIN SW
8 1 2
+0.95VS_VCCIOP
1 2 5 12 1 2
<33,61> RUN_ON_P EN VOUT

47U_0603_6.3V6M

47U_0603_6.3V6M

22U_0603_6.3V6M
VID1_VCCIO 3 2 PR840 100_0402_1% 1 1

0.1U_0402_25V6
C1 PGND

1
@ PC806

PC807

PC808

@ PC809
PR804 VID0_VCCIO 4 11
C0 AGND

3V3
1M_0402_1%

PG
2

2
2 2

13

10
NB681AGD-Z_QFN13_2X3-SVR
PVT_01

+3VALW @ PR838

1
0_0402_5%
PR809 VCCIO_SENSE <11>
@ PR819 1 2
100K_0402_5% 1 2
+3VALW @ PR841
0_0402_5%

2
5.1_0402_1% 1 2 VSSIO_SENSE <11>

1
EVT_0122
PC810
1

1U_0402_6.3V6K 1 2

2
PR839 100_0402_1%
PR805 @ PR806
10K_0402_1% 10K_0402_1%
comfirm with EE,
2

VID0_VCCIO PR839,PR840 need change to 0 ohm if sense nonpop

C
VID1_VCCIO C
1

@ PR807 PR808
10K_0402_1% 10K_0402_1% PJP801
1 2
+0.95VS_VCCIOP +VCCIO
2

1 2
JUMP_43X118
@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.35VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E994P
Date: Wednesday, June 06, 2018 Sheet 73 of 76
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 NA NA 2014/12/12 EE NA NA X01
2 EE X01
D D
3 EE X01
4 EE X01
5 EE X01
6 EE X01
7 EE X01
8 EE X01
9 EE X01
10 EE X01
11 EE X01
12 EE X01
13 EE X01
14 EE X01
C 15 EE X01 C

16 EE X01
17 EE X01
18 EE X01
19 EE X01
20 EE X01
21 EE X01
22 EE X01
23 EE X01
24 EE X01
25 EE X01
26 EE
27 EE
B B

28 EE
29 EE
30 EE
31 EE
32 EE
33 EE
34 EE
35 EE
36 EE
37 EE
38 EE
39 EE
A A
40 EE
41 EE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title

P74-EE - NOTE2
WWW.AliSaler.Com 5 4 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
Size

Date:
Document Number

LA-G341P
Wednesday, June 06, 2018
1
Sheet 74 of 76
Rev
1.0(A00)
 5 4 3 2 1

Compal Confidential PCB CPU PCH GPU Samsung 7G for G0/G1/Q1/Q3 Micron 7G for G0/G1/Q1/Q3 RE301 RE301
UH1 SR3Z0@ UH1 SR3Z1@ UV18 N18PQ1@ UV23 UV24
ZZZ UH2 SR40E@ UV23 UV24
R3 R3
Project Code :
File Name : SR3Z0 3E10h U-0 nvPRO SR3Z1 3E10h U-0 vPRO N18P-Q1-A1 FCBGA 908P GPU MT51J256M32HF-70:A MT51J256M32HF-70:A
62K_0402_5%
N17PG0@
130K_0402_5%
UMA@
PCB 26W LA-F541P R10 M/B GOLD CL8068403373522 CL8068403373614 SR40E CM246 B-0 K4G80325FB-HC28 K4G80325FB-HC28 VRAMM@ VRAMM@
3PHASEPCB@ VRAMS@ VRAMS@ RE301 RE301CE3319 CONFIG
UV18 N17PG0@ UV25 UV26
UH1 SR3YZ@ UH1 SR3YY@ UV25 UV26
R3 240K 4700p
ZZZ
MPR3
130K 4700p UMA
33K_0402_5%
N17P-G0-A1 FCBGA 908P GPU MT51J256M32HF-70:A MT51J256M32HF-70:A N17PG1@ 62K 4700p N17P-G0
SR3YZ 3EC4h U-0 vPRO SR3YY 3EC4h U-0 nvPRO K4G80325FB-HC28 K4G80325FB-HC28 VRAMM@ VRAMM@
CL8068403359725 CL8068403359524 VRAMS@ VRAMS@ 33K 4700p N17P-G1
PCB 26W LA-G341P REV0 M/B RV652 RV645 RV653 RE301
4PHASEPCB@ RV652 RV651 RV653 8.2K 4700p N18P-Q1
UH1 SRCKN@ UV18 N18PQ3@
R1 4.3K 4700p N18P-Q3
2K 4700p
100K_0402_5% 100K_0402_5% 100K_0402_5% 8.2K_0402_5%
D 100K_0402_5% 100K_0402_5% 100K_0402_5% VRAMM@ VRAMM@ VRAMM@ N18PQ1@ 1K 4700p D
SRCKN 3EC4h U-0 nvPRO N18P-Q3-A1 FCBGA 908P GPU VRAMS@ VRAMS@ VRAMS@
CL8068403805708 RE301

UH1 SR3YX@ UV18 N17PG1@

Hynix 7G for G0/G1 4.3K_0402_5%