Computer System

11 Memory

Tim Dosen
Reference
Computer Organization And
Architecture 10th Global Edition,
William Stallings, Pearson
Education
Characteristics of Memory
Characteristics
1. Location
2. Capacity
3. Unit of transfer
4. Access method
5. Performance
6. Physical type
7. Physical characteristics
8. Organisation
1/8 Location
• Internal
• Register
• Cache
• Main Memory
• External
• Storage
2/8 Capacity
• Typically expressed in terms of bytes (1 byte = 8 bits) or words
• Word size
• The natural unit of organisation
• Number of words
• or Bytes
3/8 Unit of Transfer
Unit of transfer is equal to the number of electrical lines into and out of
the memory module.
• Internal
• Usually governed by data bus width
• External
• Usually, a block which is much larger than a word
4/8 Access Methods (1)
• Sequential
• Start at the beginning and read
through in order
• Access time depends on location
of data and previous location
• e.g. tape
4/8 Access Methods (2)
• Direct
• Individual blocks have unique
address
• Access is by jumping to vicinity
plus sequential search
• Access time depends on location
and previous location
• e.g. disk
4/8 Access Methods (3)
• Random
• Individual addresses identify locations exactly
• Access time is independent of location or previous access
• e.g. RAM
• Associative
• Data is located by a comparison with contents of a portion of the store
• Access time is independent of location or previous access
• e.g. cache
5/8 Memory Hierarchy
• Registers
• In CPU

• Main memory
• May include one or more
levels of cache
• “RAM”

• External memory
• Backing store
6/8 Performance
• Access time
• Time between presenting the address and getting the valid data

• Memory Cycle time

• Time may be required for the memory to “recover” before next access
• Cycle time is access + recovery

• Transfer Rate
• Rate at which data can be moved
7/8 Physical Types
• Semiconductor
• RAM
• Magnetic
• Disk & Tape
• Optical
• CD & DVD
• Others
• Bubble
• Hologram
8/8 Physical Characteristics
• Volatility
• Volatile: data decays naturally or is lost when electrical power is switched off
• Non-Volatile: data once recorded remains without deterioration until
deliberately changed (Magnetic-surface memories)
• Erasable
• Non-erasable: data cannot be altered, except by destroying the storage unit
(ROM)
• Power consumption
Cache Memory Principle
Cache Memory
• Cache memory is designed to combine the memory access time of
expensive, highspeed memory combined with the large memory size
of less expensive, lower-speed memory.

• The cache contains a copy of portions of main memory. When the

processor attempts to read a word of memory, a check is made to
determine if the word is in the cache. If so, the word is delivered to
the processor. If not, a block of main memory, consisting of some
fixed number of words, is read into the cache and then the word is
delivered to the processor.
Cache
• Small amount of fast memory

• Sits between normal main

memory and CPU

• May be located on CPU chip or

module
Cache/Main Memory Structure
Cache operation – overview
• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of main memory is in each
cache slot
Cache Read
Operation

RA: Read Address

Cache Design
Typical Cache Organization
Cache Design
• Size
• Mapping Function
• Replacement Algorithm
• Write Policy
• Block Size
• Number of Caches
Cache Size
• Small enough so that the overall average cost per bit is close to that
of main memory alone; and
• Large enough so that the overall average access time is close to that
of the cache alone.
Size does matter
• Cost
• More cache is expensive (created using SRAM Static RAM, data doesn’t need
to be refreshed as opposed to DRAM)

• Speed
• More cache is faster (up to a point)
• Checking cache for data takes time
Comparison
of Cache
Sizes
Cache Mapping Function
Mapping Function
• Cache of 64kByte
• Cache block of 4 bytes
• i.e. cache is 16k (214) lines of 4 bytes
• 16MBytes main memory
• 24 bit address
• (224=16M)
1/3 Direct Mapping
1/3 Direct Mapping
• A particular block of main
memory can map only to a
particular line of the cache.

• How to define Line No in cache :

• Cache line number = (Memory

Block Address) Mod (Number of
lines in Cache)
2/3 Associative Mapping
2/3 Associative Mapping
• A block of main memory can
map to any line of the cache that
is freely available at that
moment.

• This makes fully associative

mapping more flexible than
direct mapping.
3/3 Two-Way set Mapping
3/3 Two-Way set Mapping

• Cache lines are grouped into sets where each

set contains k-number of lines.

• A particular block of main memory can map

to only one particular set of the cache.

• However, within that set, the memory block

can map any cache line that is freely available.
Replacement Algorithms (1)
Direct mapping
• No choice
• Each block only maps to one line
• Replace that line
Replacement Algorithms (2)
Associative & Set Associative
• Hardware implemented algorithm (speed)
• Algorithm:
• Least Recently used (LRU)
• First in first out (FIFO)
• replace block that has been in cache longest
• Least frequently used
• replace block which has had fewest hits
• Random
Cache Write Policy
Write Policy
• Must not overwrite a cache block unless main memory is up to date
• Multiple CPUs may have individual caches
• I/O may address main memory directly

• There are 2 methods when a system is writing into cache memory:

1/2 Write through
• All writes go to main memory as well as cache
• Multiple CPUs can monitor main memory traffic to keep local (to CPU)
cache up to date

• Downside:
• Lots of traffic
• Slows down writes
2/2 Write back
• Updates initially made in cache only
• Update bit for cache slot is set when update occurs
• If block is to be replaced, write to main memory only if update bit is
set

• Downside:
• Other caches get out of sync
• I/O must access main memory through cache
• N.B. 15% of memory references are writes
More reading
• How Memory Is Accessed (intel.com)
• AMD Infinity Cache Explained : L3 Cache Comes To The GPU! | Tech
ARP
Internal Memory Types
Semiconductor Memory Types

Volatile means it needs power to maintain data on memory.

Semiconductor Memory
• RAM
• Misnamed as all semiconductor
memory is random access
• Read/Write
• Volatile
• Temporary storage
• Static or dynamic
Memory Cell Operation
Dynamic RAM
• Bits stored as charge in capacitors
• Essentially analogue
• Level of charge determines value
• Charges leak
• Need refreshing even when powered
• Simpler construction
• Smaller per bit
• Less expensive
• Slower
• Main memory
DRAM Operation
• Address line active when bit read or written
• Transistor switch closed (current flows)
• Write
• Voltage to bit line
• High for 1 low for 0
• Then signal address line
• Transfers charge to capacitor
• Read
• Address line selected
• transistor turns on
• Charge from capacitor fed via bit line to sense amplifier
• Compares with reference value to determine 0 or 1
• Capacitor charge must be restored
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
• Uses flip-flops
Static RAM Operation
• Transistor arrangement gives stable logic state
• State 1
• C1 high, C2 low
• T1 T4 off, T2 T3 on
• State 0
• C1 low, C2 high
• T1 T4 on, T2 T3 off
• Address line transistors T5 T6 is switch
• Write – apply value to B & compliment to B
• Read – value is on line B
SRAM v DRAM
• Both volatile
• Power needed to preserve data

• Dynamic cell • Static

• Simpler to build, smaller • Faster
• More dense • Cache
• Less expensive
• Needs refresh
• Larger memory units
Read Only Memory (ROM)
• Permanent storage
• Nonvolatile
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS)
• Function tables
Types of ROM
• Written during manufacture
• Very expensive for small runs
• Programmable (once)
• PROM
• Needs special equipment to program
• Read “mostly”
• Erasable Programmable (EPROM)
• Erased by UV
• Electrically Erasable (EEPROM)
• Takes much longer to write than read
• Flash memory
• Erase whole memory electrically
Internal Memory Organisation
Organisation in detail
• A 16Mbit chip can be organised as 1M of 16 bit words
• A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word
in chip 1 and so on
• A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
• Reduces number of address pins
• Multiplex row address and column address
• 11 pins to address (211=2048)
• Adding one more pin doubles range of values so x4 capacity
Refreshing
• Current generation of chips (DDR
SDRAM) has a refresh time of 64ms
• Refresh circuit included on chip and 8,196 rows, so the refresh cycle
• Disable chip interval is 7.8μs.
• Count through rows • Refresh Method:
• Read & Write back • CBR: CAS before RAS
• current method in all computer
• Takes time • on-chip counter keeps track of the row to be
refreshed
• Slows down apparent
• the external circuit initiates the refresh cycles
performance
• Hidden Refresh
• CBR with modification
• Refresh is done during data transfer
• Saving time
Typical 16 Mb DRAM (4M x 4)
Packaging
Error Correction
• Hard Failure
• Permanent defect
• Soft Error
• Random, non-destructive
• No permanent damage to memory
• Detected using Hamming error correcting code
Error Correcting Code Function
Advanced DRAM Organization
• Basic DRAM same since first RAM chips

• Enhanced DRAM
• Contains small SRAM as well
• SRAM holds last line read (Cache)

• Cache DRAM
• Larger SRAM component
• Use as cache or serial buffer
Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
• Address is presented to RAM
• RAM finds data (CPU waits in conventional DRAM)
• Since SDRAM moves data in time with system clock, CPU knows when data will be
ready
• CPU does not have to wait, it can do something else
• Burst mode allows SDRAM to set up stream of data and fire it out in block
• DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)
RAMBUS
• Adopted by Intel for Pentium & Itanium
• Main competitor to SDRAM
• Vertical package – all pins on one side
• Bus addresses up to 320 RDRAM chips at 1.6Gbps
• Asynchronous block protocol
• 480ns access time
• Then 1.6 Gbps
RAMBUS Diagram
DDR SDRAM
• SDRAM can only send data once per clock
• Double-data-rate SDRAM can send data twice per clock cycle
• Rising edge and falling edge
Magnetic Disk
External Memory
Magnetic Disk
• Disk substrate coated with
magnetizable material (iron oxide…rust)
• Substrate used to be aluminium
• Now glass
• Improved surface uniformity
• Increases reliability
• Reduction in surface defects
• Reduced read/write errors
• Lower flight heights (See later)
• Better stiffness
• Better shock/damage resistance
 Read and Write Mechanisms
• Recording & retrieval via conductive coil called a
head
• May be single read/write head or separate ones
• During read/write, head is stationary, platter rotates
• Write
• Current through coil produces magnetic field
• Pulses sent to head
• Magnetic pattern recorded on surface below
• Read (traditional)
• Magnetic field moving relative to coil produces
current
• Coil is the same for read and write
• Read (contemporary)
• Separate read head, close to write head
• Partially shielded magneto resistive (MR) sensor
• Electrical resistance depends on direction of magnetic
field
• High frequency operation
• Higher storage density and speed
Data Organization and
Formatting
• Concentric rings or tracks
• Gaps between tracks
• Reduce gap to increase capacity
• Same number of bits per track (variable
packing density)
• Constant angular velocity
• Tracks divided into sectors
• Minimum block size is one sector
• May have more than one sector per block
 Disk Velocity
• Bit near centre of rotating disk passes fixed point slower
than bit on outside of disk
• Increase spacing between bits in different tracks
• Rotate disk at constant angular velocity (CAV)
• Gives pie shaped sectors and concentric tracks
• Individual tracks and sectors addressable
• Move head to given track and wait for given sector
• Waste of space on outer tracks
• Lower data density
• Can use zones to increase capacity
• Each zone has fixed bits per track
• More complex circuitry
Comparison of Disk Layout Methods
Finding Sectors
• Must be able to identify start of track and sector
• Format disk
• Additional information not available to user
• Marks tracks and sectors
Winchester Disk Format
Seagate ST506
Hard Disk Comparison
Speed
• Seek time
• Moving head to correct track
• (Rotational) latency
• Waiting for data to rotate under head
• Access time = Seek + Latency
• Transfer rate
Timing of Disk I/O Transfer
Solid State Drive
External Memory
Architecture
• Controller: Provides SSD device
level interfacing and firmware
execution.

• Addressing: Logic that performs

the selection function across the
flash memory components.

• Data buffer/cache: High speed

RAM memory components used
for speed matching and to
increased data throughput.

• Error correction: Logic for error

detection and correction.

• Flash memory components:

Individual NAND flash chips.
SSD Solid State Drive
• Made from semiconductor chips
• Non-volatile types (data stays when
power is out)
• A device to store data similar to Flash
Drive.
• The device is not moving like
magnetic disk, hence Solid State.
Comparison of Solid State Drives and Disk Drives
Two Types of Flash Memory
• NOR and NAND, both contain transistors.

Difference:
• Wiring method
• Cells in NOR are wired in parallel
• Cells in NAND are wired in series
• Wiring requirement
• NOR uses more wiring, cannot be packed together like NAND
• NAND uses less wiring, can be packed more tightly
• Because of these wiring method
• NOR ideal for lower-density, high-speed, read-only application
• NAND is less expensive, can read/write much faster
NOR NAND
SSD Solid State Drive
• Solid State Drive is a device that uses
NAND flash to provide non-volatile
rewritable memory.

• SSD, even though very much like

RAM, can be use as hard drive
replacement.
Storing Data
• NAND Flash has transistors arranged in a grid with column and rows.
• If a chain of transistors conducts current, it has the value of 1,
otherwise, 0.
• It has Control Gate and Floating Gate. When Floating gate is charge, it
means bit 1, otherwise bit 0.
NAND Flash’s Gates Under Microscope

(Oxide-Nitrite-Oxide)
Types of Cells in NAND Flash
• Single-level cell (SLC) NAND
• Store one bit, 1 or 0
• Faster to read/write, wears longer

• Multi-level cells (MLC) NAND

• Store two bits per cells
• Longer to read/write, wears quickly

• Triple-level cells (TLC) NAND

• Store three bits per-cells
• Longer to read/write, wears quickly than MLC
Types of Cells in NAND Flash
SSD Advantages
• No moving part like magnetic disk. It means longer lifetime.

• Data delivery is very quick, no need to adjust reading arm like

magnetic disk.

• Consume less power than magnetic disk.

SSD Disadvantage
• Expensive.

• NAND Flash has finite number of writes.

• Some charge is left in the floating-gate each erasing (changes its
resistance). As the resistance builds, the amount of current required
to change the gate increases. Eventually, the gate can't be flipped at
all, rendering it useless.
• Before writing new bits, it must erase residence charge
• NAND Flash wears about 5.000 cycles.
 RAID

• Redundant Array of Independent Disks

• Redundant Array of Inexpensive Disks
• 6 levels in common use
• Not a hierarchy
• Set of physical disks viewed as single
logical drive by O/S
• Data distributed across physical drives
• Can use redundant capacity to store
parity information
RAID 0
• No redundancy • Multiple data requests probably not
on same disk
• Data striped across all disks • Disks seek in parallel
• Round Robin striping • A set of data is likely to be striped
• Increase speed across multiple disks
RAID 1
• Mirrored Disks • Write to both
• Data is striped across disks • Recovery is simple
• 2 copies of each stripe on separate • Swap faulty disk & re-mirror
disks • No down time
• Read from either • Expensive
RAID 2
• Disks are synchronized • Multiple parity disks store Hamming
• Very small stripes code error correction in
• Often single byte/word
corresponding positions
• Error correction calculated across • Lots of redundancy
corresponding bits on disks • Expensive
• Not used
RAID 3
• Similar to RAID 2 • Data on failed drive can be
• Only one redundant disk, no matter reconstructed from surviving data
how large the array and parity info
• Simple parity bit for each set of • Very high transfer rates
corresponding bits
RAID 4
• Each disk operates independently • Bit by bit parity calculated across
• Good for high I/O request rate stripes on each disk
• Large stripes • Parity stored on parity disk
 RAID 5
• Like RAID 4 • Avoids RAID 4 bottleneck at parity
• Parity striped across all disks disk
• Round robin allocation for parity • Commonly used in network servers
stripe
RAID 6
• Two parity calculations • High data availability
• Stored in separate blocks on • Three disks need to fail for data loss
different disks • Significant write penalty
• User requirement of N disks
needs N+2
RAID 0

Data
Mapping