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Vlsi Record 6

The document describes the design and simulation of a Booth multiplier using Verilog code. It includes the source code, flowchart, Booth algorithm, testbench, and output results including the simulation, schematic, power and delay analyses.

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36 views5 pages

Vlsi Record 6

The document describes the design and simulation of a Booth multiplier using Verilog code. It includes the source code, flowchart, Booth algorithm, testbench, and output results including the simulation, schematic, power and delay analyses.

Uploaded by

Anika
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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2021105011/VLSI RECORD

Expt. No: 9
Date: 27/03/2024 IMPLEMENTATION OF BOOTH MULTIPLIER

AIM:

To design and simulate Booth Multiplier using Verilog code and Basys3 board.

REQUIREMENTS:

SOFTWARE: VIVADO 2021.1

HARDWARE: BASYS3

SOURCE CODE:

module booth_multi(X, Y, Z);


input signed [3:0] X, Y;
output signed [7:0] Z;
reg signed [7:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [3:0] Y1;
always @ (X, Y)
begin
Z = 8'd0;
E1 = 1'd0;
for (i = 0; i < 4; i = i + 1)
begin
temp = {X[i], E1};
Y1 = - Y;
case (temp)
2'd2 : Z [7 : 4] = Z [7 : 4] + Y1;
2'd1 : Z [7 : 4] = Z [7 : 4] + Y;
default : begin
end
endcase

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2021105011/VLSI RECORD

FLOWCHART:

BOOTH ALGORITHM:

BOTH POSITIVE
[7 X 4]
A3 A2 A1 A0 Q3 Q2 Q1 Q0 Q-1 OPERTATION

0 0 0 0 0 1 0 0 0 Initial
0 0 0 0 0 0 1 0 0 Right Shift
0 0 0 0 0 0 0 1 0 Right Shift
1 0 0 1 0 0 0 1 0 A A-B
1 1 0 0 1 0 0 0 1 Right Shift
0 0 1 1 1 0 0 0 1 A A+B
0 0 0 1 1 1 0 0 0 Right Shift
ANS = 7 X 4 =28; 0111 X 0100 = 00011100 and -1 x 2 = -2; 1111 x 0010 = 11111110

ONE POSITIVE AND ONE NEGATIVE


[-1 X 2]
A3 A2 A1 A0 Q3 Q2 Q1 Q0 Q-1 OPERTATION

0 0 0 0 0 0 1 0 0 Initial
0 0 0 0 0 0 0 1 0 Right Shift
0 0 0 1 0 0 0 1 0 A A-B
0 0 0 0 1 0 0 0 1 Right Shift
1 1 1 1 1 0 0 0 1 A A+B
1 1 1 1 1 1 0 0 0 Right Shift
1 1 1 1 1 1 1 0 0 Right Shift

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2021105011/VLSI RECORD

Z = Z >> 1;
Z[7] = Z[6];
E1 = X[i];
end if (Y == 4'd8)
begin
Z = - Z;
end
end
endmodule

TESTBENCH:

module boothmult_TB();
// Inputs
reg [3:0] X;
reg [3:0] Y;
// Outputs
wire [7:0] Z;
// Instantiate the Unit Under Test (UUT)
booth_multi uut (
.X(X),
.Y(Y),
.Z(Z) );
initial begin
// Initialize Inputs
X = 0;
Y = 0;
// Wait 100 ns for global reset to finish
#100;
X=7;
Y=4;
#100;
X=-1;
Y=2;
#100;
$finish;
// Add stimulus here
end
endmodule

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2021105011/VLSI RECORD

OUTPUTS:
(i) Simulation Result:

(ii) RTL Schematic:

(iii) Power Analysis:

(iv) Design Utilization:

(v) Delay Analysis:

TOTAL DELAY LOGIC DELAY NET DELAY


SET UP 9.430 5.624 3.806
HOLD 2.583 1.595 0.988

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2021105011/VLSI RECORD

RESULT:

Thus, the implementation of booth multiplier using Vivado and Basys3 has been done
and verified.

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