Training
UVM ASSIGNMENT-2
Questions
1) What is the difference between a sequence and sequence item?
Sequence is like a generator.
Inside the sequence we instantiate the sequence_item.
Sequence_item helps to generate the sequence.
2) What is the difference between get_name () and get_full_name () methods in a
uvm_object class?
get_name ():
Returns the name of the object, as provided by the name argument in
the new constructor or set_name method.
get_full_name ():
Returns the full hierarchical name of this object. The default implementation is
the same as get_name, as uvm_objects do not inherently possess hierarchy.
3) What is the difference between a monitor and a scoreboard in UVM?
Monitor:
Extract signal level info and translate to objects/events or high level
information.
Passes this info to other testbench components through TLM
connections.
Usually passes info to coverage collectors or scoreboards using
analysis_ports/exports.
Scoreboard:
Receives the data from monitor and compares them with expected
values
Expected values generated from reference model.
4) Which method activates UVM testbench and how is it called?
Test is the top-level class that instantiates Env, configure the testbench
and initiates construction.
Testbench activated with a call to run_test() which starts build phases.
5) What steps are needed to run a sequence?
Step1- sequence creation
Step2- sequence configuration
Step3-starting the sequence
6) Explain the protocol handshake between a sequencer and driver?
Connected using TLM ports.
Driver pulls data from the sequencer using get_next item ().
Driver has a sequence_item_port that is connected to a
sequence_item_export in the sequencer.
7) What are pre_body() and post_body() functions in a sequence? Do they always
get called?
Pre_body():
This task is a user-definable callback that is called before the execution of
body only when the sequence is started with start. If start is called
with call_pre_post set to 0, pre_body is not called.
Post_body():
This task is a user-definable callback task that is called after the
execution of body only when the sequence is started with start If start is called
with call_pre_post set to 0, post_body is not called unless the sequence is
started with call_pre_post=0. This method should not be called directly by the
user
8) What are the different arbitration mechanisms available for a sequencer?
o UVM_SEQ_ARB_FIFO
o UVM_SEQ_ARB_WEIGHTED
o UVM_SEQ_ARB_RANDOM
o UVM_SEQ_ARB_STRICT_FIFO
o UVM_SEQ_ARB_STRICT_RANDOM
o UVM_SEQ_ARB_USER
9) How do we specify the priority of a sequence when it is started on a
sequencer?
Inside the test it checks what are all the sequences available,
Run_test() decides which sequence is to be perform to the sequencer.
10) How can a sequence get exclusive access to a sequencer?
lock () – by using this method sequence can get exclusive access to a
sequencer
11) What is the difference between a grab () and a lock () on sequencer?
grab ()
grab () request is put infront of the arbitration queue. A grab () request
will be arbitrated before any other requests.
grab is blocking task.
If no argument is supplied, then current default sequencer is chosen.
lock ()
lock() request is put in back of the arbitration queue. A lock request
will be arbitrated the same as any other request.
lock is blocking task and when access is granted, it will unblock.
If no argument is supplied, then current default sequencer is chosen.
12) What is the difference between a pipelined and a non-pipelined
sequencedriver model?
Pipelined: If the driver models more than one active transaction at a time,
then it is called a pipelined model. In this case sequence can keep sending
new transactions to driver without waiting for driver to complete a previous
transaction
Non-pipelined: If the driver models only one active transaction at a time, then
it is called a non-pipelined model. In this case, sequence can send one
transaction to the driver and driver might take several cycles to finish driving
that transaction. Only after that the driver will accept a new transaction from
sequencer
13) How do we make sure that if multiple sequences are running on a sequencerdriver,
responses are sent back from driver to the correct sequence?
If responses are returned from the driver for one of several sequences, the
sequence id field in the sequence is used by the sequencer to route the
response back to the right sequence. The response handling code in the
driver should use the set_id_info() call to ensure that any response items
have the same sequence id as their originating request.
14) What is m_sequencer handle?
m_sequencer handle – contains the reference to the sequencer on
which sequence is running.
Sequence can access any information and other resources handles
in the UVM component hierarchy.
15) What is a p_sequencer handle and how is it different in m_sequencer?
m_sequencer is a handle type uvm_sequencer_base which is available
by-default in a uvm_sequence.
p_sequencer is to access the real sequencer on which sequence is
running.
16) What is a subsequence?
A subsequence is a sequence that is started from another sequence. From the
body () of a sequence, if start () of another sequence is called, it is generally
called a subsequence.
17) What is the difference between get_next_item() and try_next_item() methods in
UVM driver class?
get_next_item() :is a blocking call (part of the driver-sequencer API) which
blocks until a sequence item is available for driver to process, and returns a
pointer to the sequence item.
try_next_item(): is a nonblocking version which returns a null pointer if no
sequence item is available for driver to process.
18) What is the difference between get_next_item() and get() methods in UVM
driver class?
get_next_item() :
It is a blocking call to get the sequence item from the sequencer FIFO for
processing by driver. Once the sequence item is processed by driver, it needs
to call item_done() to complete the handshake before a new item is requested
using get_next_item().
get () :
It is also a blocking call which gets the sequence item from sequencer FIFO for
processing by driver. However, while using get (), there is no need to explicitly
call item_done() as the get() method completes the handshake implicitly
19) What is the difference in item_done() method of driver-sequencer API when
called with and without arguments?
current_grabber function from the sequencer base class to get a handle of the
sequence which currently has a lock or grab on the sequence.
stop_sequences will stop the sequence currently loaded on a sequence.
20) How can you stop all sequences running on a sequencer?
item_done():
method is a nonblocking method in driver class that is used to complete
handshake with the sequencer after a get_next_item() or try_next_item() is
successful. If there is no need to send a response back, item_done() is called
with no argument which will complete the handshake without placing
anything in the sequencer response FIFO. If there is a need to send a
response back, item_done() is passed with a pointer to a response
sequence_item as an argument.
21) i) What is a virtual sequence and where do we use a virtual sequence? ii)
What are its benefits?
A virtual sequence is a sequence whose purpose is to manage the behaviour
of sequences in other sequencers.it is a container class to start multiple
sequences on different sequencers in the environment.
Benefits: we can be able to run different sequences on different environments
any time
22) Given a simple single port RAM as shown below that can either do a read or a
write to an address, write a sequence and driver following UVM to test for read
and write. Assume that read_enable=1 means read and write_enable=1
means write. Only one of read or write can happen in a single cycle.
https://www.edaplayground.com/x/EEuL
23) How can we implement a simulation timeout mechanism in
UVM methodology?
set_global_timeout(timeout) – is a convenience function that sets uvm_top.
phase_timeout variable with the timeout value. If the run () phase doesn’t end
before this timeout value, then the simulation is stopped and an error is
reported.
24) Is it possible for a component lower in testbench hierarchy to pass a handle to
a component in higher level of hierarchy using get/set config methods?
The higher-level component sets up configuration data base with handles and
the lower-level components do get them using get/set methods.
25) i) What is the recommended way of assigning virtual interfaces to different
components in a UVM verification methodology?
In uvm, virtual sequence can be implemented using 2 approaches
1)In the 1st approach, virtual sequence will contain itself the handles of the
agent’s sequencer on which the sub-sequences are to be executed.
2)In the 2nd approach, virtual sequence will run on a virtual sequencer which
is of type uvm_sequencer. In this approach, virtual sequencer will contain the
target agent sequencer’s handle.
26) What is UVM RAL (UVM Register Abstraction Layer)?
UVM RAL - Register Abstraction Layer:
It is a feature supported in UVM that helps in verifying the registers in a
design as well as in configuration of DUT using an abstract register model.
The UVM register model provides a way of tracking the register content of a
DUT and a convenience layer for accessing register and memory locations
within the DUT.
27) What is UVM Call back?
The uvm_callback class is a base class for implementing callbacks,
which are typically used to modify or augment component behavior
without changing the component class.
The methods are used to implement overriding of the component class
behavior.
28) What is UVM_root class?
The uvm_root class serves as the implicit top-level and phase controller for all
UVM components. Users do not directly instantiate uvm_root. The UVM
automatically creates a single instance of uvm_root that users can access via
the global (uvm_pkg-scope) variable, uvm_top.
29) What is the parent class for uvm_test?
uvm_top – it is assigned as the parent of test class.
30) i) How UVM Phases Initiate?
Once the run_test() method is called, it constructs the root component of the
UVM environment & then triggers/initiates the UVM Phasing process.
ii) How Test Cases Run from Simulation Command Line?
A test is usually started within testbench top by a task called
run_test.
If +UVM_TESTNAME is specified, the UVM factory creates a
component of the given test type and starts its phase mechanism.
Fatal error – If the specified test is not found or created by the
factory.
If no test is specified via command-line and the argument to the
run_test() task is blank, then all the components constructed before
the call to run_test() will be cycled through their simulation phases.
