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TAS5630B
SLES217D – NOVEMBER 2010 – REVISED MARCH 2015

TAS5630B 300-W Stereo and 400-W Mono PurePath™ HD Analog-Input Power Stage
1 Features 3 Description
1• PurePath™ HD Enabled Integrated Feedback The TAS5630B device is a high-performance analog-
Provides: input class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
– Signal Bandwidth up to 80 kHz for High- technology) with the ability to drive up to 300 W (1)
Frequency Content From HD Sources stereo into 4-Ω to 8-Ω speakers from a single 50-V
– Ultralow 0.03% THD at 1 W into 4 Ω supply.
– Flat THD at All Frequencies for Natural Sound PurePath HD technology enables traditional AB-
– 80-dB PSRR (BTL, No Input Signal) amplifier performance (< 0.03% THD) levels while
providing the power efficiency of traditional class-D
– > 100-dB (A-weighted) SNR
amplifiers.
– Click- and Pop-Free Start-up
Unlike traditional class-D amplifiers, the distortion
• Multiple Configurations Possible on the Same
curve does not increase until the output levels move
PCB With Stuffing Options: into clipping.
– Mono Parallel Bridge-Tied Load (PBTL)
PurePath HD technology enables lower idle losses,
– Stereo Bridge-Tied Load (BTL) making the device even more efficient. When coupled
– 2.1 Single-Ended Stereo Pair and BTL with TI’s class-G power-supply reference design for
Subwoofer TAS563x, industry-leading levels of efficiency can be
– Quad Single-Ended Outputs achieved.
• Total Output Power at 10% THD+N Device Information(1)
– 400 W in Mono PBTL Configuration PART NUMBER PACKAGE BODY SIZE (NOM)
– 300 W per Channel in Stereo BTL HSSOP (44) 15.90 mm × 11.00 mm
TAS5630B
Configuration HTQFP (64) 14.00 mm × 14.00 mm
– 145 W per Channel in Quad Single-Ended (1) For all available packages, see the orderable addendum at
Configuration the end of the data sheet.
• High-Efficiency Power Stage (> 88%) With 60-mΩ
Output MOSFETs Typical TAS5630B Application Block Diagram
3 ´ OPA1632
• Two Thermally Enhanced Package Options:
♫♪
– PHD (64-Pin QFP)
TM
– DKD (44-Pin PSOP3) ANALOG PurePath HD
AUDIO TAS5630B ♫♪
• Self-Protection Design (Including Undervoltage, INPUT (2.1 Configuration)
Overtemperature, Clipping, and Short-Circuit ♫♪
Protection) With Error Reporting ±15 V 12 V 25 V–50 V

• EMI Compliant When Used With Recommended

TM
System Design PurePath HD
Class-G Power Supply
Ref. Design
2 Applications
• Mini Combo System 110 VAC ® 240 VAC

• AV Receivers (1) Achievable output power levels are dependent on the thermal
configuration of the target application. A high-performance
• DVD Receivers thermal interface material between the exposed package heat
• Active Speakers slug and the heat sink should be used to achieve high output
power levels.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5630B
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Table of Contents
1 Features .................................................................. 1 7.1 Overview ................................................................. 14
2 Applications ........................................................... 1 7.2 Functional Block Diagram ....................................... 14
3 Description ............................................................. 1 7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 18
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4 8 Application and Implementation ........................ 19
8.1 Application Information............................................ 19
6 Specifications......................................................... 7
8.2 Typical Application .................................................. 20
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7 9 Power Supply Recommendations...................... 27
6.3 Recommended Operating Conditions....................... 7 10 Layout................................................................... 27
6.4 Thermal Information .................................................. 8 10.1 Layout Guidelines ................................................. 27
6.5 Electrical Characteristics........................................... 8 10.2 Layout Example .................................................... 28
6.6 Audio Characteristics (BTL) .................................... 10 11 Device and Documentation Support ................. 30
6.7 Audio Specification (Single-Ended Output) ............ 10 11.1 Trademarks ........................................................... 30
6.8 Audio Specification (PBTL) .................................... 11 11.2 Electrostatic Discharge Caution ............................ 30
6.9 Typical Characteristics ............................................ 11 11.3 Glossary ................................................................ 30
7 Detailed Description ............................................ 14 12 Mechanical, Packaging, and Orderable
Information ........................................................... 30

4 Revision History
Changes from Revision C (September 2012) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Changed Thermal Information table data. .............................................................................................................................. 8

Changes from Revision B (November 2011) to Revision C Page

• Changed Analog comparator reference node, VI_CM Vlaues From: MIN = 1.5 TYP = 1.75 MAX = 1.9 To: MIN =
1.75 TYP = 2 MAX = 2.15 ...................................................................................................................................................... 8
• Changed ANALOG INPUTS - VIN TYP value From 3.5 to 5 VPP............................................................................................ 8
• Changed the VIH and VIL Test Conditions From: INPUT_X, M1, M2, M3, RESET To: M1, M2, M3, RESET ........................ 9
• Deleted - RL = 2 Ω, 1% THD+N, unclipped output signal From PO in the Audio Specification (PBTL) table....................... 11

Changes from Revision A (November 2011) to Revision B Page

• Changed the RINT_PU parameters from /OTW1 to VREG, /OTW2 to VREG, /SD to VREG to /OTW, /OTW1, /OTW2,
/CLIP, READY, /SD to VRE.................................................................................................................................................... 9
• Added text to the PHD Package section. ............................................................................................................................. 17
• Added text to the DKD Package section .............................................................................................................................. 17

Changes from Original (November 2010) to Revision A Page

• Changed Title From: 600-W MONO To: 400-W MONO......................................................................................................... 1

• Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL
Configuration .......................................................................................................................................................................... 1
• Changed the Pin One Location Package image .................................................................................................................... 5
• Changed RL(PBTL) Load Impedance Min value From: 1.6 Ω To: 2.4 Ω, and Typ value From 2 To: 3 Ω ............................. 7
• Added footnotes to the ROC table ......................................................................................................................................... 7
• Added ROCP information to the ROC Table ............................................................................................................................ 8
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• Changed the IOC Typical Value From: 19 A To: 15 A............................................................................................................. 9

• Deleted - RL = 2 Ω, 10%, THD+N, clipped input signal From PO in the Audio Specification (PBTL) table.......................... 11
• Replaced the TYPICAL CHARACTERISTICS, PBTL CONFIGURATION graphs ............................................................... 12
• Added section - Click and Pop in SE-Mode ......................................................................................................................... 18
• Added section - PBTL Overload and Short Circuit ............................................................................................................... 18
• Replaced the PACKAGE HEAT DISSIPATION RATINGS table with the THERMAL INFORMATION table....................... 18

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5 Pin Configuration and Functions

DKD Package
44 Pins HSSOP
Top View

PSU_REF 1 44 GVDD_AB
VDD 2 43 BST_A
OC_ADJ 3 42 PVDD_A
RESET 4 41 PVDD_A
C_STARTUP 5 40 OUT_A
INPUT_A 6 39 OUT_A
INPUT_B 7 38 GND_A
VI_CM 8 37 GND_B
GND 9 36 OUT_B

44 pins PACKAGE
AGND 10 35 PVDD_B

(TOP VIEW)
VREG 11 34 BST_B
INPUT_C 12 33 BST_C
INPUT_D 13 32 PVDD_C
FREQ_ADJ 14 31 OUT_C
OSC_IO+ 15 30 GND_C
OSC_IO- 16 29 GND_D
SD 17 28 OUT_D
OTW 18 27 OUT_D
READY 19 26 PVDD_D
M1 20 25 PVDD_D
M2 21 24 BST_D
M3 22 23 GVDD_CD

PHD Package
64 Pins HTQFP
Top View
PSU_REF

GVDD_B
GVDD_A

PVDD_A
PVDD_A
GND_A
OUT_A
OUT_A
BST_A
GND
GND
VDD

NC
NC
NC
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

OC_ADJ 1 48 GND_A
RESET 2 47 GND_B
C_STARTUP 3 46 GND_B
INPUT_A 4 45 OUT_B
INPUT_B 5 44 OUT_B
VI_CM 6 43 PVDD_B
GND 7 42 PVDD_B
AGND 8 41 BST_B
VREG 9 40 BST_C
INPUT_C 10 39 PVDD_C
INPUT_D 11 38 PVDD_C
FREQ_ADJ 12 37 OUT_C
OSC_IO+ 13 36 OUT_C
OSC_IO- 14 35 GND_C
SD 15 64-pins QFP package 34 GND_C
OTW1 16 33 GND_D
26
17
18
19
20
21
22
23
24
25

27
28
29
30
31
32
OTW2

READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
CLIP

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Electrical Pin 1
Pin 1 Marker
White Dot

Figure 1. Pin One Location PHD Package

Pin Functions
PIN
FUNCTION (1) DESCRIPTION
NAME HTQFP HSSOP
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_A required.
BST_B 41 34 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_B required.
BST_C 40 33 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_C required.
BST_D 27 24 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_D required.
CLIP 18 — O Clipping warning; open drain; active-low
C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode
FREQ_ADJ 12 14 I PWM frame-rate-programming pin requires resistor to AGND
7, 23, 24, 57,
GND 9 P Ground
58
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate-drive voltage supply requires 0.1-μF capacitor to GND_A
GVDD_B 56 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_B
GVDD_C 25 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_C
GVDD_D 26 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_D
GVDD_AB — 44 P Gate drive voltage supply requires 0.22-μF capacitor to GND_A/GND_B
GVDD_CD — 23 P Gate drive voltage supply requires 0.22-μF capacitor to GND_C/GND_D
INPUT_A 4 6 I Input signal for half-bridge A
INPUT_B 5 7 I Input signal for half-bridge B
INPUT_C 10 12 I Input signal for half-bridge C
INPUT_D 11 13 I Input signal for half-bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect; pins may be grounded.

(1) I = Input, O = Output, P = Power

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Pin Functions (continued)

PIN
FUNCTION (1) DESCRIPTION
NAME HTQFP HSSOP
Analog overcurrent-programming pin requires resistor to AGND. 64-pin
OC_ADJ 1 3 O
package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ
OSC_IO+ 13 15 I/O Oscillator master/slave output/input
OSC_IO– 14 16 I/O Oscillator master/slave output/input
OTW — 18 O Overtemperature warning signal, open-drain, active-low
OTW1 16 — O Overtemperature warning signal, open-drain, active-low
OTW2 17 — O Overtemperature warning signal, open-drain, active-low
OUT_A 52, 53 39, 40 O Output, half-bridge A
OUT_B 44, 45 36 O Output, half-bridge B
OUT_C 36, 37 31 O Output, half-bridge C
OUT_D 28, 29 27, 28 O Output, half-bridge D
PSU_REF 63 1 P PSU reference requires close decoupling of 330 pF to AGND.
Power-supply input for half-bridge A requires close decoupling of 0.01-μF
PVDD_A 50, 51 41, 42 P
capacitor in parallel with 2.2-μF capacitor to GND_A.
Power-supply input for half-bridge B requires close decoupling of 0.01-μF
PVDD_B 42, 43 35 P
capacitor in parallel with 2.2-μF capacitor to GND_B.
Power-supply input for half-bridge C requires close decoupling of 0.0- μF
PVDD_C 38, 39 32 P
capacitor in parallel with 2.2-μF capacitor to GND_C.
Power-supply input for half-bridge D requires close decoupling of 0.01-μF
PVDD_D 30, 31 25, 26 P
capacitor in parallel with 2.2-μF capacitor to GND_D.
READY 19 19 O Normal operation; open-drain; active-high
RESET 2 4 I Device reset input; active-low
SD 15 17 O Shutdown signal, open-drain, active-low
Power supply for digital voltage regulator requires a 10-μF capacitor in parallel
VDD 64 2 P
with a 0.1-μF capacitor to GND for decoupling.
Analog comparator reference node requires close decoupling of 1 nF to
VI_CM 6 8 O
AGND.
VREG 9 11 P Regulator supply filter pin requires 0.1-μF capacitor to AGND.

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range unless otherwise noted
MIN MAX UNIT
VDD to AGND –0.3 13.2 V
GVDD to AGND –0.3 13.2 V
PVDD_X to GND_X (2) –0.3 69 V
OUT_X to GND_X (2) –0.3 69 V
BST_X to GND_X (2) –0.3 82.2 V
BST_X to GVDD_X (2) –0.3 69 V
VREG to AGND –0.3 4.2 V
GND_X to GND –0.3 0.3 V
GND_X to AGND –0.3 0.3 V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF to AGND –0.3 4.2 V
INPUT_X –0.3 7 V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 7 V
Continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA
Operating junction temperature, TJ 0 150 °C
Storage temperature, Tstg –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±500 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 25 50 52.5 V
GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 3.5 4
(2) (1) Output filter according to schematics in the
RL(SE) Load impedance 1.8 2 Ω
application information section
(2)
RL(PBTL) 2.4 3
LOUTPUT(BTL) 7 10
(2) (1)
LOUTPUT(SE) Output filter inductance Minimum output inductance at IOC 7 15 μH
(2)
LOUTPUT(PBTL) 7 10
Nominal 385 400 415
PWM frame rate selectable for AM interference
fPWM AM1 315 333 350 kHz
avoidance; 1% resistor tolerance.
AM2 260 300 335
Nominal; master mode 9.9 10 10.1
RFREQ_ADJ PWM frame-rate-programming resistor AM1; master mode 19.8 20 20.2 kΩ
AM2; master mode 29.7 30 30.3

(1) Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component
rating.
(2) See additional details for SE and PBTL in System Design Considerations.
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Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Voltage on FREQ_ADJ pin for slave mode
VFREQ_ADJ Slave mode 3.3 V
operation

Overcurrent-protection-programming resistor, 64-pin QFP package (PHD) 22 33

cycle-by-cycle mode 44-Pin PSOP3 package (DKD) 24 33
ROCP kΩ
Overcurrent-protection-programming resistor,
PHD or DKD 47 68
latching mode
TJ Junction temperature 0 125 °C

6.4 Thermal Information

TAS5630B
(1)
THERMAL METRIC PHD (HTQFP) DKD (HSSOP) UNIT
64 PINS 44 PINS
RθJA Junction-to-ambient thermal resistance 8.6 8.8
RθJC(top) Junction-to-case (top) thermal resistance 0.3 0.4
RθJB Junction-to-board thermal resistance 2.1 3.0 °C/W
ψJT Junction-to-top characterization parameter 0.4 0.4
ψJB Junction-to-board characterization parameter 2.1 3.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.75 2 2.15 V
Operating, 50% duty cycle 22.5
IVDD VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
IGVDD_X GVDD_x gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output
13.3 mA
IPVDD_X Half-bridge supply current filter
Reset mode, No switching 870 μA
ANALOG INPUTS
RIN Input resistance READY = HIGH 33 kΩ
Maximum input voltage with symmetrical
VIN 5 VPP
output swing
IIN Maximum input current 342 μA
G Voltage gain (VOUT/VIN) 23 dB
OSCILLATOR
Nominal, master mode 3.85 4 4.15
fOSC_IO+ AM1, master mode FPWM × 10 3.15 3.33 3.5 MHz
AM2, master mode 2.6 3 3.35
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V

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Electrical Characteristics (continued)

PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) TJ = 25°C, excludes metallization 60 100
RDS(on) mΩ
Drain-to-source resistance, high side (HS) resistance, GVDD = 12 V 60 100
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
Vuvp,G 9.5 V
VDD
Vuvp,hyst (1) 0.6 V
(1)
OTW1 Overtemperature warning 1 95 100 105 °C
OTW2 (1) Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTW
OTWhyst (1) temperature for OTW to be inactive after 25 °C
OTW event
Overtemperature error 145 155 165 °C
OTE (1)
OTE-OTW differential 30
A reset must occur for SD to be released °C
OTEhyst (1) 25
following an OTE event.
OLPC Overload protection counter fPWM = 400 kHz 2.6 ms
Resistor – programmable, nominal peak
current in 1-Ω load,
15
64-pin QFP package (PHD)
ROCP = 22 kΩ
Overcurrent limit protection
Resistor – programmable, nominal peak
IOC current in 1-Ω load, A
15
44-pin PSOP3 package (DKD),
ROCP = 24 kΩ
Resistor – programmable, nominal peak
Overcurrent limit protection, latched current in 1-Ω load, 15
ROCP = 47 kΩ
Time from switching transition to flip-state
IOCT Overcurrent response time 150 ns
induced by overcurrent
Connected when RESET is active to
Internal pulldown resistor at output of each
IPD provide bootstrap charge. Not used in SE 3 mA
half-bridge
mode
STATIC DIGITAL SPECIFICATIONS
VIH High-level input voltage 2 V
M1, M2, M3, RESET
VIL Low-level input voltage 0.8 V
Ilkg Input leakage current 100 μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW, OTW1,
RINT_PU 20 26 32 kΩ
OTW2, CLIP, READY, SD to VREG
Internal pullup resistor 3 3.3 3.6
VOH High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low-level output voltage IO = 4 mA 200 500 mV
Device fanout OTW, OTW1, OTW2, SD,
FANOUT No external pullup 30 devices
CLIP, READY

(1) Specified by design.

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6.6 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 680 nF,
MODE = 010, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 4 Ω, 10% THD+N, clipped output signal 300
RL = 6 Ω, 10% THD+N, clipped output signal 210
RL = 8 Ω, 10% THD+N, clipped output signal 160
PO Power output per channel W
RL = 4 Ω, 1% THD+N, unclipped output signal 240
RL = 6 Ω, 1% THD+N, unclipped output signal 160
RL = 8 Ω, 1% THD+N, unclipped output signal 125
THD+N Total harmonic distortion + noise 1W 0.03%
A-weighted, AES17 filter, input capacitor
Vn Output integrated noise 270 μV
grounded
|VOS| Output offset voltage Inputs ac-coupled to AGND 20 50 mV
SNR Signal-to-noise ratio (1) A-weighted, AES17 filter 100 dB
DNR Dynamic range A-weighted, AES17 filter 100 dB
(2)
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching 2.7 W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

6.7 Audio Specification (Single-Ended Output)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 15 μH, CDEM = 470 μF,
MODE = 100, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 2 Ω, 10% THD+N, clipped output signal 145
RL = 3 Ω, 10% THD+N, clipped output signal 100
RL = 4 Ω, 10% THD+N, clipped output signal 75
PO Power output per channel W
RL = 2 Ω, 1% THD+N, unclipped output signal 110
RL = 3 Ω, 1% THD+N, unclipped output signal 75
RL = 4 Ω, 1% THD+N, unclipped output signal 55
THD+N Total harmonic distortion + noise 1W 0.07%
Vn Output integrated noise A-weighted, AES17 filter, input capacitor grounded 340 μV
SNR Signal-to-noise ratio (1) A-weighted, AES17 filter 93 dB
DNR Dynamic range A-weighted, AES17 filter 93 dB
Power dissipation due to idle losses
Pidle PO = 0, four channels switching (2) 2 W
(IPVDD_X)

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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6.8 Audio Specification (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 3 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 1.5 μF,
MODE = 101-10, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 3 Ω, 10% THD+N, clipped output signal 400
RL = 4 Ω, 10% THD+N, clipped output signal 300
PO Power output per channel W
RL = 3 Ω, 1% THD+N, unclipped output signal 310
RL = 4 Ω, 1% THD+N, unclipped output signal 230
THD+N Total harmonic distortion + noise 1W 0.05%
Vn Output integrated noise A-weighted 260 μV
SNR Signal to noise ratio (1) A-weighted 100 dB
DNR Dynamic range A-weighted 100 dB
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2) 2.7 W

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

6.9 Typical Characteristics

6.9.1 BTL Configuration

10 340
4Ω 320 4Ω
6Ω 6Ω
THD+N − Total Harmonic Distortion + Noise − %

8Ω 300 8Ω
280
260
1 240
PO − Output Power − W

220
200
180
160

0.1 140
120
100
80
60
40
0.01 TC = 75°C
TC = 75°C 20 THD+N at 10%
0.005 0
20m 100m 1 10 100 400 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V
G001 G001

Figure 2. Total Harmonic + Noise vs Output Power Figure 3. Output Power vs Supply Voltage

300 100
4Ω 95
280
6Ω 90
260 8Ω 85
240 80
220 75
70
PO − Output Power − W

200 65
Efficiency − %

180 60
160 55
50
140 45
120 40
100 35
30
80 25
60 20
40 15 4Ω
10 6Ω TC = 25°C
20 5
TC = 75°C 8Ω THD+N at 10%
0 0
25 30 35 40 45 50 0 100 200 300 400 500 600 700
PVDD − Supply Voltage − V 2 Channel Output Power − W
G001 G001

Figure 4. Unclipped Output Power vs Supply Voltage Figure 5. System Efficiency vs Output Power

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BTL Configuration (continued)

100 340
95 4Ω 320
90 6Ω
8Ω 300
85
280
80
75 260
70 240

PO − Output Power − W
65 220
Power Loss − W

60 200
55
180
50
160
45
40 140
35 120
30 100
25 80
20
60
15 4Ω
10 40
TC = 25°C 6Ω
5 THD+N at 10% 20 8Ω THD+N at 10%
0 0
0 100 200 300 400 500 600 700 −10 0 10 20 30 40 50 60 70 80 90 100 110
2 Channel Output Power − W TC − Case Temperature − °C
G001 G001

Figure 6. System Power Loss vs Output Power Figure 7. Output Power vs Case Temperature

0
TC = 75°C 4Ω
−10
VREF = 35.36 V
−20 Sample Rate = 48kHz
−30 FFT Size = 16384
−40
−50
Noise Amplitude − dB

−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
f − Frequency − Hz
G001

Figure 8. Noise Amplitude vs Frequency

6.9.2 SE Configuration
1 Channel Driven

10 170
2Ω 160 2Ω
3Ω 3Ω
THD+N − Total Harmonic Distortion + Noise − %

4Ω 150 4Ω
140
130
1 120
PO − Output Power − W

110
100
90
80

0.1 70
60
50
40
30
20
0.01 TC = 75°C
TC = 75°C 10 THD+N at 10%
0.005 0
20m 100m 1 10 100 200 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V
G001 G001

Figure 9. Total Harmonic Distortion + Noise vs Output Figure 10. Output Power vs Supply Voltage
Power

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SE Configuration (continued)
180
170
160
150
140
130

PO − Output Power − W
120
110
100
90
80
70
60
50
40
30
2Ω
20
3Ω
10 4Ω THD+N at 10%
0
−10 0 10 20 30 40 50 60 70 80 90 100 110
TC − Case Temperature − °C
G001

Figure 11. Output Power vs Case Temperature

6.9.3 PBTL Configuration

10 500
3Ω 3Ω
4Ω 450 4Ω
THD+N − Total Harmonic Distortion + Noise − %

6Ω 6Ω
8Ω 8Ω
400

1 350
PO − Output Power − W
300

250

0.1 200

150

100

0.01 50 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
20m 100m 1 10 100 700 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V
G001 G001

Figure 12. Total Harmonic Distortion + Noise vs Output Figure 13. Output Power vs Supply Voltage
Power

500

450

400

350
PO − Output Power − W

300

250

200

150

100
3Ω
4Ω
50 6Ω
8Ω THD+N at 10%
0
−10 0 10 20 30 40 50 60 70 80 90 100 110
TC − Case Temperature − °C
G001

Figure 14. Output Power vs Case Temperature

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7 Detailed Description

7.1 Overview
TAS5630B is an analog input, audio PWM (class-D) amplifier. The output of the TAS5630B can be configured for
single-ended, bridge-tied load (BTL) or parallel BTL (PBTL) output. It requires two rails for power supply, PVDD
and 12 V (GVDD and VDD). The following functional block diagram shows interconnections of internal supplies,
control logic, gate drives and power amplifiers. Detailed schematic can be viewed in TAS5630B EVM User's
Guide (SLAU287).

7.2 Functional Block Diagram

/CLIP

READY

/OTW1

/OTW2

/SD

M1

PROTECTION & I/O LOGIC

M2 VDD

M3
POWER-UP
UVP VREG VREG
RESET
/RESET
AGND
TEMP GVDD_A GVDD _C
STARTUP SENSE
GND
CONTROL GVDD_B GVDD_D
C_STARTUP

OVER-LOAD CURRENT
CB3C OC_ADJ
PROTECTION SENSE
OSC_SYNC_IO+
4
OSC_SYNC_IO- OSCILLATOR PVDD_X
4
PPSC OUT_X
4
FREQ_ADJ GND_X

GVDD_A

PWM
ACTIVITY BST_A
DETECTOR
4
PSU_REF PVDD_X PVDD_A
PSU_FF
VI_CM GND
PWM TIMING
CONTROL GATE-DRIVE OUT_A
RECEIVER CONTROL

GND_A

GVDD_B

-
BST_B
ANALOG
LOOP FILTER
+
INPUT_A
PVDD_B

+ PWM TIMING
CONTROL GATE-DRIVE OUT_B
ANALOG RECEIVER CONTROL
LOOP FILTER
-
INPUT_B
GND_B
ANALOG COMPARATOR MUX
ANALOG INPUT MUX

GVDD_C

BST_C

-
INPUT_C PVDD_C
ANALOG
LOOP FILTER +
PWM TIMING
CONTROL GATE-DRIVE OUT_C
RECEIVER CONTROL
+
INPUT_D GND_C
ANALOG
LOOP FILTER
-
GVDD_D

BST_D

PVDD_D

PWM TIMING
CONTROL GATE-DRIVE OUT_D
RECEIVER CONTROL

GND_D

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7.3 Feature Description

7.3.1 Power Supplies
To facilitate system design, the TAS5630B needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see Typical Application for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See SLAU287 for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5630B reference design. For additional information on recommended power
supply and required components, see Typical Application.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630B is fully protected against erroneous
power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within
the specified range (see Recommended Operating Conditions).

7.3.2 System Power-Up and Power-Down Sequence

7.3.2.1 Powering Up
The TAS5630B does not require a power-up sequence. The outputs of the H-bridges remain in a high-
impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see Electrical Characteristics). Although not specifically required, it is
recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.

7.3.2.2 Powering Down

The TAS5630B does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see Electrical Characteristics). Although not specifically required, it is a good practice to hold RESET
low during power down, thus preventing audible artifacts including pops or clicks.

7.3.3 Error Reporting

The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.

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Feature Description (continued)

Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see Table 1).

Table 1. Error Reporting

OTW2,
SD OTW1 DESCRIPTION
OTW
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
0 0 1
warning)
0 1 1 Overload (OLP) or undervoltage (UVP)
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)

Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, for example, turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see Electrical
Characteristics for further specifications).

7.3.4 Device Protection System

The TAS5630B contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5630B responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, that is, the supply voltage has increased.
The device functions on errors, as shown in the following table.

Table 2. Device Protection System

BTL Mode PBTL Mode SE Mode
Local error in Turns Off or in Local error in Turns Off or in Local error in Turns Off or in
A A A
A+B A+B
B B B
A+B+C+D
C C C
C+D C+D
D D D

Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.

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7.3.5 Pin-to-Pin Short-Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, that is, when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device
does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and
SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection
system is not tripped, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.

7.3.6 Overtemperature Protection

The two different package options have individual overtemperature protection schemes.
PHD Package:
The TAS5630B PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until
OTW1 has cleared.
DKD Package:
The TAS5630B DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET.
Thereafter, the device resumes normal operation.

7.3.7 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5630B fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach the levels stated in Electrical
Characteristics. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-
impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply
voltages have increased above the UVP threshold.

7.3.8 Device Reset

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output; that is, SD is forced high. A rising-edge transition on reset input allows the device to resume operation
after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms
after the falling edge of SD.

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7.3.9 Click and Pop in SE-Mode

The BTL startup has low click and pop due to the trimmed output dc offset, see Audio Characteristics (BTL).
The startup of the BTL+2 x SE system (Figure 21) or 4xSE (Figure 20) is more difficult to get click and pop free,
than the pure BTL solution; therefore, evaluating the resulting click and pop before designing in the device is
recommended.

7.3.10 PBTL Overload and Short Circuit

The TAS5630B has extensive overload and short circuit protection. In BTL and SE mode, it is fully protected
against speaker terminal overloads, terminal-to-terminal short circuit, and short circuit to GND or PVDD. The
protection works by limiting the current, by flipping the state of the output MOSFETs; thereby, ramping currents
down in the inductor. This only works when the inductor is NOT saturated, the recommended minimum inductor
values are listed in Recommended Operating Conditions. In BTL mode, the short circuit currents can reach more
than 15 A, so when connecting the device in PBTL mode (Mono), the currents double – that is more than 30 A,
and with these high currents, the protection system will limit PBTL speaker overloads, terminal-to-terminal shorts,
and terminal-to-GND shorts. PBTL mode short circuit to PVDD is not recommended.

7.3.11 Oscillator
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower-value switching frequencies together result in the fewest cases of interference throughout the AM band,
and can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave-mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs, which must be slaved from an external clock.

7.4 Device Functional Modes

Table 3. Mode Selection Pins

MODE PINS OUTPUT
ANALOG INPUT DESCRIPTION
M3 M2 M1 CONFIGURATION
0 0 0 Differential 2 × BTL AD mode
0 0 1 — — Reserved
0 1 0 Differential 2 × BTL BD mode
Differential single-
0 1 1 1 × BTL +2 ×SE BD mode, BTL differential
ended
1 0 0 Single-ended 4 × SE AD mode
(1) (1)
INPUT_C INPUT_D
1 0 1 Differential 1 × PBTL 0 0 AD mode
1 0 BD mode
1 1 0
Reserved
1 1 1

(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND).

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 PCB Material Recommendation
TI recommends FR-4 2-oz. (70-μm) glass epoxy material for use with the TAS5630B. The use of this material
can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB
trace resistance).

8.1.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 μF, 63-V supports more applications.
The PVDD capacitors should be the low-ESR type, because they are used in a circuit associated with high-speed
switching.

8.1.3 Decoupling Capacitor Recommendations

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, quality decoupling capacitors should be used. In practice, X7R should be used in this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2.2-μF capacitor that is placed on the power supply to each half-bridge. The decoupling capacitor
must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high
power output, and the ripple current created by high power output. A minimum voltage rating of 63 V is required
for use with a 50-V power supply.

8.1.4 System Design Considerations

A rising-edge transition on the reset input allows the device to execute the startup sequence and starts switching.
Apply audio only when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used either to activate a
volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum
efficiency.
The device inverts the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.

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8.2 Typical Application

The following schematics and PCB layouts illustrate best practices used for the TAS5630B.

8.2.1 Typical Application Schematic

Caps for
System External
microcontroller Filtering
or &
Analog circuitry Startup/Stop
(2)

/RESET

PSU_REF
VI_CM
/CLIP

READY

C_STARTUP
/SD

/OTW1, /OTW2, /OTW

BST_A
Oscillator OSC_IO+

Synchronization Bootstrap
OSC_IO-
BST_B Caps

nd
INPUT_A OUT_A 2 Order
ANALOG_IN_A Input DC L-C Output
Input Output 2
Blocking Filter for
INPUT_B H-Bridge 1 H-Bridge 1 OUT_B
ANALOG_IN_B Caps each
2
H-Bridge
Hardwire
PWM Frame 2-CHANNEL
Rate Adjust
FREQ_ADJ
H -BRIDGE
& BTL MODE
Master/Slave
Mode
nd
INPUT_C 2 Order
ANALOG_IN_C Input DC OUT_C
Input Output L-C Output
Blocking 2
Filter for
INPUT_D H-Bridge 2 H-Bridge 2 OUT_D
ANALOG_IN_D Caps each
2
H-Bridge
M1 BST_C
GVDD_A, B, C, D
PVDD_A, B, C, D

Hardwire
GND_A, B, C, D

M2 Bootstrap
Mode
M3 BST_D Caps
OC_ADJ
Control
VREG

AGND
GND

VDD

8 8 4

PVDD PVDD GVDD, VDD, Hardwire

50V Power Supply Over-
& VREG
Decoupling Current
SYSTEM Power Supply
Power Decoupling Limit
Supplies
GND
GND
GVDD (12V)/VDD (12V)
12V

VAC

Figure 15. Typical Application Schematic

8.2.1.1 Design Requirements

This device can be configured for BTL, PBTL, or SE mode. Each mode will require a different output
configuration.

8.2.1.2 Detailed Design Procedure

• Pin 1 – Overcurrent adjust resistor can be between 24 kΩ to 68 kΩ depending on the application. The lower
resistance corresponds to the higher over-current protection level.
• Pin 2 – RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled
by a microprocessor.
• Pin 3 – Start-up ramp capacitor should be 4.7 nF for BTL and PBTL configurations, and 10 nF for SE
configuration.
• Pins 4, 5, 10, 11 – Differential pair inputs AB and CD. A DC blocking capacitor of 10 µF and an RC of 100 Ω
and 100 pF should be placed on each analog input.
• Pin 6 – Analog comparator reference node requires close decoupling capacitor of 1 nF to ground.
• Pin 7, 8, 23, 24, 57, 58 – Ground pins are connected to board ground.
• Pin 9 – Regulator supply filter pin requires 0.1 uF to AGND.
• Pin 12 – Frequency adjust resistor is discussed in Oscillator.

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Typical Application (continued)

• Pin 13, 14 – Oscillator input/output. When frequency adjust pin is pulled up to VREG, the oscillator pins are
configured as inputs.
• Pin 15 – Shutdown pin can be monitored by a microcontroller through GPIO pin. System can decide to assert
reset or power down. See Error Reporting.
• Pin 16, 17 – There are two overtemperature warning pins for PHD package. They have two different levels of
warning. OTW1 is lower temperature level warning than OTW2. They can be monitored by a microcontroller
through GPIO pins. System can decide to turn on fan, lower output power or shutdown. See Error Reporting.
• Pin 18 – Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide
to lower the volume.
• Pin 19 – Ready pin can be used to signal the system that the device is up and running.
• Pin 20-22 – Mode pins set the input and output configurations. See Table 2 for configuration setting of these
pins.
• Pin 25, 26, 55, 56 – Gate drive power pins provide gate voltage for half-bridges. Each needs a 3.3-Ω isolation
resistor and a 0.1-uF decoupling capacitor.
• Pins 27, 40, 41, 54 – Bootstrap pins for half-bridges A, B, C, D. Connect 33 nF from this pin to corresponding
output pins.
• Pins 28, 29, 36, 37, 44, 45, 53, 54 – Output pins from half-bridges A, B, C, D. Connect appropriate bootstrap
capacitors to the output pins. For PWM filtering, each output mode is used with different LC configuration.
• Pins 30, 31, 38, 39, 42, 43, 50, 51 – Power supply pins to half-bridges A, B, C, D. Each PVDD_X has
decoupling capacitor connecting to the appropriate GND_X pin.
• Pins 32, 33, 34, 35, 46, 47, 48, 49 – Connect decoupling capacitors of each power input pin to power supply
ground pins. Connect these pins to board ground.
• Pins 59-62 – Connect “No connect” pins to board ground. There is no internal connection to these pins.

8.2.1.3 Application Curves

10 340
4Ω 320 4Ω
6Ω 6Ω
THD+N − Total Harmonic Distortion + Noise − %

8Ω 300 8Ω
280
260
1 240
PO − Output Power − W

220
200
180
160

0.1 140
120
100
80
60
40
0.01 TC = 75°C
TC = 75°C 20 THD+N at 10%
0.005 0
20m 100m 1 10 100 400 25 30 35 40 45 50
PO − Output Power − W PVDD − Supply Voltage − V
G001 G001

Figure 16. Total Harmonic + Noise vs Output Power Figure 17. Output Power vs Supply Voltage

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8.2.2 Typical Differential-Input BTL Application With BD Modulation Filters

BTL output and differential input configuration is a typical audio class-D (PWM) amplifier. With differential input, the output can be configured for BTL
application with BD modulation. The configuration below can also be used with AD modulation. BD modulation gives better channel separation and PSSR
performance.
GVDD/VDD (+12V)

R30 PVDD
C64
3.3R 1000uF
R31
C40
33nF
3.3R L10
C25 C26
10uF 100nF 7uH GND
C30 C31 OUT_LEFT_M
100nF 100nF

GND GND C60 R70

C23 2.2uF 3.3R
GND
GND C50 C70
VREG 680nF 1nF
330pF C74

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND 10nF
R19
-

PVDD_A

GND_A
PVDD_A
OUT_A
OUT_A
BST_A
GVDD_A
GVDD_B
GND
GND
NC
NC
PSU_REF

NC
NC
VDD
R18 47k
/RESET +
C18 C75 GND
100R
GND 10nF
100pF R20
1 48
GND OC_ADJ GND_A
22.0k 2 47 C51 C71
/RESET GND_B 680nF 1nF R71
C10 C20
R10 46 L11 3.3R
GND 3
IN_LEFT_P C_STARTUP GND_B GND 7uH
10uF 100R C11 4.7nF 4 45
INPUT_A OUT_B OUT_LEFT_P
100pF
5 44
INPUT_B OUT_B C61 C41
C12 C21
R11 2.2uF 33nF
6 43
IN_LEFT_N GND VI_CM PVDD_B
10uF 100R C13 1nF 7 42 PVDD
100pF GND PVDD_B
8
U10 41 1000uF 1000uF
C68 R74
AGND BST_B 47uF C69 3.3R
C22 VREG GND
40 C65 C66 63V 2.2uF
9
C14 R12
GND
GND VREG TAS5630BPHD BST_C
C78
GND
100nF 10 39
IN_RIGHT_P INPUT_C PVDD_C 10nF
C15 38 GND GND GND GND
10uF 100R 11
100pF INPUT_D PVDD_C C62 C42 GND
R21 37 2.2uF
12 33nF
FREQ_ADJ OUT_C GND
C16 R13 10k 36 OUT_RIGHT_M
13
R_RIGHT_N OSC_IO+ OUT_C
C17 7uH R72
10uF 100R GND 14 35
OSC_IO- GND_C L12 3.3R
100pF
15 34
/SD GND_C GND
33 C52 C72
16 GND_D
/OTW1 680nF 1nF C76
10nF

GVDD_D
GVDD_C

PVDD_D
PVDD_D

GND_D
OUT_D
OUT_D
READY

BST_D
/OTW2
OSC_IO+

/CLIP

GND
GND
M3
M2
M1
OSC_IO- C77 GND +
10nF

32
31
30
29
28
26
25
24
23
22
21
20
19
18
17

27
/SD GND

/OTW1
C63 C53 C73 R73
/OTW2 2.2uF 680nF 1nF 3.3R
L13
/CLIP GND 7uH

READY OUT_RIGHT_P
VREG
PVDD

C43 C67
33nF 1000uF

R32
GND
3.3R GND
R33
GVDD/VDD (+12V)

3.3R

C33 C32
100nF 100nF

GND GND

Figure 18. Typical Differential-Input BTL Application With BD Modulation Filters

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8.2.3 Typical Differential (2N) PBTL Application With BD Modulation Filters

When there is a need for more power in an audio system, PBTL is a good choice for this application. Paralleling the output after the inductors is
recommended. In this configuration, the device can be driven with higher current (lower load impedance). Figure 19 shows the component and pin
connections.
3.3R
GVDD (+12V)
VDD (+12V)
3.3R
PVDD

100nF 100nF 3.3R

10uF 100nF 33nF 7uH
1000uF 47uF 2.2uF
63V 63V 100V
10nF
GND GND 100V
GND GND
VREG
2.2uF
100V
GND GND GND GND GND
47k GND
100R
/RESET 330pF

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
100pF 1000uF

BST_A

PVDD_A
PVDD_A
OUT_A
OUT_A

GND_A
NC

GND
NC

GND

GVDD_A
NC

GVDD_B
PSU_REF

NC
VDD
63V

GND 22.0k GND

100R 1 GND_A 48
OC_ADJ
IN_P GND 4.7nF 2 47
/RESET GND_B OUT_LEFT_M
10uF
100pF 3 46
C_STARTUP GND_B GND 7uH
GND 4 45
INPUT_A OUT_B
3.3R
100R GND 5 OUT_B 44
INPUT_B 2.2uF 1uF
33nF 250V
IN_N 6 43 100V
VI_CM PVDD_B
10uF 100pF 1nF 10nF
1nF 7 42
GND PVDD_B 100V 100V
GND
100nF VREG 8 41
-
AGND BST_B

GND
GND
9
VREG
TAS5630BPHD BST_C
40
+
VREG
39 GND 1nF 10nF GND
GND 10 PVDD_C
INPUT_C 100V 100V
11 38
INPUT_D PVDD_C 2.2uF 1uF
10k 33nF 250V
12 37 100V
FREQ_ADJ OUT_C 7uH
GND 3.3R
13 36
OSC_IO+ OUT_C
GND
14 GND_C 35
OSC_IO-
34 OUT_LEFT_P
15 /SD GND_C GND
16 33
/OTW1 GND_D

GVDD_D
GVDD_C

PVDD_D
PVDD_D

GND_D
OUT_D
OUT_D
READY

BST_D
/OTW2

/CLIP

GND
GND
M3
M2
M1
1000uF
63V

32
31
30
29
28
26
25
24
23
22
21

27
20
19
18
17
OSC_IO+

OSC_IO- 2.2uF GND

100V
PVDD
/SD GND GND
1000uF
/OTW1 VREG 7uH 63V

/OTW2
33nF
/CLIP GND
3.3R
READY 3.3R
GVDD (+12V)

100nF 100nF

GND GND

Figure 19. Typical Differential (2N) PBTL Application With BD Modulation Filters

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8.2.4 Typical SE Application

Single-ended output configuration is often used for cost effective systems. This device can be configured to drive four independent channels with four
different inputs. The delivered power is not as much as BTL configuration. The advantage is that the component count for four channels is the same as
two BTL channels. The schematic in this section shows the component and pin connections.
3.3R
VDD (+12V)

3.3R

GVDD (+12V)
100nF 100nF
10uF 100nF 33nF 15uH

GND GND GND GND

VREG PVDD

2.2uF

47k GND GND

100R
/RESET 330pF

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49
100pF GND

VDD

PSU_REF

NC

NC

NC

BST_A
NC

GND

GND

GVDD_B

GVDD_A

OUT_A

OUT_A

PVDD_A

PVDD_A

GND_A
GND
22.0k
100R 1
OC_ADJ 48
IN_A GND_A
GND 10nF
2 47
10uF /RESET GND_B
100pF
3 46
C_STARTUP GND_B GND 15uH
GND 4
INPUT_A 45
OUT_B B
100R GND 5
INPUT_B 44
IN_B OUT_B
6 2.2uF 33nF
10uF VI_CM 43
100pF PVDD_B
1nF 7
GND 42
GND PVDD_B PVDD
100nF

100R GND
VREG
GND
8

9
AGND TAS5630BPHD BST_B
41
3.3R
40 47uF
VREG BST_C 2.2uF
IN_C 63V
GND 10
INPUT_C 39
10uF PVDD_C 10nF
100pF
11 38
INPUT_D PVDD_C
10k
12 2.2uF 33nF
FREQ_ADJ 37
OUT_C 15uH GND
100R GND GND
GND 13
OSC_IO+ 36
IN_D GND OUT_C C
14 35
10uF OSC_IO- GND_C
100pF
15 34
/SD GND_C GND
16 33
/OTW1 GND_D
GND

GVDD_C

GVDD_D

PVDD_D

PVDD_D
READY

GND_D
OUT_D

OUT_D
/OTW2

BST_D
/CLIP

GND

GND
M1

M2

M3
17

18

19

20

21

22

23

24

25

26

28

29

30

31

32
27
OSC_IO+

OSC_IO-
2.2uF

/SD
GND PVDD
/OTW1
VREG 15uH
/OTW2
D
/CLIP 33nF
GND 3.3R
READY
GVDD (+12V)
3.3R

100nF 100nF

10nF 10nF
100V GND GND 100V

3.3R GND GND

3.3R

A OUT_A_M OUT_B_M
B

100nF 100nF
R_COMP
100V - R_COMP
100V -
470nF 470nF
10k 10k
PVDD 250V 250V
PVDD
+ +
470uF 10k 100nF GND 10k
470uF 100nF GND
50V 1% 100V 50V 1% 100V

OUT_A_P OUT_B_P
470uF 10k 10k
PVDD R_COMP 50V 1%
3.3R
470uF
50V 1%
3.3R

50V 147kW GND GND

100V 100V
49V 165kW 10nF GND 10nF GND

48V 187kW 10nF 10nF

<48V 191kW 100V 100V

3.3R GND GND

3.3R

C OUT_C_M OUT_D_M
D

100nF 100nF
R_COMP
100V - R_COMP
100V -
470nF 470nF
10k 10k
PVDD 250V 250V
PVDD
+ +
470uF 10k 100nF GND 10k
470uF 100nF GND
50V 1% 100V 50V 1% 100V

OUT_C_P OUT_D_P
470uF 10k 10k
470uF
50V 1% 50V 1%
3.3R 3.3R

GND GND
100V 100V
10nF GND 10nF GND

Figure 20. Typical SE Application

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8.2.5 Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application

One of the attractive features of this device is that it can be configured for mixed BTL and SE outputs. One BTL plus two SE channels make up a 2.1
audio system. While the SE channels are used to drive the front end and right speakers, the BTL channel can deliver higher power and is used to drive a
subwoofer. Figure 21 shows the component and pin connections.
GVDD (+12V)

PVDD
3.3R
VDD (+12V) 1000uF
63V
3.3R

100nF 100nF GND

10uF 100nF 33nF 7uH
OUT_CENTER_M

GND GND GND GND

VREG
3.3R
2.2uF
100V 680nF
GND GND 250V
100R 47k

/RESET 1nF 10nF

330pF
100V 100V

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49
100pF GND -

VDD

BST_A
NC

NC

NC

NC
PSU_REF

GND

GND

OUT_A

PVDD_A
OUT_A

PVDD_A
GVDD_B

GVDD_A

GND_A
+
GND 1nF 10nF GND
GND 22.0k 100V 100V

100R 1 48 680nF
OC_ADJ GND_A 250V
IN_CENTER_P 10nF
GND 2 47
10uF /RESET GND_B 3.3R
100pF
3 46
C_STARTUP GND_B
GND 7uH
GND 4 45
INPUT_A OUT_B
OUT_CENTER_P
100R GND 5 44
INPUT_B OUT_B
IN_CENTER_N 2.2uF
100V 33nF
6 43
10uF VI_CM PVDD_B
100pF
1nF 7 42
GND PVDD_B PVDD
GND
100nF VREG 8 41
AGND BST_B 3.3R
100R GND
GND
9
VREG
TAS5630BPHD BST_C 40 1000uF
63V
47uF
63V
2.2uF
100V 10nF
IN_LEFT
GND 10 39 10nF 100V
10uF INPUT_C PVDD_C
100pF 100V
11 38
INPUT_D PVDD_C
10k 2.2uF
33nF 3.3R
12 37 100V GND GND GND GND
FREQ_ADJ OUT_C
15uH GND
100R GND 13 36 OUT_LEFT_M
GND OSC_IO+ OUT_C
IN_RIGHT
14 35
10uF OSC_IO- GND_C
100nF
100pF
15
/SD GND_C
34
R_COMP
100V -
GND 470nF
10k
16 33 PVDD 250V
/OTW1 GND_D
+
GND 470uF 10k 100nF GND
50V 1% 100V

GVDD_C

GVDD_D

PVDD_D

PVDD_D

GND_D
READY

OUT_D

OUT_D
BST_D
/OTW2

/CLIP

OUT_LEFT_P

GND

GND
10k
M1

M2

M3
470uF
3.3R
50V 1%
17

18

19

20

21

22

23

24

25

26

28

29

30

31

32
27
OSC_IO+ 100V
GND GND 10nF
OSC_IO-
2.2uF
VREG 100V 10nF
/SD 100V
GND GND
/OTW1
3.3R
/OTW2 15uH GND
OUT_RIGHT_M
/CLIP 33nF
3.3R
READY 100nF
3.3R
R_COMP
100V -
470nF
10k
PVDD 250V
+
470uF 10k 100nF GND
100nF 100nF
50V 1% 100V

OUT_RIGHT_P
470uF 10k
3.3R
GND GND 50V 1%

100V
GND GND 10nF

PVDD

GVDD (+12V)

Figure 21. Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application

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8.2.6 Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package
This is the same application as described in Typical Differential-Input BTL Application With BD Modulation Filters with PHD package. For DKD package
an external heatsink is required to dissipate excess heat. In this package, the PCB space is not a limiting factor for dissipating excess heat.
R34
GVDD (+12V)
1.5R

C38 C87 PVDD

100nF 100nF

1000uF
63V
VDD (+12V)
GND

C44 C35
10uF 100nF 7uH GND
OUT_LEFT_M

GND GND
C86 3.3R
VREG 680nF
GND
250V
330pF 1nF 10nF
R44
47k U12 100V 100V
/RESET
R13
1 PSU_REF GVDD_AB 44 -
C33
100R C78 2 43
VDD BST_A +
100pF R14
3 42 33nF GND 1nF 10nF GND
GND OC_ADJ PVDD_A 100V 100V
24k 4 41
/RESET PVDD_A 680nF
R45 C45
5 40 C83 250V
IN_LEFT_P GND C_STARTUP OUT_A 2.2uF
3.3R
10uF 100R C82 4.7nF 6 39
INPUT_A OUT_A
100pF
7 38 7uH
INPUT_B GND_A
R54 C85
8 37 OUT_LEFT_P
IN_LEFT_N GND VI_CM GND_B GND
10uF 100R C79 1nF 9 36 PVDD
GND OUT_B
100pF
C42 VREG 10 35
AGND PVDD_B 3.3R
GND C90 1000uF 1000uF
GND C41 33nF
11 VREG
TAS5630BDKD BST_B
34 2.2uF 47uF 2.2uF
GND 100nF 63V 100V
R53 63V 63V
12 33 10nF
IN_RIGHT_P INPUT_C BST_C C91 100V
C37 33nF
10uF 100R C80 13 32 2.2uF GND
INPUT_D PVDD_C
100pF R20
14 31 GND GND GND GND
FREQ_ADJ OUT_C GND
R60 10k
15 30 7uH
IN_RIGHT_N OSC_IO+ GND_C OUT_RIGHT_M
GND
10uF 100R C81 16 29
OSC_IO- GND_D
100pF
17 28
/SD OUT_D GND
3.3R
18 27 C34
/OTW OUT_D 2.2uF 680nF
19 26 250V
READY PVDD_D
20 25 1nF 10nF
M1 PVDD_D 100V 100V
VREG
21 M2 BST_D
24 -
OSC_IO+ 33nF
22 23
M3 GVDD_CD C88 +
OSC_IO- GND 1nF 10nF GND
100V 100V
GND
/SD 680nF
250V
/OTW
3.3R
READY
7uH
OUT_RIGHT_P

PVDD

1.5R 1000uF
63V
R31
100nF 100nF
C89 C84 GND
GVDD (+12V)

GND

Figure 22. Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package

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9 Power Supply Recommendations

Absolute Maximum Ratings discusses most of the requirements on TAS5630B power supply. There are a few
more important guidelines that should be considered. The most important parameters are the absolute maximum
rating on PVDD pins, bootstrap pins and output pins. Over stress the device with higher that maximum voltage
rating may shorten device lifetime operation and even cause device damage. Be sure that the specifications in
section 6 are observed. For best audio performance, low ESR bulk capacitors are recommended. Depending on
the application 470-µF capacitor or higher should be used. As always, decoupling capacitors must be placed no
more than 1 mm from the power supply pins. If PCB space is not allowed for close decoupling capacitor
placement, the decoupling capacitors can be placed on the back side of the device with vias. However, it still
needs to be right below the pins.

10 Layout

10.1 Layout Guidelines

Use an unbroken ground plane to have a good low-impedance and -inductance return path to the power supply
for power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
of the audio input should be kept short and together with the accompanying audio-source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce. It is always good practice to
follow the EVM layout as a guideline.
Netlist for this printed circuit board is generated from the schematic in Figure 18.

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10.2 Layout Example

Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X
pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins
and without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins. This is valid for C60, C61, C62, and C63.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, preferably metal film types.

Figure 23. Printed Circuit Board – Top Layer

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Layout Example (continued)

Note B1: It is important to have a direct-low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short, low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors

Figure 24. Printed Circuit Board – Bottom Layer

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11 Device and Documentation Support

11.1 Trademarks
PurePath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TAS5630B

 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5630BPHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5630BPHDR HTQFP PHD 64 1000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2023

TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TAS5630BPHD PHD HTQFP 64 90 6 X 15 150 315 135.9 7620 20.3 15.4 15.45

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
PHD 64 HTQFP - 1.2 mm max height
14 x 14, 0.8 mm pitch PLASTIC QUAD FLATPACK

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224851/B

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