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New High Performance 1-Bit Full Adder Using Domino Logic

Article · March 2015

DOI: 10.1109/CICN.2014.203

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 2014 Sixth International Conference on Computational Intelligence and Communication Networks

New High Performance 1-Bit Full Adder Using

Domino Logic
Shekhar Verma Dhirendra Kumar Gaganpreet Kaur Marwah
Pursuing M.Tech ECE from Assistant Professor Assistant Professor
Lovely Professional University, Lovely Professional University Lovely Professional University
Phagwara,India Phagwara,India Phagwara,India,
[email protected] [email protected] [email protected]

Abstract— Domino CMOS Circuits are significantly used Domino logic style is generally used for designing a high
in high performance very large scale integrated (VLSI) performance circuit, rather than a static logic style [1].For
system. Designing a low power with high speed arithmetic operations full adder acts as a basic element for
performance VLSI circuit is one of the challenging parity checker, comparator and multiplier, hence it receives a
aspects. Full adder is one of the basic blocks for many lot of attention by the researchers.
circuits for multiplication, division and exponentiation
operation. This paper proposed a low power with high For designing a full adder there are two logic approaches
speed performance 1-bit full adder using domino first is static and the second is dynamic. A dynamic full
approach and also shows a comparative analysis of adder is faster and more compact, consumes less silicon
proposed full adder with other full adder using static area, but it consumes more power and more sensitive to
approach. The simulations are carried out by TANNER noise as compared to static full adder [2]. To design an
EDA tool using PTM 90nm technology node with 1.1V efficient full adder, there are lots of constraints, i.e. power
supply voltage. The results show that the proposed 22T consumption, performance of the circuit, transistor count,
domino full adder consume 54.74% less power as area, noise immunity and good driving ability. There are
compared to 10T static full adder, 54.35% less power three major contributions to power consumption in CMOS
consumed as compared to domino 27T full adder and circuits. One is the active power due to discharging and
3.2% less power consumed as compared to 28T static full charging of the circuit capacitances during switching and the
adder. The results also depict that the speed of a other is leakage power due to leakage current and the third
proposed 22T domino full adder is much faster in is short circuit currents that flow directly from the supply to
comparison to 28T static full adder by 68.163%, 1.70% ground when the n-subnetwork and the p-subnetwork of a
faster as compared to 27T domino full adder and 99% CMOS gate both conduct simultaneously.
faster as compared to 10T static full adder.
As we scale down the supply voltage for reducing the
power that decreases the threshold voltage (Vt) and gate
oxide thickness (tox) of the transistor, which leads to
increase in sub-threshold leakage (Isub) current [2]. So many
Keywords— Large Scale integration (VLSI), complementary techniques have been proposed to decrease the transistor
metal oxide semiconductor (CMOS), Power delay product (PDP) count and consequently decrease power consumption and
area [2, 3] like low swing techniques and the multiple
supply technique and the dual Vt technique, but these
I. INTRODUCTION techniques are helpful to reduce the power consumption, but
To increase the performance of VLSI circuits and at the same time they may degrade the speed and weaken
integrate more functionality into every chip, the size of the the noise immunity of the circuits. In this paper, we used
transistor is continually shrinking day by day which results in domino logic style for designing a 1-bit full adder cell and
the complexity of chips and circuit power consumption. then compared with static logic based 28 transistor full
Now a day, designing of low power and high speed adder and 10 transistor full adder cell and also compared
performance VLSI circuits is one of the biggest challenges. with 27 transistor domino full adder. In this paper, we also
Also power and delay parameters of any VLSI circuit can’t presented a comparative analysis in terms of power, delay
be reduced at the same time, but we can optimize these two and power delay product (PDP) for 28T and 27T, 22T and
parameters. 10T adder circuits. To analyze the effect on power, delay

978-1-4799-6929-6/14 $31.00 © 2014 IEEE 963

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DOI 10.1109/CICN.2014.203
10.1109/.203
and PDP of the various adder circuits we used a voltage B. 10T Static Full Adder
scaling low power technique.
The second full adder circuit using static logic
II. LOW POWER FULL ADDER DESIGN approach and implemented using only 10 transistors. The
four-transistor XNOR module also used in it. As shown in
There are several different techniques to reduce power
the fig.2., XNOR signal is used as the selector of two static
consumption in CMOS full adder circuits
multiplexers. In this circuit XNOR signal has Vth threshold
• For reducing the dynamic power output and input loss so therefore this circuit has a threshold loss problem.
capacitance values can be minimized. There is a semi-inverter to invert input A. This inverter
• For reducing the short and static power, avoid should work only when XNOR signal is equal to logic 0. So
using both Vdd and GND simultaneously in XNOR signal acts as a ground signal in this circuit to
circuit’s components. decrease short circuit and leakage power in the inverter. [4]
• To reduce the transistor count we can use a pass
transistor in a circuit that in return reduces power
consumption but sometimes it leads to threshold
loss.
• By varying the ratio of W/L to minimize the
transistor conduction.

III. 1-BIT FULL ADDER

A. 28T Basic Static Full adder

28T static based, full adder is the basic structure for
any arithmetical circuit as shown in fig.1. A, B, C are the
inputs and Sum and Cout are the outputs of full adder [6].

Fig.2. One-bit full adder using 10 Transistors

C. 27T Domino Full Adder

The third full adder based on domino logic style, uses
27 transistors as shown in fig.3. [5]. It is based on 3-
transistor implementations of the XOR and XNOR functions
presented in, pass transistors, and transmission gates [4].

Fig.3. One-bit full adder using 27 Transistors

Fig.1. One-bit full adder using 28 Transistors

IV. PROPOSED DOMINO FULL ADDER
In this section we proposed a 1-bit full adder circuit
using domino logic approach as shown in Fig.4. using 22

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transistors. In this circuit there is no direct path between Vdd TABLE 2 POWER Vs SUPPLY VOLTAGE
and GND and discharge of transistor depend on the clock
Power (μW)
signal. In the proposed design, during pre-charging phase
28T 10T 27T 22T
clock is low and dynamic node is charged. During Static Static Domino Domino
evaluation phase clock becomes high. In this design variable Supply Full Full Full Full
threshold voltage technique and multiple threshold S. No Voltage(V) Adder Adder Adder Adder
techniques are used, so that the output of the full adder will 1 1 0.3922 0.4096 0.50115 0.3616
not be swing out and it reduces the leakage current that in 2 1.02 0.4348 0.4589 0.5308 0.379
turn minimize the power dissipation of the circuit. 3 1.04 0.4733 0.5106 0.576 0.397
4 1.06 0.4872 0.5705 0.6232 0.4101
5 1.08 0.464 0.6362 0.6496 0.4344
6 1.1 0.4719 0.7072 0.7054 0.457
7 1.12 0.494 0.9813 0.7259 0.472
8 1.14 0.5038 1.329 0.74206 0.495
9 1.16 0.5419 1.754 0.7962 0.523
10 1.18 0.6189 2.26 0.8633 0.558

POWER vs SUPPLY VOLTAGE

5 10T Static
4.5 Full Adder
4
3.5
POWER (μW)

Fig.4. One-bit full adder using 22 Transistors

3 27T Domino
2.5 Full Adder
Power delay product calculated from production of delay 2
and average power consumption, according to the equation 1.5 28T Static
(1) 1 Full Adder
0.5
0
ܲ‫ ܲܦ‬ൌ ܲ‫ ࢋࢍࢇ࢘ࢋ࢜࡭ݎ݁ݓ݋‬ൈ ‫ݕ݈ܽ݁ܦ‬ (1) 22T Domino
1 1.04 1.08 1.12 1.16 Full Adder
In the proposed circuit, transistor length Lmin = 90nm and Supply Voltage(Volt)
Width W for all NMOS transistors is equal to Lmin and for
PMOS transistors is equal to 2Lmin. All the circuits Fig. 5. Variation of average power with supply voltage for different adder
optimized at 1.1 V supply voltage and 33 MHz input at 90nm technology.
frequency conditions. To make a suitable comparison, these
conditions made same for all circuits as it.

V. RESULTS AND DISCUSSION

A. Power Comparison B. Delay Comparision

In this section, effect of supply voltage on power In this section, discussed the effect of supply voltage on
consumption has been discussed. For analysis, supply the delay of the full adder, supply voltage varies from 1V to
voltage varies from 1V to 1.18V. Each circuit tested on 1.18 V. Each circuit tested on same input patterns. The
same input patterns. The comparative analysis is carried out comparative analysis is carried out by using 90nm
by using 90nm technology node. The results show that 22T technology node. The results show that 22T domino full
domino full adder shows least power consumption among adder has less delay in comparison to the other full adder at
the other full adder at supply voltage of 1.1V as per from supply voltage of 1.1V as per from Table 3 and fig.6
table 2 and fig. 5.

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 TABL 3 DELAY Vs SUPPLY VOLLTAGE TABLE 4. PDP Vs SUPPLY VOLTAGE
Delay (nS) PDP
28T 10T 27T 22T 28T 10T
T 27T 22T
Static Static Dominoo Domino Static Staticc Domino Domino
S. Supply Full Full Full Full S. Supply Full Fulll Full Full
No Voltage(V) Adder Adder Adder Adder No Voltage(V) Adder Addeer Adder Adder
1 1 50.654 60.38 30.74 30.198 1 1 19.86 24.73
3 15.40 10.91
2 1.02 50.586 60.37 30.73 30.193
2 1.02 21.99 27.70
0 16.31 11.44
3 1.04 50.503 60.36 30.71 30.189
3 1.04 23.90 30.81
1 17.68 11.98
4 1.06 50.401 60.35 30.703 30.186
5 1.08 50.76 60.34 30.702 30.182 4 1.06 24.55 34.42
2 19.13 12.37
6 1.1 50.75 60.34 30.693 30.179 5 1.08 23.55 38.38
8 19.94 13.11
7 1.12 50.74 60.33 30.685 30.175 6 1.1 23.94 42.67
7 21.65 13.79
8 1.14 50.37 60.32 30.676 30.172 7 1.12 25.06 59.20
0 22.27 14.24
9 1.16 50.36 60.323 30.66 30.169
8 1.14 25.37 80.16
6 22.76 14.93
10 1.18 50.53 60.31 30.63 30.166
9 1.16 27.29 105.8
80 24.41 15.77
10 1.18 31.27 136.30 26.44 16.83
DELAY vs SUPPLY VOL
LTAGE

VI. CONCLLUSIONS
100
Delay(ns)

22T Domino
D Full The aim of the present work iss to optimize the performance
Adderr parameter of CMOS based, full fu adder in terms of power,
0 28T sttatic Full delay and power delay productt (PDP). Generally the power
Adderr and the delay are the two facctors which can’t be reduced
1
1.04
1.08

both at a same time, but these parameters can be optimized,

1.12
1.16

27T Domino
D Full
Adderr so in the present work a prroposed full adder based on
10T Static Full domino logic approach 22T, which optimize these two
Supply Voltage(Volt)
Adderr constraints and proposed desiggn gives best result in terms of
power dissipation and delayy, power delay product as
Fig6. Variation of delay with different supply voltagee for different
adders at 90nm technology.
compared to 28T, 10T and 277T full adder based on static
and domino logic approach. It has been concluded that
C. Power Delay Product (PDP) Comparision
C proposed design, i.e. 22T dom mino, based full adder show
In this section, the effect of supply voltagge on power delay minimum power dissipation, minimum
m delay as well as a
product has been discussed for the full addder circuit. Supply power delay product (PDP) as a compared to the other full
voltage varies from 1V to 1.18 V. Eachh circuit tested on adder circuit. As domino logicc based circuit dissipate more
same input patterns. The comparative analysis
a has been power as compared to static loogic [15] but still optimizing a
carried out by using 90nm technology node. The result power in proposed circuit, 22TT domino full adder show 1.03
shows that 22T domino full adder has least PDP among the times less power dissipation as compared to 28T adder
other full adder at supply voltage of 1.1V as per from Table circuit and 1.54 times less power as compared to 10T full
4 and fig.7. adder and also in terms of delaay 22T adder show least delay
and PDP as compared to 28T anda 10T, 27T adder circuit. So
22T domino full adder circuit shows the best result among
PDP vs SUPPLY VOLTAGE
the 28T, 10T, 22T full adder. Inn future we can extend to 22T
150 domino full adder to the multi bit adder and we can design,
28T Static Full low power and high speed performance multi-bit adder
Adder
100 circuit using it.
PDP

27T Domino
.
50 Full Adder
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10T Static Full
0 Adder
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Technology” IEEE conference 20009
Fig.7. Variation of PDP with different supply voltaage for different
adders at 90nm technology

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