©2008, Dr. Meeta Yadav, www4.ncsu.

edu/~myadav/Research 1
 Outline

1. System Verilog Procedural Statements

2. System Verilog Tasks and Functions

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 2

 System Verilog Procedural Statements

• New Operators
 Increment and decrement operator
► Used the same way as C

for (i=0; i<=31; i++)

begin
…
end

► Post-increment/decrement and pre-increment/decrement

j=i++ j is assigned value of i and then i is incremented by 1

j=++i i is incremented by 1 and j is assigned value of i
j=i--; j is assigned value of i and then I is decremented by 1
j=-i; i is decremented by 1 and then j is assigned value of i

► May cause a race condition since ++ and -- operators behave as blocking

assignments

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 3

 System Verilog Procedural Statements
Example
while (i++ < LIMIT) begin
. . .
end

Last value of i will be LIMIT

while (j++ < LIMIT) begin

. . .
end

Last value of j will be LIMIT-1

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 4

 System Verilog Procedural Statements

• Assignment Operators
 Equality operators
► Logical equality operator ==, != (returns 1’bx on comparing x or z values)
► Case equality operator === , !== (looks for an exact match of x or z
values)
► SystemVerilog introduces two new operators ==? And !=? (wildcard
equality operators)
– Performs a bitwise operation and treats a z or an x as a wildcard value
– These operators only consider x or z bits in the right-hand operand as mask
bits

A = 010z,
b=0101
a==?b

unknown

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 5

 System Verilog Procedural Statements

• Set Membership Operator - inside

 inside is used to test if a value matches anywhere within a

set of values

logic [2:0] a;
if ((a==3’b001)||(a==3’b010)||(a==3’b100))

Equivalent to
logic [2:0] a;
if (a inside {3’b001, 3’b010, 3’b100}

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 System Verilog Procedural Statements

• Type Casting
 Verilog does type conversion using assignments
 SystemVerilog adds a typecast operator
► Typecasting allows the designer to specify that a conversion
should occur at any point during the evaluation of an expression,
instead of just part of an assignment

type’ (expression)
example

longint a,y;
real r;
y=a+longint’(r**3)

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 7

 System Verilog Procedural Statements

size’ (expression)
• Size Casting
 SystemVerilog allows vector widths to be cast to a different size
► If an expression is cast to a smaller size than the number of bits in
the expression, the left-most bits of the expression are truncated
► If an expression is cast to a larger vector size, then the expression
is left extended
example

logic [15:0]
a,b,c,sum;
logic carry;
sum=a+16’(5); Cast operand
{carry,sum}=17’(a+3); Cast result
sum=a+16’(b-2)/c; Cast intermediate result

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 8

 System Verilog Procedural Statements

• Sign Casting
 SystemVerilog allows casting the signed-ness of a value
► Signed-ness of an operand can be cast
► Signed-ness of an operation result can be cast
signed’ (expression)
unsigned’ (expression)

example

Sum= signed’(a) + signed’(a); Cast operand

if(unsigned’(a-b)<=5) Cast intermediate result

…

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 9

 System Verilog Procedural Statements

• Enhanced for loops

 for loop variables are declared outside the loop in Verilog
► Concurrent loops interfere with each other
 SystemVerilog allows the for loop variables to be declared
inside the loop
► Each variable is local and unique to the loop, hence same name
usage does not cause any interference
► Local loop variables are automatic
► The variables do not exist outside the loops

always @(posedge clock) begin

for(int i=1; i<=1024; i=i+1)
…
end
endmodule

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 10

 System Verilog Procedural Statements

• do…while loop
 A while loop in Verilog might not execute at all
► If the test of control values is false the first time the loop is encountered in
the execution flow
 SystemVerilog adds a do..while loop (similar to C)
► A do while loop executes atleast once
► Control of the loop is tested at the end of each pass of the loop
– All logic for setting the outputs of the loop can be placed inside the loop
– Makes code more concise and intuitive

do <statement or statement block>

while (<condition>);

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 11

 System Verilog Procedural Statements

• Case Statements - case, casex, casez

 In Verilog case statements evaluate the case selection item in the
order in which they were listed
► Synthesis tools optimize out the additional logic required for priority
encoding the selection decisions
 SystemVerilog provides unique and priority modifiers to case
statements
► Unique modifier allows designers to explicitly specify that the order of the
case selection is not significant
– Any case expression value that occurs should one and only one case select
item
– A unique case cannot have overlapping conditions
► The priority modifier indicates that:
– At least one case select expression must match the case expression when it is
evaluated
– If more than one case select expression matches the case expression when it
is evaluated the first matching branch should be taken.

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 12

 Verilog Tasks and Functions Overview
• Functions
 Functions execute in “0” time
 Functions cannot have any timing control statements
► A function cannot have a dealy (#100)
► A function cannot have a blocking statement such as @(posedge clock) or
wait(ready)
► A function cannot call a task
 A void function never returns a value: a verilog function must return a value

function [range] function_name;

parameters
input declarations
reg declarations
… text body …
endfunction

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 13

 Verilog Tasks and Functions Overview

• Tasks
 Tasks can have input, multiple outputs or inout ports
 Tasks consume time and can contain
► Delay
► Timing
► Events

task task_name;
parameters
input declarations
output declarations
reg declarations
… text body …
endtask

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 SystemVerilog Tasks and Functions
• Tasks and Functions
 SystemVerilog functions and tasks do not require begin and end
statements
 SystemVerilog adds a return statement
 Void functions do not return a value
 Functions can have output and inout as formal arguments

task reset();
reset_l = 1’b0;
function int add2(int n);
#100
return n + 2;
reset_l = 1’b1;
endfunction
endtask

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 15

 SystemVerilog Tasks and Functions

• Return Statement
 SystemVerilog adds a return statement
► Ifa return statement is executed that value is returned else the last
value assigned to the function name is the return value
► A return statement can be used to exit a task or a function

function int add_and_inc (input [31:0] a,b);

add_and_inc=a+b+1;
endfunction Return has priority over
returning the value in the
function int add_and_inc (input [31:0] a,b); name of the function
add_and_inc=a+b;
return ++add_and_inc;
endfunction

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 16

 SystemVerilog Tasks and Functions

• Void functions
 Void functions do not return a value
 Output and inout formal arguments allow a void function to
propagate changes to the scope
 A void function can be called like a task but must adhere to the
restriction of function contents
typedef struct{
logic valid;
logic [7:0] check;
logic [63:0] data;
} packet_t;

function void fill_packet (

input logic[63:0] data_in, output packet_t data_out);
data_out.data=data_in;
endfunction

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 17

 SystemVerilog Tasks and Functions

• Passing task/function arguments by name

 SystemVerilog can pass argument values to tasks or functions
using the names of formal arguments
► Reduces errors
 The arguments can be passed in any order
 Syntax for named argument passing is the same as Verilog’s
syntax for named port connections

function int divide (input int always @(posedge clock)

numerator, denominator); result<=divide(b,a)
if(denominator==0)
begin
return 0;
end always @(posedge clock)
else result<=divide(.deominator(
return numerator/denominator; b),.numerator(a))
endfunction

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 18

 SystemVerilog Tasks and Functions

• Enhanced function formal arguments

 SystemVerilog functions can have inputs and outputs

function [63:0] add (input [63:0] a,b,

output overflow);
{overflow, add} = a+b;
endfunction

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 19

 SystemVerilog Tasks and Functions

• Default formal argument direction and type

 Each formal argument can have a default type
 When a task or function is called it is not necessary to pass a
value to the arguments that have default argument values
► If a value is not passed the default values are used

function int incrementer (int count=0, step=1);

increment = count + step;
endfunction

always @(posedge clock) Not all arguments

result = incrementer(data_bus); have to be specified

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 20

 SystemVerilog Tasks and Functions
• Passing argument values by reference instead of copy
 Values are passed to tasks and functions by copy (most often)
 SystemVerilog has explicit pass by reference task/function arguments
► Use keyword ref (instead of input, output or inout)
► Only automatic tasks and functions can have ref arguments
typedef struct{
logic valid;
logic [7:0] check;
logic [63:0] data;
} packet_t;
packet_t data_packet;
logic [7:0] raw_data [0:7];

always@(posedge clock)
if(data_ready)
fill_packet (.data_in(raw_data), .data_out(data_packet));

function automatic void fill_packet (

ref logic [7:0] data_in [7:0], ref packet_t data_out);
for(int i=0; i<=7; i++) begin
data_out.data[(8*i)+:8]=data_in[i]; end
endfunction
endmodule
©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 21
 SystemVerilog Tasks and Functions
• Passing argument values by reference instead of copy
 Pass by reference can be read-only
► Allows the task/function to reference the information in the calling scope
► Prohibits the task or function from modifying the information
 Task ref arguments are sensitive to change
 Ref arguments can read current values
 Ref arguments can propagate changes immediately
Read only

function automatic void fill_packet (

const ref logic [7:0] data_in, ref packet_t data_out);
…
endfunction

Sensitive to change
task automatic check_results (
input packet_t sent, ref packet_t received, ref logic done);
wait (done)
…
endfunction

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 22

 SystemVerilog Tasks and Functions
• Argument Passing
 !! Type is sticky, following arguments default to that type
 input - copy value in at beginning - default
 output - copy value out at end
 inout - copy in at beginning and out at end
 ref - pass by reference (effects seen right away)
► Saves time and memory for passing arrays to tasks & functions
 Modifier: const - argument is not allowed to be modified
Default dir is input, a, b: input logic
default type is logic u, v: output bit [15:0]

task T33(a, b, output bit [15:0] u, v);

function void bad(ref int a[], int start=0); Watch out for ref
followed by input

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 23