M0-Based MCU

MG32F02A032
Data Sheet

Version: 1.21

This document contains information on a new product under development by Megawin.

Megawin reserves the right to change or discontinue this product without notice.
 Megawin Technology Co., Ltd. 2019 All rights reserved. 2019/11 version 1.21
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Features
CPU Core
 ARM 32-bit Cortex-M0 CPU
 Operation frequency up to 48MHz
 Built-in one NVIC for 32 external interrupt inputs with 4-level priority
 Built-in one 24-bit system tick timer
 Built-in one single-cycle 32-bit multiplier
 Built-in one SWD serial wire debugger with 2 watch points and 4 breakpoints
Flash Memory
 Built-in embedded 32K bytes flash memory for application code
 Support ICP (In-circuit program) for ISP boot code update through SWD interface
 Support ISP (In-system program) for application code update
▬ Support programmable ISP flash memory size for ISP boot code
 Support IAP (In-application program) for application data update
▬ Support programmable IAP flash memory size
SRAM Memory
 Built-in embedded 4K bytes SRAM
Power
 Built-in two brown-out detectors
▬ BOD0 detect 1.7V
▬ BOD1 detect by selected level 4.2V/3.7V/2.4V/2.0V
 Built-in a power management controller with power-down and wakeup control
 Support three power operation modes
▬ ON(Normal) mode and SLEEP , STOP power down modes
 Support wake-up from SLEEP/STOP modes via multiple sources
Reset
 Built-in embedded POR(power-on reset) circuit
 Built-in one reset source controller
▬ Programmable chip cold reset and warm reset for reset source
▬ Independent software reset control for internal modules
 Provide multiple reset source
▬ POR/BOD0/BOD1/External reset pin input/Software force reset
▬ IWDT/WWDT/ADC/Analog Comparator
▬ Illegal address error reset/Flash access protect error reset
▬ Missing clock detect (MCD) reset
Clock
 Built-in embedded ILRCO (internal low frequency RC oscillator) by 32KHz
 Built-in embedded IHRCO (internal high frequency RC oscillator)
▬ Trimmed to 11.059 or 12MHz ±1% at +25℃
 Built-in embedded PLL up to 48MHz output for system clock
 Built-in embedded XOSC oscillator with MCD for external 32KHz and 4 to 25MHz Xtal
 Support external clock input up to 36MHz
 Built-in a clock source controller with independent clock enable control for modules
 Support internal XOSC oscillator and internal ILRCO/IHRCO clock output
DMA (Direct Memory Access)
 One configurable channels with dedicated hardware DMA requests
▬ Access to Memory, APB and AHB Peripherals as source and destination
▬ Support SRAM/Flash as memory source and SRAM as memory destination
▬ Peripherals are including of ADC0, I2Cx, URTx, SPIx, TM36 and GPL modules

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 DMA transfer management type
▬ memory-to-memory
▬ peripheral-to-memory
▬ memory-to-peripheral
▬ peripheral-to-peripheral
 Programmable transfer number of data and up to 65535
 Programmable burst length 1,2,4
 Support transfer loop mode and start address auto reload control
 Provide single/block/demand mode for external pin trigger request
GPIO
 Support general purpose IO pins for application
▬ Maximum 44 GPIO pins for LQFP48 package
▬ Maximum 29 GPIO pins for QFN32 package
▬ Maximum 17 GPIO pins for TSSOP20 package
 Provide selectable IO modes by pin independent
▬ Push-Pull output
▬ Quasi bidirectional
▬ Open-drain output
▬ Digital Input with high impedance
▬ Analog IO
 Flexible pin alternate function selection
 Support programmable drive strength by pin independent
 Support IO deglitch filter by pin independent
 Support input inverse selection by pin independent
 Support pull-high option by pin independent
 Support high speed option by pin independent except RSTN,XIN
 GPIO pin state and IO mode setting keep optional after reset
Interrupt Support
 Built-in one EXIC (external interrupt controller) for NVIC connection
▬ Independent high/low level and rising/falling edge trigger selection
 Built-in one WIC (wakeup interrupt controller) for wakeup event control
 All PA/PB/PC/PD pins can be configured as interrupt source and key pad input
▬ Support port OR logic for interrupt function
▬ Support port AND logic for KBI function
 Support external pins for CPU NMI/RXEV/TXEV function
Timer
 Provide five timers/counters : TM00,TM01,TM10,TM16,TM36
 Support multi-level timer modules for different application
 Timer module common functions
▬ Selectable Full-counter, Cascade, Separate timer operation modes
▬ Multiple internal and external signals as timer clock source or trigger source
▬ Support timer reset, trigger start and clock gating for trigger source function
▬ Timer overflow as clock output to external pin output
▬ Programmable counter auto-stop mode
 Provide TM36 timer module
▬ 32-bit timer/counter
▬ 4 CCP (input Capture/output Compare/PWM) channels
▬ 3 CCP channels with OCN (complementary output compare)
▬ PWM function with center/edge-align, dead time control and break control
▬ QEI(Quadrature Encoder Interface) support

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▬ One IC and three OC with DMA capability
▬ External input timer up/down control(TM36 only)
 Provide TM1x timer modules (TM10,TM16)
▬ 32-bit timer/counter
 Provide TM0x timer modules (TM00,TM01)
▬ 16-bit timer/counter
RTC
 Built-in 32-bit counter with selectable clock source
 Support alarm function and time-stamp function
▬ Support alarm function with 32-bit programmable compare register
 Support wakeup from STOP mode
 Support periodic timer tick interrupt or wakeup
Watchdog Timer
 Built-in one IWDT (Independent Watch Dog Timer)
▬ 8-bit down counter with 12-bit prescaler and clocked by ILRCO clock
▬ Operating capability in SLEEP and STOP modes
▬ Selectable reset or interrupt when the counter underflow
▬ Support two early wakeup comparators with interrupt
 Built-in one WWDT (Window Watch Dog Timer)
▬ 10-bit counter with 1 or 256 divider , 1/2/4~/128 divider
▬ Configurable time-window to detect abnormally late or early application behavior
▬ Selectable reset or interrupt when the counter is underflow or reloaded outside the window
▬ Support warning interrupt
I2C
 Provide one I2c module : I2C0
 I2C module common functions
▬ Support master and slave mode
▬ Support programmable clock rate control and clock rate up to 1 MHz
▬ Support programmable high/low period control for master mode
▬ Support clock stretching for slave mode
▬ Support general call function
▬ Support multi-master processing capability
▬ Support both Byte mode and Buffer mode flow control
▬ Support Byte mode bus event code for simplex firmware control
▬ Support Buffer mode 4-byte data buffer and 32-bit data register for high speed communication
▬ Received and transmitted data are buffered with DMA capability
▬ Support slave address hardware detection wakeup from STOP mode
▬ Support SMBus timeout detection
UART
 Provide two identical UART modules : URT0,URT1
 UART module common functions
▬ Support UART, Synchronous, SPI master, SmartCard, LIN, Multi-processor modes
▬ Provide precise UART baud-rate control by programmable oversampling rate
▬ Support baud rate up to 6 Mbit/s
▬ Programmable data word length - 7 or 8 bits
▬ Selectable MSB or LSB first data order
▬ Configurable stop bits - 0.5,1,1.5 or 2 stop bits
▬ Hardware parity checking and parity generation
▬ Programmable 4~32 oversampling rate
▬ Swappable TX/RX pin configuration

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▬ Separate signal polarity control for transmission and reception
▬ Support a timeout timer for Idle/RX/Break/Calibration timeout detection
▬ Support 4-byte data buffer and 32-bit data register for high speed communication
▬ Received and transmitted data are buffered with DMA capability
▬ Support auto baud-rate detection and calibration
▬ Support multiprocessor communication for master and slave mode - Idle-Line , Address-Bit
▬ Support low speed UART-like frame format IrDA
▬ Support transceiver hardware flow control by CTS/RTS signals only
▬ Provide driver enable signal to activate the transmission for bidirectional communication
▬ Support transmission-error hardware detection and auto resent control for Smart-card application
▬ Support receiving parity error hardware detection and auto retry control for Smart-card application
SPI
 Support master and slave mode
▬ Support full duplex , half duplex or simplex communication mode
▬ Support data communication without NSS(slave select signal)
 Support programmable clock rate control
▬ Support clock rate up to 24 MHz for master, 16MHz for slave
 Selectable 4~32-bit frame size
▬ Support 4-byte data buffer and 32-bit data register for high speed communication
 Received and transmitted data are buffered with DMA capability
 Support multi-master processing capability
 Selectable clock polarity and phase
 Selectable MSB or LSB first data order
 NSS line management by hardware or software for master mode
 Configurable data transfer modes
▬ Standard SPI mode (separated transmit and receive line)
▬ Single SPI mode with bidirectional data transfer
▬ Dual SPI mode with bidirectional data transfer
▬ Quad SPI mode with bidirectional data transfer
 Data transmit/receive overrun detect
ADC
 12-bit SAR ADC with 800Ksps
▬ Configurable resolution : 12/10/8-bit
▬ Configurable sampling time
 Provide external 12 channels and internal 4 channels input
▬ Internal extra channel source : VBG , VSSA , LDO VR0 output , ADC Reference Voltage
 Support auto-sampling and trigger by external pin, internal events and software bit
 Data alignment for output code left/right justify
 Interrupt generation at the end of sampling, end of conversion, end of sequence conversion
 Support voltage window detection and output code limitation
 Built-in three channel independent hardware accumulators for ADC output code
 Support one-shot/channel scan/loop scan
 ADC data are buffered with DMA capability
 Support wait mode to prevent ADC overrun
Analog Comparator
 Provide 2 fast Rail-to-rail comparators
 Programmable 64-step threshold of internal voltage reference
 Provide external total 6 channels input for all comparators
 Programmable response time for optimal current consumption
 Selectable compare output polarity

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 Support wakeup from SLEEP and STOP modes
 Support analog watch dog as a reset source
GPL (General Purpose Logic)
 Support data inverse, bit order change, byte order change and parity check
▬ Data bit order change for 8/16/32-bit reverse
▬ Data byte order change between Little endian and Big endian for 16/32-bit range
▬ Parity Check for 8/16/32 bit range
 Support CRC (Cyclic Redundancy Check) calculation
▬ Programmable CRC initial value
▬ CRC output bit order change
 CRC with fixed common polynomial
▬ CRC8 polynomial 0x07
▬ CRC16 polynomial 0x8005
▬ CCITT16 polynomial 0x1021
▬ CRC32(IEEE 802.3) polynomial 0x4C11DB7
 Input data are buffered with DMA capability
Operating
 Operating voltage range 1.8V ~ 5.5V
 Operating temperature range -40℃ ~ 105℃
 Operating frequency range up to 48MHz
Package Types
 LQFP48 / QFN32 / TSSOP20

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List of Contents
Features ............................................................................................................................................................................ 3
List of Contents ................................................................................................................................................................ 8
List of Figures ................................................................................................................................................................ 11
List of Tables .................................................................................................................................................................. 12
1. General Description ................................................................................................................................................ 13
2. Order Information .................................................................................................................................................... 14
3. Block Diagram ......................................................................................................................................................... 16
3.1. System Function Block ..................................................................................................................................................... 16
3.2. Chip Main Block ............................................................................................................................................................... 17
4. Pin Description ........................................................................................................................................................ 18
4.1. Pin Outline ........................................................................................................................................................................ 18
4.1.1. LQFP48 Package Pinout........................................................................................................................................ 18
4.1.2. QFN32 Package Pinout ......................................................................................................................................... 19
4.1.3. TSSOP20 Package Pinout ..................................................................................................................................... 20
4.2. Pin Definition .................................................................................................................................................................... 21
4.3. Pin Alternate Functions Selected Table ............................................................................................................................ 27
5. Memory Map ............................................................................................................................................................ 28
5.1. Memory Organization ....................................................................................................................................................... 28
5.2. CPU Memory Map ............................................................................................................................................................ 28
5.3. Peripheral Memory Boundary ........................................................................................................................................... 29
5.4. Boot Modes ...................................................................................................................................................................... 31
6. Functional Description ........................................................................................................................................... 32
6.1. CPU Core ......................................................................................................................................................................... 32
6.1.1. Introduction ............................................................................................................................................................ 32
6.1.2. CPU Features ........................................................................................................................................................ 32
6.1.3. ARM Cortex-M0 Processor .................................................................................................................................... 32
6.2. Power Management ......................................................................................................................................................... 33
6.2.1. Introduction ............................................................................................................................................................ 33
6.2.2. Chip Power Features ............................................................................................................................................. 33
6.2.3. Power Operation Mode .......................................................................................................................................... 33
6.2.4. Power Supply ......................................................................................................................................................... 33
6.2.5. CPU Power Down .................................................................................................................................................. 34
6.3. System Reset ................................................................................................................................................................... 34
6.3.1. Introduction ............................................................................................................................................................ 34
6.3.2. Chip Reset Features .............................................................................................................................................. 34
6.3.3. Chip Reset Levels .................................................................................................................................................. 34
6.3.4. External Reset ....................................................................................................................................................... 35
6.3.5. Module Reset ......................................................................................................................................................... 35
6.4. System Clock ................................................................................................................................................................... 35
6.4.1. Introduction ............................................................................................................................................................ 35
6.4.2. Chip Clock Features .............................................................................................................................................. 35
6.4.3. System Clock Source ............................................................................................................................................. 35
6.4.4. PLL Clock............................................................................................................................................................... 35
6.4.5. Module Process Clock Control ............................................................................................................................... 35
6.5. System Common Control ................................................................................................................................................. 35

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6.5.1. Introduction ............................................................................................................................................................ 35
6.5.2. Features ................................................................................................................................................................. 35
6.6. Memory Access ................................................................................................................................................................ 36
6.6.1. Introduction ............................................................................................................................................................ 36
6.6.2. Features ................................................................................................................................................................. 36
6.6.3. Memory Controller ................................................................................................................................................. 36
6.6.4. ICP/ISP/IAP for Flash Memory ............................................................................................................................... 36
6.6.5. Hardware Option Byte Flash Memory .................................................................................................................... 36
6.7. GPIO ................................................................................................................................................................................ 36
6.7.1. Introduction ............................................................................................................................................................ 36
6.7.2. Features ................................................................................................................................................................. 37
6.7.3. GPIO Control Block ................................................................................................................................................ 37
6.8. Interrupt ............................................................................................................................................................................ 37
6.8.1. Introduction ............................................................................................................................................................ 37
6.8.2. Interrupt Features .................................................................................................................................................. 38
6.8.3. Interrupt Structure .................................................................................................................................................. 38
6.8.4. Nested Vectored Interrupt Controller ..................................................................................................................... 39
6.8.5. Wakeup Interrupt Controller ................................................................................................................................... 39
6.8.6. External Interrupt Controller ................................................................................................................................... 39
6.9. General Purpose Logic..................................................................................................................................................... 40
6.9.1. Introduction ............................................................................................................................................................ 40
6.9.2. Features ................................................................................................................................................................. 40
6.10. APB Common Control ...................................................................................................................................................... 40
6.10.1. Introduction ............................................................................................................................................................ 40
6.10.2. Features ................................................................................................................................................................. 40
6.11. Direct Memory Access...................................................................................................................................................... 40
6.11.1. Features ................................................................................................................................................................. 40
6.11.2. DMA Control Block ................................................................................................................................................. 41
6.12. ADC.................................................................................................................................................................................. 41
6.12.1. Introduction ............................................................................................................................................................ 41
6.12.2. Features ................................................................................................................................................................. 41
6.12.3. ADC Control Block ................................................................................................................................................. 41
6.13. Analog Comparator .......................................................................................................................................................... 42
6.13.1. Introduction ............................................................................................................................................................ 42
6.13.2. Features ................................................................................................................................................................. 42
6.13.3. CMP Control Block ................................................................................................................................................. 42
6.14. IWDT ................................................................................................................................................................................ 43
6.14.1. Introduction ............................................................................................................................................................ 43
6.14.2. Features ................................................................................................................................................................. 43
6.14.3. IWDT Control ......................................................................................................................................................... 43
6.15. WWDT.............................................................................................................................................................................. 43
6.15.1. Introduction ............................................................................................................................................................ 43
6.15.2. Features ................................................................................................................................................................. 43
6.15.3. WWDT Control ....................................................................................................................................................... 43
6.16. RTC .................................................................................................................................................................................. 44
6.16.1. Introduction ............................................................................................................................................................ 44
6.16.2. Features ................................................................................................................................................................. 44

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6.16.3. RTC Control ........................................................................................................................................................... 44
6.17. Timer ................................................................................................................................................................................ 44
6.17.1. Introduction ............................................................................................................................................................ 44
6.17.2. Features ................................................................................................................................................................. 44
6.17.3. Timer Modules' Function Table .............................................................................................................................. 45
6.17.4. Timer Control Block ............................................................................................................................................... 46
6.18. I2C.................................................................................................................................................................................... 46
6.18.1. Introduction ............................................................................................................................................................ 46
6.18.2. Features ................................................................................................................................................................. 46
6.18.3. I2C Control ............................................................................................................................................................. 47
6.19. UART ............................................................................................................................................................................... 47
6.19.1. Introduction ............................................................................................................................................................ 47
6.19.2. Features ................................................................................................................................................................. 47
6.19.3. UART Control ......................................................................................................................................................... 48
6.20. SPI ................................................................................................................................................................................... 48
6.20.1. Introduction ............................................................................................................................................................ 48
6.20.2. Features ................................................................................................................................................................. 49
6.20.3. SPI Control............................................................................................................................................................. 49
7. Application Notes .................................................................................................................................................... 50
7.1. Power Supply Circuit ........................................................................................................................................................ 50
7.2. Reset Circuit ..................................................................................................................................................................... 50
7.3. Xtal Oscillating Circuit ...................................................................................................................................................... 51
7.4. ADC Application Circuit .................................................................................................................................................... 52
8. Electrical Characteristics ....................................................................................................................................... 53
8.1. Parameter Glossary ......................................................................................................................................................... 53
8.2. Absolute Maximum Rating ............................................................................................................................................... 53
8.3. DC Characteristics ........................................................................................................................................................... 53
8.4. External Reset Pin Characteristics ................................................................................................................................... 55
8.5. External Clock Characteristics ......................................................................................................................................... 55
8.6. PLL Characteristics .......................................................................................................................................................... 56
8.7. IHRCO Characteristics ..................................................................................................................................................... 56
8.8. ILRCO Characteristics...................................................................................................................................................... 56
8.9. LDO Characteristics ......................................................................................................................................................... 56
8.10. Flash Characteristics ........................................................................................................................................................ 57
8.11. ADC Characteristics ......................................................................................................................................................... 57
8.12. ADC PGA Characteristics................................................................................................................................................. 58
8.13. Analog Comparator Characteristics.................................................................................................................................. 58
8.14. UART Characteristics ....................................................................................................................................................... 59
8.15. SPI Characteristics ........................................................................................................................................................... 59
8.16. I2C Characteristics ........................................................................................................................................................... 60
9. Package Dimension ................................................................................................................................................ 62
9.1. LQFP-48........................................................................................................................................................................... 62
9.2. QFN-32 ............................................................................................................................................................................ 63
9.3. TSSOP-20 ........................................................................................................................................................................ 64
10. Revision History ...................................................................................................................................................... 65
11. Disclaimers .............................................................................................................................................................. 66

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List of Figures
Figure 2-1. Part Numbering.....................................................................................................................................14
Figure 3-1. System Function Block .........................................................................................................................16
Figure 3-2. Chip Main Block ....................................................................................................................................17
Figure 4-1. LQFP48 Package Pinout ......................................................................................................................18
Figure 4-2. QFN32 Package Pinout ........................................................................................................................19
Figure 4-3. TSSOP20 Package Pinout ...................................................................................................................20
Figure 5-1. CPU Memory Map ................................................................................................................................28
Figure 6-1. ARM Cortex-M0 Processor ...................................................................................................................32
Figure 7-1. Power Supply Circuit ............................................................................................................................50
Figure 7-2. Reset Circuit .........................................................................................................................................50
Figure 7-3. XTAL Oscillating Circuit ........................................................................................................................51
Figure 7-4. ADC Application Circuit ........................................................................................................................52
Figure 9-1. LQFP-48 (7mm X 7mm ) ......................................................................................................................62
Figure 9-2. QFN-32 (5mm X 5mm ) ........................................................................................................................63
Figure 9-3. TSSOP-20 (6.5 x 4.4 x1.0 mm) ............................................................................................................64

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List of Tables
Table 2-1. Chip Selection Table ..............................................................................................................................15
Table 4-1. Abbreviations for pin definition...............................................................................................................21
Table 4-2. Pin Descriptions .....................................................................................................................................21
Table 4-3. Pin Alternate Functions Selected Table.................................................................................................27
Table 5-1. CPU Memory Address Map ...................................................................................................................29
Table 5-2. Peripheral Memory Boundary Address ..................................................................................................29
Table 6-1. Power-Down Mode Selection ................................................................................................................34
Table 6-2. Interrupt Source Table ...........................................................................................................................39
Table 6-3. Timer Modules' Function Table..............................................................................................................45
Table 7-1. Reference Capacitance of C1 & C2 for crystal oscillating circuit ..........................................................51
Table 8-1. Parameter Glossary ...............................................................................................................................53
Table 8-2. Absolute Maximum Rating .....................................................................................................................53
Table 8-3. DC Characteristics .................................................................................................................................53
Table 8-4. External Reset Pin Characteristics ........................................................................................................55
Table 8-5. External Clock Characteristics ...............................................................................................................55
Table 8-6. PLL Characteristics ................................................................................................................................56
Table 8-7. IHRCO Characteristics...........................................................................................................................56
Table 8-8. ILRCO Characteristics ...........................................................................................................................56
Table 8-9. LDO Characteristics ...............................................................................................................................56
Table 8-10. Flash Characteristics ...........................................................................................................................57
Table 8-11. ADC Characteristics.............................................................................................................................57
Table 8-12. ADC PGA Characteristics ....................................................................................................................58
Table 8-13. Analog Comparator Characteristics .....................................................................................................58
Table 8-14. UART Characteristics ..........................................................................................................................59
Table 8-15. SPI Characteristics ..............................................................................................................................59
Table 8-16. I2C Characteristics...............................................................................................................................60

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1. General Description
The MG32F02A is a single-chip 32-bit microcontroller based on a high performance Core ARM 32-bit
Cortex™-M0 CPU with embedded Nested Vectored Interrupt Controller (NVIC).

The MG32F02A has up to 32K bytes of embedded main flash memory for code and data, programmable
memory size of embedded system flash memory for boot load code and 64 bytes of embedded option-byte
flash memory for chip configuration. The all flash memory can be programmed either in serial writer mode (ICP,
In-Circuit-Programming). Also, the main flash memory can be programmed in ISP (In-System Programming)
mode or SRAM (Boot on SRAM) mode. ICP and ISP allow the user to download new code without removing
the microcontroller from the actual end product; IAP means that the device can write non-volatile data in the
flash memory while the application program is running. There needs no external high voltage for programming
due to its built-in charge-pumping circuitry.

The MG32F02A retains all features of the ARM 32-bit Cortex™-M0 with 4K bytes of SRAM, 4 I/O ports, 32
external interrupts source with 4-level interrupt controller and seven 8/16-bits timer/counters. In addition, the
MG32F02A has a System Tick Timer, two Watchdog Timers, three advance timer modules with IC/OC, four
Basic timer modules for universal using, on-chip crystal oscillator for 32.768 KHz to 25MHz, two high precision
internal oscillators IHRCO for 11.059/12MHz and ILRCO for 32 KHz, one 12-bit ADC and two analog
comparators with programmable threshold.

Also, the MG32F02A support multiple and flexible communicate interface for production application. It
provides alternate function pins those are including of GPIO, I2C, SPI, KBI, UART, SmartCard, LIN and
SWD(on chip debug). It has maximum 44 GPIO pins and provides programmable IO type - quasi-bidirectional ,
push-pull output , open-drain output , input only(Hi-z) with optional pull-high. In addition, it is built-in internal de-
bounce circuit to deglitch noise for worse signals.

One direct memory access (DMA) controller is used to improve data transfer between peripherals and
memory and memory to memory. The data can be transfer by DMA controller and does not cost any CPU time.

For power management and reset control, the MG32F02A is built-in a power supervisor including of a Low
Voltage Detector(LVD), two Brown-out Detectors(BOD0/BOD1), a Power-On Reset(POR) , a Low-voltage
Reset(LVR). The MG32F02A has multiple power-down modes to reduce the power consumption: Sleep mode
and Stop mode.

In the Sleep mode the CPU is frozen while the peripherals and the interrupt system are still operating. In
the Stop mode the RAM and SFRs’ value are saved and all other functions are inoperative; most importantly, in
the Sleep mode the chip can be waked up by many interrupt or reset sources(POR/LVR/BOD0/BOD1).

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2. Order Information
Please contact the megawin sales for available options (memory size, package …) and more information
about this device.
Figure 2-1. Part Numbering
MG 32 F 0 2A xxx yy zz

megawin

Device family
32 = 32-bit MCU

Application family
F = Mainstream
L = Low Power

MCU Series
0 = ARM Cortex-M0

Device Series

Program memory size

032 = 32 Kbyte

Package type
AD = LQFP
AY = QFN
AT = TSSOP

Pin count
48 = 48 pins
32 = 32 pins
20 = 20 pins

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 Chip Selection
Table 2-1. Chip Selection Table
Chip Number MG32F02A032 Comment
Flash ROM 32KB memory space of AP+IAP+ISP

SRAM 4KB

Max. CPU Frequency 48MHz

Internal Clock Source ILRCO+IHRCO 12MHz(default) & 11.059MHz option for IHRCO

Voltage Detector LVR+BOD0/1

IO Number 44/29/17

Timers 16-bit*2 + 32-bit*3 support Full-Counter, Cascade , Separate modes

IC/OC/PWM 4-CH OC support (normal + complement output)

WDT IWDT + WWDT

RTC yes

ADC 12-Bit , 12-CH embedded one input buffer with PGA

Analog Comparator 2 embedded two R-ladder voltage reference

support SPI master,Multi-processor,IrDa,LIN,ISO-7816
UART 2
(SmartCard),Hardware flow control
SPI 1 Support 1/2/4/8 data line modes

I2C 1 optional Byte/Buffer mode

ISO-7816-3 2 (*1) included and shared in UART module (SmartCard)

LIN 2 (*1) included and shared in UART module

memory-to-memory, memory-to-peripheral, peripheral-to-
DMA 1-CH
memory, peripheral-to-peripheral
CRC yes
LQFP48
Package QFN32
TSSOP20
Operation Voltage 1.8~5.5V -40°C ~ 105°C

ICP yes In-Chip-Programming

In-System-Programming
ISP yes ISP flash memory is included in the same space of embedded
flash memory
In-Application-Programming
IAP yes IAP flash memory is included in the same space of embedded
flash memory

 Part Number List

▬ MG32F02A032AD48 : LQFP48 (10mm x 10mm), 32KB Flash
▬ MG32F02A032AY32 : QFN32 (7mm x 7mm), 32KB Flash
▬ MG32F02A032AT20 : TSSOP20 (6.5 x 4.4 x1.0 mm), 32KB Flash

megawin Version: 1.21 15

MG32F02A032

3. Block Diagram
3.1. System Function Block
The following diagram is showing the system function block for application.

Figure 3-1. System Function Block

System Block
MCU Power
Wide Range
5.5~1.8V LDO SPIx SPI Devices
Optional Optional POR LVR (Master/Slave)
Reset Chip RC Reset
BOD0 BOD1
I2C Devices
I2Cx (Master/Slave)
SW
IWDT UART Devices
Push
Key
URTx SmartCard, LIN
Reset WWDT IrDA, Modem
Reset Circuit
SPI (Master)
RTC

Xtal
OSC/
Optional Xtal TM0x
Clock OSC Trigger
Source Capture
IHRCO Compare Output
Optional External OSC/Clock ILRCO TM1x TM3x PWM Output
Compare Out PWM
Analog Signal

ADC Key pad

EXINT level input
KBI
COMPx
GPIO Interrupt
Signal System
Device

General Purpose
I/O Control

LED Switch Control

16 Version: 1.21 megawin

 MG32F02A032
3.2. Chip Main Block
The following diagram is showing the block of internal devices in the chip.
There are one embedded ARM Cortex-M0 processor with NVIC (Nested Vectored Interrupt Controller) and
DAP (Debug Access Port); AHB lite bus with SRAM/Flash memory, Power/Reset/Clock system controllers,
GPIO control blocks and GPL (General Purpose Logic); APB bus with UART/SPI/I2C communication
controllers, timers of general timer / IWDT / WWDT / RTC and analog control block of ADC / analog
comparators; analog devices of POR (power on reset), BOD0/BOD1 (Brown-Out Detectors), ILRCO (Internal
Low-frequency RC Oscillator)/IHRCO Internal High-frequency RC Oscillator)/PLL.

Figure 3-2. Chip Main Block

Chip Main Block

AP/Boot Power
SRAM
Memory Flash Control
Control
Hardware Reset
GPL
Option Control

SWCLK DAP Bus

SWDAT SWD Matrix AHB
AHB Lite Bus
Cortex Decoder
M0 CPU
NVIC

PAx
unctionSel

Port A I/O
AlternateF

AHB/APB Clock Control

PBx DMA PLL
Port B I/O Bridge
ect

PCx GPIO OSC

Port C I/O IHRCO
PDx
Port D I/O ILRCO

IO Bus IO Bus

BOD1 EXIC IWDT

VDD
VR0 LDO
5.0v to 1.8v
VSS
POR/LVR URTx WWDT
IO Bus

BOD0
SPIx RTC
APB Bus

I2Cx TM0x
XIN
OSC
XOUT
IO Bus

TM1x
AMUX

ADC_In ADC TM3x

AMUX

CMPx_In
CMP_Cn COMPx APB

megawin Version: 1.21 17

MG32F02A032

4. Pin Description

4.1. Pin Outline

4.1.1. LQFP48 Package Pinout

Figure 4-1. LQFP48 Package Pinout

PA3/ADC3
PA2/ADC2
PA1/ADC1
PA0/ADC0
VREF+

PD10
VDD

VSS
VR0

PD9
PD8
PD7
48
47
46
45
44
43
42
41
40
39
38
37
ADC8/PA8 1 36 PD3/TM01CK
ADC9/PA9 2 35 PD2/TM00CK
ADC10/PA10 3 34 PD1/TM16CK
ADC11/PA11 4 33 PD0/TM10CK
ADC12/PA12 5 32 PC14/XOUT
ADC13/PA13 6
MG32F02A 31 PC13/XIN
ADC14/PA14 7 30 PC12
ADC15/PA15 8
LQFP48 29 PC11
NSS/PB0 9 28 PC10
MISO/PB1 10 27 PC9/RXD1
SCK/PB2 11 26 PC8/TXD1
MOSI/PB3 12 25 PC6/RSTN
13
14
15
16
17
18
19
20
21
22
23
24
TXD0/PC0
RXD0/PC1
PB13
PB14

PC2
PC3
SD3/PB8
SD2/PB9
SCL0/PB10
SDA0/PB11

SWDIO/PC5
SWCLK/PC4

2019_0118

Pin Group
GPIOA GPIOB

GPIOC GPIOD
Power/Ground Others

18 Version: 1.21 megawin

 MG32F02A032
4.1.2. QFN32 Package Pinout

Figure 4-2. QFN32 Package Pinout

PA3/ADC3

PA2/ADC2

PA1/ADC1

PA0/ADC0

VDD

VSS
VR0

PD7
32

31

30

29

28

27

26

25
ADC8/PA8 1 24 PD2/TM00CK

ADC9/PA9 2 23 PD1/TM16CK

ADC10/PA10 3 22 PD0/TM10CK

ADC11/PA11 4 MG32F02A 21 PC14/XOUT

NSS/PB0 5 QFN32 20 PC13/XIN

MISO/PB1 6 19 PC9/RXD1

SCK/PB2 7 18 PC8/TXD1

MOSI/PB3 8 0 VSS/EPAD 17 PC6/RSTN

10

11

12

13

14

15

16
9

TXD0/PC0

RXD0/PC1
SD3/PB8

SD2/PB9

SCL0/PB10

SDA0/PB11

SWDIO/PC5
SWCLK/PC4

2019_0118

megawin Version: 1.21 19

MG32F02A032
4.1.3. TSSOP20 Package Pinout

Figure 4-3. TSSOP20 Package Pinout

XIN/PC13 1 20 PC6/RSTN
XOUT/PC14 2 19 PC5/SWDIO
VSS 3 18 PC4/SWCLK

MG32F02A
TSSOP20
VR0 4 17 PC1/RXD0
VDD 5 16 PC0/TXD0
ADC8/PA8 6 15 PB11/SDA0
ADC10/PA10 7 14 PB10/SCL0
NSS/PB0 8 13 PB9/SD2
MISO/PB1 9 12 PB8/SD3
SCK/PB2 10 11 PB3/MOSI

2019_0118

20 Version: 1.21 megawin

 MG32F02A032
4.2. Pin Definition
Table 4-1. Abbreviations for pin definition
IO Type IO Structure
P Power/Ground pin I Digital Input
B Bidirection P Output Push-pull capability
I Input O Output Open drain capability
O Output Q Quasi-bidirectional
A Analog I/O A Analog I/O (Digital I/O disable)
AO Analog output only U Internal pull-up
AI Analog input only H High Speed
- C2 Programmable 2-level driving strength
- C4 Programmable 4-level driving strength
- CF Fixed driving strength(GPIO mode)

Table 4-2. Pin Descriptions

IO Type

Pin Pin Number Default IO Alternate Description

LQFP48

QFN32

TSSOP20

Type

Value

Name Structure Functions

PA0 45 29 B A A,I,P,O,U,H,C2 GPA0 GPIO/Interrupt/KBI Port-A function pin--0

ADC_I0 ADC analog single-end/differential plus input
channel 0
PA1 46 30 B A A,I,P,O,U,H,C2 GPA1 GPIO/Interrupt/KBI Port-A function pin-1
ADC_I1 ADC analog single-end/differential plus input
channel 1
PA2 47 31 B A A,I,P,O,U,H,C2 GPA2 GPIO/Interrupt/KBI Port-A function pin-2
ADC_I2 ADC analog single-end/differential plus input
channel 2
PA3 48 32 B A A,I,P,O,U,H,C2 GPA3 GPIO/Interrupt/KBI Port-A function pin-3
ADC_I3 ADC analog single-end/differential plus input
channel 3
PA8 1 1 6 B A A,I,P,O,U,H,C2 GPA8 GPIO/Interrupt/KBI Port-A function pin-8
ADC_I8 ADC analog single-end/differential plus input
channel 8
CMP0_I0 Comparator-0 analog input channel 0
VBG_OUT Bandgap voltage output
PA9 2 2 B A A,I,P,O,U,H,C2 GPA9 GPIO/Interrupt/KBI Port-A function pin-9
ADC_I9 ADC analog single-end/differential plus input
channel 9
CMP0_I1 Comparator-0 analog input channel 1
PA10 3 3 7 B A A,I,P,O,U,H,C2 GPA10 GPIO/Interrupt/KBI Port-A function pin-10
ADC_I10 ADC analog single-end/differential plus input
channel 10
CMP1_I0 Comparator-1 analog input channel 0
ADC_PGA ADC PGA voltage output
PA11 4 4 B A A,I,P,O,U,H,C2 GPA11 GPIO/Interrupt/KBI Port-A function pin-11
ADC_I11 ADC analog single-end/differential plus input
channel 11
CMP1_I1 Comparator-1 analog input channel 1

megawin Version: 1.21 21

MG32F02A032
PA12 5 B A A,I,P,O,U,H,C2 GPA12 GPIO/Interrupt/KBI Port-A function pin-12
URT1_BRO URT1 baud-rate timer overflow output signal
TM10_ETR TM10 external trigger/clock input signal
TM36_IC0 TM36 input capture channel-0
ADC_I12 ADC analog single-end/differential plus input
channel 12
PA13 6 B A A,I,P,O,U,H,C2 GPA13 GPIO/Interrupt/KBI Port-A function pin-13
CPU_TXEV CPU wakeup event output
URT0_BRO URT0 baud-rate timer overflow output signal
URT1_TMO URT1 timeout timer overflow output signal
TM10_TRGO TM10 trigger output signal
TM36_IC1 TM36 input capture channel-1
ADC_I13 ADC analog single-end/differential plus input
channel 13
PA14 7 B A A,I,P,O,U,H,C2 GPA14 GPIO/Interrupt/KBI Port-A function pin-14
CPU_RXEV CPU wakeup event input
OBM_I0 Output signal break control input signal-0
URT0_TMO URT0 timeout timer overflow output signal
URT1_CTS URT1 CTS input control signal
TM16_ETR TM16 external trigger/clock input signal
TM36_IC2 TM36 input capture channel-2
ADC_I14 ADC analog single-end/differential plus input
channel 14
PA15 8 B A A,I,P,O,U,H,C2 GPA15 GPIO/Interrupt/KBI Port-A function pin-15
CPU_NMI CPU NMI external pin input
OBM_I1 Output signal break control input signal-1
URT0_DE URT0 external drive enable output signal
URT1_RTS URT1 RTS output control signal
TM16_TRGO TM16 trigger output signal
TM36_IC3 TM36 input capture channel-3
ADC_I15 ADC analog single-end/differential plus input
channel 15
PB0 9 5 8 B A A,I,P,O,U,H,C4 GPB0 GPIO/Interrupt/KBI Port-B function pin-0
SPI0_NSS SPI0 slave select input/output signal
TM01_ETR TM01 external trigger/clock input signal
TM00_CKO TM00 timer overflow output signal
TM16_ETR TM16 external trigger/clock input signal
TM36_ETR TM36 external trigger/clock input signal
CMP_C0 Comparator analog input common channel 0
PB1 10 6 9 B A A,I,P,O,U,H,C4 GPB1 GPIO/Interrupt/KBI Port-B function pin-1
SPI0_MISO SPI0 master input / slave output signal or data-1
signal for 4-I/O mode
TM01_TRGO TM01 trigger output signal
TM10_CKO TM10 timer overflow output signal
TM16_TRGO TM16 trigger output signal
TM36_TRGO TM36 trigger output signal
CMP_C1 Comparator analog input common channel 1
PB2 11 7 10 B A A,I,P,O,U,H,C4 GPB2 GPIO/Interrupt/KBI Port-B function pin-2
ADC0_TRG ADC trigger start input

22 Version: 1.21 megawin

 MG32F02A032
SPI0_CLK SPI0 clock signal
TM01_CKO TM01 timer overflow output signal
TM16_CKO TM16 timer overflow output signal
I2C0_SDA I2C0 SDA signal
URT0_TX URT0 transmit TX signal, SPI MOSI signal
PB3 12 8 11 B A A,I,P,O,U,H,C4 GPB3 GPIO/Interrupt/KBI Port-B function pin-3
ADC0_OUT ADC threshold window compare output
SPI0_MOSI SPI0 master output / slave input signal or data-0
signal for 4-I/O mode
TM36_CKO TM36 timer overflow output signal
I2C0_SCL I2C0 SCL signal
URT0_RX URT0 receive RX signal, SPI MISO signal
PB8 13 9 12 B A A,I,P,O,U,H,C4 GPB8 GPIO/Interrupt/KBI Port-B function pin-8
CMP0_P0 Comparator-0 data output
RTC_OUT RTC selection output signal
URT0_TX URT0 transmit TX signal, SPI MOSI signal
TM36_OC01 TM36 output compare/PWM channel-01
SPI0_D3 SPI0 data-3 signal for 4-I/O mode
OBM_P0 Output signal break control output signal-0
PB9 14 10 13 B A A,I,P,O,U,H,C4 GPB9 GPIO/Interrupt/KBI Port-B function pin-9
CMP1_P0 Comparator-1 data output
RTC_TS RTC time stamp input signal
URT0_RX URT0 receive RX signal, SPI MISO signal
TM36_OC02 TM36 output compare/PWM channel-02
SPI0_D2 SPI0 data-2 signal for 4-I/O mode
OBM_P1 Output signal break control output signal-1
PB10 15 11 14 B A A,I,P,O,U,H,C2 GPB10 GPIO/Interrupt/KBI Port-B function pin-10
I2C0_SCL I2C0 SCL signal
URT0_NSS URT0 SPI NSS output signal
TM36_OC11 TM36 output compare/PWM channel-11
URT1_TX URT1 transmit TX signal, SPI MOSI signal
SPI0_NSSI SPI0 slave select input only signal
PB11 16 12 15 B A A,I,P,O,U,H,C2 GPB11 GPIO/Interrupt/KBI Port-B function pin-11
I2C0_SDA I2C0 SDA signal
URT0_DE URT0 external drive enable output signal
IR_OUT IR output signal
TM36_OC12 TM36 output compare/PWM channel-12
URT1_RX URT1 receive RX signal, SPI MISO signal
DMA_TRG0 DMA external trigger pin-0 input
PB13 17 B A A,I,P,O,U,H,C2 GPB13 GPIO/Interrupt/KBI Port-B function pin-13
TM00_ETR TM00 external trigger/clock input signal
URT0_CTS URT0 CTS input control signal
TM36_ETR TM36 external trigger/clock input signal
PB14 18 B A A,I,P,O,U,H,C2 GPB14 GPIO/Interrupt/KBI Port-B function pin-14
DMA_TRG0 DMA external trigger pin-0 input
TM00_TRGO TM00 trigger output signal
URT0_RTS URT0 RTS output control signal
TM36_BK0 TM36 break input signal
PC0 19 13 16 B Q H A,I,P,O,Q,U,H,C GPC0 GPIO/Interrupt/KBI Port-C function pin-0

megawin Version: 1.21 23

MG32F02A032
2 ICKO Internal clock source clock output
TM00_CKO TM00 timer overflow output signal
URT0_CLK URT0 clock signal
TM36_OC00 TM36 output compare/PWM channel-00
I2C0_SCL I2C0 SCL signal
URT0_TX URT0 transmit TX signal, SPI MOSI signal
PC1 20 14 17 B Q H A,I,P,O,Q,U,H,C GPC1 GPIO/Interrupt/KBI Port-C function pin-1
2 ADC0_TRG ADC trigger start input
TM01_CKO TM01 timer overflow output signal
TM36_IC0 TM36 input capture channel-0
URT1_CLK URT1 clock signal
TM36_OC0N TM36 output compare/PWM complement
channel-0
I2C0_SDA I2C0 SDA signal
URT0_RX URT0 receive RX signal, SPI MISO signal
PC2 21 B Q H A,I,P,O,Q,U,H,C GPC2 GPIO/Interrupt/KBI Port-C function pin-2
2 ADC0_OUT ADC threshold window compare output
TM10_CKO TM10 timer overflow output signal
OBM_P0 Output signal break control output signal-0
TM36_OC10 TM36 output compare/PWM channel-10
PC3 22 B Q H A,I,P,O,Q,U,H,C GPC3 GPIO/Interrupt/KBI Port-C function pin-3
2 OBM_P1 Output signal break control output signal-1
TM16_CKO TM16 timer overflow output signal
URT0_CLK URT0 clock signal
URT1_CLK URT1 clock signal
TM36_OC1N TM36 output compare/PWM complement
channel-1
PC4 23 15 18 B Q H A,I,P,O,Q,U,H,C GPC4 GPIO/Interrupt/KBI Port-C function pin-4
2 SWCLK Serial wire debug clock signal
I2C0_SCL I2C0 SCL signal
URT0_RX URT0 receive RX signal, SPI MISO signal
URT1_RX URT1 receive RX signal, SPI MISO signal
TM36_OC2 TM36 output compare/PWM channel-2
PC5 24 16 19 B Q H A,I,P,O,Q,U,H,C GPC5 GPIO/Interrupt/KBI Port-C function pin-5
2 SWDIO Serial wire debug data signal
I2C0_SDA I2C0 SDA signal
URT0_TX URT0 transmit TX signal, SPI MOSI signal
URT1_TX URT1 transmit TX signal, SPI MOSI signal
TM36_OC3 TM36 output compare/PWM channel-3
PC6 25 17 20 B Q H A,I,P,O,Q,U,CF GPC6 GPIO/Interrupt/KBI Port-C function pin-6
RSTN External hardware reset input
RTC_TS RTC time stamp input signal
URT0_NSS URT0 SPI NSS output signal
URT1_NSS URT1 SPI NSS output signal
PC8 26 18 B Q H A,I,P,O,Q,U,H,C GPC8 GPIO/Interrupt/KBI Port-C function pin-8
2 ADC0_OUT ADC threshold window compare output
I2C0_SCL I2C0 SCL signal
URT0_BRO URT0 baud-rate timer overflow output signal
URT1_TX URT1 transmit TX signal, SPI MOSI signal

24 Version: 1.21 megawin

 MG32F02A032
TM36_OC0H TM36 output compare/PWM high channel-0
TM36_OC0N TM36 output compare/PWM complement
channel-0
PC9 27 19 B Q H A,I,P,O,Q,U,H,C GPC9 GPIO/Interrupt/KBI Port-C function pin-9
2 CMP0_P0 Comparator-0 data output
I2C0_SDA I2C0 SDA signal
URT0_TMO URT0 timeout timer overflow output signal
URT1_RX URT1 receive RX signal, SPI MISO signal
TM36_OC1H TM36 output compare/PWM high channel-1
TM36_OC1N TM36 output compare/PWM complement
channel-1
PC10 28 B Q H A,I,P,O,Q,U,H,C GPC10 GPIO/Interrupt/KBI Port-C function pin-10
2 CMP1_P0 Comparator-1 data output
URT0_TX URT0 transmit TX signal, SPI MOSI signal
URT1_TX URT1 transmit TX signal, SPI MOSI signal
TM36_OC2H TM36 output compare/PWM high channel-2
TM36_OC2N TM36 output compare/PWM complement
channel-2
PC11 29 B Q H A,I,P,O,Q,U,H,C GPC11 GPIO/Interrupt/KBI Port-C function pin-11
2 URT0_RX URT0 receive RX signal, SPI MISO signal
URT1_RX URT1 receive RX signal, SPI MISO signal
TM36_OC3H TM36 output compare/PWM high channel-3
PC12 30 B Q H A,I,P,O,Q,U,H,C GPC12 GPIO/Interrupt/KBI Port-C function pin-12
2 IR_OUT IR output signal
URT1_DE URT1 external drive enable output signal
TM10_TRGO TM10 trigger output signal
TM36_OC3 TM36 output compare/PWM channel-3
PC13 31 20 1 B Q H A,I,P,O,Q,U,CF GPC13 GPIO/Interrupt/KBI Port-C function pin-13
XIN External Xtal/OSC input
URT1_NSS URT1 SPI NSS output signal
URT0_CTS URT0 CTS input control signal
TM10_ETR TM10 external trigger/clock input signal
TM36_OC00 TM36 output compare/PWM channel-00
PC14 32 21 2 B Q H A,I,P,O,Q,U,H,C GPC14 GPIO/Interrupt/KBI Port-C function pin-14
F XOUT External Xtal output
URT1_TMO URT1 timeout timer overflow output signal
URT0_RTS URT0 RTS output control signal
TM10_CKO TM10 timer overflow output signal
TM36_OC10 TM36 output compare/PWM channel-10
PD0 33 22 B A A,I,P,O,U,H,C4 GPD0 GPIO/Interrupt/KBI Port-D function pin-0
OBM_I0 Output signal break control input signal-0
TM10_CKO TM10 timer overflow output signal
URT0_CLK URT0 clock signal
TM36_OC2 TM36 output compare/PWM channel-2
SPI0_NSS SPI0 slave select input/output signal
PD1 34 23 B A A,I,P,O,U,H,C4 GPD1 GPIO/Interrupt/KBI Port-D function pin-1
OBM_I1 Output signal break control input signal-1
TM16_CKO TM16 timer overflow output signal
URT0_CLK URT0 clock signal

megawin Version: 1.21 25

MG32F02A032
TM36_OC2N TM36 output compare/PWM complement
channel-2
SPI0_CLK SPI0 clock signal
PD2 35 24 B A A,I,P,O,U,H,C4 GPD2 GPIO/Interrupt/KBI Port-D function pin-2
TM00_CKO TM00 timer overflow output signal
URT1_CLK URT1 clock signal
TM36_CKO TM36 timer overflow output signal
SPI0_MOSI SPI0 master output / slave input signal or data-0
signal for 4-I/O mode
PD3 36 B A A,I,P,O,U,H,C4 GPD3 GPIO/Interrupt/KBI Port-D function pin-3
TM01_CKO TM01 timer overflow output signal
URT1_CLK URT1 clock signal
SPI0_D3 SPI0 data-3 signal for 4-I/O mode
TM36_TRGO TM36 trigger output signal
PD7 37 25 B A A,I,P,O,U,H,C4 GPD7 GPIO/Interrupt/KBI Port-D function pin-7
TM00_CKO TM00 timer overflow output signal
TM01_ETR TM01 external trigger/clock input signal
URT1_DE URT1 external drive enable output signal
SPI0_MISO SPI0 master input / slave output signal or data-1
signal for 4-I/O mode
TM36_IC0 TM36 input capture channel-0
PD8 38 B A A,I,P,O,U,H,C4 GPD8 GPIO/Interrupt/KBI Port-D function pin-8
CPU_TXEV CPU wakeup event output
TM01_TRGO TM01 trigger output signal
URT1_RTS URT1 RTS output control signal
SPI0_D2 SPI0 data-2 signal for 4-I/O mode
TM36_IC1 TM36 input capture channel-1
PD9 39 B A A,I,P,O,U,H,C2 GPD9 GPIO/Interrupt/KBI Port-D function pin-9
CPU_RXEV CPU wakeup event input
TM00_TRGO TM00 trigger output signal
URT1_CTS URT1 CTS input control signal
SPI0_NSSI SPI0 slave select input only signal
TM36_IC2 TM36 input capture channel-2
PD10 40 B A A,I,P,O,U,H,C2 GPD10 GPIO/Interrupt/KBI Port-D function pin-10
CPU_NMI CPU NMI external pin input
TM00_ETR TM00 external trigger/clock input signal
URT1_BRO URT1 baud-rate timer overflow output signal
RTC_OUT RTC selection output signal
TM36_IC3 TM36 input capture channel-3
VSS 41 26 3 P IO/Core/ADC ground
VR0 42 27 4 AO AO Core power supply/LDO output (place
0.1uF+4.7uF capacitors and close pin)
VDD 43 28 5 P IO power supply/LDO input (place 0.1uF+10uF
capacitors and close pin)
VREF+ 44 AI AI ADC voltage reference (place 0.1uF+4.7uF
capacitors and close pin)

26 Version: 1.21 megawin

 MG32F02A032
4.3. Pin Alternate Functions Selected Table
Table 4-3. Pin Alternate Functions Selected Table
Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF10
Name
PA0 GPA0
PA1 GPA1
PA2 GPA2
PA3 GPA3
PA8 GPA8
PA9 GPA9
PA10 GPA10
PA11 GPA11
PA12 GPA12 URT1_BRO TM10_ETR TM36_IC0
PA13 GPA13 CPU_TXEV URT0_BRO URT1_TMO TM10_TRGO TM36_IC1
PA14 GPA14 CPU_RXEV OBM_I0 URT0_TMO URT1_CTS TM16_ETR TM36_IC2
PA15 GPA15 CPU_NMI OBM_I1 URT0_DE URT1_RTS TM16_TRGO TM36_IC3
PB0 GPB0 SPI0_NSS TM01_ETR TM00_CKO TM16_ETR TM36_ETR
PB1 GPB1 SPI0_MISO TM01_TRGO TM10_CKO TM16_TRGO TM36_TRGO
PB2 GPB2 ADC0_TRG SPI0_CLK TM01_CKO TM16_CKO I2C0_SDA URT0_TX
PB3 GPB3 ADC0_OUT SPI0_MOSI TM36_CKO I2C0_SCL URT0_RX
PB8 GPB8 CMP0_P0 RTC_OUT URT0_TX TM36_OC01 SPI0_D3 OBM_P0
PB9 GPB9 CMP1_P0 RTC_TS URT0_RX TM36_OC02 SPI0_D2 OBM_P1
PB10 GPB10 I2C0_SCL URT0_NSS TM36_OC11 URT1_TX SPI0_NSSI
PB11 GPB11 I2C0_SDA URT0_DE IR_OUT TM36_OC12 URT1_RX DMA_TRG0
PB13 GPB13 TM00_ETR URT0_CTS TM36_ETR
PB14 GPB14 DMA_TRG0 TM00_TRGO URT0_RTS TM36_BK0
PC0 GPC0 ICKO TM00_CKO URT0_CLK TM36_OC00 I2C0_SCL URT0_TX
PC1 GPC1 ADC0_TRG TM01_CKO TM36_IC0 URT1_CLK TM36_OC0N I2C0_SDA URT0_RX
PC2 GPC2 ADC0_OUT TM10_CKO OBM_P0 TM36_OC10
PC3 GPC3 OBM_P1 TM16_CKO URT0_CLK URT1_CLK TM36_OC1N
PC4 GPC4 SWCLK I2C0_SCL URT0_RX URT1_RX TM36_OC2
PC5 GPC5 SWDIO I2C0_SDA URT0_TX URT1_TX TM36_OC3
PC6 GPC6 RSTN RTC_TS URT0_NSS URT1_NSS
PC8 GPC8 ADC0_OUT I2C0_SCL URT0_BRO URT1_TX TM36_OC0H TM36_OC0N
PC9 GPC9 CMP0_P0 I2C0_SDA URT0_TMO URT1_RX TM36_OC1H TM36_OC1N
PC10 GPC10 CMP1_P0 URT0_TX URT1_TX TM36_OC2H TM36_OC2N
PC11 GPC11 URT0_RX URT1_RX TM36_OC3H
PC12 GPC12 IR_OUT URT1_DE TM10_TRGO TM36_OC3
PC13 GPC13 XIN URT1_NSS URT0_CTS TM10_ETR TM36_OC00
PC14 GPC14 XOUT URT1_TMO URT0_RTS TM10_CKO TM36_OC10
PD0 GPD0 OBM_I0 TM10_CKO URT0_CLK TM36_OC2 SPI0_NSS
PD1 GPD1 OBM_I1 TM16_CKO URT0_CLK TM36_OC2N SPI0_CLK
PD2 GPD2 TM00_CKO URT1_CLK TM36_CKO SPI0_MOSI
PD3 GPD3 TM01_CKO URT1_CLK SPI0_D3 TM36_TRGO
PD7 GPD7 TM00_CKO TM01_ETR URT1_DE SPI0_MISO TM36_IC0
PD8 GPD8 CPU_TXEV TM01_TRGO URT1_RTS SPI0_D2 TM36_IC1
PD9 GPD9 CPU_RXEV TM00_TRGO URT1_CTS SPI0_NSSI TM36_IC2
PD10 GPD10 CPU_NMI TM00_ETR URT1_BRO RTC_OUT TM36_IC3

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5. Memory Map
5.1. Memory Organization
There are 4K bytes of SRAM built in the chip. The chip has up to 32K bytes of embedded main flash
memory for code and data, programmable memory size of embedded system flash memory for boot load code
and 64 bytes of embedded option-byte (OB) flash memory for chip configuration. Others, there are many
module independent hardware control registers and locate at the memory space of AHB/APB devices.
User can configure the whole flash to store for his Application Program (AP) code, In-System-Program (ISP)
code and In-Application-Program (IAP) memory. User can adjust the size for the three flash memories.
5.2. CPU Memory Map
The following diagram is showing the memory map of CPU. There are separated eight memory blocks and
the memory size is 512M-byte for each block. The block is signed “XN” which is not able to execute code.

CPU
Figure 5-1. CPU Memory Map Memory Map
Block/Type CPU Address Linear Logical Address Size

Device
System Device 512MB
XN Space
Private Peripheral Bus
0xE000 0000

External
1GB
Device External Device Space
XN
0xA000 0000

1GB
External RAM External RAM Space
0x6000 0000

Peripheral 512MB
XN
AHB/APB Devices Space
0x4000 0000

512MB
SRAM
Space
0x2000 0000
SRAM
0x1FF4 0000
OB2 Flash
0x1FF3 0000
OB1 Flash
0x1FF2 0000
OB0 Flash
0x1FF1 0000
0x1FF0 0000 ISPD Flash

0x1C00 0000 ISP Flash

Code 512MB
(Flash) Space
0x1A00 0000 IAP Flash

AP Flash
0x1800 0000

Relocated Boot
Memory Space
0x0000 0000 (no physical memory)

<Note-1> : XN ~ eXecute Never

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Table 5-1. CPU Memory Address Map
Block Block Boundary address Size
XN Address Space Note
Index Name Start address End address
0xE010 0000 0xFFFF FFFF 511MB VENDOR_SYS
System
7 Device XN Private Peripheral M0 Reserved
0xE000 0000 0xE00F FFFF 1MB
Bus(PPB) Cortex M0 internal peripherals
External
6 Device XN 0xC000 0000 0xDFFF FFFF 512MB Reserved External memory (SRAM, Flash)

5 External XN 0xA000 0000 0xBFFF FFFF 512MB Reserved External memory (SRAM, Flash)
Device
4 External 0x8000 0000 0x9FFF FFFF 512MB Reserved External memory (SRAM, Flash)
RAM
External
3 RAM 0x6000 0000 0x7FFF FFFF 512MB Reserved External memory (SRAM, Flash)
2 Peripheral XN 0x4000 0000 0x5FFF FFFF 512MB APB/AHB APB/AHB modules
0x2000 1000 0x3FFF FFFF 512MB Reserved
1
0x2000 0000 0x2000 0FFF 4KB SRAM
0x1FF4 0000 0x1FFF FFFF 768KB Reserved
0x1FF3 0400 0x1FF3 FFFF 63KB Reserved
0x1FF3 0040 0x1FF3 03FF 960B
OB Flash-2
0x1FF3 0000 0x1FF3 003F 64B Hardware Option byte-2 (64-byte)
0x1FF2 0400 0x1FF2 FFFF 63KB Reserved
0x1FF2 0050 0x1FF2 03FF 944B
0x1FF2 0040 0x1FF2 004F 16B OB Flash-1 Random ID (16-byte)
0x1FF2 0000 0x1FF2 003F 64B Hardware Option byte-1 (64-byte)
0x1FF1 0400 0x1FF1 FFFF 63KB Reserved
0x1FF1 0040 0x1FF1 03FF 960B
OB Flash-0
0x1FF1 0000 0x1FF1 003F 64B Hardware Option byte-0 (64-byte)
0 Code 0x1FF0 0400 0x1FF0 FFFF 63KB Reserved
0x1FF0 0000 0x1FF0 03FF 1KB ISPD Flash ISP data flash
0x1C00 8000 0x1FEF FFFF 63MB Reserved
Boot Flash memory (configurable
0x1C00 0000 0x1C00 7FFF 32KB ISP Flash
size)
0x1A00 8000 0x1BFF FFFF 32MB Reserved
Data Flash memory (configurable
0x1A00 0000 0x1A00 7FFF 32KB IAP Flash
size)
0x1800 8000 0x19FF FFFF 32MB Reserved
Application Flash memory
0x1800 0000 0x1800 7FFF 32KB AP Flash
(configurable size by chip option)
0x0000 8000 0x17FF FFFF 384MB Reserved
Relocated memory Interrupt Vector
0x0000 0000 0x0000 7FFF 32KB
space 0x0000 00C0~0x0000 0000
XN : eXecute Never , 1 Block = 512MB
Relocated memory space : Main flash memory, Boot flash memory or SRAM depending on BOOT configuration

5.3. Peripheral Memory Boundary

Table 5-2. Peripheral Memory Boundary Address
Boundary address Sections /
Address Size Groups Module Note
Type Start address End address
Peripheral
0x5F00 0100 0x5FFF FFFF 16MB Reserved
APB
0x5F00 0000 0x5F00 00FF 256B APB APB module global control
0x5E00 0000 0x5EFF FFFF 16MB Reserved Reserved
0x5D04 0100 0x5DFF FFFF 16MB Reserved
APB 0x5D04 0000 0x5D04 00FF 256B RTC Real Time Clock
0x5D01 0100 0x5D03 FFFF 192KB Reserved
WDT/RTC
0x5D01 0000 0x5D01 00FF 256B WWDT Window WatchDog Timer
0x5D00 0100 0x5D00 FFFF 64KB Reserved
0x5D00 0000 0x5D00 00FF 256B IWDT Independent WatchDog Timer

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0x5C00 0100 0x5CFF FFFF 16MB Reserved
CMP/DAC
0x5C00 0000 0x5C00 00FF 256B CMP Analog Comparator 0,1
0x5B00 0100 0x5BFF FFFF 16MB Reserved
ADC
0x5B00 0000 0x5B00 00FF 256B ADC Analog-to-Digital controller
0x5700 0000 0x5AFF FFFF 64MB Reserved Reserved
0x5686 0100 0x56FF FFFF 8MB Reserved
0x5686 0000 0x5686 00FF 256B TM2x/3x TM36 32-bit Timer with 4 IC/OC/PWM
0x5600 0000 0x5685 FFFF 8MB Reserved
0x5586 0100 0x55FF FFFF 8MB Reserved
0x5586 0000 0x5586 00FF 256B TM16 Basic32-bit Timer/Counter
0x5580 0100 0x5585 FFFF 384KB Reserved
0x5580 0000 0x5580 00FF 256B TM10 Basic32-bit Timer/Counter
TM0x/1x
0x5501 0100 0x557F FFFF 8MB Reserved
0x5501 0000 0x5501 00FF 256B TM01 Basic 16-bit Timer/Counter
0x5500 0100 0x5500 FFFF 64KB Reserved
0x5500 0000 0x5500 00FF 256B TM00 Basic 16-bit Timer/Counter
0x5400 0000 0x54FF FFFF 16MB Reserved Reserved
0x5300 0100 0x53FF FFFF 16MB Reserved
SPI
0x5300 0000 0x5300 00FF 256B SPI0 SPI bus controller with data buffer
0x5201 0100 0x52FF FFFF 16MB Reserved
0x5201 0000 0x5201 00FF 256B URT1 Advance UART bus controller
UART
0x5200 0100 0x5200 FFFF 64KB Reserved
0x5200 0000 0x5200 00FF 256B URT0 Advance UART bus controller
0x5100 0100 0x51FF FFFF 16MB Reserved
I2C
0x5100 0000 0x5100 00FF 256B I2C0 I2C bus controller
0x5000 0100 0x50FF FFFF 16MB Reserved
EXT Interrupt
0x5000 0000 0x5000 00FF 256B EXIC External Interrupt Controller
0x4FF0 0100 0x4FFF FFFF 1024KB Reserved
0x4FF0 0000 0x4FF0 00FF 256B CFG Hardware option (NVR0/1/2)
Chip
0x4F00 0100 0x4FEF FFFF 15MB Reserved
0x4F00 0000 0x4F00 00FF 256B WRI Writer Interface Control
0x4E00 0000 0x4EFF FFFF 16MB Reserved Reserved
0x4D00 0100 0x4DFF FFFF 16MB Reserved
Memory
0x4D00 0000 0x4D00 00FF 256B MEM Internal Memory Controller
AHB 0x4C03 0100 0x4CFF FFFF 16MB Reserved
0x4C03 0000 0x4C03 00FF 256B SYS System and Chip Control
0x4C02 0100 0x4C02 FFFF 64KB Reserved
0x4C02 0000 0x4C02 00FF 256B PW Power Management Controller
System
0x4C01 0100 0x4C01 FFFF 64KB Reserved
0x4C01 0000 0x4C01 00FF 256B CSC Clock Source Controller
0x4C00 0100 0x4C00 FFFF 64KB Reserved
0x4C00 0000 0x4C00 00FF 256B RST Reset Source Controller
0x4BF0 0100 0x4BFF FFFF 1024KB Reserved
0x4BF0 0000 0x4BF0 00FF 256B DMA Direct memory access
General Purpose
0x4B00 0100 0x4BEF FFFF 15MB Reserved
0x4B00 0000 0x4B00 00FF 256B GPL General Purpose Logic
0x4500 0000 0x4AFF FFFF 96MB Reserved Reserved Reserved for future design
0x4403 0100 0x44FF FFFF 16MB Reserved
0x4403 0000 0x4403 00FF 256B PD
0x4402 0100 0x4402 FFFF 64KB Reserved
0x4402 0000 0x4402 00FF 256B PC
IO Configure
0x4401 0100 0x4401 FFFF 64KB Reserved
0x4401 0000 0x4401 00FF 256B PB
0x4400 0100 0x4400 FFFF 64KB Reserved
0x4400 0000 0x4400 00FF 256B PA
0x4100 0200 0x43FF FFFF 48MB Reserved Reserved for future design
0x4100 0000 0x4100 01FF 512B GPIO IOP IO Port Input/Output

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0x4000 0000 0x40FF FFFF 16MB Reserved Reserved for future design

5.4. Boot Modes

During chip startup, the hardware configuration option-byte (OB) is used to select one of the three boot
options:
 Boot from User Application Program (AP) Flash
 Boot from In-System-Program (ISP)
 Boot from embedded SRAM

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6. Functional Description
6.1. CPU Core
6.1.1. Introduction
The chip is embedded a CPU core of Cortex™-M0 processor. The processor is a configurable, multistage,
32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has
optional DAP hardware debug functionality.
The processor can execute Thumb code and is compatible with other Cortex-M profile processor. The
profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an
exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can
be entered as a result of an exception return.
6.1.2. CPU Features
 ARM 32-bit Cortex-M0 CPU
 Operation frequency up to 48MHz
 Built-in one NVIC for 32 external interrupt inputs with 4-level priority
 Built-in one 24-bit system tick timer
 Built-in one single-cycle 32-bit multiplier
 Built-in one SWD serial wire debugger with 2 watch points and 4 breakpoint
 The ARMv6-M Thumb® instruction set
6.1.3. ARM Cortex-M0 Processor
The following diagram is showing the block of ARM Cortex-M0 Processor.

Figure 6-1. ARM Cortex-M0 Processor

ARM Cortex-M0 Block
Power Domain

Always-On System Debug

Domain Domain Domain

CK_AHB
Clock Gating Control

Cortex-M0 Components
Clock Domain

Cortex-M0 Processor
FCLK SCLK HCLK DCLK SWCLKTCK
DAP
Debug
Nested
Interrupts SWD
Vectored Cortex-M0 Breakpoint
and SWCLKTCK
Interrupt Processor
Controller Core Watchpoint
(NVIC) Unit

Wakeup Interrupt Debugger Debug Access

Bus matrix
Controller Interface Port
(WIC) SysTick (DAP)

AHB-Lite Interface Serial Wire or

to system JTAG debug-port
Reset

Separate Reset HRESETn DBGRESETn PORESETn

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6.2. Power Management
6.2.1. Introduction
The chip power is implemented only by single power supply input and embedded one LDO to supply the
internal core logic power. The chip supports one power controller (PW) to manage Power-on reset (POR) circuit,
Low-voltage reset (LVR) circuit, Brown-Out Detectors (BOD0/1), power down control and wakeup control.
It supports power-down modes: SLEEP mode and STOP modes. The power-down modes reduce chip
power and provide the different power-saving scheme for chip application.
6.2.2. Chip Power Features
 Built-in one 1.8V output regulator for core logic power
 Built-in two brown-out detectors
▬ BOD0 detect 1.7V
▬ BOD1 detect by selected level 4.2V/3.7V/2.4V/2.0V
 Built-in a power management controller with power-down and wakeup control
 Support three power operation modes
▬ On(Normal) mode and SLEEP , STOP power down modes
6.2.3. Power Operation Mode
There are three power operation modes of ON, SLEEP, STOP to be supported in the power controller.
 ON mode
In ON mode, the CPU is able running in full speed. All peripheral modules can use full power to do normally
full function operation. These modules can enable or disable independent to save power consumption.
 SLEEP mode
In SLEEP mode, only the CPU is stopped and entering CPU sleep mode. All peripheral modules can be
configurable to continue to operate or sleep.
In this mode, the chip can be waked up by the related interrupt or event occurs.
 STOP mode
The STOP mode provides the lowest power consumption. The different from SLEEP mode is that CPU is
entering CPU deep-sleep mode and all peripheral modules are disabled except some special modules or
devices. These modules or devices can be configurable to continue to operate in STOP mode or not. They
include of IWDT, RTC, CMP modules and LVR, BOD0, BOD1 devices. The internal voltage regulator is also
running in low power mode.
In this mode, the chip can be waked up by some of the external input lines (GPIO) and some events
detection.
6.2.4. Power Supply
The chip power is implemented only by single power supply input for easy application PCB design. It is
embedded one internal low dropout linear regulator (LDO) to generate the +1.8 volt voltage power VDDC for
core logic power supply.
The VDD pin(s) is/are using for IO power supply input and internal LDO input. The VSS pin(s) is/are used to
connect the external ground for internal reference ground of internal LDO, hard macros and digital logic. The
VR0 pin is the LDO output and it needs to connect bypass capacitors for normal operation. The +VREFF pin is
the input of ADC reference voltage which can connect to VDD pin for general application.

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6.2.5. CPU Power Down
For chip entering power down mode, the firmware must execute WFI or WFE instruction to force the CPU
enters sleep mode or deep sleep mode. Then the chip will enter the power down mode of SLEEP or STOP.
User can configure the CPU sleep mode by setting CPU register of SLEEPDEEP after firmware executes WFI
or WFE instruction.
Table 6-1. Power-Down Mode Selection
CPU Register
CPU System
SLEEPDEEP
Run ON x
sleep SLEEP 0
deep sleep STOP 1

6.3. System Reset

6.3.1. Introduction
During reset, all Registers are set to their initial values, and the program starts execution from the Reset
Vector. The chip includes a reset source controller (RST) to manage multiple sources of reset and generates
Warm reset and Cold reset signals to chip system and internal modules. This controller also provides the reset
event flags for firmware, which are used to recognize the reset occurred source.
6.3.2. Chip Reset Features
 Built-in embedded POR(power-on reset)/LVR(low-voltage reset) circuit
 Built-in one reset source controller
▬ Programmable chip cold reset and warm reset for reset source
▬ Independent software reset control for internal modules
 Provide multiple reset sources
▬ POR/LVR/BOD0/BOD1/External reset pin input/Software force reset
▬ IWDT/WWDT/ADC/Comparator
▬ IAR(Illegal address error reset)/Flash access protect error reset
▬ Missing clock detect (MCD) reset
6.3.3. Chip Reset Levels
The chip provides three reset levels – POR reset, Cold reset and Warm reset. POR reset is the highest
priority reset and is generated by chip hardware. Code reset is the 2nd priority and Warm reset is the lowest
priority reset.
When POR reset occurred, it will cause to generate Cold reset to chip. Also when Cold reset occurred, it
will cause to generate Warm reset to chip.
 Power-On Reset
Power-on reset (POR) is used to internally reset the chip and also the CPU during power-up. The chip will
keep in reset state and will not start to work until the VDD power rises above the voltage of Power-On Reset.
And, the reset state is activated again whenever the VDD power falls below the POR threshold voltage. During
a power off cycle, VDD must fall below the POR threshold voltage before power is reapplied in order to ensure
a power-on reset.
 Cold Reset
Cold reset is the 2nd priority reset. The Cold reset is also generated and caused by POR reset occurred. It
sends to some modules like as IWDT, WWDT … to do deep level module reset. It will cause to reload all
hardware configurations OB and disable the register lock function for the modules which are support the register lock
function.
 Warm Reset
Warm reset is the lowest priority reset. The Warm reset is also generated and caused by Cold reset
occurred. It sends to all modules to clear flags and hardware circuit. It will cause to reload some hardware
configuration OB and reset the registers of module to default value if the module is unlocked or not supported
lock function. It will clear Warm reset source enable bits in RST controller if the RST controller is unlocked.

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6.3.4. External Reset
The chip provides an external hardware reset input from RSTN pin, which is accomplished by holding low
level for the RSTN pin. The RSTN pin is configured to as external reset pin or others (GPIO …) by hardware
configuration OB. To ensure a reliable power-up reset, then the hardware reset from RSTN pin is necessary.
6.3.5. Module Reset
For each AHB or APB control module, it can receive the system Warm reset signal to reset the module’s
control flags, registers and logical circuit. For some modules of IWDT, WWDT, RTC, PW, CSC and MEM, they
can receive the Cold reset to unlock the register locked function and reset the module.

6.4. System Clock

6.4.1. Introduction
The chip builds in a clock source controller (CSC) for system clock source management. There are four
clock sources for the system application: Internal High-frequency RC Oscillator (IHRCO), Internal crystal
oscillator (XOSC), Internal Low-frequency RC Oscillator (ILRCO) and External Clock Input (EXTCK).
One XOSC oscillator is embedded for external Xtal circuit. One PLL is embedded to multiply the frequency
of clock source and output clock for CPU and other peripheral modules. One missing clock detector (MCD) is
built-in to monitor the clock of external Xtal or external clock source.
6.4.2. Chip Clock Features
 Built-in embedded ILRCO (internal low frequency RC oscillator) by 32KHz
 Built-in embedded IHRCO (internal high frequency RC oscillator)
▬ Trimmed to 11.059 or 12MHz ±1% at +25℃
 Built-in embedded PLL up to 48MHz output for system clock
 Built-in embedded XOSC oscillator with MCD for external 32KHz or 4 to 25MHz Xtal
 Support external clock input up to 36MHz
 Built-in a clock source controller with clock enable control for modules
 Support internal XOSC oscillator and internal ILRCO/IHRCO clock output
6.4.3. System Clock Source
There are four clock sources for the system application: Internal High-frequency RC Oscillator (IHRCO),
Internal crystal oscillator (XOSC), Internal Low-frequency RC Oscillator (ILRCO) and External Clock Input
(EXTCK). Software can select the one of the four clock sources by application required and switches them on
the fly. But software needs to settle the clock source stably before clock switching.
6.4.4. PLL Clock
One PLL is embedded to multiply the frequency of system clock source from IHRCO, ILRCO, XOSC and
EXTCK. The PLL input frequency range is 5~7 MHz and output clock frequency is up to 96-MHz or 144-MHz.
6.4.5. Module Process Clock Control
The CSC module is able to do the process clock enable setting and select the process clock source for
internal modules. User must select the module process clock and enable the module process clock before
configure the module for operation normal.

6.5. System Common Control

6.5.1. Introduction
The chip embeds one system control (SYS) module for system common control. It is including of one
system event interrupt global enable control, chip manufacture identification code.
6.5.2. Features
 System interrupt global enable control for system interrupt source
 Chip manufacture identification code - Device ID, Product ID, User ID, Module Options
 32-bit non-reset backup register

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6.6. Memory Access

6.6.1. Introduction
The chip has separate address spaces for program and data memory. The logical separation of program
and data memory allows the memory to be accessed by 32bit addresses, which can be quickly stored and
manipulated by the CPU. The chip supports one memory controller (MEM) to manage the internal flash
memory and SRAM access operation.
6.6.2. Features
 Embedded Memory
 Built-in embedded 32K bytes flash memory for application code
 Built-in embedded 4K bytes SRAM
 Memory Controller Features
 Support ICP (In-circuit program) for ISP boot code update through SWD interface
 Support ISP (In-system program) for application code update
▬ Support programmable ISP flash memory size for ISP boot code
▬ Provide fixed 1K bytes ISPD flash memory as ISP private data
 Support IAP (In-application program) for application data update
▬ Support programmable 1M bytes address low boundary
 Support flash memory page erase in 1K bytes
6.6.3. Memory Controller
A memory controller is supported to access on chip flash memory, SRAM on AHB bus. It includes ICP (In-
Circuit Programming)/ ISP (In-System Programming)/ IAP (In-Application Programming) circuits for flash
memory accessing, option byte loader for hardware option registers loading.
The chip has up to 32K bytes of embedded main flash memory for code and data, programmable memory
size of embedded system flash memory for boot load code and 64 bytes of embedded option-byte flash
memory for chip configuration.
The memory controller (MEM) supports to Read/ Program (Write)/ Erase the flash memory. User can
directly read the data from flash memory by CPU read instruction commands and do not need through any
register. For “Program” mode, MEM provides the 32-bit data write operation into flash memory for new data
updated. For “Erase” mode, the Erase address is only valid at low 10-bit CPU address=0 (X..X00 0000 0000B)
and is addressing 1K-byte alignment.
6.6.4. ICP/ISP/IAP for Flash Memory
There are 3 flash access modes are provided in chip for ICP, ISP and IAP application: program mode and
read mode. ICP is allowed to update the entire contents of the flash memory by using the hardware SWD
interface and no any firmware request. Others, User can use these two modes of ISP and IAP to update new
data into flash storage and get flash content by a firmware flash memory access handler.
6.6.5. Hardware Option Byte Flash Memory
There can be up to 64 bytes of on-chip Option Bytes Flash memory. It is used to store the hardware option
configuration setting.
The embedded option-byte (OB) flash memory will load into the hardware configuration option-byte register
(OR) after power-on reset. The hardware configuration OR are designed to configure the clock source from
internal RC oscillator or crystal oscillator; the booted memory selection from AP, ISP flash memory or SRAM;
the memory size of IAP flash memory; other chip configurations … etc.

6.7. GPIO
6.7.1. Introduction
The chip has following I/O ports: PA[0:3][8:15], PB[0:3][8:11][13:14], PC [0:6][8:14], PD[0:3][7:10].
Support maximum 44 GPIO pins for LQFP48 package. RSTN pin is an alternated function pin on PC6. If select

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 MG32F02A032
external crystal oscillator as system clock input, PC13 and PC14 are configured to XIN and XOUT. The exact
number of I/O pins available depends upon the package types.
The chip has built in several IO mode control (PA/PB/PC/PD) modules for each GPIO port. These modules
are used for GPIO pin IO mode control, alternated function selection, driver strength setting, input inverse
selection, pull-high enable, deglitch filter setting and high speed enable. Also one IO Port access control (IOP)
module is built-in to control the input and output state of GPIO mode for all GPIO ports.
6.7.2. Features
 Support general purpose IO pins for application
▬ Maximum 44 GPIO pins for LQFP48 package
 Provide selectable IO modes by pin independent
▬ Push-Pull output
▬ Quasi bidirectional
▬ Open-drain output
▬ Input only with high impedance
▬ Analog IO
 Flexible pin alternate function selection
 Support programmable drive strength by pin independent
 Support IO deglitch filter by pin independent
 Support input inverse selection by pin independent
 Support pull-high option by pin independent
 Support high speed option by pin independent
 GPIO pin state and IO mode setting keep optional after reset
6.7.3. GPIO Control Block
The GPIO Control block includes IOM (IO pad Mode control), IOP (IO Port access control) and AFS
(Alternate Function Select) blocks.
 IO Operation Mode
The IO operating modes are supported analog IO, digital input, push-pull output, and open-drain output,
quasi-bidirectional. Provide selectable IO modes by pin independent.
The IO mode control block supports programmable IO operation modes, output high speed option, pull-high
option, output drive strength, IO deglitch filter and input inverse selection by pin independent.
 IO Port Access
When the AFS setting is set GPIO function mode for any IO pin, user can directly set the logical output or
get the logical input for the IO pin. There is one independent data out register bit to store the output logic value
for each GPIO pin. Also user can directly read the input data register bit to get the GPIO pin logical state for
each GPIO pin.
For firmware control, there are one set control bit to set the data out register bit and one clear control bit to
clear the data out register bit for each GPIO pin.
The chip provides one set-or-clear register control bit to set, clear the data out register bit or read pin status
for each GPIO pin. The register bit is written 1 to set data bit and written 0 to clear data. Read the register bit to
get the GPIO pin status. As this register bit is cost eight bit memory space, firmware is easy to control single
GPIO pin by CPU byte-access instruction command. It is like the bit access IO control of 8051 MCU.
 Alternate Function Select Control
User can configure the alternate function between module function IO and IO pins through the AFS matrix
for each GPIO pin independently. Usually the AFS default setting is GPIO function for each GPIO pin except
the XIN/XOUT, SWCLK/SWDIO and RSTN function pins. These pins may be changed by hardware
configuration OB.

6.8. Interrupt
6.8.1. Introduction
After reset, the CPU begins execution from the location of reset interrupt vector (0x00000004) addressing,
where should be the starting of the user’s application code. To service the interrupts, the interrupt service

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locations (called interrupt vectors) should be located in the address 0x000000BF~0x00000000.
The chip is built-in ARM cortex M0 CPU and is embedded a NVIC (Nested Vectored Interrupt Controller) for
32 external interrupt inputs with 4-level priority. Also builds in an EXIC (External Interrupt Controller) module
and connects to NVIC.
6.8.2. Interrupt Features
 Built-in one NVIC for 32 external interrupt inputs with 4-level priority
 Built-in one EXIC (external interrupt controller) for NVIC connection
▬ Independent high/low level and rising/falling edge trigger selection
 Built-in one WIC (wakeup interrupt controller) for wakeup event control
 All GPIO pins can be configured as interrupt source and key pad input
▬ Support port OR logic for interrupt function
▬ Support port AND logic for KBI function
 Support external pins for CPU NMI/RXEV/TXEV function
▬ Configurable pin for CPU NMI input function
▬ Configurable pin for CPU RXEV input function
▬ Configurable pin for CPU TXEV output function
6.8.3. Interrupt Structure
Each interrupt is assigned a fixed location in the program memory. The interrupt causes the CPU to jump to
that location, where it commences execution of the service routine. NMI interrupt, for example, is assigned to
location 0x00000008. If NMI is going to be used, its service routine must begin at location 0x00000008.
The interrupt service locations are spaced at an interval of 4 bytes: 0x00000004 for Reset Interrupt,
0x00000008 for NMI, 0x0000000C for Hard-Fault, 0x0000002C for SVCall, 0x00000038 for PendSV,
0x0000003C for SysTick, etc.
 Exception types
The NVIC has 7 exception types: Reset, NMI, HardFault, SVCall, PendSV, SysTick and Interrupt (IRQ).
The NVIC supports 32 external interrupt input. An interrupt is an exception signaled by a peripheral or
generated by a software request. The four priority level interrupt structure allows great flexibility in handling
these interrupt sources.
 Interrupt Sources
The ‘Pending Bits’ are the interrupt flags that will generate an interrupt if it is enabled by setting the ‘Set
Enable Bit’. The ‘Pending Bits’ can be set or cleared by software, with the same result as though it had been
set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in
software. The ‘Priority Bits’ determine the priority level for each interrupt. The ‘Priority within Level’ is the polling
sequence used to resolve simultaneous requests of the same priority level. The ‘Vector Address’ is the entry
point of an interrupt service routine in the program memory.

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Table 6-2. Interrupt Source Table
NVIC
Exception IRQ Interrupt Exception Comment
Priority Activation
No. No. Name handlers
0 - Initial -
1 - Reset -3 Asynchronous Reset exception

2 -14 NMI -2 Asynchronous System handlers Non Maskable Interrupt

3 -13 HardFault -1 Synchronous Fault handler Cortex-M0 Hard Fault Interrupt

4~10 - Reserved -

11 -5 SVC Configurable Synchronous System handlers Cortex-M0 SV Call Interrupt

12~13 - Reserved -

14 -2 PendSV Configurable Asynchronous System handlers Cortex-M0 Pend SV Interrupt

15 -1 SysTick Configurable Asynchronous System handlers Cortex-M0 System Tick Interrupt

16~47 0~31 - Configurable Asynchronous ISRs Peripheral Interrupts

Configurable : Programmable priority level 0~3

 Interrupt Priority
The priority scheme for servicing the interrupts has four interrupt levels. The priority bits in CPU registers,
IPR0-7, SHPR2 and SHPR3, determine the priority level of each interrupt.
The interrupt priority registers provide an 8-bit priority field for each interrupt and each register holds four
priority fields. The processor implements only bits [7:6] of each field, bits [5:0] read as zero and ignore writes.
Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two interrupt requests of
different priority levels are received simultaneously, the request of higher priority is serviced. If interrupt
requests of the same priority level are received simultaneously, an internal polling sequence determine which
request is serviced. The table of “interrupt sources” shows the internal polling sequence in the same priority
level and the interrupt vector address. The lower exception number gets the higher priority.
6.8.4. Nested Vectored Interrupt Controller
The Cortex-M0 processor integrates a configurable Nested Vectored Interrupt Controller (NVIC) that
supports low latency interrupt processing and includes a non-mask interrupt (NMI). The NVIC provides a zero-
jitter interrupt option and four interrupt priority levels.
Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs.
Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with sleep mode. Optionally, sleep mode support can
include a deep sleep function that enables the entire device to be rapidly powered down.
6.8.5. Wakeup Interrupt Controller
The chip includes a Wakeup Interrupt Controller (WIC) which can detect an interrupt or wakeup event from
EXIC and wake the processor from deep sleep mode. The WIC is enabled only when the DEEPSLEEP bit in
the CPU register of SCR is set to 1. The WIC is not programmable, and does not have any registers or user
interface. It operates entirely from hardware signals.
6.8.6. External Interrupt Controller
The External Interrupt Controller (EXIC) includes four external port interrupt blocks (EXINT) to manage the
external pin input interrupt events, one wakeup control block for wakeup event control and control the
NMI/RXEV events. The EXIC also do as the interface controller between internal modules and NVIC for the
interrupt and wakeup events management

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6.9. General Purpose Logic
6.9.1. Introduction
The chip builds in one general purpose logic (GPL) module. It provides the combined functions of Data
Order Change, Parity Check, Data Inverse and CRC.
6.9.2. Features
 Support data inverse, bit order change, byte order change and parity check
▬ Data bit order change for 8/16/32-bit reverse
▬ Data byte order change between Little endian and Big endian for 32-bit range
▬ Parity Check for 8/16/32 bit range
 Support CRC (Cyclic Redundancy Check) calculation
▬ Programmable CRC initial value
▬ CRC output bit order change
▬ CRC computation done in 4/2/1 AHB clock cycles for 32/16/8-bit data
 CRC with fixed common polynomial
▬ CRC8 polynomial 0x07
▬ CRC16 polynomial 0x8005
▬ CCITT16 polynomial 0x1021
▬ CRC32(IEEE 802.3) polynomial 0x4C11DB7
 Input data are buffered with DMA capability

6.10. APB Common Control

6.10.1. Introduction
The chip builds in one APB (APB bus common control) module for the common control of APB devices.
6.10.2. Features
 Timer synchronous enable global control for TMx timer modules
 Timer internal trigger/clock source selection for TMx timer modules
 OBM(Output Signal Break and Modulation) control
▬ Support two sets of OBM for output signal break and modulation control
 Infrared Remote Modulation Output

6.11. Direct Memory Access

The chip is built-in a direct memory access controller (DMA) which is used to improve the performance of
data transfer between peripheral and memory, memory to memory and peripheral to peripheral. Data can be
quickly transfer by through DMA without costing any CPU resources.
Notify: The sign of (n= DMA channel index number) is using for Registers, Signals and Pins/Ports in the
descriptions of this chapter.
6.11.1. Features
 One configurable channels with dedicated hardware DMA requests
▬ Access to Memory, APB and AHB Peripherals as source and destination
▬ Support SRAM/Flash as memory source and SRAM as memory destination
▬ Peripherals are including of ADC0, I2Cx, URTx, SPIx, TM36 and GPL modules
 DMA transfer management type
▬ memory-to-memory
▬ peripheral-to-memory
▬ memory-to-peripheral
▬ peripheral-to-peripheral
 Programmable transfer number of data and up to 65535

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 Programmable burst length 1,2,4
 Support transfer loop mode and start address auto reload control
 Provide single/block/demand mode for external pin trigger request
6.11.2. DMA Control Block
The DMA controller (DMA) is used to transfer data between these sources and destinations of AHB
peripheral, APB peripheral, SRAM and internal Flash. One external pin of DMA_TRG0 is able to input as the
trigger signal of DMA data transfer.

6.12. ADC
6.12.1. Introduction
The chip builds in one ADC0 module which embeds one 12-bit successive approximation ADC (analog-to-
digital converter), one PGA (programmable gain amplifier) with gain 1~4 and digital logic for output code control.
It supports the configurable multiplexed channels those include 12 external and 4 internal sources. The analog-
to-digital conversion can be performed in one-shot, continuous, one-loop scan or continuous loop scan modes.
6.12.2. Features
 12-bit SAR ADC with 800Ksps
▬ Configurable resolution : 12/10/8-bit
▬ Configurable sampling time
 Provide external 12 channels and internal 4 channels input
▬ Internal channel source : VBG, VSSA, LDO VR0 output, ADC Reference Voltage
 Support auto-sampling and trigger by external pin , internal events and software bit
 Data alignment for output code left/right justify
 Built-in input buffer stage with bypass option
 Programmable offset
 Programmable gain : 1~4
 Interrupt generation at the end of sampling, end of conversion, end of scan conversion
 Support voltage window detect
▬ Two level programmable window threshold
 Built-in one hardware accumulator for ADC output code
 Support one-shot/channel scan/loop scan
 ADC data are buffered with DMA capability
 Support wait mode
▬ Prevents ADC overrun in application with low frequency
6.12.3. ADC Control Block
The ADC control block consists of an analog multiplexer (AMUX) with 16 input channels, a 800Ksps/12-bit
SAR (successive-approximation-register) ADC, reference voltage circuit, ADC conversion trigger start control
block and change scan control block.
 ADC Input Channels
The analog multiplexer (AMUX) selects the inputs to the ADC, allowing any of the input pins to be
measured in single-ended mode.
The analog input pins used for the A/D converters also have its I/O pins for digital input and output function.
In order to give the proper analog performance, a pin that is being used with the ADC should have its digital
output as disabled. It is done by putting the port pin into the input-only mode. And when an analog signal is
applied to the ADC_I[15:8][3:0] pin and the digital input from this pin is not needed, software could set the
corresponding pin to AIO mode to turn off the digital input buffer to reduce power consumption.
 Single-End Input Mode
The ADC supports single-end input operation modes. The ADC can convert the ADC output to unsigned
code.
 ADC Sampling Time

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For input signal quality and conversion speedy issue, user can adjust the ADC sampling time. Usually
increase the ADC sampling time to get more stable voltage and better ADC performance if the conversion rate
and signal bandwidth are reasonable and valid for actual application.
 ADC Conversion Mode
The ADC is supported three conversion modes of One Shot, Channel Scan and Loop Scan.
 ADC Output Control
When an ADC conversion is complete, the ADC raw code is generated and sends to the ADC output
control blocks those are including of Digital Offset Adjuster, Signed Code Converter, Digital Resolution Adjuster,
Voltage Window Detector, Code Limiter and Data Alignment Adjuster.
The ADC output code will be adjusted by the ADC output control blocks and store the conversion result
date to the ADC data register.
 Voltage Window Detect and Code Limit
The ADC can compare the input voltage by a threshold window. Also the ADC output code can be
compared by a code limit area to skip or clamp the code by the same threshold window.
 ADC Data Sum Accumulate
The ADC built-in one hardware accumulator for ADC output code. The accumulator is used to accumulate
the sequential ADC data with programmable data number and records the sum to the summary registers. User
can set the accumulated ADC data number. The ADC is supported three sum data registers and user can get
the accumulated sum from these registers.
 ADC Wait
The ADC supports a wait mode function to prevent ADC overrun in application with low frequency ADC
sampling clock.

6.13. Analog Comparator

6.13.1. Introduction
The chip builds in one CMP module which embeds two general purpose analog comparators with flexible
input multiplexer, two internal voltage references of R-ladder and independent digital synchronized filter for
each analog comparator. These analog comparators can be configured to four standalone comparators or a
combined window comparator. The module provides the comparator output result status bit and the interrupt
flags of rising edge or falling edge change. Also the output result can be output to external pin or internal other
modules for trigger event.
6.13.2. Features
 Provide 2 fast Rail-to-rail comparators
 Programmable 64-step threshold of internal voltage reference
 Provide external total 6 channels input for all comparators
 Provide flexible 6 channels input for each +/- input path selection
 Programmable response time for optimal current consumption
 Combined window comparator from two comparators
 Selectable compare output polarity
 Support power-down wakeup
 Compare output to I/O , interrupt or as internal module trigger event
▬ Timer internal trigger, Capture events, or Break events
 Support analog watch dog as a reset source
6.13.3. CMP Control Block
The CMP module includes four general purpose analog comparators CMP0~1 by the same design
structure and two internal voltage references IVREF/IVREF2 by R-ladder structure. Each one is with the
independent input multiplexer, digital synchronized filter and digital output circuit. The IVREF is using for CMP0
and the IVREF2 is using for CMP1.
The analog comparator is built-in two internal voltage references – IVREF and IVREF2 with 64-steps R-
ladder structure. They can use as one of the analog comparator input and compare with another input from
external source.

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The analog multiplexers (AMUX) select the inputs of CMPn_I0,CMPn_I1 to each analog comparator and
CMP_C0,CMP_C1 to all analog comparator CMP0/1. It allows any of the input pins to CMP0/1/2/3 to be
compared between positive input and negative input.
The analog input pins used for the comparators also have its I/O port ‘s digital input and output function. In
order to give the proper analog performance, a pin that is being used should have its digital output as disabled.
It is done by putting the port pin into the digital input mode. And when an analog signal is applied to the analog
input pin and the digital input from this pin is not needed, software could set the corresponding pin to AIO mode
to reduce power consumption in the digital input buffer.

6.14. IWDT
6.14.1. Introduction
The chip has one independent Watch-dog timer to use as a recovery method in situations where the CPU
may be subjected to software upset. It will trigger system reset when the counter reaches a given timeout value.
6.14.2. Features
 8-bit down counter with 12-bit prescaler and clocked by its own CK_ILRCO
 Operating capability in SLEEP and STOP modes
 Selectable reset or interrupt when the counter underflow
 Support two early wakeup comparators with interrupt
 Support register key-protected and reset-locked functions
6.14.3. IWDT Control
The IWDT watch-dog timer consists of a 12-bit prescaler and an 8-bit timer. When the watch-dog timer is
enabled, software should always reset the timer before the timer is timeout. When the watch-dog timer is reset,
the timer will be reloaded 0xFF value to restart counting.
If the chip is out of control by any disturbance, the firmware may miss to reset the timer and the timer
timeout will be coming. It makes the IWDT generating a reset event and sends it to Reset Source Controller
(RST) to do as the warm reset events or cold reset events.
The IWDT is able to record default initialized value in hardware option byte (OB) about IWDT on/off, input
clock divider value, IWDT registers write protection.
The IWDT is able to operate in STOP mode and the APB clock is stopped and the module is asynchronous
control for all logic.
The IWDT supports to wakeup chip in STOP mode by the events of watch-dog timer underflow and early
wakeup-0/1 detection. When the chip is entering STOP mode and any of these IWDT wakeup events is
happened, the IWDT will send the wakeup event to Power Controller (PW) to do as the system wakeup events.

6.15. WWDT
6.15.1. Introduction
The system window watchdog is used to detect the occurrence of a software fault which causes the
application program abnormal. The watchdog circuit generates a system reset when the counter reaches a
given timeout value.
The WWDT has a configurable time-window that can be programmed to detect abnormally late or early
application behavior.
6.15.2. Features
 10-bit counter with 1 or 256 divider , 1/2/4~/128 divider
 Configurable time-window to detect abnormally late or early application behavior
 Selectable reset or interrupt when the counter is underflow or reloaded outside the window
 Support warning interrupt
 Support register key-protected and reset-locked functions
6.15.3. WWDT Control
The WWDT watch-dog timer consists of one /1 or /256 clock prescaler, one 7-bit clock divider and one 10-

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bit timer. When the watch-dog timer is enabled, software should always reset the timer before the timer is
timeout. When the watch-dog timer is reset, the timer will reload the value to restart counting.
When the firmware is out of control, which may miss to reset the timer and the timer timeout will be coming.
It makes the WWDT generating a reset event and sends it to Reset Source Controller (RST) to do as the warm
reset events or cold reset events. If the firmware reset the timer and the counter value is over the threshold
value of window compare threshold in the same time, it also makes the WWDT generating a reset event.

6.16. RTC
6.16.1. Introduction
The real-time clock is an independent 32-bit timer. The RTC provides a time clock with programmable
alarm interrupt. User can use as a calendar with software programmable alarm seconds, minutes, hours, day,
and date.
The RTC provides a wakeup flag to perform auto wakeup from power down mode with interrupt.
6.16.2. Features
 Built-in 32-bit counter with selectable clock source
 Support alarm function with 32-bit programmable compare register
 Support time-stamp function for event saving
 Support wakeup from Stop mode
 Support register key-protected and reset-locked functions
6.16.3. RTC Control
The RTC supports an alarm function and one register to sets the RTC alarm compare value. When the
RTC timer value is matched with RTC alarm compare value, the RTC alarm flag is asserted and generates an
interrupt. Also the RTC can capture from the 32-bit timer value or reload value to the 32-bit timer.
The RTC supports a time stamp function by external input. User can select input trigger edge of rising edge,
falling edge or dual-edge. When an external input signal is matched, the RTC time stamp flag is asserted and
generates an interrupt.
One RTC_OUT output is able to output the RTC internal signals to internal modules or external pin. There
are four signals of timer overflow signal toggle output, time stamp trigger event, timer input periodic clock signal
and alarm compare output event which can be selected and sent from RTC_OUT output.
The RTC is able to operate in STOP mode and the APB clock is stopped and the module is asynchronous
control for all logic.
The RTC supports to wakeup chip in STOP mode by the events of timer overflow, timer input periodic clock
and alarm compare output. When the chip is entering STOP mode and any of these RTC wakeup events is
happened, the RTC will send the wakeup event to Power Controller (PW) to do as the system wakeup events.

6.17. Timer
6.17.1. Introduction
The chip has five Timer/Counter modules: TM00, TM01, TM10, TM16 and TM36. All of them can be
configured as timers or event counters.
TM0x has an 8-bit timer/counter with 8-bit prescaler. TM1x has a 16-bit timer/counter with 16-bit prescaler.
TM36 has a 16-bit timer/counter with 16-bit prescaler and embeds four input capture/output compare channels.
6.17.2. Features
 Provide seven timers/counters : TM00,TM01,TM10,TM16,TM36
 Timer module common functions
▬ Selectable Full-counter , Cascade , Separate modes
▬ Multiple internal and external signals as timer clock source or trigger source
▬ Internal timer events output to pin or other modules as input trigger event
▬ Support timer reset , trigger start and clock gating for trigger source function
▬ Timer overflow as clock output to external pin output
▬ Programmable counter auto-stop mode

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▬ Main counter support up/down control (TM16 /TM36 only)
▬ 2nd counter support up/down control (Separate mode)
 Provide TM36 timer module
▬ 32-bit timer/counter
▬ 4 CCP (input Capture/output Compare/PWM) channels
▬ 3 CCP channels with OCN (complementary output compare)
▬ PWM function with center-align, dead time control and break control
▬ Support OC comparator split to two separated comparators mode
▬ Programmable dead time control
▬ QEI(Quadrature Encoder Interface) support
▬ External input timer up/down control
▬ One IC and three OC with DMA capability
 Provide TM1x timer modules
▬ 32-bit timer/counter
▬ External input timer up/down control (TM16 only)
 Provide TM0x timer modules
▬ 16-bit timer/counter

6.17.3. Timer Modules' Function Table

The following table is showing the implemented functions of Timer modules.
Table 6-3. Timer Modules' Function Table
Module Functions TM00 TM01 TM10 TM16 TM36
Timer/Counter total bits 16 16 32 32 32
Timer Cascade Mode yes yes yes yes yes
Timer Separate Mode yes yes yes yes yes
Timer Full-Counter
yes yes yes yes yes
Mode
Independent channels 4
Internal TRGI lines 8 8 8 8 8
External TRGI lines 1 1 1 1 1
Output TRGO lines 1 1 1 1 1
Output CKO lines 1 1 1 1 1
Input Capture IC lines 4
Output OC lines 4
Output OCN lines 3
Output OCH lines 4
Input Break lines 1
PWM separated two yes
PWM edge-align yes
PWM center-align yes
Dead-time generator yes
Up/Down of 1st Timer U U U U/D U/D
Up/Down of 2nd Timer U/D U/D U/D U/D U/D
Timer auto Stop yes yes yes yes yes
QEI timer U/D control yes
3-input XOR to CH-0 yes
DMA request capability yes
Note 1. Timer Cascade Mode ~ 16-bit_counter+16-bit_prescaler or 8-bit_counter+8-bit_prescaler
2. Timer Separate Mode ~ two 16-bit_counter or 8-bit_counter
3. Timer Full-Counter Mode ~ 32-bit_counter or 16-bit counter

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6.17.4. Timer Control Block
The TMx module is including of a Trigger/Clock control block, a Counter Stage, an Capture/Compare
control block and Input/Output Stages of channel I/O control (TM3x only) and a Break control block (TM36 only).
TMx support three timer operation modes: (1) Cascade Mode (2) Separate Mode (3) Full-Counter Mode.
 Trigger Control Block
The Trigger Control block has two functions, one is to control the timer trigger input events and another is to
control the timer trigger output events.
The timer trigger input events are including of Reset Timer, Gated Clock and Timer-Start Trigger for Main
Timer and 2nd Timer. The input source of the timer trigger input events is selected from external trigger signal,
internal trigger signals or external channel input signal of TMx_IN0/TMx_IN1.
The source of the timer trigger output events are able to come from many internal events or signals of this
timer module. Also user can use the software register to set the trigger output directly. This source of output
event can select and invert the output signal by registers.
 Timer Input/Output Channels
The following table is showing the channel input signals for each timer module. TM0x and TM1x modules
are no channel input selection function as the input capture/output compare is not support. Each channel has
four input lines.
 Timer Input Capture and Output Compare
The input capture (IC) and output compare (OC) functions are only supported for TM3x module. TM0x and
TM1x modules are no the functions of the input capture/output compare.
User can configure each of the timer IC/OC channel independently as input capture, output compare or
PWM mode.
 PWM Dead-Time Control
The Dead Time Generator (DTG) is only support for TM36 module. User can use with the DTG function and
configure the timer channel as 16bit PWM mode or Two 8bit PWMs mode.
 Break Control Block
The break control block is only support for TM36 module. The module can input the break events from
internal events, external events or software register to break the timer output signals.
 QEI Control Block
The QEI (Quadrature Encoder Interface) control block is only support for TM26 and TM36 modules. The
QEI block can input from two external signals to control the Main Timer up or down counting. The QEI block
provides five control modes and user can enable QEI control and configure the QEI control mode by register.
When the QEI control block is enabled, the timer will reset during up counting or reload the auto-reload
value during down counting if detect the index signal active pulse.

6.18. I2C
6.18.1. Introduction
The I2C interface is a two-wire, bi-directional serial bus. It is ideally suited for typical microcontroller
applications. The I2C protocol allows the systems designer to interconnect up to 128 different devices using
only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The I2C bus provides control of
SDA, SCL generation and synchronization, arbitration logic, and START/STOP control and generation. The
only external hardware needed to implement this bus is a single pull-up resistor for each of the I2C bus lines.
All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are
inherent in the I2C protocol.
The I2C module builds in the shadow buffer and data register to improve transmit and receive communication
performance.
6.18.2. Features
 Provide one identical I2c module : I2C0
 I2C module common functions
▬ Support master and slave mode
▬ Support programmable clock rate control and clock rate up to 1 MHz
▬ Support programmable high/low period control for master mode

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▬ Support clock stretching for slave mode
▬ Support general call function
▬ Support multi-master processing capability
▬ Support both Byte mode and Buffer mode flow control
▬ Support Byte mode bus event code for simplex firmware control
▬ Support Buffer mode 4-byte data buffer and 32-bit data register for high speed communication
▬ Received and transmitted data are buffered with DMA capability
▬ Support slave address hardware detection wakeup from STOP mode
▬ Support SMBus timeout detection
6.18.3. I2C Control
 I2C Data Byte Mode Control
The module is provides one bus event register to get the I2C Event Code for software byte-mode simplex
control. An 8-bit shift buffer and an 8-bit data register are using for the I2C data Byte mode.
 I2C Data Buffer Mode Control
The module implements an 8-bit shift buffer, a 32-bit shadow buffer and a 32-bit data register for data flow
control of data Buffer mode. The following diagram is showing the I2C Data Buffer mode control block.
 I2C Master Timing Control
Two timing control registers are simply used to configure the I2C timing of high and low cycle time.
 I2C Timeout Timer Control
The module is provides one 8-bit timeout timer (TMO) for I2C access time-out control.

6.19. UART
6.19.1. Introduction
The UART module support full-duplex transmission, meaning it can transmit and receive simultaneously.
The module builds in the shadow buffer and data register by transmit and receive independently to improve
transmit and receive communication performance. It can commence reception of a second byte before a
previously received byte has been read from the register. However, if the first byte still hasn’t been read by the
time reception of the second byte is complete, one of the bytes will be lost.
The module can operate in multiple modes: asynchronous communication, synchronous communication,
SPI master, SmartCard, LIN, multi-processor mode. The asynchronous communication operates as a full-
duplex Universal Asynchronous Receiver and Transmitter (UART), which can transmit and receive
simultaneously and at different baud rates.
6.19.2. Features
 Provide two identical UART modules : URT0,URT1
 UART module common functions
▬ Support UART , Synchronous , SPI master , SmartCard , LIN , Multi-processor mode
▬ Provide precise UART baud-rate control by programmable oversampling rate
▬ Support baud rate up to 6 Mbit/s
▬ Programmable data word length - 7 or 8 bits
▬ Selectable MSB or LSB first data order
▬ Configurable stop bits - 0.5,1,1.5 or 2 stop bits
▬ Hardware parity checking and parity generation
▬ Programmable 4~32 oversampling rate
▬ Swappable TX/RX pin configuration
▬ Separate signal polarity control for transmission and reception
▬ Support a timeout timer for Idle/RX/Break/Calibration timeout detection
▬ Support 4-byte data buffer and 32-bit data register for high speed communication
▬ Received and transmitted data are buffered with DMA capability
▬ Receive baud rate up to 6 Mbit/s
▬ Support auto baud-rate detection and calibration

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MG32F02A032
▬ Support Multiprocessor communication for master and slave mode - Idle-Line , Address-Bit
▬ Support Low speed UART-like frame format IrDA
▬ Support transceiver hardware flow control by CTS/RTS signals only
▬ Provide driver enable signal to activate the transmission for one line communication
▬ Support transmission-error hardware detection and auto resent control for Smart-card
▬ Support receiving parity error hardware detection and auto retry control for Smart-card
6.19.3. UART Control
The UART module is able to configure the control mode from one of UART (asynchronous mode), SYNC
(synchronous mode), IDLE (multi-processor idle mode) and ADR (multi-processor address-bit mode).
The UART module implements two operation modes of Idle-Line mode or Address-Bit mode for multi-
processor communication.
 UART Data Buffer
The UART module implements two 8-bit shift buffers, two 32-bit shadow buffer and two 32-bit data register
for data flow control and reduce the CPU overhead.
 UART Data Character Format Setting
The UART character is defined as the data unit for UART transaction. Generally, the character is including
of one Start bit, 8-bit or 7-bit data bits and one Stop bit. Others, it also can insert one parity bit (PAR) and one
address bit (ADR) for multi-processor mode.
 UART TMO Timeout Control
The module is provides one 16-bit timeout timer (TMO) for UART access time-out control. It can configure
as an UART timeout timer or a general using timer by register. When the TMO timer is configured as a general
using timer, there is one reload register for the timer.
The TMO timer can use to detect Idle Line condition, Break Timeout, RX Timeout, Idle Timeout and Baud-
Rate Calibration Timeout.
 UART Baud-Rate Control
The Baud-Rate timer (BR) can configure as an UART Baud-Rate generator or a general using timer. The
Baud-Rate timer generator is able to output the internal clock for UART communication Baud-Rate control.
 UART Mute Mode Control
The UART module is support a mute mode to disable receiving data character but the shift buffer is still
operation for status detection. When the UART is entering mute mode, the RX shadow buffer is never load into
data from shift buffer. The mute mode is useful for multi-processor communication.
The mute mode can be automatic by hardware detection to enter or exit by register configuration. Also it
can be directly forced to enter or exit by register setting and user can manual to control the mute mode entering
and exiting.
 UART IrDA Control
The UART module is built an IrDA encoder and an IrDA decoder in the data interface for IrDA
communication.
 UART DE Control
The UART module provides one data enable signal of URTx_DE. This signal is used to indicate the data
transmitted period and can output to external signal drive device. The external signal drive device can receive
the UART TX signal and drive it with a signal enhanced buffer to the target of UART receiver for long distance
communication.
 UART Hardware Flow Control
The UART supports a hardware flow control function for data transaction and provides two control signals
of URTx_CTS (Clear to Send) and URTx_RTS (Request to Send) for the hardware flow control.

6.20. SPI
6.20.1. Introduction
The chip provides a high-speed serial peripheral interface (SPI). SPI is a full-duplex, high-speed and
synchronous communication bus with two operation modes: Master mode and Slave mode. SPI clock rate can
be supported up to 24 MHz in Master mode or up to 16 MHz in Slave mode under a 48MHz system clock.
The SPI module builds in the shadow buffer and data register by transmit and receive independently to

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 MG32F02A032
improve transmit and receive communication performance.
6.20.2. Features
 Support one SPI module – SPI0
 Support master and slave mode
▬ Support full duplex , half duplex or simplex communication mode
▬ Support no NSS(slave select signal) communication mode
 Support programmable clock rate control
▬ Support clock rate up to 24 MHz for master and 16 MHz for slave
 Selectable 4~32-bit frame size
▬ Support 4-byte data buffer and 32-bit data register for high speed communication
 Received and transmitted data are buffered with DMA capability
 Support multi-master processing capability
 Selectable clock polarity and phase
 Selectable MSB or LSB first data order
 NSS line management by hardware or software for both master and slave
 Configurable data transfer modes
▬ Standard SPI mode (separated transmit and receive line)
▬ Single SPI mode with bidirectional data transfer
▬ Dual SPI mode with bidirectional data transfer
▬ Quad SPI mode with bidirectional data transfer
 Data transmit/receive overrun detect
 Support hardware master mode failure detection and auto slave mode change
6.20.3. SPI Control
 SPI Data Buffer Mode Control
The module implements two 32-bit shift buffers, two 32-bit shadow buffer and two 32-bit data register for
data flow control and reduce the CPU overhead.
 SPI Data Frame
User can set the data frame bit size from 4-bit to 32-bit by register. Also user can configure the frame data
order by Lsb first or Msb first.
 SPI Data Modes
The SPI module provides serval data modes and can be configured to one of the modes of standard SPI, 1-
Line SPI, 2-Line SPI, 4-Line SPI for flexible SPI application.

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7. Application Notes
7.1. Power Supply Circuit
To have the chip work with power supply varying from 1.8V to 5.5V, adding some external decoupling and
bypass capacitors is necessary, as shown in following figure.

Figure 7-1. Power Supply Circuit Power Supply Circuit

Power Supply
Power
VDD VR0
(optional)

(close chip)

(close chip)
10uF 0.1uF 0.1uF 4.7uF

Ground
VSS

Megawin MCU

7.2. Reset Circuit

Normally, the power-on reset can be successfully generated during power-up. However, to further ensure
the MCU a reliable reset during power-up, the external reset is necessary. The following figure shows the
external reset circuit, which consists of a capacitor CEXT connected to VSS (ground) and a resistor REXT
connected to VDD (power supply).
In general, REXT is optional because the RSTN pin has an internal pull-high resistor (RRST). This internal
diffused resistor to VDD permits a power-up reset using only an external capacitor CEXT to VSS.

Figure 7-2. Reset Circuit External Reset Circuit

[External RC Reset] [External Trigger Reset]
Power Supply Power Supply

VDD VDD
(optional)
10uF 0.1uF
47K RExT (Internal (Internal
(optional)

RRST pull-up RRST pull-up

resister) resister)

RSTN RSTN
4.7uF CExT

VSS VSS

Megawin MCU Megawin MCU

<Note> : MCU VDD PCB layout trace must route from 10uF, 0.1uF capacitor to VDD pin. REXT must connect to the point
which is close VDD pin after 10uF/0.1uF capacitors’layout trace for ESD consideration.

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7.3. Xtal Oscillating Circuit
To achieve successful and exact oscillating (up to 25MHz), the capacitors C1 and C2 are necessary, as
shown in following figure. Normally, C1 and C2 have the same value.
XTAL Oscillating Circuit
Figure 7-3. XTAL Oscillating Circuit

R1
OSC_OUT
C1 (optional)
(Internal
Crystal

Rf feedback
resister)
C2
(close chip) OSC_IN
C1/C2 = 10~33pF
R1 : drive limit resister Megawin MCU

The following table lists the suggested C1 & C2 value for the different frequency crystal application. Refer
the capacitor load value in Xtal manufacture specification for the final matching capacitor of C1 & C2.

Table 7-1. Reference Capacitance of C1 & C2 for crystal oscillating circuit

Crystal C1, C2 Capacitance

12MHz ~ 25MHz 15pF (12~20pF)

4MHz ~ 12MHz 20pF (15~33pF)
32KHz 10pF (7~12pF)

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MG32F02A032
7.4. ADC Application Circuit
The ADC reference voltage source can be from (1) VDD power by connecting +VREF pin to VDD pin
directly (2) external quiet reference voltage source.
When uses the VDD power as the ADC reference voltage, it must connect +VREF pin trace to the point
which is at current flow behind the power capacitor(s). When uses the external reference voltage source as the
ADC reference voltage, it must add some decoupling and bypass capacitors, as shown in following figure.
An optional ADCx_TRG pin is able to input the trigger signal for ADC input conversion and an optional
ADCx_OUT pin is used to output the internal ADC window detection status.

ADC Application Circuit

Figure 7-4. ADC Application Circuit
[ADC VREF+ Using VDD Power Voltage]
[ADC Conversion Trigger Input]
ADC0_TRG
Power Supply
VDD [Voltage Window
Detect Output]
VREF+ ADCx_OUT

MCU

[ADC VREF+ Using External Voltage] [RC Filter]

R
[ADC Conversion Trigger Input] ADC_In
ADC0_TRG (n={0~15}) (optional)
(optional)

C
VREF+
(close chip)

10uF 0.1uF 100pF

(R/C decide by
application)

MCU

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 MG32F02A032

8. Electrical Characteristics
8.1. Parameter Glossary
Table 8-1. Parameter Glossary

Symbol Definition Descriptions

Abbreviations for electrical characteristics

Unless otherwise specified, the value is guaranteed in worst conditions of
Min Minimum value
ambient temperature, supply voltage by referring sample testing mean value.
Unless otherwise specified, the value is guaranteed in worst conditions of
Max Maximum value
ambient temperature, supply voltage by referring sample testing mean value.
Typ Typical value Unless otherwise specified, the value is based on TA=25 °C, VDD=5V.
VDD Power supply voltage The voltage range is specified in characteristics table or conditions column.
VSS Power reference voltage Unless otherwise specified, all voltages are referred to VSS.
The temperature range is specified in characteristics table or conditions
TA Ambient temperature
column.
The peripheral input clock source may select APB, SYS or other clock. This
TPC Peripheral clock cycle time
clock frequency needs lower than 1/2 of the module process clock frequency.

8.2. Absolute Maximum Rating

Table 8-2. Absolute Maximum Rating

Parameter Rating Unit

Ambient temperature under bias -40 ~ +105 °C

Storage temperature -65 ~ + 150 °C
Voltage on any Port I/O Pin or RST with respect to VSS -0.5 ~ VDD + 0.5 Volt
Voltage on VDD with respect to VSS -0.5 ~ +6.0 Volt
Maximum total current through VDD and VSS 200 mA
Maximum output current sunk by any I/O pin 40 mA
Note: stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device
reliability.

8.3. DC Characteristics
Table 8-3. DC Characteristics
VDD=5.0V±10%, VSS=0V, TA = 25 °C and execute NOP for each CPU cycle (unless otherwise specified)
Limits
Symbol Parameter Conditions Unit
Min Typ Max
Input/Output Characteristics
VIH Input High voltage Except RSTN,XIN/XOUT pins 2.4 Volt
VIH_XOSC Input High voltage (XIN) XIN pin GPIO mode 3 Volt
VIL Input Low voltage Except RSTN,XIN/XOUT pins 1.2 Volt
VIL_XOSC Input Low voltage (XIN) XIN pin GPIO mode 1.3 Volt
IIH Input High Leakage current VPIN = VDD 0 0.1 uA
Logic 0 input current (quasi-bidirectional
IIL1 0 0.001 uA
mode or input mode with on-chip pull-up

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MG32F02A032
resistor)
Logic 0 input current (input mode or open-
IIL2 0 0.001 uA
drain mode)
Logic 1 to 0 input transition current (quasi-
IH2L bidirectional or input mode with on-chip pull- VPIN = 1.8V 320 500 uA
up resistor)
Output High current (quasi-bidirectional
IOH1 251 uA
mode)
Output High current (push-pull output mode
IOH2 VDD = 4.5V , VPIN = 2.4V 32.1 mA
& 20mA level)
Output High current (push-pull output mode
IOH3 VDD = 4.5V , VPIN = 2.4V 16.5 mA
& 10mA level)
Output High current (push-pull output mode
IOH4 VDD = 4.5V , VPIN = 2.4V 8.5 mA
& 5mA level)
Output High current (push-pull output mode
IOH5 VDD = 4.5V , VPIN = 2.4V 4.4 mA
& 2.5mA level)
IOL1 Output Low current(20mA level) 23.7 mA
IOL2 Output Low current(10mA level) 12.3 mA
IOL3 Output Low current(5mA level) 3.2 mA
IOL4 Output Low current(2.5mA level) 3.2 mA
RPU IO pin pull-high resistance Except RSTN 12.5 Kohm
IO rising time( No high speed mode
TR1 Except RSTN,XIN/XOUT pins 10.2 ns
and IO output drive strength is 20mA)
IO rising time( No high speed mode
TR2 Except RSTN,XIN/XOUT pins 53.6 ns
and IO output drive strength is 5mA)
IO rising time( High speed mode
TR3 Except RSTN,XIN/XOUT pins 5.2 ns
and IO output drive strength is 20mA)
IO rising time( High speed mode
TR4 Except RSTN,XIN/XOUT pins 53.5 ns
and IO output drive strength is 5mA)
TR5 IO rising time(XOUT) 7.9 ns
TR6 IO rising time(XIN) 5.4 ns
TR7 IO rising time(RSTIN) 9.7 ns
IO falling time( No high speed mode
TF1 Except RSTN,XIN/XOUT pins 10.2 ns
and IO output drive strength is 20mA)
IO falling time( No high speed mode
TF2 Except RSTN,XIN/XOUT pins 22.2 ns
and IO output drive strength is 5mA)
IO falling time( High speed mode
TF3 Except RSTN,XIN/XOUT pins 9.6 ns
and IO output drive strength is 20mA)
IO falling time( High speed mode
TF4 Except RSTN,XIN/XOUT pins 20.3 ns
and IO output drive strength is 5mA)
TF5 IO falling time(XOUT) 10.1 ns
TF6 IO falling time(XIN) 1.5 ns
TF7 IO falling time(RSTIN) 9.7 ns
Power Consumption
IOP1 TL1 (APB=AHB=32KHz) dhrystone 0.056 mA
IOP2 TL2 (APB=AHB=12MHz) dhrystone 3.7 mA
ON(normal) mode operating current TL3 (APB=AHB=24MHz)
IOP3 11.4 mA
dhrystone + IP
IOP6 TL6 (APB=AHB=48MHz) 15.4 mA

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 MG32F02A032
dhrystone + all IP + I/O
SL1 (IHRCO:
ISLP1 842 uA
APB=6MHz,AHB=3MHz)
ISLP2 SL2 (IHRCO: APB=AHB=12MHz) 1156 uA
Istp0 ST0 (ILRCO disabled) 5.5 uA
STOP mode operating current
Istp1 ST1 (Enable IWDT, ILRCO=32KHz) 7 uA
(LVR/BOD0/BOD1 disabled)
Istp2 ST2 (Enable RTC, ILRCO=32KHz) 6.9 uA
BOD Characteristics
VLVR LVR detection level (VR0) TA = -40℃ to +105℃ 1.45 1.57 1.65 Volt
VBOD0 BOD0 detection level (VR0) TA = -40℃ to +105℃ 1.6 1.65 1.7 Volt
IBOD0+LVR BOD0 and LVR Power Consumption TA = 25℃ 5
VBOD10 BOD1 detection level for 2.0V TA = -40℃ to +105℃ 1.8(*1) 2.0 2.2(*1) Volt
VBOD10 BOD1 detection level for 2.4V TA = -40℃ to +105℃ 2.22(*1) 2.4 2.62(*1) Volt
VBOD11 BOD1 detection level for 3.7V TA = -40℃ to +105℃ 3.50(*1) 3.7 3.90(*1) Volt
VBOD11 BOD1 detection level for 4.2V TA = -40℃ to +105℃ 3.89(*1) 4.2 4.59(*1) Volt
IBOD1 BOD1 Power Consumption TA = 25℃ 4.5 8.3 uA
Operating Condition
VPSR Power-on Slop Rate TA = -40℃ to +105℃ 0.05 V/ms
VOP1 CPU Operating Speed 0–48MHz TA = -40℃ to +105℃ 2.7 5.5 Volt
VOP2 CPU Operating Speed 0–12MHz TA = -40℃ to +105℃ 1.8 5.5 Volt
(*1) Data based on characterization results, not tested in production.

8.4. External Reset Pin Characteristics

Table 8-4. External Reset Pin Characteristics
VDD=5.0V±10%, VSS=0V, TA = 25 °C (unless otherwise specified)
Limits
Symbol Parameter Conditions Unit
Min Typ Max
Input/Output Characteristics
VIH_RST Input High voltage RSTN pin reset mode 2.95 volt
VIL_RST Input Low voltage RSTN pin reset mode 1.69 volt
RRST Internal reset pull-high resistance 250 Kohm

8.5. External Clock Characteristics

Table 8-5. External Clock Characteristics
VDD=2.7V ~ 5.5V, VSS=0V, TA = -40°C ~ +105°C (unless otherwise specified)
Crystal External Clock
Symbol Parameter Conditions Unit
Min Max Min Max
VDD = 2.7V ~ 5.5V 4 25 0 36 MHz
fXOSC Oscillator Frequency
VDD = 2.0V ~ 5.5V 4 25 0 12 MHz
tXOSC Clock Period 40 27.7 ns
tH_XOSC High Time 0.4T 0.6T 0.4T 0.6T tXOSC
tL_XOSC Low Time 0.4T 0.6T 0.4T 0.6T tXOSC
tr_XOSC Rise Time 20 7 ns
tf_XOSC Fall Time 20 7 ns

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MG32F02A032
8.6. PLL Characteristics
Table 8-6. PLL Characteristics

Limits
Parameter Conditions Unit
Min Typ Max
Supply Voltage 1.8 5.0 5.5 Volt
Input Clock Frequency Range TA = -40℃ to +105℃ 5 (*1) 7 (*1) MHz
PLL Locking Time TA = -40℃ to +105℃ 4 (*2) us
PLL Power Consumption TA = +25℃, VDD=5.0V 0.45 mA
CTL='10
PLL Peak-Peak Jitter 500 1000 pS
TA = -40℃ to +105℃
(*1) Data guaranteed by design, not tested in production.
(*2) Data based on characterization results, not tested in production.

8.7. IHRCO Characteristics

Table 8-7. IHRCO Characteristics

Limits
Parameter Conditions Unit
Min Typ Max
Supply Voltage 1.8 5.0 5.5 Volt
IHRCO0 Frequency TA = +25℃ 12 MHz
IHRCO1 Frequency TA = +25℃ 11.0592 MHz
IHRCO0 Frequency Deviation TA = +25℃ -1.0 +1.0 %
(factory calibrated) TA = -40℃ to +105℃ -2.0(*1) +2.0(*1) %
IHRCO1 Frequency Deviation TA = +25℃ -1.0 +1.0 %
(factory calibrated) TA = -40℃ to +105℃ -2.0(*1) +2.0(*1) %
IHRCO Start-up Time TA = 25℃ 6(*1) us
IHRCO Power Consumption TA = +25℃, VDD=5.0V 0.35 mA
(*1) Data based on characterization results, not tested in production.

8.8. ILRCO Characteristics

Table 8-8. ILRCO Characteristics

Limits
Parameter Conditions Unit
Min Typ Max
Supply Voltage 1.8 5.0 5.5 Volt
ILRCO Frequency TA = +25℃ 32 KHz
ILRCO Frequency Deviation TA = +25℃, VDD=5.0V -8 +8 %
(factory calibrated) TA = -40℃ to +105℃ -15(*1) +15(*1) %
ILRCO Power Consumption TA = +25℃, VDD=5.0V 5 uA
(1) Data based on characterization results, not tested in production.

8.9. LDO Characteristics

Table 8-9. LDO Characteristics
VDD=5.0V±10%, VSS=0V, TA = -40℃~ +105 °C
Symbol Parameter Conditions Limits Unit

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 MG32F02A032
Min Typ Max
Supply Range
Supply Voltage Normal Mode 2.6 — 5.5 V
General
LDO Output Voltage ON(Normal) mode 1.83 Volt
VDD18
(VR0 pin) Low power mode (VDD=2.6V~5.5V) 1.75 Volt
VDD=2.6V~5.5V, Temp.= 25℃ 50 uA
IQ Current
VDD=2.6V~5.5V 50(*1) uA
Dropout Voltage
VDROP IOUT=50mA, VDD=2.6V~5.5V 700 mV
(VDD-VDD18)
VDD=5.0V 50 mA
IOUT Max output current VDD=3.6V 50 mA
VDD=2.6V 40 mA
(1) Data based on characterization results, not tested in production.

8.10. Flash Characteristics

Table 8-10. Flash Characteristics
VDD=5.0V±10%, VSS=0V, TA = -40℃~ +105 °C
Limits
Parameter Conditions Unit
Min Typ Max
Supply Voltage 2.0 5.5 Volt
Flash Write (Erase/Program) Voltage 2.2 5.5 Volt
Flash Erase/Program Cycle 10000 Times
Flash Data Retention TA = +25℃ 100 Year

8.11. ADC Characteristics

Table 8-11. ADC Characteristics
VDDA=VDD=5.0V±10%, VSS=0V, TA = 25 °C, CLOAD=10pF, Gain=x1 (unless otherwise specified)
Limits
Symbol Parameter Conditions Unit
Min Typ Max
Supply Range
VDDA Analog Supply Voltage 2.7 5.0 5.5 Volt
IADC_ON Operation Current - normal 2.2 mA
IADC_OFF Operation Current - power-down 0.1 uA
ADC Static Parameters
Bits Resolution 12 bits
VREF = 5V, VDD = 5V,
INL Integral nonlinearity (INL) 800Ksps Conversion Rate ±3 LSB
(sampling clock = 24 MHz)
VREF = 5V, VDD = 5V,
DNL Differential nonlinearity (DNL) 800Ksps Conversion Rate 1.5 LSB
(sampling clock = 24 MHz)
VREF = 5V, VDD = 5V,
EOFFSET Offset error 800Ksps Conversion Rate -15 LSB
(sampling clock = 24 MHz)
VREF = 5V, VDD =
EFS Full scale error 5V,800Ksps Conversion -15 LSB
Rate(sampling clock = 24

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MG32F02A032
MHz)
ADC Input and DC Characters
VAIN ADC input voltage range (Single Ended) gain = 1.0 0 Vref Volt
CLOAD Input Capacitance 8 pF
VREF External reference voltage 2.7 VDDA Volt
VREFINT Internal reference voltage -40 °C < < 105 °C 1.4 Volt
Internal reference voltage spread over the -40 °C < < 105 °C
15 mV
temperature range e.g. [25°C] VREFINT=1.402V
ADC Conversion Parameters
Fs Sampling clock 24 MHz
VDDA = 5.5 ~ 4.0 V 800 Ksps
Conversion rate
VDDA = 4.0 ~ 2.7 V 640 Ksps
Conversion time in conversion clock
30 clocks
(not including acquisition time)
ADC Other Characters and Definitions
TADEN ADC enable time 5 uS
(*1) The UGBW will be divided by the GAIN setting. (ex: Ideal UGF will be 1MHz/4 when PGA gain=4)

8.12. ADC PGA Characteristics

Table 8-12. ADC PGA Characteristics

Limits
Symbol Parameter Conditions Unit
Min Typ Max
Supply Range
VDDA PWR Source Voltage 2.7 5.0 5.5 Volt
DC Characteristics
VDDA=5.0V, VIN= VDDA/2; VOUT=VDDA/2
GAIN<5:0>=00000b, Gain=x1
I_Q Ground Current 1050 uA
(RFB=120KΩ current Not included when
Gain=x1)
AC Characteristics
UGF PGA Bandwidth Frequency (*1) Normal Operation 10 MHz
(*1) The UGF will be divided by the GAIN setting. (ex: Ideal UGF will be 10MHz/4 when PGA gain=4)

8.13. Analog Comparator Characteristics

Table 8-13. Analog Comparator Characteristics
VDD=5.0V±10%, VSS=0V, TA = 25 °C (unless otherwise specified)
Limits
Symbol Parameter Conditions Unit
Min Typ Max
Supply Range
Analog Supply Voltage -40°C ~ +105°C 2.0 5.0 5.5 Volt
Operation Current - CMP0 High response time without IVREF (*1) 10 uA
ICOMP0 High response time with IVREF (*1) 210 uA
Low response time 1.2 uA
Operation Current - CMP1 High response time without IVREF (*1) 10 uA
ICOMP1 High response time with IVREF (*1) 210 uA
Low response time 1.2 uA

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 MG32F02A032
Analog Comparator Core
VOS Input Offset Voltage 20 mV
VCM Input Common Mode Voltage 50 VDD-50 mV
Comparator hysteresis Disable Hysteresis 0 mV
Input voltage range 50mV~VDD- High response time 10 mV
50mV Low response time 10 mV
Response time High response time - Falling 230 ns
High response time - Rising 200 ns
TRT
Low response time - Rising 1.2 us
Low response time – Rising 1 us
High response time 0.5 1.5 us
tPWON Power on Time (from power-down)
Low response time 16.2 us
RU Unit Resistance 309 ohm
(*1) IVREF : Internal voltage reference circuit

8.14. UART Characteristics

Table 8-14. UART Characteristics
VDD=5.0V±10%, VSS=0V, TA = -40°C ~ +105°C (unless otherwise specified)
Limits
Parameter Conditions Unit
Min Typ Max
UART Mode
Serial Port Clock Frequency 6 MHz
Serial Port Clock Cycle Time 2 TPC
Output Data Setup to Clock Rising Edge TPC -20 ns
Output Data Hold after Clock Rising Edge TPC -10 ns
Input Data Hold after Clock Rising Edge 0 ns
Clock Rising Edge to Input Data Valid TPC -20 ns
SPI Master Mode (Synchronous Mode)
VDD=3.3V ~ 5.5V 16 MHz
SPI Clock Frequency
VDD=1.8V ~ 3.3V 12 MHz
SPI Clock High Time 3 TPC
SPI Clock Low Time 3 TPC
TPC : APB clock or SYS clock cycle time

8.15. SPI Characteristics

Table 8-15. SPI Characteristics
VDD=5.0V±10%, VSS=0V, TA = -40°C ~ +105°C (unless otherwise specified)
Limits
Parameter Conditions Unit
Min Typ Max
Master Mode
VDD=3.3V ~ 5.5V 24 MHz
SPI Clock Frequency
VDD=1.8V ~ 3.3V 16 MHz
SPI Clock High Time 2 TPC
SPI Clock Low Time 2 TPC
DIN Valid to SPI Clock Shift Edge 2TPC +20 ns
SPI Clock Shift Edge to DIN Change 0 ns
SPI Clock Shift Edge to DOUT Change 10 ns
Slave Mode

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MG32F02A032
VDD=3.3V ~ 5.5V 16 MHz
SPI Clock Frequency
VDD=1.8V ~ 3.3V 12 MHz
NSS Falling to First SPI Clock Edge 2 TPC
Last SPI Clock Edge to NSS Rising 2 TPC
NSS Falling to DOUT Valid 4 TPC
NSS Rising to DOUT High-Z 4 TPC
SPI Clock High Time 3 TPC
SPI Clock Low Time 3 TPC
DIN Valid to SPI Clock Sample Edge 2 TPC
SPI Clock Sample Edge to DIN Change 2 TPC
SPI Clock Shift Edge to DOUT Change 4 TPC
Last SPI Clock Edge to DOUT Change
1 2 TPC
(CPHA = 1 only)
TPC : APB clock or SYS clock cycle time
DIN : SPI input data signal
DOUT : SPI output data signal

8.16. I2C Characteristics

Table 8-16. I2C Characteristics
VDD=5.0V±10%, VSS=0V, TA = -40°C ~ +105°C (unless otherwise specified)
Standard-mode Fast-mode Fast-mode Plus
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
fSCL SCL Clock Frequency 0 100 0 400 0 1000 KHz
tLow Low period of the SCL clock 4.7 1.3 0.5 us
Low period of the SCL clock
tLow_M 2 2 2 TPC
(Master Mode)
Low period of the SCL clock
tLow_S 4 4 4 TPC
(Slave Mode)
tHigh High period of the SCL clock 4.0 0.6 0.26 us
High period of the SCL clock
tHigh_M 3 3 3 TPC
(Master Mode)
High period of the SCL clock
tHigh_S 5 5 5 TPC
(Slave Mode)
tHD;STA Hold time for START condition 4.0 0.6 0.26 us
Setup time for START
tSU;STA 4.7 0.6 0.26 us
condition
tHD;DAT Data hold time 0 0 0 us
tSU;DAT Data setup time 250 100 50 ns
tSU;STO Setup time for STOP condition 4.0 0.6 0.26 us
Bus free time between a
tBUF 4.7 1.3 0.5 us
STOP and START
tVD;DAT Data valid time 3.45 0.9 0.45 us
tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us
Rise time of both SDA and
tr 1000 300 120 ns
SCL signals
Fall time of both SDA and SCL 20x 20x
tf 300 300 120 ns
signals (VDD/5.5V) (VDD/5.5V)
Capacitive load for each IO
Ci 10 10 10 pF
pin

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TPC : APB clock or SYS clock cycle time

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9. Package Dimension

9.1. LQFP-48

Figure 9-1. LQFP-48 (7mm X 7mm )

Symbols Dimensions in mm
Min. Mom. Max.
A --- --- 1.60
A1 0.05 --- 0.15
A2 1.35 1.40 1.45
b 0.17 0.22 0.27
c 0.09 --- 0.20
D 9.00 BSC
D1 7.00 BSC
E 9.00 BSC
E1 7.00 BSC
e 0.50 BSC
L 0.45 0.60 0.75
L1 1.00 REF
ɵ 0° 3.5° 7°

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9.2. QFN-32

Figure 9-2. QFN-32 (5mm X 5mm )

Symbols Dimensions in mm
JEDEC MO-220
PKG WQFN(X532)
Symbols Min. Nom. Max.
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.203 REF.
b 0.18 0.25 0.30
D 5.00 BSC
E 5.00 BSC
e 0.50 BSC
L 0.35 0.40 0.45
K 0.20 ---- ----

E2 D2 LEAD FINISH
JEDEC
Min. Nom. Max. Min. Nom. Max. Pure
PAD SIZE PPF CODE
Tin
114x114MIL 2.60 2.70 2.75 2.60 2.70 2.75 X V W(V)HHD-2
134x134MIL 3.10 3.20 3.25 3.10 3.20 3.25 V V W(V)HHD-2
153x153MIL 3.15 3.25 3.30 3.15 3.25 3.30 V V W(V)HHD-5

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9.3. TSSOP-20

Figure 9-3. TSSOP-20 (6.5 x 4.4 x1.0 mm)

Unit mm inch
Symbols Min. Nom. Max. Min. Nom. Max.
A ---- ---- 1.20 ---- ---- 0.047
A1 0.05 ---- 0.15 0.001 ---- 0.005
A2 0.80 0.90 1.05 0.031 0.035 0.041
b 0.19 ---- 0.30 0.007 ---- 0.011
C 0.09 ----- 0.20 0.003 ----- 0.007
D 6.40 6.50 6.60 0.251 0.255 0.259
E1 4.30 4.40 4.50 0.169 0.173 0.177
E 6.40 BSC 0.251 BSC
e 0.65 BSC 0.025 BSC
L1 1.00 REF 0.039 REF
L 0.50 0.60 0.75 0.019 0.023 0.029
S 0.20 ---- ---- 0.007 ---- ----
ɵ 0° ---- 8° 0° ---- 8°

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10. Revision History

Revision V1.21 (2019_1115) Chapter

Correct the text “SPI (Slave)” to “SPI (Master) “ on the diagram of “Figure 3 1. System
1 3.1
Function Block”.
Update the ILRCO Frequency Deviation parameters in the table of “Table 8-8. ILRCO
2 8.8
Characteristics”.
Revision V1.20 (2019_1106) Chapter
Update the SRAM size to 4KB and the AP/IAP/ISP flash to 32KB in the table of “Table 5 1.
1 5.2
CPU Memory Address Map”.
Update the ADC Offset error and Full scale error parameters in the table of “Table 8-11.
2 8.11
ADC Characteristics”.
Update the analog comparator hysteresis parameters in the table of “Table 8-13. Analog
3 8.13
Comparator Characteristics”.
Revision V1.10 (2019_0712) Chapter

1 Modify ADC conversion rate from 1Msps to 800Ksps in Features chapter.

2 Update the table of “Table 2-1. Chip Selection Table”. 2

3 Remove “Auto-Off” function in 6.12 ADC section. 6.12.3

4 Remove “Octal SPI mode with bidirectional data transfer” function for SPI module. 6.20.2
Add UART synchronous mode (SPI master mode) timing electrical in “Table 8-14. UART
5 8.14
Characteristics”.
Revision V1.00 (2019_0614) Chapter

1 Released version.

2 Update the parameters’ value in Electrical Characteristics chapter. 8

Revision V0.10 (2019_0403) Chapter

1 Initial version

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11. Disclaimers
Herein, Megawin stands for “Megawin Technology Co., Ltd.”

Life Support — This product is not designed for use in medical, life-saving or life-sustaining applications, or
systems where malfunction of this product can reasonably be expected to result in personal injury. Customers
using or selling this product for use in such applications do so at their own risk and agree to fully indemnify
Megawin for any damages resulting from such improper use or sale.

Right to Make Changes — Megawin reserves the right to make changes in the products - including circuits,
standard cells, and/or software - described or contained herein in order to improve design and/or performance.
When the product is in mass production, relevant changes will be communicated via an Engineering Change
Notification (ECN).

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