Spring -2020

EEE 312 – ELECTRONICS II

Lab # 7 Final Lab

Submitted By: Ege EREREN

Student ID: 2152387

1) Objective
In this design, the goal is to build a converter which converts 3 bit input to
analog output. This design is separated by blocks as usual in any engineering
design.
Design should be like that 3input -> decoder -> 8bit D-Latch -> dac core ->
amplifier -> analog output.
We need to make sure that each block should work under expected values.
Therefore, we should test each block. For example, decoder takes 3-bit input
and convert to 8-bit output. 8 bit D-Latch should store decoder’s output at high
clock phase. DAC core should convert digital inputs (from switches) to analog
output. Finally, the amplifier block should amplify the analog output to give
accurate result.
2) Hierarchical design and analysis
The main idea is to keep portion of the equation same. Kn’(W/L)=Kp’(W/L).
The reference inverter is used in this design as 20*(2.5) = 50*(1).
W/L for PMOS => 2.5
W/L for NMOS => 1
And Gate Design:

Out= A.B or Out=A.B.C

CMOS AND2 Gate consists of 2 parallel PMOS and 2 series NMOS connected to
an inverter.

As shown in the Fig 1, in order to keep Kp and Kn ratios, W/L of NMOSs are set
to 4/2 which makes 1 in series connection and W/L of PMOSs are set to 5/2 to
keep 2.5.

(2//2)=1 for NMOS. Parallel PMOSs are turned on one by one. Therefore, W/L is
5/2=2.5.

The ratio also kept same in reference inverter.

Figure 1: And2 Gate

AND3 gate (OUT=A*B*C) is made with similar approach. Series NMOS 6/2=3,
parallel PMOS 5/2=2.5. Series connection makes total 1 and parallel connection
makes total 2.5. Moreover, the ratio is kept same.

Figure 2: And3 Gate

Or Gate Design:
CMOS OR2 Gate (OUT=A+B) consists of 2 series PMOS and 2 parallel NMOS
connected to an inverter.
As shown in Fig 3;
Series PMOSs are set to 10/2=5 to keep total W/L=2.5
Parallel NMOSs are set to 2/2=1 to keep total W/L=1

Figure 3: OR2 Gate

As shown in Fig 4, OR3 gate (OUT=A+B+C) is made with similar approach. Series
PMOS 15/2=7.5, parallel NMOS 2/2=1. Series connection makes total 2.5 and
parallel connection makes total 1. Moreover, the ratio is kept same.

Figure 4: OR3 Gate

Figure 5: AND3 Symbol

Decoder Design:

I used truth table from lab manual to build decoder.

Figure 6: Truth table of Decoder

I used ones to build outputs. I wrote the output and simplified the equation. As
we are limited to 3 input gates, I separated EN signal to another AND2 Gate.
 Figure 7: Truth Table Simplification
Based on Fig 7 , I draw the circuit of decoder.
Figure 8: Decoder
 Figure 9: Decoder Test

I tested the decoder to make sure its running accurately.

Input= 010 Out= 00000111 as expected (Fig 9).
D-Latch Design:

Figure 10: D-Latch Design

Figure 11: CMOS D-Latch Design

In the D latch design, I used reference inverter( NMOS W/L=1 , PMOS W/L=2.5).
Moreover, I used NMOS W/L=1, PMOS W/L=2.5 for transmission gate as well.
For the nand gate, I used same design that I did before, which is NMOS
W/L=4/2=2 PMOS W/L=5/2=2.5 to keep ratio accurate. W/L ratios can be seen
in Fig 11.
 Figure 12: D-Latch Test

As we can see in Fig 12, when data gets low and clock is in rising edge, output
also gets low as predicted. D-Latch works as expected.

Figure 13: Symbol of D-Latch

8-bit Resettable D-Latch Design:

After completing 1-bit D-Latch design, I designed 8-bit one.

As can be seen in fig 14, all of the clock, reset, data and vdd inputs are
connected to each other and set another input for block design.

Figure 14: 8-bit D-Latch

DAC Core Design:

Figure 15: DAC Core

Vbias Generator:

Simple dc bias generator is made up of an inverter which output connected to

input. Vbias=1V and Vm=1V as indicated.

When we set Vm to 1V, both nmos and pmos transistors are in the saturation
region.

To make this design I used;

2.5 − 0.8 + (0.8) ∗ √𝐾𝑅

1=
1 + √𝐾𝑅
When I solved this equation for KR, KR=12.25.
After that I used Kp’(W/L)=Kn’(W/L).
Kp and Kn are known and L set to 2um. By using that I found Wn/Wp= 9.8/2.
 Figure 16: DC Generator

Figure 16 shows that my DC generator gives accurate 1V.

Voltage Controlled Current Source:

In order to build a transistor work as current source, we need to make sure that
it is in the saturation region. In saturation region the Id current of transistor
should be constant.
These current sources are connected to the ground so NMOS should be used in
this design.

In order to keep current 1uA;

𝐾𝑁 𝑊
𝐼𝐷 = (𝑉𝑏𝑖𝑎𝑠 − 𝑉𝑇𝑁 )2
2 𝐿
𝑊
1𝜇 = 25𝜇 ∗ (1 − 0.8)2
𝐿
W/L= 2/2.

4f(Vbias)=4uA . Therefore, I used W/L=8/2 for most right NMOSs.

Switches:

I used NMOS for the switches with W/L=2/2. Gate of the switches are connected
to inputs. When input is 0, switch will be OFF.
a) Edge of saturation for ON and cut-off for OFF.
b) I think its about the cost reduction. When we try to use transmission gate, we
should use total of 4 MOSFET (including clock and inverted clock).

Figure 17: Switches

Current Load MOSFETS and Current Mirror Design:

a) These MOSFETs are in the saturation region.

b) Current source NMOS has W/L=2/2 and switch has W/L=2/2. In series
connection makes 0.5. Therefore, I set the current load PMOS to 2.5/2. To keep
ratio (1/2.5).
𝑊 𝑊
( )𝑚𝑎𝑖𝑛 = ( )𝑏𝑎𝑙 = 2.5/2
𝐿 𝐿

𝑊
𝐼𝑜𝑢𝑡 3( )
𝐿 𝑚𝑎𝑖𝑛
c) =3 𝑊 = 3 To find 𝐼𝑚𝑎𝑖𝑛 I assumed switches are OFF, but
𝐼𝑚𝑎𝑖𝑛 ( )
𝐿 𝑚𝑎𝑖𝑛
current source has 4uA. 𝐼𝑚𝑎𝑖𝑛 = 4𝑢𝐴 𝐼𝑜𝑢𝑡 = 12𝑢𝐴

𝐼𝑜𝑢𝑡 Getting larger in every step.

Transimpedance Amplifier:

Figure 18: Transimpedance Amplifier:

I assumed Qnot switches are all of. Therefore, Q’s are all ON. In this case I
should get Vo= -0.6.

When we do simple KCL on V- node.

0 − 𝑉𝑜𝑢𝑡
= −𝐼𝑜𝑢𝑡
𝑅
0.6
= 12𝑢 R=50k in this case.
𝑅
Final Design:

Clock is set to 100 kHz in this design. I used block circuits as mentioned in
manual (Fig 19).

Figure 19: Final Design

Highest value that we can take is 0.6V, when inputs are 111 (Fig 20).

Figure 20: Highest Value

Lowest value that we can take is 1.65V, when inputs are 000 (Fig 21).

Figure 21: Lowest Value

When RST=0 and Input=000, I get -1.8 as expected in lab manual (Fig 22).

Figure 22: RST=0 case

3.

Figure 23: Simulated input vs Vout Graph

Theoretical Simulated
Resolution/avg step
Resolution % 2.5/2^8
MSB size 2.5/2=1.25

My design strictly increases 0.15V after each input increases.

Conclusion
In this design, I learnt how to make 3 bit to analog converter design. I believe
that I am using LTSPICE very effectively after this assignment. This design is very
complex I used 203 transistor in total.

Firstly, I had to build decoder. I simplified each output of the decoder to build
AND/OR schematic. After that I tested decoder.

Secondly, I designed 1-bit d-latch cmos schematic. When I am able to do that, I

add eight 1-bit d-latch blocks. I have tested d-latch as well.

Thirdly, I build dc generator and by using the saturation current equation, I

designed currents sources as well. For switches I used reference NMOSs. By
using switch and current source I designed current loads.

Finally, I used Iout and expected Vout I set the resistance to 50k (ohm).

In conclusion, my design works in expected region. When I change input values,

Vout increases accurately. This assignment taught me so many things about
LTSPICE.