A Pixel-Shared CMOS Image Sensor Using Lateral Overflow Gate

Shin Sakai', Yoshiaki Tashiro', Nana Akahane'<, Rihito Kuroda', Koichi Mizobuchi2 and Shigetoshi Sugawa'
'Graduate School of Engineering, Tohoku University, Sendai, Japan
2DISP Development, Texas Instruments Japan, Ibaraki, Japan
E-mail: [email protected]

Abstract-s- A lateral overflow integration capacitor (LOFIC)

~ R -+--------~-­
based CMOS image sensor sharing two pixels and without row- es, -+---------t-~
select transistors has been developed using a newly added lateral es, -+---------t~+_

overflow gate which directly connects the photodiode and the

LOFIC. A 0.18-J.Lm, 2-Poly 3-Metal CMOS technology with a
buried pinned photodiode process was employed for the
fabrication of the CMOS image sensor having 1I3.3-inch optical
format, 1280H x 960 v pixels, and RGB Bayer color filter and on-
chip micro-lens on each pixel. The fabricated CMOS image
sensor exhibits a high conversion gain of 84-J.LV/e- and a high
full well capacity of 6.9 x 104_e- in spite of its pixel size of 3.0 x
3.0-J.Lm 2•

I. INTROD UCTION

In recent years, image sensors with high-resolution

performances due to pixel size reductions have been reported.
The pixel size reductions have been achieved by the
miniaturization technology of devices and circuit technology ~ T, --f-+----------
~ T, - - ~ - - - - - - - - -
enabling the pixel device sharing [1-3]. However, recent excessive
Figure I. Schema tic circuit of the shared two pixels.
pixel pitch reductions such as 1.5-f.lm and more have resulted in
a decrease in sensitivity and deterioration in the lens resolution'",
Meanwhile, newly developed CMOS image sensors with
lateral overflow integration capacitor (LOFIC) have enabled
high-resolution imaging [5-7]. The advantageous characteristics of
these image sensors are realized by resolving the trade-off
between the full well capacity (FWC) and the sensitivity. The
floating diffusion capacitor (Cm) is minimized for high
sensitivity and the LOFIC is maximized for high saturation. In
the LOFIC CMOS image sensor, the Cm and the LOFIC can be
designed independently [7]. These are summarized as a high SIN
ratio, a high sensitivity, a high FWC, and a low dark current.
However, the reported LOFIC CMOS image sensor has a pixel
size of 5.6 x 5.6-f.lm2 [6]. Therefore, a high-resolution
performance has been a challenge.
In this paper, a CMOS image sensor with a high sensitivity, a
3-f.lm ll
high FWC and a high-resolution performance is demonstrated by
Figure 2. Layout diagram of the shared two pixels.
using a combination of the LOFIC and a newly added lateral
overflow gate that directly connects the photodiode (PO) and the
LOFIC. This combination enables pixel component sharing, and
also the elimination of row-select transistors is achieved by
A
------------------A '
controlling of the operation bias ofthe reset voltage.

II. D EVICE STRUCTURE AND CIRCUIT DIAGRAM

Fig. I shows a schematic diagram of the pixel circuit of

the developed image sensor. The pixel size is reduced to 3.0
x 3.0-f.lm2 per one pixel due to a two pixels sharing
technique using the same 0.18-f.lm, 2-Poly 3-Metal CMOS PO
Figure 3. Schem atic cross sectional view
of the line A-A ' shown in Fig. 2.

9 78-1-4244-4 35 3-6 / 09 /$25 . 0 0 ©2 0 0 9 IEEE

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 1H
E )
I I
I I
I I
~T I
I
I
I
V
T
OFF
I I
I I

~S 4--i
I
4- I
I

I
~R
I
I I
I I

Lift
I
Y RESET LLr········· V RESET( H)
I ........... V RFSF r( L)
I I ,. .
I
! !
t l t 2 t3 r, t 5 t6 t, t 8 t. ' t 2 ' t 3 '
Figure 4. Operation Timing diagram.

......
from t8
I'D

Cs Cs FD Cs FD

i ~ i ~ LjJJ-~ S~~~~LO
W r---I'"'U:
T S
PD

Cs FD CS FD cs:::..L FD Cs FD

~ ~
Figure 5. Potential profiles ofthe PO, FD and Cs corresponding to the timings illustrated in Fig. 4.

technology as the previously reported LOFlC CMOS image Fig. 2 and 3 show the pixel layout diagram of the image
sensor'?', Each pixel consists of the following components. sensor, and a schematic cross sectional v iew of the line A-A '
A pinned PD, a floating diffusion to convert the photo- show n in Fig. 2, respectively. The LO-gate and Tare
electron to the voltage (FD), a charge transfer switch (T), an connected with each PD. Cs is formed by the gate electrode
overflow photoelectron integration cap acitor (C s), a switch 1st Poly-Si of the LO-gate and the 2nd Poly-Si above the LO-
between FD and Cs (S) , a reset switch (R), a source follower gate. As the lateral overflow capacitor in the past LOFIC was
amplifier (SF), and an overflow photoelectron transfer gate to composed of the two Poly-Si laye rs, there is no additional
transfer photoelectron from PD to Cs directly (LO-gate). The area expansion caused by the newly added LO-gate.
modifications from the previously reported LOFIC CMOS Moreover, the power-supply voltage of the pixel SF is shared
image sensors include the addition of the LO-gate and the with the pixel reset voltage. Pixel size reduction is achieved
removal of the row-select transistor. YRESET is shared by the by layout optimization and sharing of the pixel components.
reset voltages of FD and Cs as well as, the power-supply Fig. 4 and 5 show the timing diagram of the pixel operation
voltage of the pixel SF. Y LO is supplied for the gate voltage of and the potential profile of PD, FD, and Cs corresponding to
the LO-gate and the counter voltage of the Cs. Pixel size the timings illu strated in Fig . 4, respectivel y. This sensor
reduction is achieved by sharing FD, R, and SF by two pixels needs the row-select operation in addition to the series of
and removing the row -select switch transistor. Pixel selection operations o f the past LOFIC CMOS image sensor
is executed by activating SF by the control of YRESET instead architecture. Prior to the exposure, T, S, and R are turned off.
of the switch transistor. Moreover, the sharing of YRESET with PD is fully depleted at this moment. Then, the switches T, S,
the supply voltage of the pixel SF contributes to the pix el size and R are turned on to reset all of the PD , FD and Cs (t.), The
reduction. By an introduction of the LO-gate in each pixel, a reset noise at FD +Cs is read out as the N2 soon after turning
direct integration of overflow photoelectrons fro m PD to Cs the switch R off (t 2) . After reading out the N2 , the low level
is achieved without an overflow to FD. Consequently, the OfY RESET (Y RESET(L)) is written to the FD to tum off the SF
sharing of the pixel components is achieved without a mi xing (t-), Here, YRESET (L) is set to a relatively higher voltage so as
of overflow photoelectrons in FD from another PD in the not to leak the switch S. During the charge integration of the
shared pixels. exposure (t.), non-saturated photoelectrons are integrated at

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 I Horizontal Shift Rezister 2 I the PD. All of the saturated overflow photoelectrons are also
I
¢ I>-- N2
collected in the Cs through the LO-gate. Therefore the
.....
Signal and Noise Hold 2
¢I>-- S2+N2
overflow photo electrons from the PO are integrated at the Cs
in additional to the N2 signal. The low level of ~T (V TOFF )
*'"
~
9i
<:::
:2 Pixel Array
and the V LO are controlled to overflow the saturated
photoelectrons only to Cs through the LO-gat e. This
VJ operation utilizes the overflow photo electrons in order to
0;
o
'2
achieve a high sensitivity and a high FWC. After the
>'" integration, the switch R is turned on, the high level of V RESET
..... (V RESET (H» is input into the FD (t-), Here the gate voltage of
¢ I>-- S I+N l
I Signal and Noise Hold I
¢ I:>-- Nl
the SF is set to a high er level than the other SFs in the same
I Horizontal Shift Reaister I I column to start the read out operation of the pixel. When the
pixel SF is turned on, saturated electrons overflow to the FD
Figure 6. Block diagram of the imag e sensor.
and are thrown away to VRESET. The FD reset noise is read out
~,~su/g~- I
as the N I (t6), soon after resetting the FD. The noise signal
~ I .- \ ' : ! . -.~ ~
.rof iii~ N I includes the fixed pattern noise component due to the
J
_. f' ..s",,,I,,,dN,,,~",,ldC,",,,'&
'It r~ lkrri zomalShit Rcgisrcr z
threshold voltage variation of the SF transistors. Next , the
I. ::~ Pixel Array J. switch T is turned on, and the photoelectrons are completely
transferred from the PO to the FD (t7) and the signal S I+ N I
~ 1-
,,lI I !t~ -·t·
!
• ~. ]e t280" x 960'" ' , is read out. Then , the switches Sand T are turned on, and the
-1
.. ..

",
.•
..
-> SigllalandN"isc ll"ldCircuil&
HorizontalShit Register I ..
11lo
~
signal charges integrated in the PO are fully transferred to the
'.ooIl
~
1
.' r .. t \ ..; -, ". FD and Cs. All of the mixed charges are read out as the
';'1/ 6__ .. 1l '''" S2+N2 signal. Each shared pixels is operated at the same
Figure 7. Micrograph of the fabricated chip. timing.
Fig. 6 shows the block diagram of this sensor. A vertical
100 I u shift register, a horizontal shift register, current sourc e, and
D
90 signal and noise hold circuit are placed around the two
"Cl ~ 80 dimensional pixel arrays.
-'" '"=
D
.. z;
.. e 70 f- O Fig. 7 shows a micrograph of the fabricat ed chip.
.2.=
;;; ~ 60 __0 Fig. 8 shows the ratio of the saturated overflow photo-
.. 0)
I 0: Overflow to CS I.-
--. •
.; .s
... c
50 - i I .: Overflow to FD
electrons into the Cs through LO-gate, and those into the FD
o .c
C c- 40
through T as a function of the difference between VLO and
o.:: ::
'" c 30 f-
V TOFF • When the difference between V LO and VT OFF is more
~ ce
.c .. than 1.4-V, all of the saturated photo electron s overflow into
5 20
•
.
f-
10
the Cs through LO-gate. V LO of 1.4-V corresponds to the Si
o •, surface voltage of about 0.6-V. Fig. 9 shows the relative
0.0 0.5 1.0 1.5 2.0 2.5 amoun t of the integrated charge s at the PO as a function of
VLO- VTOFFIVI the V LO, which indicat es the FWC at the PD. The values are
Fig ure 8. The ratio of the saturated overflow photoelectro ns
set at 100-% when both of the V LO and the VTOFF are O.O-V. If
into the Cs and FO as a functi on ofVLO-V/ )FF. V LO is set at 1.4-V, about 70-% of charges are integrated at
the PD. The remaining 30-% of the charg es overflow into the
100 Cs, and are read out as saturated overflow photoelectrons.
00 1
90 . - - 0 Subsequently, the value of the FWC does not decrease.
0
80 Fig. 10 shows the photoelectric conversion characteristics.
0
70
0
The integration time was 1/10 seconds. This sensor has
60 0 excellent linearity from about 1.1 x 10'2 -Ix to about 3.3 x
50 0 102-lx and achieves an about 90-dB dynamic range
40 0
performance.
0
30 0 Fig. II shows the sample image of a resolution chart taken
0
20 by this sensor. The obtained resolution is more than 800-
10 1 0
00 line/em, indicating a high- resolution photography has been
I 000000
o achi eved using this image sensor. Fig. 12 shows the sample
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 imag e taken by the wide dynamic rang e image sensing. The
VwlVI imag e is composed of the non-s aturated signal S I converted
Figure 9. The relat ive amount of the integrat ed charges at the FD and the mixed signa l S2 conv erted at the FD+Cs as
at the PO as a funct ion of VLO indicated in the figure. The wid e dynamic range imag e is

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 synthesi zed by using the S1 and S2. There is no black out or
white out spots in the dark and the bright regions of the image.
Also, no specific noise is found in the region around the
switching point of the signal S1 to S2. A high-resolution
image with wide dynamic range characteristics is successfull y
obtained from the dark to the bright regions in one exposure.
Table I shows the summary of the image sensor
performance. The conversion gain is 84-I.lV /e- , and the FWC
is 6.9 X 104 -e-. This sensor realizes a high sensitivity and a
high FWC in spite of3.0 x 3.0-l.lm2 pixel size.

III. CONCLUSIO N
\0 -4 "---'--'-----'_ _-'-'-'--'---'--'-"-'---'---'--'--'-_'--'-'-'-' A LOFIC based CMOS image sensor with shared pixel
\0 -2 \0 -1 \0 0 I0 1 I02 103 components and without the row-select transistor has been
Light inten sity on the senso r surface [Ix] developed using the newly added lateral overflow gate.
Figure 10. Photoelectric conversion characteristics. Optimization of the voltage bias setting has been
experimentally performed in order to overflow the saturated
800
- 400 photoelectrons selectivity into the lateral overflow integrated
700 capacitor. The advantageous characteristics, such as the pixel
size of3.0 x 3.0-l.lm2, the high sensitivity of 84-I.lV /e- and the
60 0 :300
high full well capacity of 6.9x 1Q4_e- are successfully obtained
at the same time.
50 0

R EFERENCES
400 ?1V1

Figure II. Sample image of a resolution chart. [I] H. Takahashi, et aI., "A 3.9/-lm Pixel Pitch VGA Format lOb
Digital Image Sensor with I.5-Transistor/Pixel," ISSCC Dig.
Tech. Papers, pp.108-109, Feb., 2004.

[2] K. Mabuchi, et aI., "C MOS Image Sensor Using a Floating

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[3] M. Mori, et aI., "A 1/4in 2M Pixel CMOS Image Sensor with
I. 75Transistor/Pixel," ISSCC Dig. Tech. Papers, pp.80-81,
Feb., 2004.

[4] G. Arganov, et aI., " Super Small, sub 2/-lm Pixels for CMOS
Image Sensors," in Program of 2007 International Image
S2 (y=0.45) WDR(y=0.3) Sensors Workshop, p.307.
Figure 12. Sample image of a color chart etc..
[5] S. Sugawa, et aI., "A 100 dB Dynamic Range CMOS Image
TABLE I. SUMMARY OF THE IMAGE SENSOR PERFORM ANCE Sensor Using a Lateral Overflow Integration Capacitor,"
Process techn ology 0.18-11m 2 P3M CMOS ISSCC Dig. Tech. Papers, pp.352-353, Feb., 2005.
with pinned PD
Die size 5.6H x 5.8v -mm- [6] N. Ide, et aI., "A wide dynamic range and linear response
Pixel size 3.GH x 3.Qv -J..lm2 CMOS image sensor with three photocurrent integrations in
Number of Pixel I Effective 1280" x 960 v photod iodes, lateral overflow capacitors and column
I Total 13 12" x 968 v capacitors," in Proc. ESSCIRC, Sep. 2007, pp. 336-339.
Fill Factor (bared) 18-%
Conv ersion gai n (input referred) 84-11Vle- [7] S. Adachi, ct aI., "A 200-/-lV/e- CMOS Image Sensor with
Dark Random Noise I Total ( Pixel & Column ) 2.4-e- 100-ke- Full Well Capacity," IEEE lournal Solid-State
(input referred)
IColumn 1.5-e- Circuits, 43, 4, pp. 823-830, April 2008.
Full Well Ca pacity 6.9 x 10' -e-
Dynamic Range -90-dB
Image Lag No detect ion «0.1-%)
FPN (Pixel & Column) (input referre d) 1.6-e-
PRNU (at near satura tion) 1.1-%

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