Chapter2: introduction to

VHDL
• Introduction
• VHDL Description of combinational circuits
1. Introduction
• As integrated circuit technology has improved to allow more and
more components on a chip, digital systems have continued to grow
in complexity.
• The categories depending on the density of integration.
LSI (large scale VLSI (Very large
SSI (small scale MSI (medium scale scale integration) ULSI (Ultra large
integration)
integration) integration) scale integration)
200-few thousand 10,000 gates
1-20 gates 20-200 gates More 100 million
gates

• As digital systems have become more complex, detailed design of the

systems at the gate and flip-flop level has become very tedious and
time-consuming.
2. computer aided design

• Computer-aided design (CAD) tools have

advanced significantly in the past
decade, and nowadays, digital design is
performed using a variety of software
tools. Prototypes or even final designs
can be created without discrete
components and interconnection wires.
• A hardware description language allows
a digital system to be designed and
debugged at a higher level of abstraction
than schematic capture with gates, flip-
flops, and standard MSI building blocks.
• The details of the gates and flip-flops do
not need to be handled during early
phases of design.
• The design can be entred as:
• Behavioral description: general working of
the design at a ow-chart or algorithmic level
without associating to any specific physical
parts, components, or implementations.
• Structural design description: specific
components or specific implementations of
components are associated with the design
• For the step of specific realizations of the
design, different technologies to programmable array logic (PAL)
implement: simple programmable logic devices (SPLDs).
complex programmable logic devices (CPLDs).
field programmable gate arrays (FPGAs)
mask programmable gate arrays (MPGAs)
fully custom application-specific integrated circuit (ASIC) SoC
 • VHDL is a hardware description language used to describe the behavior and
3. Hardware structure of digital systems.
• VHDL is a general-purpose HDL that can be used to describe and simulate the
Description operation of a wide variety of digital systems, ranging in complexity from a few
gates to an interconnection of many complex integrated circuits.
Langages • VHDL can describe a digital system at several different levels—behavioral, data ow,
and structural.
• Example: a binary adder could be described at the behavioral level in terms of its
function of adding two binary numbers without giving any implementation details.
The same adder could be described at the data ow level by giving the logic
equations for the adder. Finally, the adder could be described at the structural level
by specifying the gates and the interconnections between the gates that comprise
the adder.
• Since VHDL is a hardware description language, it differs from an ordinary
programming language in several ways.
• VHDL has statements that execute concurrently since they must model real
hardware in which the components are all in operation at the same time.
4. VHDL Description of Combinational Circuits
• VHDL models combinational circuits using concurrent statements:
✓ ready to execute.
✓ get evaluated any time and every time a signal on the right side of the statement changes.
• Example: describe a simple gate

A signal in VHDL usually corresponds to a signal in a physical system

A, B, C, D, and E are signals.

Concurrent statements:
➢ The first statement will be evaluated anytime A or B changes
➢ The second statement will be evaluated anytime C or D changes

The symbol “,<=” is the signal assignment operator

• In VHDL program there is no loops but concurrent
statements may execute repeatedly as if they were
in a loop.
• Example: inverter with the output connected back The signal CLK oscillate between '0' and '1'
to the input
• If the output is '0', then this '0' feeds back to the
input, and the inverter output changes to '1' after
the inverter delay, assumed to be 10 ns
• The corresponding concurrent VHDL statement will
produce the same result.
• If CLK is initialized to '0', the statement executes
and CLK changes to '1' after 10 ns.
➢ run-time error during simulation.
• Since CLK has changed, the statement executes ➢ there is 0 delay, the value of CLK will change
again, and CLK will change back to '0' after another
10 ns. at times 0 +, 0+2D, 0+3D, and so on.
➢ time will never advance to 1 ns.
• Words such as and, or, and after
are reserved to the VHDL compiler
• In the preceding examples, every
signal is of type bit, which means
it can have a value of '0' or '1’.
• A one-dimensional array of bit
signals is referred to as a bit-
vector Practice

Declare

B <= "1100"

Assign '1' to B(3), '1' to B(2), '0' to B(1), and '0' to B(0).
5. VHDL Modules

• General structure of a VHDL

module
✓ entity description declares the
input and output signals
✓ architecture description specifies
the internal operation of the
module.

To describe a system in VHDL:

✓ specify an entity and architecture at the top level • The signal C is an internal signal
✓ specify an entity and architecture for each of the (declared in the architecture)
component modules that are part of the system
• Entity declaration

• The interface-signal
declaration:

• Mode➔ the direction of information: in /out/inout

• Type ➔ the data type: (bit, bit-vector,,,,)
• Example
 • Architecture declaration

• Associated with each entity is one

or more architecture declarations
of the form

• In the declarations section, we can declare signals and

components that are used within the architecture.
• The architecture body contains statements that describe
the operation of the module
• Example1: Entity and Architecture declaration for a full adder module

• A full adder adds 2 bits and a carry input to generate a sum

bit and a carry output bit.
• The entity specifies the inputs and outputs of the adder
module.

• The port declaration specifies that X, Y, and Cin are input the entity name (FullAdder) must match
signals of type bit, and that Cout and Sum are output signals the name used in the associated entity declaration
of type bit. The VHDL assignment statements for Sum and Cout
represent the logic equations for the full adder.
• Example2: Four-Bit Full Adder

• We will use the Full Adder module defined above as a component in

a system, which consists of four full adders connected to form a 4-
bit binary adder,

• Any time a module created in one part of the code must

be used in another part, a component declaration needs to be used.

• The component declaration does not need to be in the same le

where you are using the component. It can be where the
component entity and architecture are defined.

• It is typical to create libraries of components for reuse in code, and

typically the component declarations are placed in the library,
• We first declare the 4-bit adder as an entity
• we declare inputs and outputs as bit-
vectors which are dimensioned 3 downto
0.
• we specify the FullAdder as a component
within the architecture of Adder4
• we declare a 3-bit internal carry signal C
• we create several instances of the
FullAdder component in the body of the
architecture
• The signal names following the port map
correspond one-to-one with the signals in
the component port.
• Note that the order of the signals in the
port map must be the same as the order of
the signals in the port of the component
declaration.
• Buffer use Case1

• D should be either inout or buffer

mode?
• Use of inout mode results in the
synthesis tools creating a truly
bidirectional signal.
• D is not an external input to the circuit
➔the mode buffer is more appropriate Case2

The mode buffer indicates a signal that is

an output to the external world;
however, its value can also be read
inside the entity's architecture.
Annex
• Review of: full adder and 4bit binary adder (slides collected from CCCN212 course)
Chapter2: introduction to
VHDL
• Introduction
• VHDL Description of combinational circuits
• Sequential statements and VHDL prcrocesses
6- Sequential statements and VHDL processes
• synchronous sequential logic responds to changes dependent on the clock.
Many input changes might be ignored since output and state changes
occur only at valid conditions of the clock.
• A VHDL process has the following basic form:

• When a process is used, the statements between the begin and the end are
executed sequentially. The expression in parentheses after the word
process is called a sensitivity list, and the process executes whenever any
signal in the sensitivity list changes.
• Whenever one of the signals in the sensitivity list changes, the sequential
statements in the process body are executed in sequence one time. When a
process finishes executing, it goes back to the beginning and waits for a signal on
the sensitivity list to change again.

• Concurrent statements in a process➔ sequential statements executed in

the order in which they appear in the process.
• Note: The process executes once when any of the signals A, B, C, or D changes.
• If C changes when the process executes, then the process will execute a second time because C is on the
sensitivity list
• Example:
• The sensitivity list: A, B, and C:
only external inputs to the circuit
• Assume: all variables are '0' at 0
ns
• Then A changes to '1' at 10 ns
➔the process execute:
statements inside the process
execute once sequentially
• Execution of statement 2 is with
the value of D at the beginning of
the process. D becomes '1' at 15
ns, but E stays at ‘0’➔the change
in D does not propagate to signal E
• Note that: If D was included in the
sensitivity list of the process, the
process would execute again
making E change at 20 ns.
 7- Flip Flop using VHDL
• A flip-flop can change state either
on the rising or on the falling edge
of the clock input➔ a process in
VHDL
• D flip flop

• whenever CLK changes, the process executes once • The expression CLK'event (read as “clock tick event”) is TRUE
through and then waits at the start of the process whenever the signal CLK changes.
until CLK changes again. • If CLK = '1' is also TRUE, this means that the change was
from '0' to '1', which is a rising edge.
• D latch

• Both G and D are on the sensitivity list since if G= '1', a

change in D causes Q to change.
• If G changes to '0', the process executes, but Q does not
change.
The basic if statement has the form

• VHDL if statements are sequential statements that can

be used within a process, but they cannot be used as
concurrent statements outside of a process.
 • JK flip flop

• State changes related to J and K occur on the falling

edge of the clock.
• In this chapter, we use a sufix N to indicate an active-
low (negative-logic) signal.
• For simplicity, we will assume that the condition SN =
RN = 0 does not occur.

Within the architecture we dene a signal Qint that represents the state of the flip-
flop internal to the module

The two concurrent statements after begin transmit this internal signal to the Q
and QN outputs of the flip-flop

We do it this way because an output signal in a port cannot appear on the right
side of an assignment statement within the architecture

• 8-ns delay =time it takes to set or clear the flip-flop output

• 10-ns delay =the time it takes for Q to change after the falling edge of the clock
 • Wait statements can be of three different forms:

8- Processes For example:

wait on A, B, C;

Using Wait wait for 5 ns;

wait until A = B;
Statements:
• wait statements instead of a
sensitivity list. A process cannot have both wait statements and a sensitivity list

• The wait statement at the end of the process replaces the sensitivity
list at the beginning.
• both processes will initially execute the sequential statements one
time and then wait until A, B, C, or D changes.
• Note: The order in which sequential
statements execute in a process is not
necessarily the order in which the signals
are updated.

• This process waits for a rising clock edge.

• the clock rises at time=20 ns➔ Statements (1), (2), (3), (4) immediately execute in sequence.
• A is scheduled to change to E at time=30 ns;
• B is scheduled to change to F at time =25 ns;
• C is scheduled to change to G at time=20+ delta;
• D is scheduled to change to H at time 25 ns.
• ➔C changes, then B and D change at time=25 ns, and finally A changes at time 30 ns.
• When clk changes to '0', the wait statement is reevaluated.
Practice:

• Consider this code, and verify if it

will simulate?
9-VHDL Data Types and Operator

• Data Types

• Note: Users can define and create their own data types: the
enumeration type in which all of the values are enumerated.
• VHDL Operators: Example1:
A, B, C, and D are bit_vectors:
• Predefined VHDL operators can be
grouped into seven classes:

To evaluate the expression, the operators are applied in the

order

If A= ''110‘’, B= ''111‘’, C= ''011000'', and D= ''111011'', the

computation proceeds as follows:

Example2:
• The binary logical operators (class 1) can • The ** operator raises an integer or floating-point
not be applied to bits, booleans, number to an integer power, and abs finds the
bit_vectors, and boolean_vectors.
absolute value of a numeric operand.
• The result of applying a relational
operator (class 2) is always a Boolean
(FALSE or TRUE). • The shift operators can be applied to any bit_vector or
boolean_vector.
• Equals (=) and not equals (/=) can be
applied to almost any type.
• The + and - operators can be applied to
integer or real numeric operands.
• Example: A = "10010101":
• The & operator can be used to
concatenate two vectors to form a longer
vector.
• The * and / operators perform
multiplication and division .
• The rem and mod operators calculate the
remainder and modulus for integer
operands.
Chapter2: introduction to
VHDL
• Introduction
• VHDL Description of combinational circuits
• Sequential statements and VHDL prcrocesses
• Simulation and Synthesis Examples
• Behavioral, data flow and structural VHDL
10- Compilation, simulation and synthesis of VHDL codes

• Describing a digital system in

VHDL
➔ simulation of the VHDL code:
➢ verify the VHDL code correctly
implements the intended design
➢ verify that the design meets its
specifications.
➔synthesize it to the target
technology (e.g., FPGA or custom
ASIC).
• The VHDL compiler: checks the VHDL source code for syntax semantic errors, reference to libraries
➔intermediate code
• Elaboration : conversion of the intermediate code to a form used by the simulator. A driver is created
for each signal. Each driver holds the current value of a signal and a queue of future signal values.
• ports are created for each instance of a component; memory storage is allocated for the required
signals; the interconnections among the port signals are specified; and a mechanism is established for
the execution,
➔The resulting data structure = the digital system being simulated.
• The simulation process : initialization of signals ➔simulation.
• VHDL simulation is a discrete event simulation: The passage of time is simulated in discrete steps
• During simulation, statements are executed and corresponding actions (transactions) are scheduled.
The process is called scheduling a transaction.
• The scheduled action happens, not necessarily when the statement executes, but when the
scheduled time has been reached.
• A transaction does not mean that there is a change in the value of a signal. If a change in the value
occurs, we say that an event has taken place.
• Execution of a process happens once, and then the process waits for a signal in the sensitivity list to
change
• Simulation Example: Illustration of Delta Delays during
Simulation of Concurrent Statements
• Suppose that A changes at time= 3
ns.
• Statement 1 executes, and B is
scheduled to change at time 3 + ∆
• Statement 2 executes at time 3+
∆, C is scheduled to change at
time 3 + 2∆.
• Time advances to 3 + 2 ∆, and
statement 3 executes. D is then
scheduled to change at 8 ns.
• Note: when events are scheduled
a finite time in the future, the ∆ s
are ignored.
• Simulation with Multiple
Processes:
• If a model contains more than one
process, all processes execute
concurrently with other processes.
• If there are concurrent statements
outside processes, they also
execute concurrently.
• Statements inside of each process
execute sequentially.
• An example of simulation of
multiple processes
• After elaboration is finished, each driver holds '0', since this is the
default initial value for a bit.
• When simulation begins, initialization takes place
• Both processes are executed simultaneously one time through, and
then the processes wait until a signal on the sensitivity list changes
• When process P1 executes at zero time: two changes in A are
scheduled (A changes to '1' at time D and back to '0' at time =5 ns).
• process P2 executes at zero time, but no change in B occurs, since A is
still '0' during execution at time 0 ns.
• Time advances to D, and A changes to '1'. The change in A causes
process P2 to execute, and since A = '1’, B is scheduled to change to
'1' at time 10 ns.
• The next scheduled change occurs at time = 5 ns, when A changes to
'0'. This change causes P2 to execute, but B does not change. B
changes to '1' at time = 10 ns.
• The change in B causes P1 to execute, and 2 changes in A are
scheduled.
• When A changes to '1' at time 10 1 D, process P2 executes, and B is
scheduled to change at time 20 ns. Then A changes at time 15 ns, and
the simulation continues in this manner until the run-time limit is
reached
• Why A changes at 15ns and not at 15+∆?

Note: a change in a signal is referred to as an event.

11-Simple Synthesis Examples

• Synthesis tools try to infer the

hardware components needed by
“looking” at the VHDL code
➔certain conventions must be
followed.

• A changes➔ the process to execute once.

• If B changes ?
• Timing problems may prevent the • If this code is synthesized, the output: OR gate
hardware from working properly
even though the simulation results
are correct.
• Example 1: • The synthesizer will also ignore the 5-ns delay ➔ use
counters.
this circuit functions differently from what simulated before
synthesis
 Example2

• C is an internal signal
• The signal assignment statements are in a process
• An edge-triggered clock
➔C and G need to be retained after the clock edge, flip-flops
are required for both C and G

Note:a change in the value of C from statement 1 will not be

considered during the execution of statement 2 in that pass of
the process. It will be considered only in the next pass ➔ flip-flop
for C makes this happen in the hardware also. Hardware Corresponding to VHDL Code
12- VHDL models for Multiplexer

• A multiplexer is a combinational circuit

• can be modeled using :
➢ concurrent statements
➢ using processes
➢ A conditional signal assignment statement such as when
➢ selective signal assignment statement using with select
➢ A case statement within a process
➢ Using Concurrent Statements:
• Conditional signal assignment statement
• The MUX output is F=A’. I0 + A . I1

This statement executes whenever A, I0, or I1 changes

• The general form of a conditional signal assignment

statement is:

• Single concurrent signal assignment statement

➔This concurrent statement is executed whenever a change

occurs in a signal used in one of the expressions or conditions
• Cascaded 2-to-1 MUXes • a 4-to-1 multiplexer (MUX) with four data inputs and two
control inputs, A and B.

• conditional assignment statement:

• use a selected signal assignment • The general form of a selected signal assignment
statement statement

➔This concurrent statement executes whenever a signal

changes in any of the expressions.
➢ Using Processes:

• If a MUX model is used inside a process, a • The case statement has the general form
concurrent statement cannot be used. As
an alternative, the MUX can be modeled
using a case statement:

Conclusion:
• combinational circuits can be described using concurrent or
sequential statements.
• Sequential circuits generally require a process statement.
• Process statements can be used to make sequential or
combinational circuits
13-Modeling Registers and Counters Using VHDL
Processes

When several flip-flops change state on the same clock edge

➔ flip-flops can be placed in the same clocked process.

• A cyclic shift register

change state following the rising edge of the clock.

5-ns propagation delay
• If CLR='1', the register is cleared, and if Ld = ‘1’,
the D inputs are loaded into the register.

• This register is fully synchronous ➔

Q outputs only change in response to the clock edge

Q and D are bit-vectors dimensioned 3 downto 0.

CLR is not on the sensitivity list.

If CLR = Ld = '0', no change of Q occurs

• A simple synchronous counter

• On the rising edge of the clock:

➢ the counter is cleared when ClrN = ‘0’,
➢ incremented when ClrN = En = '1’.

• Q signal represents the 4-bit value

• Q is declared to be of type unsigned
• The statement Q <= Q+1; increments the counter
• When the counter is in state “1111,” the next increment
takes it back to state “0000”.
 • Any logic circuit can be described with different levels of detail.
15-Behavioral and • VHDL allows you to create design descriptions at multiple levels of
Structural VHDL abstraction. The most common ones are behavioral models, dataflow
(register transfer language [RTL]) models, and structural models.
• Behavioral VHDL models describe the circuit at a high level of
abstraction without implying any particular structure or technology.
• The structural VHDL model is at a low level of abstraction: the
components used and the structure of the interconnection between
the components are clearly specified.
• The dataflow or RTL level :an intermediate level of abstraction. data
path and control signals are specified. The working of the system is
described in terms of the data transfer between registers
• Modeling a Sequential Machine

• Behavioral model for a Mealy sequential

circuit represented by the state table
• first approach : use two processes
to represent the two parts of the
circuit.
• One process models the
combinational part of the circuit
and generates the next state
information and outputs.
• The other process models the
state register and updates the
state at the appropriate edge of
the clock.
• Since the circuit outputs, Z and
Nextstate, can change when either
the State or X changes, the
sensitivity list includes both State
and X
• A simulator command file that can
be used to test

• The first command specifies the

signals that are to be included in
the waveform output.
• The next command defines a clock
with a period of 200 ns. CLK is '0'
at time 0 ns, is '1' at time 100 ns,
and repeats every 200 ns.
• X is '0' at time 0 ns, changes to '1'
at time 350 ns, changes to '0' at
time 550 ns, and so on.
• Dataflow model for a Mealy sequential circuit
• based on the next state and output equations
• The flip-flops are updated in a process that is sensitive to
CLK.
• A 10-ns delay is included to represent the propagation delay
between the active edge of the clock and the change of the
flip-flop outputs.
• Even though the assignment statements in the process are
executed sequentially, Q1, Q2, and Q3 are all scheduled to be
updated at the same time,
• Thus, the old value of Q1 is used to compute Q2 1, and the
old values of Q1, Q2, and Q3 are used to compute Q3 1. The
concurrent assignment statement for Z causes Z to be
updated whenever a change in X or Q3 occurs. The 20-ns
delay represents two gate delays
• Structural model for a Mealy
sequential circuit:
• describing the gates and flip-flops
in the circuit
• The code requires component
modules DFF, Nand3, Nand2, and
Inverter
• the component modules can be
included in the same fie as the
main VHDL description, or they be
inserted as separate files in a
VHDL project.
 • Variables may be used for local storage in processes. They
16- Variables, can also be used in procedures and functions
Signals, Constant
and arrays • Variables are updated with no delay

• Signals declared at the start of an architecture can be used

anywhere within that architecture.

• The expression is evaluated when this statement is

executed, and the signal is scheduled to change after delay.
• Constants
• Constants declared at the start of an architecture can be used anywhere within that architecture, but
constants declared within a process are local to that process.

• Arrays
• we must first declare an array type and then declare an array object.

• Example: one-dimensional array type named SHORT_WORD:

• Now, we can declare array objects of type SHORT_WORD as follows:

Example: parity generator
• Parity bits are often used in digital communication for error detection
and correction. The simplest of these involve transmitting one
additional bit with the data, a parity bit.
• Use VHDL arrays to represent a parity generator that generates a 5-
bit-odd-parity generation for a 4-bit input number using the look-up
table (LUT) method.
18- Loops in VHDL
• 1. infinite loop
a device works continuously and continues to work until the power is off.

An exit statement of the form

exit; or exit when condition;
may be included in the loop.
• 2. for loop

• 3. while loop
14-VHDL Libraries

• VHDL libraries and packages are used to extend the functionality of VHDL by defining types, functions, components, and overloaded operators
• One of the earliest extensions was to dene multivalued logic as an IEEE standard
• The package IEEE. std_logic_1164 defines a std_logic type that has nine values, including '0', '1', 'X' (unknown), and 'Z' (high impedance). Also
std_logic_vectors, which are vectors of the std_logic type.
• This standard defines logic operations and other functions for working with std_logic and std_logic_vectors, but it does not provide for arithmetic
operations.
• the IEEE introduced two packages to facilitate writing synthesizable code: IEEE.numeric_bit and IEEE.numeric_std.
• The former uses bit_vectors to represent unsigned and signed binary numbers, and the latter uses std_logic_vectors.
• To access functions and components from a library, you need a library statement and a use statement:
✓ The statement
library IEEE;
✓ The statement use
IEEE.numeric_bit.all;
• Whenever a package is used in a module, the library and use statements must be placed before the
entity in that module period.
• The numeric_bit package defines unsigned and signed types as unconstrained arrays of bits:

• Signed numbers are represented in 2’s complement form.

• The numeric_bit package denes the following overloaded operators:
• Unsigned and signed types are basically bit-vectors. However, overloaded operators are
defined for these types and not for bit-vectors.
• The statement C <= A + B; will cause a compiler error if A, B, and C are bit_vectors.
• When the + and - operators are used with unsigned operands of different lengths, the
shortest operand will be extended by ling in 0’s on the left.
• Any carry is discarded so that the result has the same number of bits as the longest
operand. For example, when working with unsigned numbers

• The numeric_bit package provides an overloaded operator to add an integer to an

unsigned, but not to add a bit to an unsigned type.
• Thus, if A and B are unsigned, A + B + 1 is allowed, but a statement of the form
Sum <= A + B + carry; is not allowed when carry is of type bit.
• The carry must be converted to unsigned before it can be added to the unsigned vector
A + B.
• The notation unsigned’(0 => carry) will accomplish the necessary conversion.
• Example: behavioral VHDL code VHDL Code for 4-Bit Adder Using Unsigned Vectors
that uses overloaded operators type unsigned is used instead of bit_vector.
from the numeric_bit package to
describe a 4-bit adder with a carry
input.
• If you compute A + B, the result is a 5-bit signal (Sum5) is declared
only 4 bits. Since you want a 5-bit
result, you must extend A to 5 bits
by concatenating '0' and A
• Sum5 is calculated using the
overloaded operators from the
numeric_bit package, it is split into
a 4-bit sum (S) and a carry (Co).
Corresponding Synthesizer Output (Xilinx )
 • If multivalued logic is desired, one can use
• Useful conversion functions found
in the numeric_bit package IEEE standard numeric_std package
include the following:
• TO_INTEGER(A): converts an • The numeric_std package denes unsigned
unsigned vector A to an integer and signed types as std_logic vectors instead of
• TO_UNSIGNED(B, N): converts an bit_vectors.
integer to an unsigned vector of
length N
• UNSIGNED(A): causes the Three statements are required to use this package:
compiler to treat a bit_vector A as
an unsigned vector
• BIT_VECTOR(B): causes the
compiler to treat an unsigned
vector B as a bit_vector