Hardware Modeling Overview

1
What is Verilog HDL?

2
Levels of Abstraction

3
Levels of Abstraction

4
Language Subsets

5
Hierarchical Design

6
Partitioning Guidelines

7
Top-Down Component

8
Device-Level Optimization

9
Inference versus Vendor Macro Instantiation

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 Modules , Ports,
Data-Flow Level Modeling

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Half-Adder

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Full Adder

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Structured Half Adder

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4-bit Binary Full Adder

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DLatch

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DFF

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ISE Software Editing Resources

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Module Description

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Module Example

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Driving Output Ports

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Continuous Assignments

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Continuous Assignments

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Using `define for Ports

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Using parameter for Ports

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Port Declarations

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Port Rules Summary

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reg Output(s)

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reg Output(s)

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reg Output(s)

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Creating Hierarchy

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Mapping Ports

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Internal Module Connectivity

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Unconnected Ports

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Using defparam

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Using Module Instance

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Controlled Operation Statements

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Conditional Execution

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Language Structure

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if/else Statements

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else Clause

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if/else if Statements

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if/else if Example

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if/else if Rules

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Language Structure

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case Statement

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Handling Multiple Statements

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case Guidelines

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case Guidelines

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Full and Parallel case

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Default Assignments

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if/else Default Assignment Question

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if/else Default Assignment Answer

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case Default Assignment Question

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case Default Assignment Answer

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Alternate Default Approach

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Verilog Procedural Statements

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Behavioral Modeling

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Behavioral and Procedural Coding

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Simulation versus Hardware

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Simulation

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Testbench versus UUT

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Procedural Statements

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initial versus always

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Procedural Assignments

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Initialization

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initial Blocks

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always Blocks

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Triggering and Stopping always

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Event-Based Control

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Modeling Combinatorial Logic

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Event-Control Examples

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Edge-Triggered Event

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Modeling D-Type Flip-Flops

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Blocking versus Non-Blocking

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Blocking

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Non-Blocking

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Why Non-Blocking?

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Effect of Non-Blocking

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Blocking and Non-Blocking Uses

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Blocking and Non-Blocking

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Verilog Language Concepts

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Syntax and Structure

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Keywords and Identifiers

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Comments

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Data Values

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Data Types

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Verilog Net Types

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Variable Data Types

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Comparing reg versus wire

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reg and Flip-Flop Confusion

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reg and Flip-Flop Confusion

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Numerical Representation

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Explicitly Sized Numbers

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Implicitly Sized Numbers

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Integers

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Integers

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real

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time

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Bus Declaration (1)

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Bus Declaration (2)

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Bus Declaration (3)

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Bus Declaration (4)

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Memory

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Multi-Dimensional Memory

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Bit Select

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Part Select

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Verilog Operators and Expressions

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Operators

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Bitwise Operators

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Bitwise Operator Examples

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Logical Operators

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Logical Operator Examples

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Relational Operators

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Relational Operator Examples

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Equality Operators

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Equality Operator Examples

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Reduction Operators

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Reduction Operator Examples

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Conditional Operators

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Conditional Operators

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Conditional Operators

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Concatenation Operators

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Concatenation Operator Examples

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Shift Operators

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Shift Operator Example

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Building Shift Registers

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Arithmetic Operators

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Arithmetic Operator Examples

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Resource Sharing

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Introduction to Testbenches

131
Design Verification

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Testbench Concept

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Application of a Testbench

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Complete IEEE 1364

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Simulation I/O Flexibility

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Recommended Verification Stages

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Timing Verification

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Testbench Consistency

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Procedural Coding

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Verify at Each Level

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Before the Testbench

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Components of a Testbench

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`timescale Directives

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Testbench Example

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CNTR32 Testbench

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Creating Clock Signals

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Other Clock Approaches

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Modeling Input Stimulus

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One Possible Solution

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Gate Delays

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Simulating Delays

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Modeling Delays

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Delay Specification

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Delay Specification

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Cumulative Delays

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System Tasks

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System Tasks

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Formatting Data

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$monitor System Tasks

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$stop and $finish System Tasks

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Outputting $time

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Using $display and $monitor

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One Possible Solution

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Finite State Machines

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Simple Code to Complex Logic

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FSM Overview

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FSM Coding

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Mealy versus Moore

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Moore Machine

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Mealy Machine

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Initialization

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Synchronous Initialization

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Unreachable States

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“Safe” State Machines

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Parameters

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Local Parameters

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Using Parameters

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`define Statements

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Using `define Statements

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One or More Procedural Blocks

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One Possible Approach

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Using always

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Modeling Next-State Logic

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Assigning Moore Outputs

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Assigning Mealy Outputs

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Using assign for Outputs

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Registered Moore Outputs

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Registered Mealy Outputs

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Using Single always

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Single always Block

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FSM Outputs

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FSM Coding Example

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FSM Coding Example

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FSM Coding Example

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FSM Coding Example

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