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%4 Power MOSFET

FEATURES
PRODUCT SUMMARY
• Low figure-of-merit (FOM) Ron x Qg
VDS (V) 650
• Low input capacitance (Ciss)
RDS(on) max. at 25 °C (Ω) VGS = 10 V 0.17 • Reduced switching and conduction losses Available
Qg max. (nC) 109 • Ultra low gate charge (Qg)
Qgs (nC) 15 • Avalanche energy rated (UIS)
Qgd (nC) 31
Configuration Single

D
TO-220 FULLPAK

G D S N-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 650
V
Gate-Source Voltage VGS ± 30
TC = 25 °C 20
Continuous Drain Current (TJ = 150 °C) VGS at 10 V ID
TC = 100 °C 13 A
Pulsed Drain Current a IDM 56
Linear Derating Factor 1.8 W/°C
Single Pulse Avalanche Energy b EAS 691 mJ
Maximum Power Dissipation PD 30 W
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C
Drain-Source Voltage Slope TJ = 125 °C 70
dV/dt V/ns
Reverse Diode dV/dt d 26
Soldering Recommendations (Peak Temperature) c for 10 s 300 °C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.

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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 65
°C/W
Maximum Junction-to-Case (Drain) RthJC - 3.6

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 650 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.74 - V/°C
Gate-Source Threshold Voltage (N) VGS(th) VDS = VGS, ID = 250 μA 3 - 5 V
VGS = ± 20 V - - ± 100 nA
Gate-Source Leakage IGSS
VGS = ± 30 V - - ±1 μA
VDS = 650 V, VGS = 0 V - - 1
Zero Gate Voltage Drain Current IDSS μA
VDS = 520 V, VGS = 0 V, TJ = 125 °C - - 10
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 11 A - 0.170 - Ω
Forward Transconductance gfs VDS = 8 V, ID = 5 A - 6.7 - S
Dynamic
Input Capacitance Ciss VGS = 0 V, - 2414 -
Output Capacitance Coss VDS = 100 V, - 118 -
Reverse Transfer Capacitance Crss f = 1 MHz - 4 -
Effective Output Capacitance, Energy pF
Co(er) - 89 -
Related a
VDS = 0 V to 520 V, VGS = 0 V
Effective Output Capacitance, Time
Co(tr) - 307 -
Related b
Total Gate Charge Qg - 73 110
Gate-Source Charge Qgs VGS = 10 V ID = 11 A, VDS = 520 V - 15 - nC
Gate-Drain Charge Qgd - 32 -
Turn-On Delay Time td(on) - 22 45
Rise Time tr VDD = 520 V, ID = 11 A, - 33 66
ns
Turn-Off Delay Time td(off) VGS = 10 V, Rg = 9.1 Ω - 73 110
Fall Time tf - 38 76
Gate Input Resistance Rg f = 1 MHz, open drain - 0.64 - Ω
Drain-Source Body Diode Characteristics
MOSFET symbol
Continuous Source-Drain Diode Current IS D
- - 22
showing the
A
integral reverse G

Pulsed Diode Forward Current ISM p - n junction diode S - - 56

Diode Forward Voltage VSD TJ = 25 °C, IS = 11 A, VGS = 0 V - - 1.2 V

Reverse Recovery Time trr - 400 - ns
TJ = 25 °C, IF = IS = 11 A,
Reverse Recovery Charge Qrr - 5.9 - μC
dI/dt = 100 A/μs, VR = 400 V
Reverse Recovery Current IRRM - 20 - A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

60 3
TOP 15 V TJ = 25 °C
14 V ID = 11 A
ID, Drain-to-Source Current (A)

13 V

On Resistance (Normalized)
50 12 V 2.5

RDS(on), Drain-to-Source
11 V
10 V
9V
40 8V 2
7V

30 1.5

20 1 VGS = 10 V

6V
10 0.5
5V
0 0
0 5 10 15 20 25 30 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

40 10 000
TOP 15 V
TJ = 150 °C Ciss
ID, Drain-to-Source Current (A)

14 V
ġ
13 V
12 V 1000 VGS = 0 V, f = 1 MHz
Capacitance (pF)

30
11 V Ciss = Cgs + Cgd, Cds Shorted
10 V Crss = Cgd
9V 7V Coss = Cds + Cgd
Coss
20 8V 100
ġ

10 10 Crss
6V ġ

5V
0 1

0 5 10 15 20 25 30 0 100 200 300 400 500 600

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

60
16
ID, Drain-to-Source Current (A)

50 5000 14

12
40
10
Coss (pF)

Eoss (μJ)

30 Coss Eoss
TJ = 150 °C 8
500
20 6

TJ = 25 °C 4
10
VDS = 30 V
2
0
0 5 10 15 20 25 50 0
0 100 200 300 400 500 600
VGS, Gate-to-Source Voltage (V) VDS

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Coss and Eoss vs. VDS

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24 25
VDS = 520 V
VGS, Gate-to-Source Voltage (V)

VDS = 325 V
20 VDS = 130 V 20

ID, Drain Current (A)

16
15

12
10
8

5
4

0 0
0 30 60 90 120 150 25 50 75 100 125 150
Qg, Total Gate Charge (nC) TJ, Case Temperature (°C)

Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature

100 800
ISD, Reverse Drain Current (A)

775

Breakdown Voltage (V)

TJ = 150 °C
VDS, Drain-to-Source
750
TJ = 25 °C
10
725

700

675
1
650

VGS = 0 V 625

0.1 600
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
VSD, Source-Drain Voltage (V) TJ, Junction Temperature (°C)

Fig. 8 - Typical Source-Drain Diode Forward Voltage Fig. 11 - Temperature vs. Drain-to-Source Voltage

1000
Operation in this Area
Limited by RDS(on)
100 IDM = Limited
ID, Drain Current (A)

10
100 μs
Limited by RDS(on)*
1
1 ms

0.1 TC = 25 °C 10 ms
BVDSS Limited
TJ = 150 °C
Single Pulse
0.01
1 10 100 1000
VDS - Drain -to-Source Voltage (V)
* VGS > minimum V GS at which R DS(on) is specified

Fig. 9 - Maximum Safe Operating Area

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1
Duty Cycle = 0.5
Normalized Effective Transient

0.2
Thermal Impedance

0.1
0.1
0.05

0.02

Single Pulse
0.01
0.0001 0.001 0.01 0.1 1 10
Pulse Time (s)

Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case

RD VDS
VDS
tp
VGS VDD
D.U.T.
RG
+
- VDD VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 % IAS
Fig. 16 - Unclamped Inductive Waveforms
Fig. 13 - Switching Time Test Circuit

VDS QG
90 % 10 V

QGS QGD

10 % VG
VGS
td(on) tr td(off) tf
Charge
Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform
L Current regulator
VDS Same type as D.U.T.
Vary tp to obtain
required IAS 50 kΩ

RG D.U.T + 12 V 0.2 µF
0.3 µF
V DD
- +
IAS VDS
D.U.T. -
10 V
tp 0.01 Ω VGS

3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit

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Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 19 - For N-Channel

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TO-220 FULLPAK

A
E F
Q1

G
ØR
D

A3

3 x b2 Mold flash
L1

3 x b1 bleeding Q

Exposed Cu
L

3xb

2xe C Bottom view

MILLIMETERS
DIM. MIN. NOM. MAX.
A 4.60 4.70 4.80
b 0.70 0.80 0.91
b1 1.20 1.30 1.47
b2 1.10 1.20 1.30
C 0.45 0.50 0.63
D 15.80 15.87 15.97
e 2.54 BSC
E 10.00 10.10 10.30
F 2.44 2.54 2.64
G 6.50 6.70 6.90
L 12.90 13.10 13.30
L1 3.13 3.23 3.33
Q 2.65 2.75 2.85
Q1 3.20 3.30 3.40
ØR 3.08 3.18 3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking

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FACILITY
E A
ØP A1
n

d1
d3
D
u

L1
V

b3
A2
b2
c
b

MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
A 4.570 4.830 0.180 0.190
A1 2.570 2.830 0.101 0.111
A2 2.510 2.850 0.099 0.112
b 0.622 0.890 0.024 0.035
b2 1.229 1.400 0.048 0.055
b3 1.229 1.400 0.048 0.055
c 0.440 0.629 0.017 0.025
D 8.650 9.800 0.341 0.386
d1 15.88 16.120 0.622 0.635
d3 12.300 12.920 0.484 0.509
E 10.360 10.630 0.408 0.419
e 2.54 BSC 0.100 BSC
L 13.200 13.730 0.520 0.541
L1 3.100 3.500 0.122 0.138
n 6.050 6.150 0.238 0.242
ØP 3.050 3.450 0.120 0.136
u 2.400 2.500 0.094 0.098
V 0.400 0.500 0.016 0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking

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