InnoSwitch-CH Family

Off-Line CV/CC Flyback Switcher IC with Integrated 650 V MOSFET,

Synchronous Rectification and Feedback

Product Highlights
Highly Integrated, Compact Footprint
• Incorporates flyback controller, 650 V MOSFET, secondary-side
sensing and synchronous rectification driver SR FET
• Integrated FluxLink™, HIPOT-isolated, feedback link
• Exceptional CV/CC accuracy, independent of transformer design or
external components
• Instantaneous transient response ±5% CV with 0%-100%-0%

FWD

GND

BPS
load step

SR

FB
D
InnoSwitch-CH
EcoSmart™ – Energy Efficient Primary FET VOUT
• <10 mW no-load at 230 VAC when supplied by transformer bias and Controller
Secondary
winding S BPP IS Control IC
• Easily meets all global energy efficiency regulations
• Low heat dissipation
Advanced Protection / Safety Features PI-6986-103014

• Primary sensed output OVP Figure 1. Typical Application/Performance.

• Secondary sensed output overshoot clamp
• Secondary sensed output OCP to zero output voltage
• Hysteretic thermal shutdown

Full Safety and Regulatory Compliance

• 100% production HIPOT compliance testing equivalent to
6 kV DC/1 sec
• Reinforced insulation
• Isolation voltage >3,500 VAC
• UL1577 and TUV (EN60950 and EN62368) safety approved
• EN61000-4-8 (100 A/m) and EN61000-4-9 (1000 A/m) compliant Figure 2. High Creepage, Safety-Compliant eSOP Package.

Green Package
• Halogen free and RoHS compliant

Applications
• Chargers and adapters for smart mobile devices Output Power Table
• High efficiency, low voltage, high current power supplies 85-265 VAC
Description Product 3,4 Peak or
Adapter1
The InnoSwitch™-CH family of ICs dramatically simplifies the develop- Open Frame2
ment and manufacturing of low-voltage, high current power supplies, INN20x3K 12 W 15 W
particularly those in compact enclosures or with high efficiency require-
INN20x4K 15 W 20 W
ments. The InnoSwitch-CH architecture is revolutionary in that the
devices incorporate both primary and secondary controllers, with sense INN20x5K 20 W 25 W
elements and a safety-rated feedback mechanism into a single IC.
Table 1. Output Power Table.
Close component proximity and innovative use of the integrated Notes:
1. Minimum continuous power in a typical non-ventilated enclosed typical size
communication link permit accurate control of a secondary-side adapter measured at 40 °C ambient. Max output power is dependent on the
synchronous rectification MOSFET and optimization of primary-side design. With condition that package temperature must be < = 125 °C.
switching to maintain high efficiency across the entire load range. 2. Minimum peak power capability.
Additionally, the minimal DC bias requirements of the link enables the 3. Package: eSOP-R16B.
system to achieve less than 10 mW no-load in challenging applications 4. x = 0 (No cable compensation), x = 2 (6% cable compensation).
such as smart-mobile device chargers.

www.power.com June 2020

This Product is Covered by Patents and/or Pending Patent Applications.
 InnoSwitch-CH

PRIMARY BYPASS DRAIN

(BPP) (D)
REGULATOR
5.95 V

FAULT BYPASS PIN

PRESENT UNDERVOLTAGE
+
AUTO- BYPASS
RESTART -
CAPACITOR
COUNTER SELECT AND 5.95 V
VI
CURRENT 5.39 V LIMIT
RESET LIMIT STATE
MACHINE
CURRENT LIMIT
COMPARATOR
-

JITTER
CLOCK
DCMAX THERMAL
SHUTDOWN

FROM OSCILLATOR
PRI/SEC
FEEDBACK
DRIVER RECEIVER
CONTROLLER S Q

PULSE
DCMAXS
R Q

6.4 V LEADING
OVP EDGE
LATCH BLANKING
20 Ω

SOURCE
PI-7432-110414 (S)

Figure 3. Primary-Side Controller Block Diagram.

OUTPUT
VOLTAGE FORWARD
(VO) (FWD)
REGULATOR
4.45 V

DETECTOR

SCONDARY
BYPASS HAND SHAKE
(BPS) PULSES
+
4.45 V CONTROL
-
3.80 V
FEEDBACK
(FB)
+

-
CABLE TO
COMPENSATION FEEDBACK RECEIVER
DRIVER
ISENSE
(IS)
+

-
CLOCK
IS THRESHOLD

OSCILLATOR
ENABLE
SYNC RECT SR
(SR) ENB
Q S

Q R +

- SECONDARY
GROUND
SR THESHOLD (GND)

PI-7433-092717

Figure 4. Secondary-Side Controller Block Diagram.

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 InnoSwitch-CH

Pin Functional Description InnoSwitch-CH Functional Description

DRAIN (D) Pin (Pin 1) The InnoSwitch-CH combines a high-voltage power MOSFET switch
This pin is the power MOSFET drain connection. and both primary-side and secondary-side controllers in one device.
The feedback scheme using a proprietary FluxLink coupling scheme
SOURCE (S) Pin (Pin 3-6)
using the package lead frame and bond wires to provide a reliable
This pin is the power MOSFET source connection. It is also the
and low-cost means to provide accurate direct sensing of the output
ground reference for the PRIMARY BYPASS pin.
voltage and output current on the secondary to communicate
PRIMARY BYPASS (BPP) Pin (Pin 7) information to the primary IC. Unlike conventional PWM (pulse width
It is the connection point for an external bypass capacitor for the modulated) controllers, it uses a simple ON/OFF control to regulate
primary IC supply. the output voltage and current. The primary controller consists of an
oscillator, a receiver circuit magnetically coupled to the secondary
NO CONNECTION (NC) Pin (Pin 8) controller, current limit state machine, 5.95 V regulator on the
This pin should be left open or tied to PRIMARY BYPASS pin. PRIMARY BYPASS pin, overvoltage circuit, current limit selection
NO CONNECTION (NC) Pin (Pin 9) circuitry, over temperature protection, leading edge blanking and a
This pin should be left open. 650 V power MOSFET. The InnoSwitch-CH secondary controller
consists of a transmitter circuit that is magnetically coupled to the
FORWARD (FWD) Pin (Pin 10) primary receiver, constant voltage (CV) and constant current (CC)
The connection point to the switching node of the transformer output control circuitry, a 4.45 V regulator on the SECONDARY BYPASS pin,
winding for sensing and other functions. synchronous rectifier MOSFET driver, frequency jitter oscillator and a
host of integrated protection features. Figures 3 and 4 show the
OUTPUT VOLTAGE (VOUT) Pin (Pin 11)
functional block diagrams of the primary and secondary controllers
This pin is connected directly to the output voltage of the power
with the most important features.
supply to provide bias to the secondary IC.
PRIMARY BYPASS Pin Regulator
SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 12)
The PRIMARY BYPASS pin has an internal regulator that charges the
Connection to external SR FET gate terminal.
PRIMARY BYPASS pin capacitor to VBPP by drawing current from the
SECONDARY BYPASS (BPS) Pin (Pin 13) voltage on the DRAIN pin whenever the power MOSFET is off. The
It is the connection point for an external bypass capacitor for the PRIMARY BYPASS pin is the internal supply voltage node. When the
secondary IC supply. power MOSFET is on, the device operates from the energy stored in
the PRIMARY BYPASS pin capacitor. Extremely low power consump-
FEEDBACK (FB) Pin (Pin 14) tion of the internal circuitry allows the InnoSwitch-CH to operate
This pin connects to an external resistor divider to set the power continuously from current it takes from the DRAIN pin.
supply CV voltage regulation threshold.
In addition, there is a shunt regulator clamping the PRIMARY BYPASS
SECONDARY GROUND (GND) (Pin 15) pin voltage to VSHUNT when current is provided to the PRIMARY
Ground connection for the secondary IC. BYPASS pin through an external resistor. This facilitates powering the
ISENSE (IS) Pin (Pin 16) InnoSwitch-CH externally through a bias winding to decrease the
Connection to the power supply output terminals. Internal current no-load consumption to less than 10 mW (5 V output design).
sense is connected between this pin and the SECONDARY GROUND pin. PRIMARY BYPASS Pin Capacitor Selection
The PRIMARY BYPASS pin can use a ceramic capacitor as small as
0.1 mF for decoupling the internal power supply of the device. A
larger capacitor size can be used to adjust the current limit. A 1 mF
capacitor on the PRIMARY BYPASS pin will select a higher current limit
equal to the standard current of the next larger device. A 10 mF
capacitor on the PRIMARY BYPASS pin selects a lower current limit
equal to the standard current limit of the next smaller device
D1 16 IS
15 GND PRIMARY BYPASS Pin Undervoltage Threshold
The PRIMARY BYPASS pin undervoltage circuitry disables the power
14 FB
MOSFET when the PRIMARY BYPASS pin voltage drops below VBPP-VBPP(H)
S 3-6 13 BPS
in steady-state operation. Once the PRIMARY BYPASS pin voltage
12 SR falls below this threshold, it must rise back above VBPP to enable
11 VOUT switching the power MOSFET.
BPP 7 10 FWD
PRIMARY BYPASS Pin Output Overvoltage Latching Function
NC 8 9 NC
The PRIMARY BYPASS pin has an OV protection latching feature.
A Zener diode in parallel to the resistor in series with the PRIMARY
BYPASS pin capacitor is typically used to detect an overvoltage on the
primary bias winding to activate this protection mechanism. In the
PI-7398-072915 event the current into the PRIMARY BYPASS pin exceeds (ISD) the
device will disable the power MOSFET switching. The latching
Figure 5. Pin Configuration. condition is reset by bringing the primary bypass below the reset
threshold voltage (VBPP(RESET)).

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 InnoSwitch-CH

Over-Temperature Protection
The thermal shutdown circuitry senses the primary die temperature.
This threshold is set to 142 °C with 75 °C hysteresis. When the die P: Primary Chip
temperature rises above this threshold the power MOSFET is disabled S: Secondary Chip
Start
and remains disabled until the die temperature falls by 75 °C, at which P: Powered Up, Switching
point it is re-enabled. A large hysteresis of 75 °C is provided to S: Powering Up
prevent over-heating of the PC board due to continuous fault condition.

Current Limit Operation

The current limit circuit senses the current in the power MOSFET. P: Auto-Restart
When this current exceeds the internal threshold (ILIMIT), the power S: Powering Up
MOSFET is turned off for the remainder of that switch cycle. The
current limit state-machine reduces the current limit threshold by tAR(OFF)
discrete amounts under medium and light loads.

The leading edge blanking circuit inhibits the current limit comparator S: Has powered No P: Goes to Auto-Restart Off
for a short time (tLEB) after the power MOSFET is turned-on. This up within tAR S: Bypass Discharging
leading edge blanking time has been set so that current spikes
caused by capacitance and secondary-side rectifier reverse recovery
Yes
time will not cause premature termination of the switching pulse. tAR
Each switching cycle is terminated when the Drain current of the
P: Switching
primary power MOSFET reaches the current limit of the device. S: Sends Handshaking Pulses
Auto-Restart
In the event of a fault condition such as output overload, output
short-circuit or external component/pin fault, the InnoSwitch-CH
enters into auto-restart (AR) operation. In auto-restart operation the P: Has Received No P: Continuous Switching
power MOSFET switching is disabled for t AR(OFF). There are 2 ways to Handshaking S: Doesn’t Take Control
enter auto-restart after the secondary has taken control: Pulses

1. Continuous switching requests from the secondary for time period Yes
exceeding t AR.
2. No requests for switching cycles from the secondary for a time P: Stops Switching, Hands
period exceeding t AR(SK). Over Control to Secondary

The first condition corresponds to a condition wherein the secondary

controller makes continuous cycle requests without a skipped-cycle
for more than t AR time period. The second method was included to
ensure that if communication is lost, the primary tries to restart again. S: Has Taken No P: Not Switching
Although this should never be the case in normal operation, this can Control? S: Doesn’t Take Control
be useful in the case of system ESD events for example where a loss
of communication due to noise disturbing the secondary controller, is
Yes
resolved when the primary restarts after an auto-restart off time.

The auto-restart alternately enables and disables the switching of the End of Handshaking,
power MOSFET until the fault is removed. The auto-restart counter is Secondary Control Mode
gated by the switch oscillator in SOA mode the auto-restart off timer
PI-7416-110414
may appear to be longer.

The auto-restart counter is reset once the primary PRIMARY BYPASS

Figure 6. Primary – Secondary Handshake Flowchart.
pin falls below the undervoltage threshold VBPP-VBPP(HYS).

Safe-Operating-Area (SOA) Protection onwards the secondary is in control of demanding switching cycles
In the event there are two consecutive cycles where the primary when required.
power MOSFET switch current reaches current limit (ILIM) within the
The handshake flowchart is shown in Figure 6.
blanking (tLEB) and current limit (tILD) delay time, the controller will
skip approximately 2.5 cycles or ~25 msec. This provides sufficient In the event the primary stops switching or does not respond to cycle
time for reset of the transformer without sacrificing start-up time into requests from the secondary during normal operation when the
large capacitive load. Auto-restart timing is increased when the secondary has control, the handshake protocol is imitated to ensure
device is operating in SOA-mode. that the secondary is ready to assume control once the primary
begins switching again. This protocol for an additional handshake is
Primary-Secondary Handshake Protocol
also invoked in the event the secondary detects that the primary is
At start-up, the primary initially switches without any feedback
providing more cycles than were requested.
information (this is very similar to the operation of a standard
TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers). If no The most likely event that could require an additional handshake is
feedback signals are received during the auto-restart on-time, the when the primary stops switching resulting from a momentary line
primary goes into auto-restart and repeats. However under normal drop-out or brown-out event. When the primary resumes operation,
conditions, the secondary chip will power-up through the FORWARD it will default into a start-up condition and attempt to detect hand-
pin or directly from VOUT and then take over control. From then shake pulses from the secondary.

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 InnoSwitch-CH

The communication is extremely robust. Measures against loss of The secondary will stop requesting cycles for t AR(SK), to begin primary-
communication have been implemented to make the device tolerant side auto-restart of t AR(OFF). In this condition, the total apparent AR
to extreme conditions such as surge, ESD events, or failure of off-time is t AR(SK) + t AR(OFF). During normal operation, the secondary
external component (single point faults). will stop requesting pulses from the primary to initiate an auto-restart
cycle when the FEEDBACK pin voltage falls below VFB(OFF) threshold.
In the event the secondary does not detect that the primary responds The deglitch filter on the VFB(OFF) is less than 10 msec. The secondary
to requests for 3 consecutive cycles, or if the secondary detects that will relinquish control after detecting the FEEDBACK pin is shorted to
the primary is switching without cycle requests for 3 or more ground.
consecutive cycles, the secondary controller will initiate a second
OUTPUT VOLTAGE Pin Auto-Restart Threshold
handshake sequence.
The OUTPUT VOLTAGE pin includes a comparator to detect when the
This protection mode also provides additional protection against output voltage falls below the VOUT(AR) threshold for a duration exceed-
cross-conduction of the SR MOSFET while the primary is switching ing tVOUT(AR). The secondary controller will relinquish control when it
with the primary-side in control. This protection mode also prevents detects the OUTPUT VOLTAGE pin has fallen below VOUT(AR) for a time
output overvoltage in the event the primary is reset while the duration longer than tVOUT(AR). This threshold is meant to limit the
secondary is still in control and light/medium load conditions exist. range of constant current (CC) operation.

Secondary Controller Cable Drop Compensation (CDC)

The feedback driver block is the drive to the FluxLink communication The amount of cable drop compensation is a function of the load with
loop transferring switching pulse requests to the primary IC. respect to the constant current regulation threshold as illustrated in
Figure 7 below.
As shown in the block diagram in Figure 4, the secondary controller
is powered through a 4.45 V Regulator block by either VOUT or
FORWARD pin connections to the SECONDARY BYPASS pin. The
SECONDARY BYPASS pin is connected to an external decoupling φCD × VFB
capacitor and fed internally from the regulator block.

The FORWARD pin also connects to the negative edge detection FEEDBACK Pin Cable Drop
Voltage Compensation
block used for both handshaking and timing to turn on the synchro-
nous rectifier MOSFET (SR FET) connected to the SYNCHRONOUS
VFB
RECTIFIER DRIVE pin. The FORWARD pin is also used to sense when
to turn off the SR FET in discontinuous mode operation when the
voltage across the FET on resistance drops below VSR(TH).

In continuous mode operation the SR FET is turned off when the

No-Load Onset of CC
pulse request is sent to demand the next switching cycle, providing Load Current Regulation
excellent synchronization free of any overlap for the FET turn-off
while operating in continuous mode. PI-7417-110714

The mid-point of an external resistor divider network between the Figure 7. Cable Drop Compensation Characteristic.
VOUT and SECONDARY GROUND pins is tied to the FEEDBACK pin
to regulate the output voltage. The internal voltage comparator The lower feedback pin resistor must be tied to the SECONDARY
reference voltage is VREF (1.265V). GROUND pin (not ISENSE pin) to have output cable drop compensa-
tion enabled.
The resistor connected between IS and SECONDARY GROUND pins is
the bonding wire sense resistor which is used to regulate the output Cable drop compensation only applies for 5 V designs. Cable drop
current in constant current regulator mode. The ISENSE pin is compensation function is disabled for higher output voltage designs.
connected to the internal bond wire sense resistor and a 33 mV ISV(TH)
threshold comparator used to determine the value at which the power Output Constant Current Regulation
supply output current is regulated. The InnoSwitch-CH regulates the output current through internal
sense across bond wires between the ISENSE and SECONDARY
Output Overvoltage Protection GROUND pins. An external diode may be required across the
In the event the sensed voltage on the FEEDBACK pin is 2% higher ISENSE-SECONDARY GROUND pins to limit the peak voltage across
than the regulation threshold, a bleed current of ~10 mA is applied on the bond wire during fault condition. Larger output capacitance
the VOUT pin. This bleed current increases to ~140 mA in the event especially at higher output voltages, the output capacitor discharge
the FEEDBACK pin voltage is raised to beyond ~20% of the internal into a short-circuited output can exceed the bond wire fusing current.
FEEDBACK pin reference voltage. The current sink on the VOUT pin
is intended to discharge the output voltage for momentary overshoot SR Disable Protection
events. The secondary does not relinquish control to the primary On a cycle-by-cycle basis the SR is only engaged in the event a cycle
during this mode of operation. was requested by the secondary controller and the negative edge is
detected on the FORWARD pin. In the event the voltage on the
FEEDBACK Pin Short Detection ISENSE pin exceeds approximately 3 times the ISV(TH) threshold, the
In the event the FEEDBACK pin voltage is below the VFB(OFF) threshold SR MOSFET drive is disabled until the surge current has diminished
at start-up, the secondary will complete the primary/secondary to nominal levels.
handshake and will stop requesting pulses to initiate an auto-restart.

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 InnoSwitch-CH

InnoSwitch-CH Operation required. If the InnoSwitch-CH is appropriately chosen for the power
level, the current in the calculated inductance will ramp up to current
InnoSwitch-CH devices operate in the current limit mode. When limit before the DCMAX limit is reached.
enabled, the oscillator turns the power MOSFET on at the beginning
of each cycle. The MOSFET is turned off when the current ramps up InnoSwitch-CH senses the output voltage on the FEEDBACK pin using
to the current limit or when the DCMAX limit is reached. Since the a resistive voltage divider to determine whether or not to proceed
highest current limit level and frequency of a InnoSwitch-CH design with the next switching cycle. The sequence of cycles is used to
are constant, the power delivered to the load is proportional to the determine the current limit. Once a cycle is started, it always
primary inductance of the transformer and peak primary current completes the cycle. This operation results in a power supply in
squared. Hence, designing the supply involves calculating the primary which the output voltage ripple is determined by the output capacitor,
inductance of the transformer for the maximum output power and the amount of energy per switch cycle.

CLOCK CLOCK

DMAX DMAX

IDRAIN IDRAIN

VDRAIN VDRAIN

PI-7041-101014 PI-7040-101014

Figure 8. Operation at Near Maximum Loading. Figure 9. Operation at Moderately Heavy Loading.

CLOCK CLOCK

DCMAX DMAX

IDRAIN IDRAIN

VDRAIN VDRAIN

PI-7038-101014 PI-7039-101014

Figure 10. Operation at Medium Loading. Figure 11. Operation at Very Light Load.

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 InnoSwitch-CH

ON/OFF Operation with Current Limit State Machine supply output (Figure 9). At medium loads, cycles will be skipped and
The internal clock of the InnoSwitch-CH runs all the time. At the the current limit will be reduced (Figure 10). At very light loads, the
beginning of each clock cycle, the voltage comparator on the current limit will be reduced even further (Figure 11). Only a small
FEEDBACK pin decides whether or not to implement a switch cycle, percentage of cycles will occur to satisfy the power consumption of
and based on the sequence of samples over multiple cycles, it the power supply.
determines the appropriate current limit. At high loads, the state
The response time of the ON/OFF control scheme is very fast compared
machine sets the current limit to its highest value. At lighter loads,
to PWM control. This provides accurate regulation and excellent
the state machine sets the current limit to reduced values.
transient response.
At near maximum load, InnoSwitch-CH will conduct during nearly
all of its clock cycles (Figure 8). At slightly lower load, it will “skip”
additional cycles in order to maintain voltage regulation at the power

200

PI-2395-101014
PI-7042-053013
100 VDC-INPUT 200

0 100 VDC-INPUT

10 0

5 VBPP 400

0 300

400 200 VDRAIN

200 VDRAIN 100

0 0
0 1 2 0 2.5 5
Time (ms) Time (s)
Figure 12. Power-Up Timing. Figure 13. Normal Power-Down Timing.

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 InnoSwitch-CH

Applications Example

VAC
85 115 230 265
Average 84.2 84.2
Efficiency
Full Load 82.6 84.2 85.1 84.8
at PCB (%)
10% Load 78.3 78.9 78.6 78.7 C8
100 pF
No-Load Input (mW) 7 7 8 9 400 VAC
L2
4.7 µH 5 V, 2 A
4 6

R8
100 kΩ
1%
C1 C9 C10
1 nF R1 560 µF
200 kΩ R7 1.5 nF
250 V 3 20 Ω 200 V 6.3 V
R9 R10
RS2MA-13-F

D1 34 kΩ
D3 R14 DFLR1600-7 330 kΩ
1%
D5

RS2MA-13-F 30 Ω 600 V
5
1

SI7478DP-T1-E3
F1
3.15 A D+/D-

Q1
2 T1
C2 C4 EE1621 C16
85 - 264 8.2 µF 8.2 µF NC 1 µF
VAC 400 V 400 V 50 V
RT1 C7
DFLR1200-7

10 Ω R5 2.2 µF
C5 47 Ω 25 V
200 V

R4
22 µF
D2

t
O

3 kΩ R11
16 V InnoSwitch-CH 100 kΩ
U1

SR/P
FWD

GND
BPS
INN2023K

VO
RS2MA-13-F

D
D4 CONTROL
D6

RS2MA-13-F FB

C15
100 pF
S BPP IS 100 V

L1 C6
100 µH 1 µF
25 V RTN

PI-7424-111014

Figure 14. 5 V, 2 A Universal Input Charger.

The circuit shown in Figure 14 is a low cost, very high efficiency effectively limits the turn-off voltage spike at the DRAIN pin of U1 to
charger designed to provide 5 V, 2 A CV/CC charging, using an a safe value.
INN2023K integrated power supply controller.
The InnoSwitch-CH IC is self-starting, using an internal high-voltage
This single 5 V output charger design features DoE Level 6 and EC current source to charge the PRIMARY BYPASS pin capacitor (C6)
CoC 5 compliance (84% measured vs. 79% requirement) and <10 mW when AC is first applied. During normal operation the primary-side
no-load input power. The integration offered by InnoSwitch-CH controller is powered from an auxiliary winding on the transformer
devices reduces the total component count from typically >45 to only T1. Output of the auxiliary (or bias) winding is rectified using diode
32. The built-in secondary-side synchronous rectification (SR) D2 and filtered using capacitor C5. Resistor R4 limits the current
controller of U1, allows expensive high current Schottky barrier diodes being supplied to the PRIMARY BYPASS pin of the InnoSwitch-CH IC
to be replaced with lower cost MOSFETs while increasing efficiency (U1) to be close to the IC supply current so as to minimize no-load
and removing hot spots. With control on the secondary-side, cross input power.
conduction problems normally associated with SR are eliminated
Output regulation is achieved using ON/OFF control, the number of
under all conditions.
enabled switching cycles are adjusted based on the output load. At
The input stage required a small thermistor (RT1) to prevent inrush high-load, most switching cycles are enabled, and at light-load or
currents exceeding the specification of D3-D6 and causing fuse F1 no-load, most cycled are disabled or skipped. Once a cycle is enabled,
to open. the MOSFET will remain on until the primary current ramps to the
device current limit for the specific operating state. There are four
The total input capacitance of capacitor C2 and C4 is sufficient to operating states (current limits) arranged such that the frequency
maintain full output power delivery at 85 VAC, the converter being content of the primary current switching pattern remains out of the
able to operate at the minimum DC voltage, just before the next AC audible range until at light-load where the transformer flux density
cycle refreshes the input. The DC voltage is applied to the primary and therefore audible noise generation is at a very low level.
winding of T1. The other end of the primary winding is driven by the
MOSFET inside the InnoSwitch-CH IC. The secondary-side of the InnoSwitch-CH IC provides output voltage,
output current sensing and drive to a MOSFET providing synchronous
A low-cost RCD clamp formed by diode D1, resistors R1 and R14, and rectification.
capacitor C1 limits the peak drain voltage of the InnoSwitch-CH IC at
the instant of turn-off of the MOSFET. The clamp helps dissipate the The secondary of the transformer is rectified by MOSFET Q1 and
energy stored in the leakage reactance of transformer T1 and filtered by capacitor C10. Resistor R7 and C9 limit high-frequency

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 InnoSwitch-CH

ringing during switching transients that would otherwise create Better load regulation and lower output ripple can be achieved by
radiated EMI. The gate of Q1 is turned on by secondary-side matching the time constants of upper and lower feedback divider
controller inside the InnoSwitch-CH IC based on the winding voltage network. As shown in Figure 15.
sensed via resistor R5 and fed into the FORWARD pin of the IC. RB CB , RA CA
In continuous conduction mode of operation, Q1 is turned off just
Key application Considerations
prior to the secondary-side commanding a new switching cycle from
the primary. In discontinuous mode of operation, Q1 is turned off Output Power Table
when the voltage drop across the MOSFET falls below a threshold of The data sheet output power table (Table 1) represents the minimum
approximately -24 mV [VSR(TH)]. practical continuous output power level that can be obtained under
the following assumed conditions:
As both SR and primary MOSFET control resides on the secondary-
side, any possibility of cross conduction of the two MOSFETs is 1. The minimum DC input voltage is 90 V or higher for 85 VAC input,
eliminated. In turn the time Q1 is on can be maximized for lowest or 220 V or higher for 230 VAC input or 115 VAC with a voltage
loss and allows removal of a parallel Schottky diode and/or the use of doubler. The value of the input capacitance should be sized to
a lower cost higher RDS(ON) device for the same efficiency compared to meet these criteria for AC input designs.
standalone SR controllers. 2. Efficiency of >82%.
3. Minimum data sheet value of I2f.
The secondary-side of the InnoSwitch-CH IC is self-powered from
4. Transformer primary inductance tolerance of ±10%.
either the secondary winding forward voltage or the output voltage.
5. Reflected output voltage (VOR) of 110 V.
Capacitor C7 connected to the SECONDARY BYPASS pin of
6. Voltage only output of 12 V with a synchronous rectifier.
InnoSwitch-CH IC (U1) provides decoupling for the internal circuitry.
7. Increased current limit is selected for peak and open frame power
During CC (constant current) operation, when the output voltage columns and standard current limit for adapter columns.
falls, the device will power itself from the secondary winding directly. 8. The part is board mounted with SOURCE pins soldered to a
During the on-time of the primary-side power MOSFET, the forward sufficient area of copper and/or a heat sink is used to keep the
voltage that appears across the secondary winding is used to charge SOURCE pin temperature at or below 110 °C.
the decoupling capacitor C7 via resistor R5 and an internal regulator. 9. Ambient temperature of 50 °C for open frame designs and 40 °C
This allows output current regulation to be maintained down to <2.5 V. for sealed adapters.
Below this level the unit enters auto-restart until the output load is
*Below a value of 1, KP is the ratio of ripple to peak primary current.
reduced.
To prevent reduced power delivery, due to premature termination of
Output current is sensed internally between the ISENSE and switching cycles, a transient KP limit of ≥0.25 is recommended. This
SECONDARY GROUND pins with a threshold of approximately 33 mV prevents the initial current limit (IINIT) from being exceeded at
(ISV(TH)) to reduce losses. Once the internal current sense threshold is MOSFET turn-on.
exceeded, the device adjusts the number of switch pulses to maintain
Overvoltage Protection
a fixed output current.
The output overvoltage protection provided by the InnoSwitch-CH IC
Below the CC threshold, the device operates in constant voltage uses an internal latch that is triggered by a threshold current of
mode. The output voltage is sensed via resistor divider R8 and R9. approximately 7.6 mA into the PRIMARY BYPASS pin. In addition to
Output voltage is regulated so as to achieve a voltage of 1.265 V on an internal filter, the PRIMARY BYPASS pin capacitor forms an external
the FEEDBACK pin. Capacitor C15 provides decoupling to the filter providing noise immunity from inadvertent triggering. For the
FEEDBACK pin that ensure stable operation and prevents switching bypass capacitor to be effective as a high frequency filter, the
noise from coupling into the IC. capacitor should be located as close as possible to the SOURCE and
PRIMARY BYPASS pins of the device.

The primary sensed OVP function can be realized by connecting

VOUT
a Zener diode from the rectified and filtered bias winding voltage
supply to the PRIMARY BYPASS pin (parallel to R4 in Figure 14).
RC Selecting the Zener diode voltage to be approximately 6 V above
RA
the bias winding voltage (28 V for 22 V bias winding) gives good OVP
CA
performance for most designs, but can be adjusted to compensate
CB for variations in leakage inductance. Adding additional filtering can
be achieved by inserting a low value (10 Ω to 47 Ω) resistor in series
RB with the bias winding diode and/or the OVP Zener diode. The resistor
in series with the OVP Zener diode also limits the maximum current
into the BYPASS pin.
GND

InnoSwitch
FB

Reducing No-load Consumption

The InnoSwitch-CH IC can start in self-powered mode from the
BYPASS pin capacitor charged through the internal current source.
Use of a bias winding is however required to provide supply current to
IS the PRIMARY BYPASS pin once the InnoSwitch-CH IC has become
operational. Auxiliary or bias winding provided on the transformer is
RTN required for this purpose. The addition of a bias winding that provides
bias supply to the PRIMARY BYPASS pin enables design of power
PI-8443-092717
supplies with no-load power consumption down to <10 mW. Resistor
R4 shown in Figure 14 should be adjusted to achieve the lowest
Figure 15. Feedback Network. no-load input power.

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 InnoSwitch-CH

Audible Noise However a smaller capacitor value <22 µF also can be used as long
The cycle skipping mode of operation used in the InnoSwitch-CH IC as there is enough bias current into the PRIMARY BYPASS pin during
can generate audio frequency components in the transformer. To no-load operation at the lowest rated output voltage such that the
limit this audible noise generation the transformer should be designed internal tap does not turn on.
such that the peak core flux density is below 3000 Gauss (300 mT).
A small resistor ranging from 2.2 Ω to 10 Ω in series with the bias
Following this guideline and using the standard transformer produc-
winding diode is recommended in order to damp the ringing that
tion technique of dip varnishing practically eliminates audible noise.
could get coupled to FORWARD pin from bias winding. Waveforms
Vacuum impregnation of the transformer should not be used due to
shown in FORWARD Pin Resistor section are the examples for
the high primary capacitance and increased losses that result. Higher
acceptable and unacceptable waveforms on the FORWARD pin during
flux densities are possible, however careful evaluation of the audible
secondary rectifier on period.
noise performance should be made using production transformer
samples before approving the design. Ceramic capacitors that use Primary Sensed OVP (Overvoltage Protection)
dielectrics such as Z5U, when used in the clamp circuits and especially The voltage developed across the bias winding output tracks the
the bias supply (C1 and C5 in Figure 14) may also generate audio power supply output voltage. Though not precise, a reasonably
noise. If this is the case, try replacing them with a capacitor having accurate detection of output voltage condition can be achieved by the
a different dielectric or construction, for example a film type for the primary-side controller using the bias winding voltage. A Zener diode
clamp or electrolytic for the bias. connected from the bias winding output to the PRIMARY BYPASS pin
can reliably detect a fault condition that leads to increase in output
Selection of Components
voltage beyond the set limits and causes the primary-side controller to
Components for InnoSwitch-CH Primary-Side Circuit latch off preventing damage of components due to the fault conditions.

BPP Capacitor It is recommended that the highest voltage at the output of the bias
Capacitor connected from the PRIMARY BYAPSS pin of the winding should be measured for normal steady-state conditions at full
InnoSwitch-CH IC provides decoupling for the primary-side controller rated load and lowest rated input voltage and also under transient
and also selects current limit. A 0.1 mF, 10 mF or 1 mF capacitor may load conditions. A Zener diode rated for 1.25 times this measured
be used as indicated in the InnoSwitch-CH data sheet. Though voltage will typically ensure that OVP protection will not operate
electrolytic capacitors can be used, often surface mount multi-layer under any normal operating conditions and will only operate in case
ceramic capacitors are preferred for use on double sided boards as of a fault condition.
they enable placement of capacitors close to the IC and design of
Use of the primary sensed OVP protection is highly recommended.
compact switching power supplies. 16 V or 25 V rated X5R or X7R
dielectric capacitors are recommended to ensure minimum capaci- Primary-Side Snubber Clamp
tance requirements are met. A snubber circuit should be used on the primary-side as shown in the
example circuit. This prevents excess voltage spikes at the drain of
Bias Winding and External Bias Circuit
the MOSFET at the instant of turn-off of the MOSFET during each
The internal regulator connected from the drain pin of the MOSFET to
switching cycle. Though conventional RCD clamps can be used, RCDZ
the PRIMARY BYPASS pin of the InnoSwitch-CH primary-side controller
calmps offer the highest efficiency. The circuit example shows in
charges the capacitor connected to the PRIMARY BYPASS pin to
Figure 14 uses RCD clamp with a resistor in series with the clamp
achieve start-up. A bias winding should be provided on the trans-
diode . This resistor dampens the ringing at the drain and also limits
former with a suitable rectifier and filter capacitor to create a bias
the reverse current through the clamp diode during reverse recovery.
supply that can be used to supply at least 1 mA of current to the
Standard recover glass passivated diodes with low junction capaci-
PRIMARY BYPASS pin.
tance are recommended as these enable partial energy recovery from
Turns ratio for the bias winding should be selected such that 9 V is the clamp thereby improving efficiency.
developed across the bias winding at the lowest rated output voltage
of the charger at the lowest (or no-load) load condition. If the Components for InnoSwitch-CH Secondary-Side Circuit
voltage is lower than this, the no-load input power will be higher than SECONDARY BYPASS Pin – Decoupling Capacitor
expected. A 2.2 mF, 25 V multi-layer ceramic capacitor should be used for
decoupling the SECONDARY BYPASS pin of the InnoSwitch-CH IC. A
The bias current from the external circuit should be set to approxi-
significantly higher value will lead to output voltage overshoot during
mately 300 mA to achieve less than 10 mW no load power consump-
start-up and lower values may lead to unpredictable operation. The
tion when operating the charger at no load and 230 VAC input voltage.
capacitor must be located adjacent to the IC pins. The 25 V rating is
A glass passivated standard recovery rectifier diode with low junction necessary to guarantee the actual value in operation since the capaci-
capacitance is recommended to prevent snapped recovery typical of tance of ceramic capacitors drops with applied voltage. 10 V rated
fast or ultrafast diodes which typically leads to higher radiated EMI. examples are not recommended for this reason. Capacitors with X5R
or X7R dielectrics should be used for best results.
A filter capacitor of at least 22 mF with a voltage rating 1.2 times
greater than the highest voltage developed across the capacitor is FORWARD Pin Resistor
recommended. Highest voltage is typically developed across this A 47 W, 5% resistor is recommended to ensure sufficient IC supply
capacitor when the supply is operated at the highest rated output current. A higher or lower resistor value should not be used as it can
voltage and rated load with the lowest input AC supply voltage. affect device operation such as the synchronous rectifier drive timing.

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 InnoSwitch-CH

0V
VSRTH
0V
VSRTH

VD VD

PI-8392-082317 PI-8393-080917

Figure 16. Unacceptable FORWARD Pin Waveform After Handshake With Figure 19. Acceptable FORWARD Pin Waveform Before Handshake With Body
SR MOSFET Conduction During Flyback Cycle. Diode Conduction During Flyback Cycle.

SR MOSFET Operation and Selection

Although a simple diode rectifier and filter is adequate for the
secondary-winding, use of a SR MOSFET enables significant improve-
ment in operating efficiency often required to meet the European CoC
and the U.S. DoE energy efficiency requirements.

The secondary-side controller turns on the SR MOSFET once the

flyback cycle begins. The SR MOSFET gate should be tied directly to
the SYNCHRONOUS RECTIFIER DRIVE pin of the InnoSwitch-CH IC
and no additional resistors should be connected in the gate circuit of
0V the SR MOSFET.
VSRTH
The SR MOSFET is turned off once the drain voltage of the SR
MOSFET drops below -24 mV [VSR(TH)]. Therefore the use of MOSFETs
with a very small RDS(ON) can be counterproductive as it reduces the
VD
MOSFET on-time, commutating the current to the body diode of the
PI-8393-080917 MOSFET or an external parallel Schottky diode if used.

A MOSFET with 18 mW RDS(ON) is a good choice for designs rated for

Figure 17. Acceptable FORWARD Pin Waveform After Handshake With
5 V, 2 A output. The SR MOSFET driver uses the secondary SECOND-
SR MOSFET Conduction During Flyback Cycle.
ARY BYPASS pin for its supply rail and this voltage is typically 4.4 V.
A MOSFET with too high a threshold voltage is therefore not suitable
and MOSFETs with a low threshold voltage of 1.5 V to 2.5 V are ideal
although MOSFETs with a threshold voltage (absolute maximum) as
high as 4 V may be used.

There is a slight delay between the commencement of the flyback

cycle and the turn-on of the SR MOSFET. During this time, the body
diode of the SR FET conducts. If an external parallel Schottky diode
is used, this current mostly flows through the Schottky diode. Once
0V the InnoSwitch-CH IC detects end of the flyback cycle, voltage across
VSRTH
SR MOSFET RDS(ON) drops below 24 mV, the remaining portion of the
flyback cycle is completed with the current commutating to the body
diode of the SR MOSFET or the external parallel Schottky diode.

Use of the Schottky diode parallel to the SR MOSFET may be added

VD to provide higher efficiency and typically a 1 A surface mount
Schottky diode is often adequate. The gains are modest, for a 5 V,
t1 t2 2 A design the external diode adds ~0.1% to full load efficiency at
PI-8394-080917 85 VAC and ~0.2% at 230 VAC.
Figure 18. Unacceptable FORWARD Pin Waveform Before Handshake With The voltage rating of the Schottky diode and the SR MOSFET should
Body Diode Conduction During Flyback Cycle. be at least 1.3 to 1.4 times the expected peak inverse voltage (PIV)
based on the turns ratio used for the transformer. 60 V rated
Note:
MOSFETs and diodes are suitable for most 5 V designs that use a
If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail the handshake and
VOR <60 V.
trigger a primary bias winding OVP latch-off.

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 InnoSwitch-CH

The interaction between the leakage reactance of the secondary and Recommendations for Circuit Board Layout
the MOSFET capacitance (COSS) leads to ringing on the voltage
waveforms at the instance of voltage reversal at the winding due to See Figure 20 for a recommended circuit board layout for
the primary MOSFET turn-on. This ringing can be suppressed using a InnoSwitch-CH IC.
RC snubber connected across the SR FET. A snubber resistor in the Single-Point Grounding
range of 10 W to 47 W may be used though a higher resistance value Use a single-point ground connection from the input filter capacitor
leads to noticeable drop in efficiency. A capacitance of 1 nF to 1.5 nF to the area of copper connected to the SOURCE pins.
is adequate for most designs.
Bypass Capacitors
Output Capacitor The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must
Low ESR aluminum electrolytic capacitors are suitable for use with be located directly adjacent to the PRIMARY BYPASS-SOURCE and
most high frequency flyback switching power supplies though the use SECONDARY BYPASS-SECONDARY GROUND pins respectively and
of aluminum-polymer solid capacitors have gained considerable connections to these capacitors should be routed with short traces.
popularity due to their compact size, stable temperature characteris-
tics, extremely low ESR and simultaneously high RMS ripple current Primary Loop Area
rating. These capacitors enable design of compact chargers and The area of the primary loop that connects the input filter capacitor,
adapters. transformer primary and InnoSwitch-CH IC should be kept as small as
possible.
Typically, 200 mF to 300 mF of aluminum-polymer capacitance is often
adequate for every ampere of output current. The other factor that Primary Clamp Circuit
influences choice of the capacitance is the output ripple. Care should A clamp is used to limit peak voltage on the DRAIN pin at turn-off.
be taken to ensure that capacitors with a voltage rating higher than This can be achieved by using an RCD clamp or a Zener diode (~200 V)
the highest output voltage with sufficient margin (>20%) be used. and diode clamp across the primary winding. To reduce EMI, minimize
the loop from the clamp components to the transformer and
Output Voltage Feedback Circuit InnoSwitch-CH IC.
The nominal output voltage feedback pin voltage is 1.265 V [VFB].
A voltage divider network should be connected at the output of the Thermal Considerations
power supply to divide the output voltage such that the voltage at the The SOURCE pin is internally connected to the IC lead frame and
FEEDBACK pin will be 1.265 V when the output voltage is at the set provides the main path to remove heat from the device. Therefore
nominal voltage. The lower feedback divider resistor should be tied the SOURCE pin should be connected to a copper area underneath
to the SECONDARY GROUND pin. A 300 pF or higher decoupling the InnoSwitch-CH IC to act not only as a single point ground, but
capacitor should be connected at the FEEDBACK pin to the SECOND- also as a heat sink. As this area is connected to the quiet source
ARY GROUND pin of the InnoSwitch-CH IC. This capacitor should be node, this area should be maximized for good heat sinking. Similarly
placed physically close to the InnoSwitch-CH IC. An R-C network for output SR MOSFET, maximize the PCB area connected to the pins
may also need to be connected across the upper divider resistor in on the package through which heat is dissipated in the SR MOSFET.
the feedback divider network. Capacitor value should be chosen such
Sufficient copper area should be provided on the board to keep the
that the time constant matches with lower feedback divider to
InnoSwitch-CH IC temperature safely below the absolute maximum
achieve better load regulation and lower output ripple. Recommended
limits. It is recommended that the copper area provided for the
value for R is 1 kΩ in order to limit the current flowing through the
copper plane on which the SOURCE pin of the InnoSwitch-CH IC is
FEEDBACK pin in case of a short-circuit at the output.
soldered is sufficiently large to keep the IC temperature below 85 °C
Protection Diode for Secondary Current Shunt when operating the charger at full rated load and at the lowest rated
The InnoSwitch-CH IC includes a secondary-side current sense input AC supply voltage. Further de-rating can be applied depending
function which enables a precise CC mode of operation. The power on any additional specific requirements.
supply transitions from CV to CC mode automatically when the output
Y Capacitor
current exceeds the constant current regulation threshold as specified
The placement of the Y capacitor should be directly from the primary
in the data sheet.
input filter capacitor positive terminal to the output positive or return
To sense the output the load current flows from the ISENSE pin terminal of the transformer secondary. Such a placement will route
through an internal shunt to the SECONDARY GROUND pin of the IC. high magnitude common mode surge currents away from the
The transition to CC operation occurs when the shunt voltage InnoSwitch-CH IC. Note – if an input π (C, L, C) EMI filter is used
exceeds ~33 mV, the very low sensing voltage ensures very low then the inductor in the filter should be placed between the negative
dissipation. terminals of the input filter capacitors.

During an output short-circuit the output filter capacitor (C10 in Output SR MOSFET
Figure 1) discharges instantaneously through the internal shunt. For best performance, the area of the loop connecting the secondary
Depending on the output voltage, value of the output capacitance winding, the output SR MOSFET and the output filter capacitor,
and short circuit impedance the energy dissipated in the shunt can should be minimized. In addition, sufficient copper area should be
be very high. provided at the terminals of the SR MOSFET for heat sinking.

To prevent any damage to the IC, an external 1 A Schottky diode ESD

between the ISENSE and the SECONDARY GROUND pins is recom- Sufficient clearance should be maintained (>8 mm) between the
mended for designs with an output voltage above 5 V, where the primary-side and secondary-side circuits to enable easy compliance
power supply can be shorted at the output terminals. When this with any ESD / hi-pot requirements.
diode is used, the anode should be connected to the ISENSE pin and
the cathode should be connected to the SECONDARY GROUND pin.

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 InnoSwitch-CH

The spark gap is best placed between output positive rail and one Shield windings can also be used in conjunction with common
of the AC inputs directly. In this configuration a 5 mm spark gap is mode filter inductors at input to achieve improved conducted and
often sufficient to meet the creepage and clearance requirements of radiated EMI margins.
many applicable safety standards. This is less than the primary to 5. Values of components of the RC snubber connected across the
secondary spacing because the voltage across spark gap does not output SR MOSFET can help reduce high frequency radiated and
exceed the peak of the AC input. conducted EMI.
6. A π filter comprising of differential inductors and capacitors can
Drain Node be used in the input rectifier circuit to reduce low frequency
The drain switching node is the dominant noise generator. As such differential EMI.
the components connected the drain node should be placed close to 7. A 1 µF ceramic capacitor when connected at the output of the
the IC and away from sensitive feedback circuits. The clamp circuit power supply helps to reduce radiated EMI.
components should be located physically away from the PRIMARY
BYPASS pin and associated circuit and trace lengths in this circuit Recommendations for Audible Noise Suppression
should be minimized.
The state machine used in the InnoSwitch-CH IC automatically
The loop area of the loop comprising of the input rectifier filter adjusts the current limit so as to adjust the operating frequency at
capacitor, the primary winding and the InnoSwitch-CH IC primary-side light load. This helps to eliminate audible noise that typically results
MOSFET should be kept as small as possible. from intermittent switching of the power supply at very light loads.

Figure 14 shows a design example for an InnoSwitch-CH IC based In case of audible noise from a power supply, following should be
charger design. Considerations provided in this design are marked in considered as guidelines for audible noise reduction:
the figure and are listed below:
1. Ensure that the flyback transformers are dip varnished.
Recommendations for EMI Reduction 2. Often the source of audible noise are ceramic capacitors. Check
both the bias winding and primary-side clamp capacitors. To find
1. Appropriate component placement and small loop areas of the the source substitute the clamp capacitor with a metalized film
primary and secondary power circuits help minimize radiated and type and the bias with an electrolytic type. By far the most
conducted EMI. Care should be taken to achieve a compact loop common source is the bias capacitor.
area for these loops. 3. If the noise is generated by the bias winding filter capacitor,
2. A small capacitor in parallel to the clamp diode on the primary generally, use of a capacitor of higher voltage rating will typically
side can help reduced radiated EMI. resolve the issue. If the circuit board layout and any physical
3. A resistor in series with the bias winding helps reduce radiated EMI. enclosure size constraints, allow, an electrolytic capacitor should
4. Common mode chokes are typically required at the input of the be used instead.
charger to sufficiently attenuate common mode noise. The same
can be achieved by using shield windings on the transformer.

Maximize source area

for good heat sinking Slot under InnoSwitch-CH
via to pass heat to to maintain hi-pot
copper layout on pass if part fails
Place forward Place BPP and BPS Keep drain and other side of board (board contamination)
and feedback Maximize drain
capacitors near the IC clamp loop short area of SR FET for
sense resistors
near the IC good heat sinking
8 mm

Keep SR FET 5.5 mm spark gap [6.4 mm for

and output capacitor 5000 m altitude compliant design] Place slots between primary and
traces short secondary components for ESD
Optional Y capacitor connection to the plus immunization – no arcing to
Bulk rail on the primary-side for surge protection InnoSwitch-CH pins

PI-7428-102615

Figure 20. PCB Layout Guidelines. Bottom (Left Side), Top (Right Side).

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 InnoSwitch-CH

4. Reducing the AC flux density (∆B) of the transformer will also lead
IR
to reduction in audible noise from the core. KP ≡ KRP =
5. If the secondary-winding is terminated with flying leads verify if IP
the wires as vibrating against the bobbin or each other.
6. If the circuit board shows any signs of pulse bunching (multiple
switching cycles followed by no switching activity), this could be IR
a cause of audible noise. Pulse bunching can be caused by Primary IP
incorrect circuit board layout in which the feedback node is being
affected by switching noise. Guidelines provided for FEEDBACK
pin decoupling and the phase lead RC network described in this (a) Continuous, KP < 1
note can be evaluated. Verify the board layout recommendations
associated with feedback divider network have been followed.

Recommendations for Transformer Design

IR IP
Transformer design must ensure that the power supply is able to Primary
deliver the rated power at the lowest operating voltage. The lowest
voltage on the rectified DC bus of the power supply depends on the
capacitance of the filter capacitor used. At least 2 mF / W is recom- (b) Borderline Continuous/Discontinuous, KP = 1
mended to keep the DC bus voltage always above 70 V though 3 mF/W
provides sufficient margin. The ripple on the DC bus should be PI-2587-103114
measured and care should be taken to verify this voltage to confirm
the design calculations for transformer primary-winding inductance Figure 21. Continuous Mode Current Waveform, KP ≤1.
selection.

Reflected Output Voltage, VOR (V) charger designs are often thermally challenged due to the small
This parameter is the secondary-winding voltage during the diode/SR enclosure requirement.
conduction time reflected back to the primary through the turns ratio
Safety Margin, M (mm)
of the transformer. A VOR of 60 V is ideal for most 5 V only designs.
For designs that require safety isolation between primary and
For design optimization purposes, the following should be kept in mind:
secondary but are not using triple insulated wire the width of the
1. Higher VOR allows increased power delivery at VMIN, which safety margin to be used on each side of the bobbin should be
minimizes the value of the input capacitor and maximizes power entered here. Typically for universal input designs a total margin of
delivery from a given InnoSwitch-CH device. 6.2 mm would be required, and a value of 3.1 mm would be entered
2. Higher VOR reduces the voltage stress on the output diodes and into the spreadsheet. For vertical bobbins the margin may not be
SR MOSFTs. symmetrical, however if a total margin of 6.2 mm were required then
3. Higher VOR increases leakage inductance that reduces efficiency 3.1 mm would still be entered even if the physical margin were only
of the power supply. on one side of the bobbin.
4. Higher VOR increases peak and RMS current on the secondary-side
For designs using triple insulated wire it may still be necessary to use
which may increase secondary-side copper and diode losses.
a small margin in order to meet the required safety creepage
Ripple to Peak Current Ratio, KP distances. Typically many bobbins exist for each core size and each
Below a value of 1, indicating continuous conduction mode, KP is the will have different mechanical spacing. Refer to the bobbin data
ratio of ripple to peak primary current (Figure 21) sheet or seek guidance from your safety expert or transformer
vendor to determine what specific margin is required.
I
K P / K RP = I R As the margin reduces the available area for the windings, margin
P
construction may not be suitable for small core sizes. It is recom-
Following a value of 1, indicating discontinuous conduction mode, KP
mended that for compact charger designs using an InnoSwitch-CH
is the ratio of primary MOSFET off time to the secondary diode
IC, triple insulated wire should be used for secondary which then
conduction time.
^1 - D h # T
eliminates need for margins.
K P / K DP = t Primary Layers, L
VOR # ^1 - D MAX h Primary layers should be in the range of 1 < L < 3 and in general it
^ V MIN - V DS h # D MAX
= should be the lowest number that meets the primary current density
limit (CMA). Values of ≥200 Cmils/Amp can be used as a starting
value for most designs though higher values may be required based
It is recommended that a K P close to 0.9 at the minimum DC bus
on thermal design constraints. Values above 3 layers are possible but
voltage of 70 V should be used for most InnoSwitch-CH designs.
the increased leakage inductance and physical fit of the windings
A KP value of <1 results in higher transformer efficiency by lowering should be considered. A split primary construction may be helpful for
the primary RMS current but results in higher switching losses in the designs where leakage inductance clamp dissipation is too high.
primary-side MOSFET resulting in higher InnoSwitch-CH temperature. In split primary construction, half of the primary winding is placed on
either side of the secondary (and bias) winding in a sandwich
Core Type arrangement. This arrangement is often disadvantageous for low
Choice of suitable core is dependent on the physical design power charger designs as this typically requires additional common
constraints of the enclosure to be used for the charger. It is mode filtering which increases cost.
recommended that cores with low loss should only be used as

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 InnoSwitch-CH

(1-D) × T
KP ≡ KDP =
t

T = 1/fS

Primary
D×T (1-D) × T

Secondary
(a) Discontinuous, KP > 1

T = 1/fS

Primary
D×T (1-D) × T = t

Secondary

(b) Borderline Discontinuous/Continuous, KP = 1

PI-2578-103114

Figure 22. Discontinuous Mode Current Waveform, KP ≥1.

Maximum Operating Flux Density, BM (Gauss) The following minimum set of tests is strongly recommended:
A maximum value of 3000 Gauss during normal operation is recom- 1. Maximum drain voltage – Verify that VDS does not exceed 600 V
mended to limit the maximum flux density under start-up and output at highest input voltage and peak (overload) output power. The
short-circuit. Under these conditions the output voltage is low and 50 V margin to the 650 V BVDSS specification gives margin for
little reset of the transformer occurs during the MOSFET off-time. design variation.
This allows the transformer flux density to staircase above the normal 2. Maximum drain current – At maximum ambient temperature,
operating level. A value of 3000 Gauss at the peak current limit of maximum input voltage and peak output (overload) power, verify
the selected device together with the built-in protection features of drain current waveforms for any signs of transformer saturation
InnoSwitch-CH IC provides sufficient margin to prevent core and excessive leading edge current spikes at start-up. Repeat
saturation under start-up or output short-circuit conditions. under steady-state conditions and verify that the leading edge
Transformer Primary Inductance, (LP) current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN).
Once the lowest operating voltage and the required VOR are deter- Under all conditions, the maximum drain current should be below
mined, transformer primary inductance can be calculated. Care the specified absolute maximum ratings.
should be taken to ensure that the selected inductance value does 3. Thermal Check – At specified maximum output power, minimum
not violate the maximum duty cycle specification in the data sheet of input voltage and maximum ambient temperature, verify that the
the InnoSwitch-CH IC. The PIXls design spreadsheet which is part of temperature specifications are not exceeded for InnoSwitch-CH
the free PI Expert suite can be used to assist in designing the IC, transformer, output SR MOSFET, and output capacitors.
transformer. Enough thermal margin should be allowed for part-to-part
variation of the RDS(ON) of InnoSwitch-CH IC as specified in the
Quick Design Checklist data sheet.
As with any power supply design, all InnoSwitch-CH designs should Under low-line, maximum power, a maximum InnoSwitch-CH SOURCE
be verified on the bench to make sure that component specifications pin temperature of 110 °C is recommended to allow for these variations.
are not exceeded under worst-case conditions.

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 InnoSwitch-CH

Absolute Maximum Ratings1,2

DRAIN Pin Voltage..................................................... -0.3 V to 650 V Notes:
DRAIN Pin Peak Current3 INN20x3.............................1200 (2250) mA 1. All voltages referenced to Source and Secondary Ground,
INN20x4.............................1360 (2550) mA TA = 25 °C.
INN20x5............................. 1680 (3150) mA 2. Maximum ratings specified may be applied one at a time without
PRIMARY BYPASS/SECONDARY BYPASS Pin Voltage.........-0.3 V to 9 V causing permanent damage to the product. Exposure to Absolute
PRIMARY BYPASS/SECONDARY BYPASS Pin Current................ 100 mA Maximum Ratings conditions for extended periods of time may
FORWARD Pin Voltage.............................................. -1.5 V to 1507 V affect product reliability.
FEEDBACK Pin Voltage......................................................-0.3 to 9 V 3. Higher peak Drain current is allowed while the Drain voltage is
SR Pin Voltage.................................................................-0.3 to 9 V6 simultaneously less than 400 V.
OUTPUT VOLTAGE Pin Voltage........................................-0.3 to 158 V 4. Normally limited by internal circuitry.
Storage Temperature....................................................-65 to 150 °C 5. 1/16” from case for 5 seconds.
Operating Junction Temperature4................................. -40 to 150 °C 6. -1.8 V for a duration of ≤500 nsec. See Figure 28.
Ambient Temperature...................................................-40 to 105 °C 7. The maximum current out of the FORWARD pin when the
Lead Temperature5.................................................................260 °C FORWARD pin is below Ground is -40 mA.
8. Maximum current into VOUT pin at 15 V should not exceed 10 mA.

Thermal Resistance
Thermal Resistance: eSOP-R16B Package: Notes:
(qJA)...........................................65 °C/W2, 69 °C/W1 1. Solder to 0.36 sq. in (232 mm2), 2 oz. (610 g/m2) copper clad.
(qJC)........................................................ 12 °C/W3 2. Solder to 1 sq. in (645 mm2), 2 oz. (610 g/m2) copper clad.
3. The case temperature is measured at the plastic surface at the top
of the package.

Parameter Conditions Rating Units

Ratings for UL1577 (Adapter power rating is derated power capability)

Primary-Side
Current from pin (3-6) to pin 1 1.5 A
Current Rating

Primary-Side TAMB = 25 °C
1.35 W
Power Rating (Device mounted in socket resulting in TCASE = 120 °C)

Secondary-Side
Current from pin 16 to pin 15 2.5 A
Current Rating

Secondary-Side TAMB = 25 °C
0.125 W
Power Rating (Device mounted in socket)

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJI = -40 °C to +125 °C
(Note C) (Unless Otherwise Specified)
Control Functions

Output Frequency Average 93 100 107

Applies to Both Primary
fOSC TJ = 25 °C kHz
and Secondary
Controllers Peak-to-Peak Jitter 6

Maximum Duty Cycle DCMAX TJ = 0 °C to 125 °C 60 %

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Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Control Functions (cont.)

TJ = 25 °C, VBPP + 0.1 V

IS1 (MOSFET not Switching) 250
See Note B
PRIMARY BYPASS Pin
INN20x3 635 750 mA
Supply Current
TJ = 25 °C, VBPP + 0.1 V
IS2 (MOSFET Switching at fOSC) INN20x4 790 900
See Note A, C
INN20x5 970 1100

TJ = 25 °C, VBP = 0 V
ICH1 -5.4 -4.5 -3.6
See Notes D, E
PRIMARY BYPASS Pin
mA
Charge Current
TJ = 25 °C, VBP = 4 V
ICH2 -3.8 -2.9 -2.0
See Notes D, E

PRIMARY BYPASS Pin

VBPP See Note D 5.73 5.95 6.15 V
Voltage

PRIMARY BYPASS Pin

VBPP(H) 0.48 0.56 0.65 V
Voltage Hysteresis

PRIMARY BYPASS Shunt

VSHUNT IBPP = 2 mA 6.15 6.45 6.75 V
Voltage

Circuit Protection

di/dt = 138 mA/ms

INN20x3 611 650 689
TJ = 25 °C

Standard Current Limit

ILIMIT di/dt = 168 mA/ms
(BPP) Capacitor = 0.1 mF INN20x4 705 750 795 mA
See Note E TJ = 25 °C

di/dt = 213 mA/ms

INN20x5 893 950 1007
TJ = 25 °C

di/dt = 138 mA/ms

INN20x3 500 550 600
TJ = 25 °C

Reduced Current Limit ILIMIT-1 di/dt = 168 mA/ms

INN20x4 591 650 709 mA
(BPP) Capacitor = 10 mF See Note E TJ = 25 °C

di/dt = 213 mA/ms

INN20x5 773 850 927
TJ = 25 °C

di/dt = 138 mA/ms

INN20x3 682 750 818
TJ = 25 °C

Increased Current Limit ILIMIT+1 di/dt = 168 mA/ms

INN20x4 773 850 927 mA
(BPP) Capacitor = 1 mF See Note E TJ = 25 °C

di/dt = 213 mA/ms

INN20x5 955 1050 1145
TJ = 25 °C

Standard Current Limit, 0.87 × 1.15 ×

Power Coefficient I2 f I2f = ILIMIT(TYP)2 × fOSC(TYP) INN20x3-20x5 I2 f A2Hz
I2f I2 f
See Note A

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 InnoSwitch-CH

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Circuit Protection (cont.)

Reduced Current Limit,

0.84 × 1.18 ×
I2f = ILIMITred(TYP)2 × fOSC(TYP) INN20x3-20x5 I2 f
I2f I2 f
See Note A
Power Coefficient I2f A2Hz
Increased Current Limit,
0.84 × 1.18 ×
I2f = ILIMITinc(TYP)2 × fOSC(TYP) INN20x3-20x5 I2 f
I2f I2 f
See Note A

TJ = 25 °C 0.75 ×
Initial Current Limit IINIT mA
See Note A ILIMIT(TYP)

Leading Edge TJ = 25 °C
tLEB 170 250 ns
Blanking Time See Note A

TJ = 25 °C
Current Limit Delay tILD 170 ns
See Note A, F

Thermal Shutdown TSD See Note A 135 142 150 °C

Thermal Shutdown
TSD(H) See Note A 75 °C
Hysteresis

PRIMARY BYPASS Pin

Shutdown Threshold ISD 5.6 7.6 9.6 mA
Current

Primary Bypass
Power-Up Reset VBPP(RESET) TJ = 25 °C 2.8 3.0 3.3 V
Threshold Voltage

Auto-Restart On-Time TJ = 25 °C
t AR 64 77 90 ms
at fOSC See Note G

Auto-Restart Trigger TJ = 25 °C
t AR(SK) 1 s
Skip Time See Note A, G

Auto-Restart Off-Time TJ = 25 °C
t AR(OFF) 2 s
at fOSC See Note G

Short Auto-Restart TJ = 25 °C
t AR(OFF)SH 0.5 s
Off-Time at fOSC See Note A, G

Output
TJ = 25 °C 3.50 4.10
INN20x3
ID = 750 mA TJ = 100 °C
5.50 6.30
See Note A

TJ = 25 °C 2.30 2.70
INN20x4
ON-State Resistance RDS(ON) W
ID = 850 mA TJ = 100 °C
3.60 4.20
See Note A

TJ = 25 °C 1.70 2.00
INN20x5
ID = 1050 mA TJ = 100 °C
2.70 3.10
See Note A

OFF-State Drain VBPP = 6.2 V, VDS = 520 V, TJ = 125 °C

IDSS1 200 mA
Leakage Current See Note H

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 InnoSwitch-CH

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Output (cont.)

OFF-State Drain VBPP = 6.2 V, VDS = 325 V, TJ = 25 °C

IDSS2 15 mA
Leakage Current See Notes A, H

VBPP = 6.2 V
Breakdown Voltage BVDSS TJ = 25 °C 650 V
See Note I

Drain Supply Voltage 50 V

Secondary
FEEDBACK Pin Voltage VFB TJ = 25 °C 1.250 1.265 1.280 V

OUTPUT VOLTAGE Pin

VOUT(AR) See Note K 3.00 3.25 3.50 V
Auto-Restart Threshold

INN202x 1.05 1.06 1.07

Cable Drop
φCD TJ = 25 °C
Compensation Factor INN200x – 1.00 –

SECONDARY BYPASS
Pin Current at ISNL TJ = 25 °C 265 315 mA
No-Load

SECONDARY BYPASS
VBPS 4.25 4.45 4.65 V
Pin Voltage

SECONDARY BYPASS
Pin Undervoltage VBPS(UVLO) 3.45 3.8 4.15 V
Threshold

SECONDARY BYPASS
Pin Undervoltage VBPS(HYS) 0.10 0.65 1.2 V
Hysteresis

Output (IS Pin) Current

ISV(TH) TJ = 25 °C 33 mV
Limit Voltage Threshold

Constant Current
ICC TJ = 0 °C to 100 °C 2.0 2.2 2.4 A
Regulation Threshold

Normalized Output
IO TJ = 25 °C 1.00 1.04 1.08
Current

OUTPUT VOLTAGE Pin

tVOUT(AR) 8 ms
AR Timer

FEEDBACK Pin
VFB(OFF) 0.1 0.14 V
Short-Circuit

Synchronous Rectifier

SYNCHRONOUS
RECTIFIER Pin VSR(TH) TJ = 25 °C -19 -24 -29 mV
Threshold

SYNCHRONOUS
TJ = 25 °C
RECTIFIER Pin ISR(PU) 125 162 200 mA
CLOAD = 2 nF, fS = 100 kHz
Pull-Up Current

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 InnoSwitch-CH

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Synchronous Rectifier1 (cont.)

SYNCHRONOUS
TJ = 25 °C
RECTIFIER Pin ISR(PD) 230 280 315 mA
CLOAD = 2 nF, fS = 100 kHz
Pull-Down Current

SYNCHRONOUS
RECTIFIER Pin VSR See Note A 4.2 4.4 4.6 V
Drive Voltage

TJ = 25 °C 0-100% 71
Rise Time tR CLOAD = 2 nF ns
See Note A 10-90% 40

TJ = 25 °C 0-100% 32
Fall Time tF CLOAD = 2 nF ns
See Note A 10-90% 15

TJ = 25 °C
Output Pull-Up VSPS = 4.4 V
RPU 11.5 W
Resistance ISR = 10 mA
See Note A

TJ = 25 °C
Output Pull-Down VSPS = 4.4 V
RPD 3.5 W
Resistance ISR = 10 mA
See Note A
Notes:
NOTES:
A. This parameter is derived from characterization.
B. IS1 is an estimate of device current consumption at no-load, since the operating frequency is so low under these conditions. Total device
consumption at no-load is sum of IS1 and IDSS2 (this does not include secondary losses)
C. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the Drain. An alternative is to
measure the PRIMARY BYPASS pin current at 6.2 V.
D. The PRIMARY BYPASS pin is not intended for sourcing supply current to external circuitry.
E. To ensure correct current limit it is recommended that nominal 0.1 mF/1 mF/10 mF capacitors are used. In addition, the BPP capacitor value
tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and
maximum capacitor values are guaranteed by characterization.

Nominal PRIMARY Tolerance Relative to Nominal

BYPASS Pin Capacitor Capacitor Value
Value
Minimum Maximum
0.1 mF -60% +100%
1 mF -50% +100%
10 mF -50% N/A

F. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT specification.
G. Auto-restart on-time has same temperature characteristics as the oscillator (inversely proportional to frequency).
H. IDSS1 is the worst-case OFF-state leakage specification at 80% of BVDSS and the maximum operating junction temperature. IDSS2 is a typical
specification under worst-case application conditions (rectified 230 VAC) for no-load consumption calculations.
I. Breakdown voltage may be checked against minimum BVDSS specification by ramping Drain voltage up to but not exceeding minimum BVDSS.
J. For reference only. This is the total range of current limit threshold which corrects for variations in the current sense bond wire. Both of
which are trimmed to set the normalized output constant current.
K. Measured at the VOUT pin of the device. At the end of the cable under load, the apparent auto-restart threshold will be lower.

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 InnoSwitch-CH

Typical Performance Characteristics

1.1 1.4

PI-7413-112414
PI-2213-101614
1.2

Normalized Current Limit

(Normalized to 25 °C)
Breakdown Voltage

1.0

0.8
1.0 Normalized
di/dt = 1
0.6
Scaling Factors: Note: For the
INN20x3 1.22 normalized current
0.4 limit value, use the
INN20x4 1.12 typical current limit
INN20x5 1.10 specified for the
0.2 appropriate BP/M
capacitor.

0.9 0
-50 -25 0 25 50 75 100 125 150 1 2 3 4
Junction Temperature (°C) Normalized di/dt
Figure 23. Breakdown vs. Temperature. Figure 24. Standard Current Limit Vs. di/dt.

300 1000

PI-7411-101614
PI-7414-101614

Scaling Factors: Scaling Factors:

INN20x3 7.9 INN20x3 7.9
250 INN20x4 11.2 Drain Capacitance (pF) INN20x4 11.2
Drain Current (mA)

INN20x5 16.0 INN20x5 16.0

200 100

150

100 10

TCASE=25 °C
50 TCASE=100 °C

0 1
0 2 4 6 8 10 1 100 200 300 400 500 600
DRAIN Voltage (V) Drain Voltage (V)

Figure 25. Output Characteristic. Figure 26. COSS vs. Drain Voltage.

VSR(t)
SYNCHRONOUS RECTIFIER DRIVE

40
PI-7412-102814

PI-7474-011215

Scaling Factors:
INN20x3 7.9 -0.0
INN20x4 11.2
Pin Voltage Limits (V)

30 INN20x5 16.0 -0.3

Power (mW)

20

10

0 -1.8
0 100 200 300 400 500 600 500 ns
Drain Voltage (V) Time (ns)
Figure 27. Drain Capacitance Power. Figure 28. SYNCHRONOUS RECTIFIER DRIVE Pin Negative Voltage.

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 eSOP-R16B

22
Rev. K 06/20
2X 0.004 [0.10] C A
3 4 0.057 [1.45] Ref.
0.023 [0.58] 13X
0.050 [1.27]
0.018 [0.46] 2
0.010 [0.25] M C A B A 0.400 [10.16]
H
8 Lead Tips
16 9 0.006 [0.15] C 9 10 11 12 13 14 15 16
2X 0.010 [0.25]
0.004 [0.10] C B
Gauge Plane
InnoSwitch-CH

Seating Plane
0.059 [1.50] 0° - 8° C
2 Ref. Typ. 0.040 [1.02]
0.350 [8.89] 0.464 [11.79] 0.028 [0.71]
0.059 [1.50]
Ref. Typ.
DETAIL A

B 0.020 [0.51]
1 8 0.006 [0.15] C 8 7 6 5 4 3 1
Ref. 0.022 [0.56] Ref.
4 Lead Tips 0.010 [0.24]
3 4 0.019 [0.48]
Ref.
Pin #1 I.D. 0.158 [4.01] Ref.
(Laser Marked) 0.045 [1.14] Ref. 0.152 [3.86]
0.080 [2.03] Ref.
0.032 [0.81]
0.028 [0.71] 0.029 [0.74]
Ref.
TOP VIEW BOTTOM VIEW

0.010 [0.25] Ref.

0.356 [9.04]Ref. Detail A

0.306 [7.77] Ref.
0.049 [1.23] 0.71 1.27
7
0.105 [2.67] [.028] [.050]
0.046 [1.16]
0.093 [2.36] 3
0.016 [0.41]
0.011 [0.28]
12X
Seating 1.78
C
Plane [.070] 11.68
0.012 [0.30] 0.092 [2.34] [.460]
0.004 [0.10] 0.086 [2.18]
0.004 [0.10] C
Seating Plane to 12 Leads
Molded Bumps Reference
Standoff Solder Pad
Dimensions
SIDE VIEW END VIEW 4.11
[.162]
Notes: 4.19
1. Dimensioning and tolerancing per ASME Y14.5M-1994. [.165]
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold 7.62
flash, tie bar burrs, gate burrs, and inter-lead flash, but including any mismatch between the top [.300]
and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 8.89 mm [INCH]
[.350]
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches [mm].
6. Datums A and B to be determined in Datum H.
7. Exposed metal at the plastic package body outline/surface between leads 6 and 7, connected PI-6995-010615
internally to wide lead 3/4/5/6. POD-eSOP-R16B Rev B

www.power.com
 InnoSwitch-CH

PACKAGE MARKING

eSOP-R16B

INN2005K C
A 1530 B
M4N343-1 D

A. Power Integrations Registered Trademark

B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code

PI-7765-102715

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 InnoSwitch-CH

Part Ordering Table

Product Cable Compensation

INN2003 0%
INN2023 6%

INN2004 0%
INN2024 6%

INN2005 0%
INN2025 6%

MSL Table

Part Number MSL Rating

INN2003
3
INN2023

INN2004
3
INN2024

INN2005
3
INN2025

ESD and Latch-Up Table

Test Conditions Results

Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 V (max) on all pins

Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins

Machine Model ESD JESD22-A115C > ±200 V on all pins

Part Ordering Information

• InnoSwitch-CH Product Family
• 20x Series Number
• Package Identifier
K eSOP-R16B
• Tape & Reel and Other Options
INN 2023 K - TL TL Tape & Reel, 1000 pcs min/mult.

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 InnoSwitch-CH

Revision Notes Date

A Initial Release. 11/14
Added Note 4 to Table 1, updated Auto-Restart section, added VFB(OFF) to Parameter Table, new Figure 23, added Part
B 01/15
Ordering Table and added Notes 6 and 7 to Absolute Maximum Ratings table.
Corrected secondary auto-restart from relative specification on the FEEDBACK pin to absolute threshold on the VOUT
C pin, that was incorrectly documented in previous revision. Updated ISR(PD), ISR(PU) and VBPP limits based on high volume 05/15
production data.
D Added extra information related to Cable Drop Compensation (CDC) function on page 5. 07/15
Updated in line with UL Report E358471. Increased Storage, Operating Junction, and Ambient Temperatures and
E Secondary-Side Current Rating Parameters. Previous Note 7 in Abs Max Ratings Table is no longer required and 08/15
deleted. Updated Figure 5, page 1 and RDS(ON) Condition parameter.
Corrected Bottom (Left side) of PCB layout in Figure 20, SOURCE (S) Pin description on page 3, added ESD table and
F 11/15
eSOP-R16B Package Marking.
G Modified page 1 sub-header text. 11/18/15
H Corrected OUTPUT VOLTAGE Pin Auto-Restart Threshold section. Improved VOUT(AR) limits tolerance, 3.5 V Max. 12/04/15
I Added Pin 8 and Pin 9 information under Pin Functional Description on page 3. 04/17
Corrected error in Figure 4. Updated text and added 4 new waveform schematics in Bias Winding and External Bias
J 10/17
Circuit section. Added 1 new figure in Applications Example section.
K Updated safety information on page 1. 06/20

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For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS,
HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert,
PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of
their respective companies. ©2020, Power Integrations, Inc.

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