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10 RAM Horizontal Expansion

The document discusses expanding the word size of a RAM from 4 bits to 8 bits using two 7489 ICs. It describes the connectivity between the address lines, data lines and output lines of the ICs to realize an 8-bit word from two 4-bit ICs. Write and read operations are also demonstrated in a table.

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176 views6 pages

10 RAM Horizontal Expansion

The document discusses expanding the word size of a RAM from 4 bits to 8 bits using two 7489 ICs. It describes the connectivity between the address lines, data lines and output lines of the ICs to realize an 8-bit word from two 4-bit ICs. Write and read operations are also demonstrated in a table.

Uploaded by

rpchatterjee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Dr.

Suman Bhowmik

RAM Horizontal Expansion


(word size expansion)
Problem
4 bit
●
Design a 16x8 = 128 bit memory 8 bit
0 0 1 0 1111 = F 0 0 0 0 0 0 1 0 1111 = F
– Word size = 8 bits 1110 = E 1110 = E
1101 = D 1101 = D
– Memory size = 16 words 1100 = C 1100 = C
1011 = B 1011 = B
– Address size = 4 bits 1010 = A
0 0 1 0 1001 = 9
1010 = A
1 1 0 1 0 0 1 0 1001 = 9
●
IC 7489  16x4 = 64 bit RAM ? 1000 = 8
0111 = 7
1000 = 8
0111 = 7
0110 = 6 0110 = 6
– Word size = 4 bits 0101 = 5 0101 = 5
0100 = 4 0100 = 4
– Memory size = 16 words 0011 = 3 0011 = 3
0010 = 2 0010 = 2
– Address size = 4 bits 1 0 0 1 0001 = 1 0 0 1 0 1 0 0 1 0001 = 1
0000 = 0 0000 = 0
●
Increase word size to 8 bit 7489 view of memory Design view of memory
Design
●
Require 7489 IC = 8/4 = 2
●
Combine 2 ICs – horizontal expansion
●
Address size = 4 bits
●
Connection strategy
– Apply 4 address lines to each IC
WE
ME
– Apply upper nibble of data to RAM2
– Apply lower nibble of data to RAM1
– Output lines of RAM2 form upper nibble of output
– Output lines of RAM1 form lower nibble of output
– ME of each IC are tied together to form final ME
– WE of each IC are tied together to form final WE
Vcc
A0 1 16
A1 15
A2 14
1kΩ

A3 13

D7 12
D6 11 O7
10

7489
2
D5 6 9 O6
D4 4 7 O5
O4
Circuit Diagram

5
WE 3
ME 2 8
Vcc

1 16
15
14
13

D3 12
D2 11 O3
10
7489
1

D1 6 9 O2
D0 4 7 O1
5 O0
3
2 8
Connectivity diagram
D3 D2 D1 D0 D7 D6 D5 D4

A3
A2
A1 vcc
A0
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
74891 74892 1KΩ
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

GND

ME WE

O0 O1 O2 O3 O4 O5 O6 O7
Location Data

Read Write Table 2 = 0010


7 = 0111
80 = 01010000
13 = 00001101
A = 1010 83 = 01010011
C = 1100 154= 10011010
●
First perform 4 write operations – as shown in the table
1111 = F
1110 = E
Address Input Data Input Output
1101 = D
10011010 1100 = C
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 o7 o6 o5 o4 o3 o2 o1 o0
1011 = B
01010011 1010 = A
0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 1 1 1 1001 = 9
1000 = 8
0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 0 00001101 0111 = 7
0110 = 6
1 0 1 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0101 = 5
0100 = 4
1 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 0011 = 3
01010000 0010 = 2
0001 = 1
●
Next hold the data – make ME, WE to H, H 0000 = 0
●
Last verify data – perfom read operations on the specified addresses

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