ADC Input Noise: The Good, input rms noise.

See Further Reading 6 for a detailed description

of how to calculate the value of  from the histogram data. It is
The Bad, and The Ugly­. common practice to express this rms noise in terms of LSBs
rms, corresponding to an rms voltage referenced to the ADC
Is No Noise Good Noise? full-scale input range. If the analog input range is expressed as
digital numbers, or counts, input values, such as , can be expressed
By Walt Kester [[email protected]] as a count of the number of LSBs.

Introduction P-P INPUT NOISE NUMBER OF

� 6.6 � RMS NOISE OCCURRENCES
All analog-to-digital converters (ADCs) have a certain amount of
input-referred noise—modeled as a noise source connected in series
with the input of a noise-free ADC. Input-referred noise is not
to be confused with quantization noise, which is only of interest
STANDARD DEVIATION
when an ADC is processing time-varying signals. In most cases, = RMS NOISE (LSBs)
less input noise is better; however, there are some instances where
input noise can actually be helpful in achieving higher resolution.
If this doesn’t seem to make sense right now, read on to find out
how some noise can be good noise.

Input-Referred Noise (Code-Transition Noise)

Practical ADCs deviate from ideal ADCs in many ways. Input- n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4
referred noise is certainly a departure from the ideal, and its OUTPUT CODE
effect on the overall ADC transfer function is shown in Figure 1.
Figure 2. Effect of input-referred noise on ADC grounded-
As the analog input voltage is increased, the “ideal” ADC (shown
input histogram for an ADC with a small amount of DNL.
in Figure 1a) maintains a constant output code until a transition
region is reached, at which point it instantly jumps to the next Although the inherent differential nonlinearity (DNL) of the ADC
value, remaining there until the next transition region is reached. will cause deviations from an ideal Gaussian distribution (for
A theoretically perfect ADC has zero code-transition noise, and a instance, some DNL is evident in Figure 2), it should be at least
transition region width equal to zero. A practical ADC has a approximately Gaussian. If there is significant DNL, the value
certain amount of code transition noise, and therefore a finite of  should be calculated for several different dc input voltages
transition region width. Figure 1b shows a situation where and the results averaged. If the code distribution is significantly
the width of the code transition noise is approximately one non-Gaussian, as exemplified by large and distinct peaks and
least-significant bit (LSB) peak-to-peak. valleys, for instance—this could indicate either a poorly designed
(a) IDEAL ADC (b) ACTUAL ADC ADC or—more likely—a bad PC board layout, poor grounding
techniques, or improper power supply decoupling (see Figure 3).
DIGITAL DIGITAL Another indication of trouble is when the width of the distribution
OUTPUT OUTPUT changes drastically as the dc input is swept over the ADC input
voltage range.

NUMBER OF
ANALOG ANALOG OCCURRENCES
INPUT INPUT

Figure 1. Code-transition noise (input-referred noise)

and its effect on ADC transfer function.

Internally, all ADC circuits produce a certain amount of rms noise

due to resistor noise and “kT/C” noise. This noise, present even
for dc input signals, accounts for the code-transition noise, now n–5 n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 n+5
generally referred to as input-referred noise. Input-referred noise is OUTPUT CODE

most often characterized by examining the histogram of a number Figure 3. Grounded-input histogram for poorly designed
of output samples, while the input to the ADC is held constant at a ADC and/or poor layout, grounding, or decoupling.
dc value. The output of most high speed or high resolution ADCs
is a distribution of codes, typically centered around the nominal Noise-Free (Flicker-Free) Code Resolution
value of the dc input (see Figure 2). The noise-free code resolution of an ADC is the number of bits
To measure the amount of input-referred noise, the input of the of resolution beyond which it is impossible to distinctly resolve
ADC is either grounded or connected to a heavily decoupled individual codes. This limitation is due to the effective input noise
voltage source, and a large number of output samples are (or input-referred noise) associated with all ADCs and described
collected and plotted as a histogram (referred to as a grounded- above, usually expressed as an rms quantity with the units of
input histogram if the input is nominally at zero volts). Since the LSBs rms. Multiplying by a factor of 6.6 converts the rms noise into
noise is approximately Gaussian, the standard deviation of the a useful measure of peak-to-peak noise—the actual uncertainty with
histogram, , which can be calculated, corresponds to the effective which a code can be identified—expressed in LSBs peak-to-peak.

Analog Dialogue 40-02, February (2006) http://www.analog.com/analogdialogue 

 Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1)
Peak-to-Peak Resolution in Counts (Bits)
Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = �80 mV = �40 mV = �20 mV = �10 mV
50 Hz 1.97 Hz 2048 460 ms 60 ms 230k (18) 175k (17.5) 120k (17) 80k (16.5)
100 Hz 3.95 Hz 1024 230 ms 30 ms 170k (17.5) 125k (17) 90k (16.5) 55k (16)
150 Hz 5.92 Hz 683 153 ms 20 ms 130k (17) 100k (16.5) 70k (16) 45k (15.5)
200 Hz* 7.9 Hz 512 115 ms 15 ms 120k (17) 90k (16.5) 65k (16) 40k (15.5)
400 Hz 15.8 Hz 256 57.5 ms 7.5 ms 80k (16.5) 55k (16) 40k (15.5) 30k (15)
*Power-On Default
Figure 4. Noise-free code resolution for the AD7730 sigma-delta ADC.

Since the total range (or span) of an N-bit ADC is 2N LSBs, the We can go even further and average 16 measurements per output;
total number of noise-free counts is therefore equal to: the output sampling rate is reduced to 6.25 kSPS, the SNR
increases by another 6 dB, and the number of noise-free bits
2N increases to 17. The arithmetic precision in the averaging must
Noise-free counts =
peak -to-peak input noise ( LSBs ) (1) be carried out to the larger number of significant bits in order to
gain the extra “resolution.”
The number of noise-free counts can be converted into noise-free
The averaging process also helps smooth out the DNL errors
(binary) code resolution by calculating the base-2 logarithm as
in the ADC transfer function. This can be illustrated for the
follows:
simple case where the ADC has a missing code at quantization
 2N  level k. Even though code k is missing because of the large DNL
Noise-free code resolution = log 2  (2)
 peak -to-peak input noise ( LSBs )  error, the average of the two adjacent codes, k – 1 and k + 1, is
equal to k.
The noise-free code resolution specification is generally associated
This technique can therefore be used effectively to increase
with high-resolution sigma-delta measurement ADCs. It is most
the dynamic range of the ADC at the expense of overall output
often a function of sampling rate, digital-filter bandwidth, and
sampling rate and extra digital hardware. It should also be noted
programmable-gain-amplifier (PGA) gain (hence input range).
that averaging will not correct the inherent integral nonlinearity
Figure 4 shows a typical table—taken from the data sheet of the
of the ADC.
AD7730 sigma-delta ADC1.
Note that for an output data rate of 50 Hz and an input range Now, consider the case of an ADC that has extremely low
of 610 mV, the noise-free code resolution is 16.5 bits (80,000 input-referred noise, and the histogram shows a single code
noise-free counts). The settling time under these conditions is no matter how many samples are taken. What will digital
460 ms, making this ADC an ideal candidate for a precision averaging do for this ADC? This answer is simple—it will
weigh-scale application. Data of this kind is available on most data do nothing! No matter how many samples are averaged, the
sheets for high-resolution sigma-delta ADCs suitable for precision answer will be the same. However, as soon as enough noise is
measurement applications. added to the input signal, so that there is more than one code
in the histogram, the averaging method starts working again.
The ratio of the full-scale range to the rms input noise (rather than Thus—interestingly—some small amount of noise is good (at
peak-to-peak noise) is sometimes used to calculate resolution. least with respect to the averaging method); however, the more
In this case, the term effective resolution is used. Note that under noise present at the input, the more averaging is required to
identical conditions, effective resolution is larger than noise-free code achieve the same resolution.
resolution by log2 (6.6), or approximately 2.7 bits.
Don’t Confuse Effective Number of Bits (ENOB) with Effective
 2N 
Effective resolution = log 2  (3) Resolution or Noise-Free Code Resolution
 rms input noise ( LSBs )  Because of the similarity of the terms, effective number of bits
and effective resolution are often assumed to be equal. This is
not the case.
Effective resolution = Noise-free code resolution + 2.7 bits (4)
Effective number of bits (ENOB) is derived from an FFT
Some manufacturers prefer to specify effective resolution rather analysis of the ADC output when the ADC is stimulated with
than noise-free code resolution because it results in a higher a full-scale sine-wave input signal. The root-sum-of-squares
number of bits—the user should check the data sheet closely to (RSS) value of all noise and distortion terms is computed, and
make sure which is actually specified. the ratio of the signal to the noise-and-distortion is defined as
SINAD, or S/(N+D). The theoretical SNR of a perfect N-bit
Digital Averaging Increases Resolution and Reduces Noise ADC is given by:
The effects of input-referred noise can be reduced by digital
averaging. Consider a 16-bit ADC which has 15 noise-free bits
at a sampling rate of 100 kSPS. Averaging two measurements
SNR = 6.02 N + 1.76 dB (5)
of an unchanging signal for each output sample reduces the ENOB is calculated by substituting the ADC’s computed
effective sampling rate to 50 kSPS—and increases the SNR by SINAD for SNR in Equation 5 and solving equation for N.
3 dB and the number of noise-free bits to 15.5. Averaging four
measurements per output sample reduces the sampling rate to
SINAD − 1.76 dB
25 kSPS—and increases the SNR by 6 dB and the number of ENOB = (6)
noise-free bits to 16. 6.02

 Analog Dialogue 40-02, February (2006)

The noise and distortion used to calculate SINAD and ENOB this scheme improves distortion produced by the ADC’s encoder
include not only the input-referred noise but also the quantization nonlinearity, it does not significantly improve distortion created
noise and the distortion terms. SINAD and ENOB are used to by its front end.
measure the dynamic performance of an ADC, while effective (a) (b)
resolution and noise-free code resolution are used to measure the SMALL AMPLITUDE LARGE AMPLITUDE
noise of the ADC under essentially dc input conditions, where
INPUT INPUT
quantization noise is not an issue. ADC ADC ADDER
+ � + �
+ –
Using Noise Dither to Increase an ADC’s Spurious-Free
�1/2 LSB RMS
Dynamic Range RANDOM
NUMBER
Spurious-free dynamic range (SFDR) is the ratio of the rms NOISE
GENERATOR
signal amplitude to the rms value of the peak spurious spectral GENERATOR
component. Two fundamental limitations to maximizing SFDR DAC
in a high-speed ADC are the distortion produced by the front-end
amplifier and the sample-and-hold circuit; and that produced by Figure 5. Using dither to randomize ADC transfer function.
nonlinearity in the transfer function of the encoder portion of
the ADC. The key to achieving high SFDR is to minimize both Another method, one that is easier to implement—especially
sources of nonlinearity. in wideband receivers—is to inject a narrow-band dither signal
outside the signal band of interest, as shown in Figure 6. Usually,
Nothing can be done externally to the ADC to significantly reduce
no signal components are located in the frequency range near
the inherent distortion caused by its front end. However, the
dc, so this low-frequency region is often used for such a dither
differential nonlinearity in the ADC’s encoder transfer function
signal. Another possible location for the dither signal is slightly
can be reduced by the proper use of dither (external noise that is
below f S /2. The dither signal occupies only a small bandwidth
intentionally summed with the analog input signal).
relative to the signal bandwidth (usually a bandwidth of a few
Dithering can be used to improve SFDR of an ADC under certain hundred kHz is sufficient), so no significant degradation in SNR
conditions (see Further Reading 2–5). For example, even in a occurs—as it would if the dither was broadband.
perfect ADC, some correlation exists between the quantization
fS
noise and the input signal. This correlation can reduce the SFDR
of the ADC, especially if the input signal is an exact sub-multiple
of the sampling frequency. Summing about 1/ 2 -LSB rms of INPUT
+ � ADC
broadband noise with the input signal tends to randomize the BPF +
quantization noise and minimize this effect (see Figure 5a). In
most systems, however, the noise already riding on top of the signal
OUT-OF-BAND NOISE
(including the input-referred noise of the ADC) obviates the need NOISE OUT-OF-BAND
GENERATOR FILTER NEAR DC OR fS/2
for additional dither noise. Increasing the wideband rms noise
level beyond approximately one LSB will proportionally reduce
the SNR and result in no additional improvement. Figure 6. Injecting out-of-band dither to improve ADC SFDR.

Other schemes have been developed using larger amounts of dither A subranging, pipelined ADC, such as the AD6645 14-bit,
noise to randomize the transfer function of the ADC. Figure 5b 105-MSPS ADC2 (see Figure 7), has very small differential
shows a dither-noise source comprising a pseudo-random-number nonlinearity errors that occur at specific code transition points
generator driving a DAC. This signal is subtracted from the across the ADC range. The AD6645 includes a 5-bit ADC
ADC input signal and then digitally added to the ADC output, (ADC1), followed by a 5-bit ADC2 and a 6-bit ADC3. The only
thereby causing no significant degradation SNR. An inherent significant DNL errors occur at the ADC1 transition points—the
disadvantage of this technique, however, is that the input signal second- and third-stage DNL errors are minimal. There are
swing must be reduced to prevent overdriving the ADC as the 25 = 32 decision points associated with ADC1, which occur every
amplitude of the dither signal is increased. Note that although 68.75 mV (29 = 512 LSBs) for a 2.2-V full-scale input range.

AVCC DVCC

25 = 32 ADC1 TRANSITIONS AD6645

AIN
A1 TH1 TH2 A2 TH3 TH4 TH5 ADC3
AIN

ADC1 DAC1 ADC2 DAC2

VREF 2.4V
5 5 6
ENCODE INTERNAL DIGITAL ERROR CORRECTION LOGIC
ENCODE TIMING

GND DMID OVR DRY D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

Figure 7. AD6645 14-bit, 105 MSPS ADC simplified block diagram.

Analog Dialogue 40-02, February (2006) 

Figure 8 shows a greatly exaggerated representation of these higher levels of noise. Two ADC1 transitions cover 1024 LSBs
nonlinearities. peak-to-peak, or approximately 155 (= 1024/6.6) LSBs rms.
FULL-SCALE = 2.2V p-p
The first plot shown in Figure 9 shows the undithered DNL over
25 = 32 ADC1 TRANSITIONS a small portion of the input signal range, including two of the
subranging points, which are spaced 68.75 mV (512 LSBs) apart.
The second plot shows the DNL after adding (and later filtering
OUTPUT CODE

out) 155 LSBs of rms dither. This amount of dither corresponds

to approximately –20.6 dBm. Note the dramatic improvement in
68.75mV
29 =
the DNL.
512 LSBs
Dither noise can be generated in a number of ways. For example,
noise diodes can be used, but simply amplifying the input voltage
noise of a wideband bipolar op amp provides a more economical
ANALOG INPUT solution. This approach, described in detail elsewhere (Further
Reading 3, 4, and 5) will not be discussed here.
Figure 8. AD6645 subranging point DNL errors (exaggerated).
The dramatic improvement in SFDR obtainable with out-of-band
With an analog input up to about 200 MHz, the distortion dither is shown in Figure 10, using a deep (1,048,576-point) FFT,
components produced by the front end of the AD6645 are where the AD6645 is sampling a –35-dBm, 30.5-MHz signal at
negligible compared to those produced by the encoder. That is, 80 MSPS. Note that the SFDR without dither is approximately
the static nonlinearity of the AD6645 transfer function is the chief 92 dBFS, compared to 108 dBFS with dither—a substantial
limitation to SFDR. 16-dB improvement!
The goal is to select the proper amount of out-of-band dither so The AD6645 ADC, introduced by Analog Devices in 2000, has
that the effects of these small DNL errors are randomized across until recently represented the ultimate in SFDR performance.
the ADC input range, thereby reducing the average DNL error. In the few years since its introduction, improvements in both
Experimentally, it was determined that making the peak-to-peak process technology and circuit design have resulted in even
dither noise cover about two ADC1 transitions gives the best higher performance ADCs, such as the AD9444 (14 bits at
improvement in DNL. The DNL is not significantly improved with 80 MSPS) 3 , AD9445 (14 bits at 105 MSPS/125 MSPS) 4 ,

UNDITHERED 155 LSBs RMS DITHER

1.5 1.5

512 LSBs 512 LSBs

1.0 1.0
DNL (LSBs)

DNL (LSBs)

0.5 0.5

0 0

–0.5 –0.5
OUTPUT CODE OUTPUT CODE

Figure 9. AD6645 DNL plot, without and with dither.

NO DITHER WITH DITHER

0 0
–10 SAMPLING RATE = 80MSPS –10 SAMPLING RATE = 80MSPS
INPUT = 30.5MHz @ –35dBm INPUT = 30.5MHz @ –35dBm
–20 NO DITHER –20 WITH DITHER @ –20.6dBm

–30 –30
–40 –40
SFDR = SFDR =
–50 92dBFS –50 108dBFS
dBFS

dBFS

–60 –60
DITHER SIGNAL
–70 –70
–80 –80
2
–90 –90
6
–100 4 –100 4
3 2
–110 –110
5 5 3 6
–120 –120
–130 –130
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
FREQUENCY (MHz) FREQUENCY (MHz)
1,048,576-POINT FFTs,
PROCESS GAIN = 60dB

Figure 10. FFT plots showing AD6645 SFDR, without and with the use of dither.

 Analog Dialogue 40-02, February (2006)

 NO DITHER 50mV RMS DITHER
0 0

–25 –25
SFDR = 100dBFS SFDR = 125dBFS
–50 –50

–75 –75
dBFS

dBFS
5 3 2 6 4
–100 –100

5 3 2 6 4
–125 –125

–150 –150

–175 –175

–200 –200
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
FREQUENCY (MHz) FREQUENCY (MHz)
1,048,576-POINT FFTs, AVERAGE OF 5 RUNS,
DATA GENERATED USING ADIsimADC AND AD9444 MODEL

Figure 11. AD9444, a 14-bit, 80-MSPS ADC; fS = 80 MSPS, fIN = 30.5 MHz, signal amplitude = –40 dBFS.

and the AD9446 (16 bits at 80 MSPS/100 MSPS) 5. These In certain high speed ADC applications, the addition of the
ADCs have very high SFDR (typically greater than 90 dBc proper amount of out-of-band noise dither can improve the DNL
for a 70-MHz, full-scale input signal) and low DNL. Still, the of the ADC and increase its SFDR. However, the effectiveness
addition of an appropriate out-of-band dither signal can improve of dither in improving SFDR is highly dependent upon the
the SFDR under certain input signal conditions. characteristics of the ADC being considered. b
Figure 11 models FFT plots of the AD9444, with and without ACKNOWLEDGEMENTS
dither. It can be seen that, under the given input conditions, the The author would like to thank Bonnie Baker of Microchip
addition of dither improves the SFDR by 25 dB. The data was taken Technology and Alain Guery of Analog Devices for their
using the ADIsimADC™ program6 and the AD9444 model. thoughtful inputs to this article.
Even though the results shown in Figures 10 and 11 are fairly
dramatic, it should not be assumed that the addition of out-of-band FURTHER READING
noise dither will always improve the SFDR of the ADC under all 1. Baker, Bonnie, “Sometimes, Noise Can Be Good,” EDN,
conditions. We reiterate that dither will not improve the linearity February 17, 2005, p. 26.
of the front-end circuits of the ADC. Even with a nearly ideal front 2. Brannon, Brad, “Overcoming Converter Nonlinearities with
end, the effects of dither will be highly dependent upon both the Dither,” Application Note AN-410, Analog Devices, 1995.
amplitude of the input signal and the amplitude of the dither signal 3. Jung, Walt, Op Amp Applications, Analog Devices, 2002,
itself. For example, when signals are near the full-scale input range ISBN 0-916550-26-5, p. 6.165, “A Simple Wideband Noise
of the ADC, the integral nonlinearity of the transfer function may Generator.” Also available as Op Amp Applications Handbook,
become the limiting factor in determining SFDR, and dither will Newnes, 2005, ISBN 0-7506-7844-5, p. 568.
not help. In any event, the data sheet should be studied carefully—
4. Jung, Walt, “Wideband Noise Generator,” Ideas for Design,
in some cases dithered and undithered data may be shown, along
Electronic Design, October 1, 1996.
with suggestions for the amplitude and bandwidth. Dither may
be a built-in feature of newer IF-sampling ADCs. 5. Kester, Walt, “Add Noise Dither to Blow Out ADCs’ Dynamic
Range,” Electronic Design, Analog Applications Supplement,
SUMMARY November 22, 1999, pp. 20-26.
In this discussion we have considered the input-referred noise, 6. Ruscak, Steve and Larry Singer, “Using Histogram Techniques to
common to all ADCs. In precision, low-frequency measurement Measure A/D Converter Noise,” Analog Dialogue, Vol. 29-2, 1995.
applications, effects of this noise can be reduced by digitally
averaging the ADC output data, using lower sampling rates and REFERENCES—VALID AS OF FEBRUARY 2006
1
additional hardware. While the resolution of the ADC can actually ADI website: www.analog.com (Search) AD7730 (Go)
2
be increased by this averaging process, integral-nonlinearity errors ADI website: www.analog.com (Search) AD6645 (Go)
3
are not reduced. Only a small amount of input-referred noise is ADI website: www.analog.com (Search) AD9444 (Go)
4
needed to increase the resolution by the averaging technique; ADI website: www.analog.com (Search) AD9445 (Go)
5
however, use of increased noise requires a larger number of samples ADI website: www.analog.com (Search) AD9446 (Go)
6
in the average, so a point of diminishing returns is reached. ADI website: www.analog.com/ADIsimADC

Analog Dialogue 40-02, February (2006)