Module 5

Syllabus
Fabrication techniques and MOSFET physical Design
Material Preparation
Purification and Crystal growth (CZ process), wafer preparation Thermal Oxidation-
Growth mechanisms, Dry and Wet oxidation.
Diffusion and ion implantation techniques.
Epitaxy : molecular beam epitaxy.
Lithography- Photo lithographic sequence, Electron Beam Lithography, Etching and
metal deposition techniques.
MOSFET Fabrication techniques
Twin-Tub fabrication sequence, Fabrication process flow.
Layout Design and Design rules, Stick Diagram and Design rulesmicron rules and
Lambda rules. (definitions only).layout of CMOS Inverter, two input NAND and NOR
gates.
Integrated Circuits (IC)

• Miniature, low cost electronic circuit

• Consists of thousands of diodes, transistors, resistors and/or capacitors on a single
tiny piece of semiconductor crystal called chip
• Advantages
• Low cost
• High reliability
• Miniaturization
• Increased functional performance
• High speed
• Low power consumption
• Batch Processing

Why silicon ?

• Available in abundance in nature in the form of silica and silicates

• Can be operated at higher temperatures due to wider energy band-gap

• SiO2 is stable oxide which is an essential condition in IC fabrication

• Possible to fabricate both active and passive devices on same substrate

• Inexpensive
• Easier processing

• Excellent Si-SiO2 interface

• Excellent quality of SiO2

Material Preparation

• To fabricate devices, silicon must be extremely pure and in crystalline form

without any defects

• Raw material is Metallurgical Grade Silicon (MGS)

• MGS is further treated with anhydrous hydrogen chloride for purification process

• By using chemical Vapor Deposition technique (CVD) and hydrogen reduction,

Electronic Grade Silicon (EGS) is prepared which is high purity and raw material for
the preparation of single crystal Silicon

• From EGS single crystals are grown and shaped to define the diameter of the
material and sawed into wafers.

• These wafers are polished to provide smooth and cleaned surfaces on which devices
will be made and then be interconnected to form a monolithic IC
• Steps involved in material preparation are:
1. Purification of silicon
2. Crystal growth
3. Crystal slicing
4. Wafer preparation
5. Wafer processing

1.Purification of Silicon

• Silicon is available in the forms of Silicon dioxide (silica) or silicates

• The silicon- Oxygen bond is very strong that reduction process is needed .

• The most common reduction process is called Carbothermic reduction, where

SiO2 reacts with Carbon to form Si and CO2

• MGS is obtained by reduction of quartzite ( a crystalline form of Si02 available in

the form of rock) in a carbon arc furnace.

• SiC + Si02 = Si + SiO + CO

• The process generate crude Silicon or MGS (98% pure).

 2. Crystal Growth

• To convert polycrystalline silicon to single crystalline silicon

• Crystallisation takes place if molten silicon is allowed to solidify to a seed crystal

• There are two main techniques for converting polycrystalline EGS into a single
crystal ingot, which is used to obtain the final wafers.

1. Czochralski technique (CZ) –

2. Float zone technique (FZ)–

Czochralski technique (CZ)

• Crystal growth typically involves a phase change from a solid, liquid, or gas
phase to a crystalline solid phase.
• The Czochralski (CZ) process accounts for 80% to 90% of worldwide silicon
consumption,

• Consists of dipping a small single crystal seed into molten silicon and slowly
withdrawing the seed while rotating it simultaneously.
• After the seed is dipped into the EGS melt, the crystal is pulled at a rate that
minimizes defects and yields a constant ingot diameter

• The apparatus is called a puller

• It includes
• Furnace
• Crystal pulling mechanism
• Ambient control
• Control system
• Furnace includes
• A fused silica crucible : contains the molten Silicon. The crucible is usually made
of quartz or graphite with a fused silica lining.
• Graphite susceptor: used to support the silica crucible
• Rotation mechanism: the susceptor is placed on a pedestal whose shaft is
connected to a motor that provides rotation
• Heating element and a power supply: to melt the charge RF heating or resistance
heating is used and finally is connected to a DC power supply
• Crystal pulling mechanism :
• Control the pull rate and crystal rotation
• The seed crystal is simultaneously pulled up and rotated to meet proper growth.

• Ambient control :
• This includes an inert gas source (Argon) ,a flow control and an exhaust system
• The gas source must meet the purity requirements
Control system:
• The control system includes control of process parameters like
temperature, crystal diameter pull rate and rotation speed

Working

• Polycrystalline Silicon is placed in the crucible and the furnace is heated to melt
Silicon.

• A suitable oriented seed crystal is placed over the crucible in the seed holder.

• The seed is dipped into the melt.

• Some part of the seed melts and some touch the liquid surface.

• The seed is then slowly pulled up.

• So freezing at the solid liquid interface occurs and single crystal is formed

• The seed crystal in this form is known as INGOT

• In the growth process a know amount of dopant is added to the melt to obtain
desired doping concentration in the grown crystal (eg. Boron[p type], Phosphorous[n
type]

• The two ends of the ingot is know as seed and tang.

• The first step is to remove this seed and tang using a circular saw

• After the crystal is grown the seed is removed and the surface is grinded so that the
diameter of the material is defined

• After grinding the ingot is sliced into wafers by diamond saws.

 Advantages

• Easy to establish thermal field for various crystals with a wider span of materials
and melting points than any other melt growth method

• Crystals grow from the free surface of the melt without contacting with crucible
• Dislocations originating from seed and thermal shock can be easily eliminated

• Oxygen(impurity) can be very useful in mechanically strengthening the silicon

crystal and in providing a means for gettering/removing other unwanted impurities
during device fabrication.
Disadvantages

• The only significant drawback to the CZ method is that the silicon is contained in
liquid form in a crucible during growth and as a result, impurities from the crucible
are incorporated in the growing crystal.

• Oxygen and carbon are the two most significant contaminants. Because of the
presence of Oxygen , the crystal will not be suitable for making power devices and
will have lower breakdown voltage.
Wafer Preparation – Basic Processing
Steps

• Crystal Growth – CZ or FZ process is carried out

(depending on the application)

• Shaping – After crystal growth, the wafers are shaped to smoothen the surface
• Two types of grinding
1) Diameter Grinding – to smoothen the surface and to obtain a uniform diameter.
2) Wafer Flat Grinding – used for alignment. Also helps to indicate the
orientation and conductivity type of the wafer

• Slicing - The ingot is sliced into wafers by diamond saws. The surface orientation,
thickness , taper and bow are determined from slicing

• Wafer lapping and Edge Grinding –

• The wafers are being lapped using a coarse abrasive
(alumina) suspended in a solvent.
• Edge Grinding helps to reduce edge chippings which can result in breakage or
dislocations in the circuit

• Etching - Etching refers to the removal of material from the wafer surface. The
process is usually combined with lithography in order to select specific areas on the
wafer from which material is to be removed. Two types

1) Wet Etching - removal of material by immersing the wafers in the solvent. It is

used for removal of
material from large areas.

2) Dry Etching - removal of material in the absence of solvent. For smaller areas,
where greater precision in removal of material is required, dry etch is preferred.

• Polishing -The surface of the wafer is then polished to a mirror finish using
chemical and mechanical polishing to obtain a smooth defect free surface. The
polishing gas is made up of artificial fabric.The wafers are now ready for the
fabrication of IC.

• Metallization is the final step in the wafer processing sequence. Metallization is the
process by which the components of IC’s are interconnected by aluminium
conductor.

• Isolation - Once all the components are fabricated on a single crystal wafer, they
must be electrically isolated from each other. Two main approaches are
• p-n junction isolation
• Oxide isolation (Dielectric isolation)

• Finally the fabricated IC s are packed after cleaning and inspection.

 Oxidation

• Oxidation refers to the chemical process of reaction of Silicon with oxygen to

form Silicon dioxide (SiO2)

• Serve as a mask during diffusion or implantation of a dopant into wafers

• Used for surface passivation/ protection

• For gate oxide in MOS devices.

• An isolation between devices

• To provide electrical isolation

• To act as a dielectric in MOS structure
Properties of SiO2

• It is an excellent electrical insulator

• It has high breakdown electric field

• It has stable Si/SiO2 interface

• Uniform oxide growth on exposed Si surface

• Very good etching selectivity between Si and SO2

• SiO2 structure is amorphous

Thermal Oxidation
• Most common oxidation technique.

• The silicon is put inside a furnace, the temperature of the furnace is raised and
either oxygen or water vapour is allowed to flow and silicon will react either with
oxygen or with water to form silicon dioxide.

• Si + O2SiO2 (Dry oxidation)

• Si+H2O SiO2 + 2H2 (Wet oxidation)

• The oxidation reaction occurs at Si-SiO2 interface.

• When the interface between the oxide and Silicon requires a low charge density
level, thermal oxidation is preferred.

• The thickness determine the amount of charge stored in it

• In thermal oxidation, a major advantage in that is all the contamination is on the

outer surface of the oxide and it does not affect the interface.
• In fact that is one of the reasons why thermal oxide is the best

• In anodic oxidation the original contaminations were present on the surface, that
same thing will be present at the interface and the quality of the interface will be
poorer.

Dry Oxidation

• During dry oxidation the wafer is placed in a pure oxygen gas (O2 ) environment
and the chemical reaction which ensues is between the solid silicon atoms (Si) on
the surface of the wafer and the approaching oxide gas

Si + O2 SiO2

• It can be noted that the oxidation rate does not exceed 50nm/h, making it a
relatively slow process which can be accurately controlled in order to achieve a
desired thickness.
• They are used to make thin oxides.

• The oxide films resulting from a dry oxidation process have a better quality than
those grown in a wet environment, which makes them more desirable when high
quality oxides are needed.
• Dry oxidation is generally used to grow films not thicker than 100nm or as a
second step in the growth of thicker films, after wet oxidation has already been used to
obtain a desired thickness.
• The application of a second step is only meant to improve the quality of the thick
oxide.

Thin Oxides

• They show good electrical characteristics and provides long term reliability.
• They serve as dielectric material for MOS capacitors which are used as storage
units in dynamic RAMS.

• The thickness determine the amount of charge stored in it. The growth of thin
oxides must be slow to obtain uniformity and reproducibility.
Wet Oxidation
• During wet oxidation, the silicon wafer is placed into an atmosphere of water
vapor (H 2O) and the ensuing chemical reaction is between the water vapor molecules
and the solid silicon atoms (Si) on the surface of the wafer, with hydrogen gas (H 2 )
released as a by-product

Si+ H2O SiO2 + 2H2

• Wet oxidation operates with much higher oxidation rates than dry oxidation, up to
approximately 600nm/h.

• The reason is the ability of hydroxide (OH) to diffuse through the already-
grown oxide much quicker than Oxygen (O).
• Due to the fast growth rate, wet oxidation is generally used where thick oxides are
required, such as insulation and passivation layers, masking layers, and for blanket field
oxides.
Deal Grove Model
• Process 1:Surface reaction of sorrounding atmosphere
• First of all, oxidizing species is there in the gas.
• From the gas stream it must be transferred to the oxide gas interface.

 Process 2: Diffusion process through existing oxide towards the interface

between silicon and silicon dioxide
 Once these oxidizing species have reached the oxide gas interface, it must diffuse
through the existing oxide layer in order to reach the silicon oxide interface, because
the oxidation is taking place by the movement inside of oxidizing species.
 So, if they want to react with silicon, they must move through the already existing
oxide layer into the siliconsilicon dioxide interface (that is this interface.)

• Process 3: Chemical reaction of silicon and oxygen

• Once these oxidizing species reach the silicon-silicon dioxide interface, it must react
with silicon there

• Therefore there are three fluxes F1,F2,F3 associated with this.

 F1 (flux of oxidising species transported from the gas phase to the gas-oxide
interface)
 F2 (flux across the existing oxide towards the silicon substrate)
 F3 (flux reacting at the Si-SiO2 interface)

• At steady state : F1 = F2 = F3 ------------------ (1)

• F1 is the flux of the oxidizing species in the bulk of the gas, from the bulk of the gas
right next to the oxide gas interface.

• Or F1 can be approximated to be proportional to the difference in concentration

of the oxidising species in the gas phase and on the oxide surface

• i.e., F1 = hG (CG-CS) ---------------------------- (2)

• CG is the concentration of the oxidizing species in the bulk of the gas
• CS is the concentration of the oxidizing species next to the gas oxide interface.
• hG is the proportionality constant and is called the gas phase mass transfer
coefficient

• By gas laws, we have PV =nKT

• P - Partial pressure of oxidizing species
• V – Volume
• N – amount of substance/no of moles
• K – ideal gas constant
• T – Temperature

• Replace CG = CS = 𝐕𝐧 = 𝐊𝐓𝐏 ---------------- (3)

• Therefore F
h G
1 = 𝐊𝐓 (PG-PS) ---------------- (4)
• Henry’s law states that in equilibrium the concentration of a species within a solid is
proportional to the partial pressure of that species in the surrounding gas i.e.,
C0 = HPS--------------------------------------- (5)
• C0 is the concentration of the oxidizing species at the outer oxide surface
• H – Henry’s Law Constant
• Ps – Partial pressure of oxidant in the gas phase adjacent to the oxide surface

• Also, by Henry’s law, C* is going to be proportional to the partial pressure of this

oxidizing species in the surrounding gas i.e., PG
C* = HPG--------------------------------------- (6)
• C* is defined as the equilibrium concentration of the oxidizing species in the oxide

• Hence, C* - C0 = H (PG-PS) ------------------------- (7)

• Therefore F1 = 𝐇𝐤hG𝐓 (C* - C0 ) -------------------- (8)

• Or, F1 = h (C* - C0) ----------------------------- (9)

• where h = hG / HkT is the gas phase mass-transfer coefficient in terms of
concentration in the solid

• F2 is the movement in the oxidising species in the oxide layer i.e., it is diffusing
through the existing oxide layer.
• Diffusion is the random motion of impurity atoms in a lattice (substrate) from
higher concentration to lower concentration,

• By Fick’s law, diffusion is always proportional to the concentration gradient.

• Concentration gradient = (C0 – Ci ) /oxide thickness =(C0 – Ci ) /x

• Thus, F2 = D (C0 – Ci )/x ------------------------ (10)

• D – Diffusion Constant
• Ci - concentration of oxidizing species at the inner surface (i.e., SiO2 – Si Interface)

• x - oxide thickness

• F3 is related to the reaction of Silicon with the oxidizing species.

• This reaction depends on the availability of the oxidixing species i.e., it depends on
the concentration of the oxidising species at the interface

• i.e if more species then more reaction takes place

• F3 is proportional to the concentration of oxidising species at the interface

• F3 α Ci
• F3 = KS Ci ---------------------------------- (11)
• Ks is the reaction rate constant
• At the steady state, F1= F2= F3. So equating equations (10) and (11), • Ks Ci = D (C0-
Ci)/x

• Ci (Ks + D/x) = D C0/x

• Ci =(D C0/x)/ (Ks + D/x) = (C0 D)/( x(Ksx + D)/x)

• Ci = (1+Ksx/D
C0
) --------------------------------- (12)

• Substitute equation (12) in equation (11 )

• F1 = F3 = Ks. Ci = Ks . C0 /(1+Ksx/D) --------------- (13)

• Equate F1 and F3

• h (C* -C0) = Ks . C0 /(1+Ksx/D)

• Solving above equation

• C C∗ (1+Ksx/D)
+ (Ks.x/D)

• Substituting (14) in (12),

• Ci = (1+ Ks/h)C+∗ (Ks.x/D) ---------------------------

(15)
• When D = 0, h (C* -C0) = 0 = ksCi

• i.e., C* = C0 and Ci =0

• The physical significance is, diffusion is controlling the oxidation.

• The oxidation is called diffusion limited.

• So, the bottleneck in the oxidation process, is the movement of the oxidizing species
is hampered by the process of diffusion.

• So, this is called the diffusion limited regime of oxidation and the thicker the
oxide layer becomes, the more difficult it becomes for diffusion to take place.

• When D = α it becomes Ci = C0 = C*/(1+ks/h)

• In other words, there is no difference between the concentration of oxidizing species

from the outer surface to the inner surface.

• i.e., the availability or the diffusion of oxidizing species through the oxide is not
posing a problem.

• The problem is after the oxidizing species have reached the interface, how fast can
they react with silicon.

• So, the oxidation is called reaction limited for this case.

• When D =α , this is called reaction limited.

Oxide Thickness Growth rate

• Since all the fluxes are identical under steady state condition, differential equation
for oxide growth is given by
• N1 𝐝𝐭𝐝 (𝐱) = F3 = (1+ Ksx/DKs. C+∗Ks/h)

• N1 - number of oxidant molecules per unit volume of the oxide, d

• (x) - oxide growth rate, dt
• x - oxide thickness
• t - time,
• KS - reaction rate constant,
• C* - equilibrium constant of the oxidant species in the oxide, • h - gas phase mass
transfer coefficient
• D - diffusion coefficient.
• The above differential equation when subjected to the initial conditions i.e., t=0 , we
have

• x2 + A x= B(t + τ) is the oxide growth rate equation.

• A = 2D[1/ks + 1/h]

• B = 2DC* / N1

• τ – shift in time coordinate to account for presence of initial oxide layer x 0 = (x0 2 +
A x0) / B
• For long oxidation times i.e., t >> τ and t >>A 2 /4B , oxidation follows a
parabolic growth rate with x2 = Bt , and B is called parabolic rate constant
• For short oxidation times i.e., (t+ τ) << A 2 /4B, oxidation follows a linear growth
rate

• curve, with x= [B/A] (t+ τ) and [B/A] is referred to as linear rate constant
Diffusion
• Random motion of impurity atoms in a lattice (substrate) from higher
concentration to lower concentration
• Process by which impurities are introduced into selected regions of a
semiconductor, for the purpose of altering its electrical properties.

• Process of introducing controlled amount of dopants into semiconductors

• Diffusion is used to :
• Form the base and emitter in BJT
• Form integrated resistor
• Form the source and drain in MOSFETs
• Dope poly-silicon gates in MOS transistor
Advantages

• It is highly adapted to batch processes where many slices are handled in a single
operation.

• It does not produce crystal damage thus high quality junctions with minimum
leakage current can be made easily with this method

• Used as a technique for disordering super lattice.

•
Fick’s Laws

• Analogy between material transfer in a solution and heat transfer by conduction •

d𝑐
Whenever an impurity concentration gradient exist in a
dx finite volume of matrix substrate (Silicon substrate), the impurity material will have
the natural tendency to move inorder to distribute itself more evenly within the matrix
and decrease the gradient
• Given enough time, this flow of impurities will result in homogeneity within the
matrix, causing the net flow of impurities to stop

• Fick’s first law states that the flux of material across a given plane is
proportional to the concentration gradient across the plane i.e. , J=-D 𝐝 𝐜(x,t)

𝐝𝐱
J – flux of atoms diffusing
D – Diffusion coefficient for material/Diffusivity x – Depth in silicon/ solute flow dc
- Concentration Gradient dx
-ve sign indicates that impurities are flowing in the direction of lower/ decreasing solute
concentration

• In other words, Fick’s first law of Diffusion states that the local rate of transfer of
solute per unit area per unit time is proportional to the concentration gradient of the
solute and defines the proportionality constant as the diffusion constant of the solute

• Fick’s first law doesn’t consider the change of flux with position

• Fick’s second law states that the change in impurity concentration with time is
equal to the change in flux with position i.e., d 𝒄(𝐱, 𝐭) = - 𝐝𝐉
𝐝𝒕 𝐝𝐱

• From First law we have ., J = -D 𝐝 𝐜(x,t)

 𝐝𝐱
• So we can rewrite second law as,
𝐝 𝐝 𝐝𝐜 d2
𝒄 (x,t) = - [-D (x,t)] = D c(x,t)
𝐝𝒕 𝐝𝐱 𝐝𝐱 dx 2

Ion Implantation
• Dominant doping technique to introduce dopant impurities into crystalline
silicon

• It is an alternative to diffusion to produce a shallow surface region of dopant atoms

• Direct bombardment of accelerated dopant ions onto the substrate

• The dopant atoms are vapourized to form ionized atoms and are accelerated by
an electrostatic field and made to strike the surface of wafer so that these particles
penetrate into the target material
• Two key parameters – ion energy which determines the penetration depth and
the ion current which sets the dose (thus the implantation time)
• By measuring ion current and adjusting electrostatic field, the penetration depth
and dose( amount of dopant atoms, n or p impurity) can be controlled
• It is because the penetration depth depends on the kinetic energy of the ions which
is proportional to the electric field.
• It mainly consist of :
• Ion source (dopant)
• Mass separation unit
• Accelerators
• Beam scanners

• Ion source:
• Choice of beam parameters depends on the system applications
• They provide the ions that are to be bombarded on the wafer surface
• Since in solid form they have to be vapourized first and then to be sent to the
accelerator.
• To ionize the dopant it is passed through a hot or cold cathode or RF electronic
discharge
• A magnetic field is provided so as to force the electrons to move in a spiral
trajectory, thus increasing ionizing efficiency of source
• Effectiveness of ion source is measured by the magnitude of ion current delivered to
the accelerator and ultimately to the target

• Mass separator
• It is used to purify the ion based on their masses
• When the ion beams are produced in the discharge chamber, they are
contaminated by atomic and molecular ion species which are sputtered from its
walls and filaments i.e., they produce one or more charged species.
• Purification of this beam to select the desired implant species is essential and the
technique used is ion separation based on their masses.
• Use of mass separation techniques provides a unique distinction between ion
implantation and diffusion, where a variety of dopants can be handled in a single
operation with complete freedom from contamination from each other
• A homogeneous field magnetic analyzer is usually used.
• The magnetic field is so adjusted that the radius of the ion path corresponds to
the radius of the magnetic analyzer.
• According to the mass the trajectory will be different.
• The ion beam is passed through a magnetic sector that selects a particular ionic
species
• So the desired ions will pass through the slit and others will be rejected.
• Accelerator:
• The ion beam is now passed through the accelerator column to impart energy to it.
• Acceleration is usually provided by high voltage established by a series of biased,
annular, ring electrodes
• The output end is maintained at ground potential for safety reasons i.e., the beam
travels from high voltage to ground
• Apparatus ensures that the beam is well collimated.
• In the acceleration tube they gain high momentum and energy because of the
electric field
• Designed in such a way so as to minimize collisions with slits and apertures, in
order to prevent the formation of secondary electrons
• Beam energy determines the projected range of an ion

• Beam scanning
• The ion beam is focused to a small spot for directing the desired dopant
patterns onto the wafer surface without the use of a masking layer
• Primary requirements of beam scanners are uniform coverage and the ability to
handle a large number of slices in a single pump-down
• In hybrid deflection system the beam is electronically scanned in one direction
while the slices are mechanically moved in the order.
• Another system is cassette loading which loads many wafers simultaneously but
automatically exposes the wafers in the ion beam

Advantages

• Low temperature process

• Precise dose and junction depth control
• Implantations through thin layers of oxide/nitride possible

• Short process times, good homogeneity, and reproducibility of the profiles

• Exact control of the amount of implanted ions by measuring the current
• Low penetration depth of the implanted ions which allows modification of thin
areas near the surface with high concentration gradients

• Non–equilibrium process i.e., the resulting carrier concentration is not limited by

thermodynamic considerations but rather by the ability of the dopant to
become electrically active in the host lattice

Disadvantages

• Implanted dopants are electrically inactive because they are situated on

interstitial sites

• Implant damage enhances diffusion

• Additional cost of annealing

• Dislocations may cause junction leakage

• Additional effects during or after implantation, eg., channeling or diffusion, make it

difficult to achieve very shallow profiles and to theoretically predict the exact profile
shapes.
 Epitaxy

Epitaxy is the combination of two words

◦ Epi means upon
◦ Taxis means ordered
i.e., epitaxy means ordered upon
Arrangement of atoms upon a crystal substrate such that the added layer is an exact
extension of the substrate crystal structure
Epitaxy means growing a thin crystalline layer over a crystalline substrate (bulk
crystal)
Epitaxy – Two Types
Homo epitaxy/Autoepitaxy

Same material is grown over the bulk crystal.

Eg. silicon layer is grown on top of a silicon bulk crystal, may be of a different doping
concentration, of a
different resistivity., it is called homo epitaxy
 On a p-type silicon substrate, if an n-type epitaxial layer grown, but both of them are
made of silicon is an
example of homo epitaxy
Results in layers of better electrical quality

Hetero epitaxy

Material of the epitaxial layer is dissimilar from the bulk material

Two materials of different crystalline structure and orientation
Eg. silicon on sapphire

Techniques for Epitaxial Growth

1. Liquid Phase Epitaxy (LPE)
2. Vapour Phase Epitaxy (VPE)
3. Molecular Beam Epitaxy (MBE)
 Molecular Beam Epitaxy
It involves the direct physical transport of the material to be grown, or its
components to a heated substrate.

It is similar to vacuum evaporation and growth is achieved by directing atomic or

molecular beams in a well controlled, ultra high vacuum system.

Gallium and Arsenic are used as the source material for GaAs.
Apparatus is made up of following parts
◦ Effusion Cell Ports : contain high purity elements, which are thermally evaporated to
obtain beams
◦ Shutter :controls the amount of flux from the effusion cells
◦ Liquid Nitrogen Cooled Shrouds : controls and maintains the ultra high vaccum
environment inside the chamber by chilling a system of cryopumps (vaccum pump that
traps gases or vapours) and
cryopanels to a temperature of -196° C

◦ Rotating Substrate Holders : rotates at few rpm for increased layer uniformity
◦ Ionization Gauze : used to measure the effusion flux
The beams of the material to be transported are usually generated by thermal evaporation
from crucibles known as effusion cells, which is shuttered in order to initiate and
terminate the flux of evaporant species.
Mean free path of evaporant must be long compared to distance from the substrate
A series of effusion cells, each with a separate shutter are set up so that their flux is
directed to the substrate
Separate effusion cell is used to provide each element needed for the growth of an
epitaxial layer and also for its doping
The substrate on which the wafer is mounted usually consists of a heated molybdenum
block, which can be rotated during growth at a few rpm, for increasing layer uniformity.
The evaporated species are transported at a relatively high velocity in a high vacuum
medium to the substrate and get deposited there.
Since the temperature is relatively low and the growth rate is also very low, precise
control of doping profile can be obtained
The condensation of the source molecules takes place at the substrate which is at lower
temperature
Accumulation of unwanted material in the surface of filament can result from continued
exposure to the effusing species, so we have to move gauge out of the flux beam path
when a direct measurement is not required
MBE consist of three vacuum chambers
◦ Growth chamber : used to grow phosphorous containing III-V compound
semiconductor and also to grow Arsenic based compounds
◦ Buffer chamber : Used for preparation and storage of samples and also act as transition
tube to allow samples to be transferred
◦ Load lock : To bring samples into and out of vacuum environment
 Advantages

It is usually done at very high vacuum condition so that no impurity can get a way
inside the substrate
By MBE one can achieve precise control in both chemical compositions and doping
profiles
Single crystal multilayer structure can be made using MBE that have very small
dimensions
low temperature processing
Lithography

process of transferring a pattern from a mask to the surface of a substrate Used for
device fabrication
Steps :
◦ Imposition of structure
◦ Chemical transformation
◦ Deposition
◦ Etching
 Photolithography

Uses a light sensitive material called photoresist to create a specific pattern on the
surface of a substrate
Process of transferring a pattern from a photo mask to a photoresist (resist is a thin
layer of radiation sensitive material)
Photo resist :
It is a light sensitive liquid solution consist of a polymer, a sensitizer and a suitable
solvent system
Polymers have properties of excellent film forming and coating
Polymer generally used are polyvinylcinnamate
When photoresist is exposed to light, sensitizer absorbs energy and initiates
chemical changes in the resist
The sensitizers
◦ Are chromophoric organic molecules
◦ Enhance cross linking of the photoresist
◦ Cross linking of polymer or long change formation is termed as photo polymerization
The solvents used to keep the polymer in solution are mixture of organic liquids
In lithography the exposing radiation such as UV in case of photolithography, is
transmitted through the clear parts of the mask
Other types of exposing radiations are electrons, X-Ray or ions
According to the change that take place photo resists are termed negative or positive

Characteristics of good photo resist

Uniform film formation
Good adhesion to the substrate
Resolution
Resistance to wet and dry etch process

Positive Photoresist

•Exposure to the UV rays results in the depolymerization of the photoresist

•This makes these exposed areas of the photo resist readily soluble in the developer
solution whereas the unexposed areas are essentially insoluble
•The developer solution will thus remove the exposed or depolymerized regions of the
photoresist whereas the unexposed areas will remain on the wafer
•Thus again there is a replication of the photo mask pattern

Negative Photoresist

Areas of photo resist that are exposed to UV radiations become polymerized.

This make resist tougher and make it essentially
insoluble in the developer solution.
The resisting photoresist pattern after the development process will therefore be a
replication of the photo masks pattern with the clear areas on the photo mask
corresponding to the areas where the photoresist remains on the wafer (reverse of mask)
 Photolithography Sequence

Consists of the following steps

1) Photoresist application/spinning
2) Pre-bake/Soft-bake
3) Mask alignment
4) Exposure
5) Development
6) Post-bake
7) Oxide etching
8) Photoresist stripping

1. Photoresist application (spinning)

Consists of laying a film of photoresist material on the surface of wafer which is covered
by the masking film
Ideally, such a film should be uniform, highly adherent and completely free from dust or
pinholes
A drop/ small quantity of pre-filtered light sensitive liquid called photoresist is
applied to the center of the oxidized silicon wafer
The wafer is then accelerated rapidly to a rotational velocity in the range of 3000 to
7000 rpm for 30 to 60 seconds
This action spreads the solution in a thin nearly uniform coat and spins off the excess
liquid.
The thickness of the photoresist layer will be approximately inversely proportional to
the square root of the rotational velocity.
2. Pre-bake / Soft - bake
Silicon wafer coated with photo resists are now baked to drive off solvents in the
photoresist and to harden it into a semisolid film.
Placed in oven at about 90oC - 100oC for about 30 to 60 minutes
Film thickness shrinks to about 85% of its spun-on value
Also reduces the solubility of the unexposed film in the developer
3. MaskAlignment
The coated wafer is now placed in an apparatus called a mask aligner in very close
proximity to a photoresist
The relative positions of the wafer and this photo mask are adjusted such that the
photo mask is correctly lined up with reference masks or a pre existing pattern on the
wafer
The photo mask is a glass plate which has a photographic emulsion pattern on one side
The pattern has clear and opaque areas
The mask aligner may be ..
◦ contact printing –
🞄The wafer is in contact with the mask
🞄very high resolution
◦ proximity printing –
🞄Here the mask and the wafer are placed close together, but not actually in contact.
🞄Not high resolution (2-4 μ)
🞄Life of mask is increased
◦ projection printing – 🞄Mask is not near the wafer
🞄Project the image of mask on wafer using some optical methods
🞄Highly focused and High resolution
4. Exposure
A highly collimated UV light is turned on and the areas of the Silicon wafer that are
not covered by the opaque areas of the photo mask are exposed to UV radiation
During exposure, the optical wave propagates through the resist and is reflected
backwards resulting in a standing wave intensity pattern causing striations
Can be reduced by the use of a antireflective coating (ARC) placed between either the
resist-layer interface or the air-resist interface
5. Devolopment
Slice is now rinsed in an appropriate developer, specified by the photoresist
manufacturer
For development either negative or positive photo resist can be used
Development step result in dissolution of the exposed region in case of positive
photoresist and dissolution of unexposed region in case of negative photoresist
6. Hard bake/ Post bake
After the development, the wafers are usually given a post bake to toughen or densify
further the remaining resist on the wafer
Placed in an oven at a temperature of about 100oC120oC forabout 30 to 60 minutes
This is to make it adhere better to the wafer and to make it more resistant to the etching
of the SiO2
Advantage : reduces striations caused by standing wave effects
7. Oxide Etching
The remaining resist is hardened and acts as a convenient mask through which the oxide
layer can be
etched away to expose areas of semiconductor underneath
Slice is etched to remove those parts of the underlying film that are not covered by
photoresist
(positive)
Results in formation of windows
These exposed areas are ready for impurity diffusion
Etching can be any of the following
◦ Wet Etching ◦ Dry Etching
8. Photoresist Stripping
Consists of removal of remaining photoresist
Positive photoresists are usually removed by means of a chemical solvent such as acetone
or methylethylketone
Negative resists are harder to remove. Here the slice is immersed in a mixture of
Sulphuric acid and hydrogen peroxide and the photoresist is removed with the help of
abrasion process
Advantages
◦ Requires only a single beam of UV light and doesn’t require any additional materials
◦ Highly efficient and cost effective while producing extremely small openings in a
substrate
◦ Controls the exact size and shape of the entire substrate
Disadvantages
◦ Requires completely flat substrate to produce effective patterns
◦ Requires extremely clean conditions
◦ Light diffractionlimits minimum feature size
Electron Beam Lithography

Process of emitting electron beam in a patterned fashion across a surface covered

with a film (called resist) and selectively removing either exposed or non exposed
regions of the resist
Create very small structures in the resist and also used for creating nano technology
architectures
It provides better resolution than photolithography
Resolution depends on electron scattering and beam optics
Advantages
◦ Beats the diffractionlimit of light
◦ Make features in the nanometer region
Disadvantages
◦ Slow system i.e., takes very long time to expose an entire Si wafer
◦ Less throughput
◦ Proximity effect- scattering causes the electron beam to broaden and expose a large
volume of resist than expected which limits the minimum spacing between pattern
feature
Etching
Etching refers to the removal of material from the wafer surface.
The process is usually combined with lithography in order to select specific areas on
the wafer from which material is to be removed.
Etching represents one way of permanently transferring the mask pattern from the
photo resist to the wafer surface.
The complementary process to etching is deposition (or growth), where new material is
added.
There are two main types of etching
1. Wet etching
2. Dry etching
Wet Etching

•In wet etching, the wafers are immersed in a tank of the etchant (mix of chemicals).
•There is a chemical reaction between the wafer surface and the etchants that helps in
material removal.
•Either a photoresist layer or a hard mask like oxide or nitride layer is used to protect the
rest of the wafer.
•The time for etching depends on the amount and type of material that needs to be
removed.
•KOH (potassium hydroxide) is a common etchant used to remove Si. {Usually, 30%
KOH solution is used, which has a etch rate of 100 µm/hr at 90 ◦C. }
•After etching, the wafers are rinsed, usually in (Deionized Water) DI water, for removal
of etchant and then finally dried.
Wet etching is used for removal of material from large areas (trench sizes > 3 µm).
For smaller areas, where greater precision in removal of material is required, dry etch is
preferred.
The wet etching process is isotropic i.e. the etch rate depends on the plane of the Si
wafer, from which atoms are being removed.
Etching uniformity is important to get a uniform thickness over the entire wafer surface.
This is usually determined by process conditions like etchant temperature, concentration,
and agitation (using stirrers).

Controlled portion of the wafer surface is exposed to the etchant which then removes
materials by chemical reaction.
Advantages:
Simple equipment
High throughput (batch process)
High selectivity
Disadvantages:
Isotropic etching leads to undercutting
Uses relatively large quantities of etch chemicals, must immerse wafer boats, must
discard partially used etch to maintain etch rate
Hot chemicals create photoresist adhesion problems
Small geometries difficult, line with > thickness, etch block caused by surface tension
Critical Etch time, dimensions change with etch time, bias develops
Chemical costs are high
Disposal costs are high
Dry Etching

Dry etching, is removal of material in the absence of solvent.

Here, etchant gases are the primary medium for the removal of material.
The process was introduced because wet etching has some limitations in its applicability
1. Wet etching is used for large pattern sizes, usually larger than 2 µm.
2. It is an isotropic process - sloped sidewalls rather than straight walls.
3.Wet etch has to be combined with subsequent rinse and dry steps. This increases
chances of defects or contamination.
4. Hazardous chemicals and conditions are used, so safety is an issue. Safe disposal of
chemicals is essential.
5. Undercutting and resist peel off can happen if time is not controlled or etch conditions
change during process

There are three main types of dry etching

1. Plasma etch
2. Ion beam milling
3. Reactive ion etch
Advantages:
No photoresist adhesion problems
Anisotropic etch profile is possible
Chemical consumption is small
Disposal of reaction products less costly Suitable for automation
Disadvantages:
Complex equipment, RF, gas metering, vacuum, instrumentation
Selectivity can be poor
Residues left on wafer, polymers, heavy metals

Metal Deposition/Metallization

Metallization is the final step in the wafer processing sequence.

Metallization is the process by which the components of IC’s are interconnected by
aluminium conductor.
Done for device contact and electrical wiring
This process produces a thin-film metal layer that will serve as the required conductor
pattern for the interconnection of the various components on the chip.
Another use of metallization is to produce metalized areas called bonding pads around
the periphery of the chip to produce metalized areas for the bonding of wire leads from
the package to the chip.
Desired properties for metallization

Low resistivity.
Easy to form.
Easy to etch for pattern generation.
Should be stable in oxidizing ambient
Mechanical stability; good adherence, low stress.
Surface smoothness.
Stability throughout processing including high temperature , dry or wet oxidation,
gettering, phosphorous glass (or any other material) passivation, metallization.
Should not contaminate device, wafers, or working apparatus.
Good device characteristics and life times.
For window contacts-low contact resistance, minimum junction penetration,
low electromigration.
Aluminium (Al) is the most commonly used material for the metallization of most
IC’s, discrete diodes, and transistors. The film thickness is as about 1 micro meters and
conductor widths of about 2 to 25 micro meters are commonly used.
Advantages of using Al
◦ It has as relatively good conductivity.
◦ It is easy to deposit thin films of Al by vacuum evaporation.
◦ It has good adherence to the silicon dioxide surface.
◦ Aluminium forms good mechanical bonds with silicon.
◦ Aluminium forms low-resistance, non-rectifying ( ohmic) contacts with p-type silicon
and with heavily doped n-type silicon.
◦ It can be applied and patterned with a single deposition and etching process.

Disadvantages
◦ During packaging operation if temperature goes too high, or if there is
overheating due to current surge, Al can fuse and can penetrate through the
oxide to the silicon and may cause short circuit in the connection. By
providing, adequate process control and testing, such failures can be minimized

For VLSI, metallization applications can be divided into three groups:

◦ Gates forMOSFET
◦ Contacts
◦ Interconnects
 Metal Deposition Techniques

Physical Vapour Deposition

◦ Thermal Evaporation
◦ Sputtering

Chemical Vapour Deposition

◦ Atmospheric Pressure CVD
◦ Low Pressure CVD
◦ Ultra High Vacuum CVD
◦ Plasma Enhanced CVD
Physical Vapour Deposition

Performed under vacuum circumstances

Involves four steps
◦ Evaporation – target is evaporated by high energy source such as electron beam
◦ Transportation – vaporised atoms moves from target to surface of substrate
◦ Reaction :
🞄If there is a gas such as nitrogen or oxygen in the system, the atoms of the material react
with the gas
🞄If the coating doesn’t contain a gas, this phase is not a part of the process
◦ Deposition – Final stage through which the surface of substrate is built

Classification
◦ Thermal Evaporation
◦Sputtering

Thermal Evaporation
◦ Also known as vacuum deposition
◦ Simplest technique for preparing thin film of micrometer thickness
◦ Consists of evaporating and condensing processes in vacuum chamber
◦ Source materials are evaporated by the heating source and is then condensed on the
substrate ◦ Uses two types of sources : 🞄Resistive source
🞄Electron beam source
Sputtering
◦ Involves ejecting material from a target (that is a source) onto a substrate (such as
silicon wafer)
◦ Re-sputtering – re-emmision of the deposited material during the deposition process by
ion or atom bombardment
◦ Sputtered atoms have a wide energy distribution, typically upto tens of eV
◦ Sputtered ions can ballistically fly from the target in straight lines and impact
energetically on the substrates or vacuum chamber (causing resputtering)
◦ Sputtering gas is often an inert gas such as argon
◦ For efficient momentum transfer, the atomic weight of the sputtering gas should be
close to atomic weight of the target
◦ For sputtering light elements, neon is preferred while for heavy elements,
krypton or xenon are used

Chemical Vapour Deposition

System in which a combination of gases reacts with the substrate surface at relatively
high temperature, leading to a decay of certain of the constituents of the gas
combination and the fabrication of a solid film of depositing of a metal or composite
on the substrate
Classification is based on the means by which the chemical reactions are
initiated (activation process) and process conditions

1. Atmospheric Pressure CVD (APCVD) – CVD process at atmospheric pressure

2. Low Pressure CVD (LPCVD) – CVD process at subatmospheric pressure. Reduced
pressures reduce
unwanted gas-phase reactions and improve film uniformity across the wafer
3. Ultrahigh Vacuum CVD – CVD process at a very low pressure
4. Plasma Enhanced CVD – CVD process that uses plasma to enhance chemical
reaction rates. It allows deposition at low temperatures