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A Development and Testing Instrumentation for GPS Software Defined Radio

With Fast FPGA Prototyping Support

Article in IEEE Transactions on Instrumentation and Measurement · August 2014

DOI: 10.1109/TIM.2014.2304352

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 63, NO. 8, AUGUST 2014 2001

A Development and Testing Instrumentation

for GPS Software Defined Radio With
Fast FPGA Prototyping Support
Arpine Soghoyan, Adnan Suleiman, and David Akopian, Senior Member, IEEE

Abstract— The modernization of global positioning systems Major challenges for advanced receiver development are
(GPS) boosts the development of civil and military applications as system development complexity, long development cycles,
accuracy and coverage of receivers continually improve. Recently, interfaces for RF front-ends and hardware accelerators for
software defined radio (SDR) approach for GPS receivers (GPS-
SDR) gained attention because of its flexibility for multimode real-time operation, and availability of end-to-end develop-
operations in different environments. The SDR receiver devel- ment and testing platforms. Continuous modernization of the
opers continually advance algorithmic and/or hardware acceler- GNSS systems, including transmission of new signals also
ator solutions. However, they need fast prototyping and testing challenges the research community to manage increased sys-
instrumentation to refine and evaluate high performance mul- tem complexities and deeper understanding of various signal
timode receivers. This paper presents a feasibility study of fast
prototyping of the GPS receiver accelerators using graphical user distortion phenomena. State-of-the-art receivers should also be
interface environments. It also describes a testbed with integrated flexible to perform multimode tasks for various environments.
RF front-ends, GPS simulator, receiver, and assistance support. To facilitate the development of these receivers, researchers
Particularly, a novel host-target codesign solution is demonstrated need reference systems, associated software development kits,
using a field programmable gate array (FPGA) peripheral and development platforms, simulators, and evaluation testbeds.
LabVIEW FPGA tool for a case study of a GPS acquisition
module. Distributing tasks between the FPGA target and the The software defined radio (SDR) framework [6], [8],
personal computer host achieves a high performance solution. [14]–[17] became popular for advanced receiver development
The fast prototyped solution is compared with a conventional and testing because the SDR receiver components are imple-
FPGA and state-of-the-art implementations. mented in software and can be reconfigured depending on
Index Terms— Fast prototyping, field programmable gate operational tasks; they are convenient for fast prototyping and
array (FPGA), global navigation satellite systems (GNSS), global academic research. Conventional state-of-the-art GPS receivers
positioning systems (GPS), software defined radio (SDR), testing. typically rely on application specific integrated circuit (ASIC)
technology for implementing massive numbers of correlators
I. I NTRODUCTION for improved sensitivity. On the contrary, the SDR solutions
use fast correlator algorithms and general purpose computing
T HE U.S. global positioning system (GPS) is one of the
existing global navigation satellite systems (GNSS) that
provides the end user with global position, velocity, and time
peripherals, such as field programmable gate arrays (FPGAs)
and/or digital signal processors (DSPs), to accelerate algo-
rithm execution (Fig. 1). The ASIC-based implementations
solutions [1], [2]. The GPS receivers are used in various
are fast but require longer development cycles and constrained
instrumentation and measurement systems from phasor mea-
hardware–software interfaces. In that sense, the FPGAs/DSPs
surements in power systems [3], [4] to ionospheric calibration
are less expensive and compromise solutions with well-
and time transfer [5].
developed support and host-target interfaces.
The GPS/GNSS receivers continually evolve supported by
Many open source and commercial SDR receiver solutions
new algorithms [1], [6], [7], computing platforms [8], [9], and
are reported [7], [14], [15], [18], [19], including the FPGA-
testing methodologies [10]. They are also integrated with other
based GPS receivers in [9] and [20] and reference designs
navigation systems for robust operation during GPS outages
mentioned in the following sections. Development platforms
[11]–[13].
range from proprietary solutions providing application pro-
Manuscript received July 29, 2013; revised December 16, 2013; accepted gram interface access to incorporate third party algorithms [6]
December 20, 2013. Date of publication February 27, 2014; date of current to MATLAB-based reference receivers [15], [18], and C/C++
version July 8, 2014. This work was supported in part by NSF under Grant
0942852 and Grant 0932339, and in part by the UTSA-NEEC Center. The based open source solutions [7], [14], [15], [19].
Associate Editor coordinating the review process was Dr. Jesus Urena. This paper presents a feasibility study of using graphi-
A. Soghoyan and D. Akopian are with the University of Texas at cal user interface environments for fast prototyping of the
San Antonio, San Antonio, TX 78249 USA (e-mail: arpisoghoyan@
gmail.com; [email protected]). GPS-SDR receiver accelerators. Particularly, competitive host-
A. Suleiman is with Cirrus Logic Inc, Austin, TX 78710 USA (e-mail: target FPGA accelerator (software–hardware) solutions are
[email protected]). obtained using LabVIEW FPGA tools from National Instru-
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. ments (NI) and related Xilinx tools [21] and compared
Digital Object Identifier 10.1109/TIM.2014.2304352 with conventional implementation approaches. In addition,
0018-9456 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2002 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 63, NO. 8, AUGUST 2014

Fig. 1. UTSAs development and testing platform for GPS SDR, including RF front-end, simulator, receiver, A-GPS support, DSP, and FPGA peripherals.
Highlighted modules on hardware-software codesign of acquisition unit using FPGA are the main focus of this paper.

the following features of LabVIEW facilitate the GPS receiver test signals. The simulator uses orbital data, i.e., ephemeris
development: 1) signal visualization; 2) fast computing and almanac data file inputs. The almanac and ephemeris file
options; 3) RF front-end and hardware accelerator interfaces; types, content, and location are described in [25] and [26].
4) GPS signal simulation; and 5) assisted GPS (A-GPS) A dedicated A-GPS LabVIEW module is integrated with the
support [22], [23]. A modular advanced GPS acquisition transmitter and uses a simulator signal to generate assistance
algorithm is used as a case study. according to the guidelines of the secure user plane location
This paper is organized as follows. Section II presents the (SUPL) [27] standard developed by open mobile alliance for
development and testing setup. The case study acquisition wireless networks [28]. When a GPS receiver is integrated with
module is described in Section III. Section IV presents the wireless communication devices, wireless networks provide
fast prototyping of the acquisition system using LabVIEW assistance data to aid the GPS receiver operation. Delivery of
FPGA. A standalone FPGA implementation for comparison orbital parameters (ephemeris and almanac) and other assis-
and host connectivity demonstration purposes is described in tance, such as coarse position and time reference, enhances
Section V. Performance figures of LabVIEW-based host-FPGA the GPS receiver operation in weak signal conditions such as
target implementation are discussed in Section VI. Section VII indoor areas [1], [23], [29], [30] as receivers are relieved from
discusses alignment of proposed solutions with state-of- the task of demodulating navigation data from satellite signals.
the-art implementations. Finally, conclusions are stated in A detailed description of the assistance data delivery solution
Section VIII. can be found in [28].
Thus, the testbed uses two channels to communicate with
the receiver. The GPS signals are broadcasted by the signal
II. D EVELOPMENT AND T ESTING S ETUP
generator-simulator, whereas A-GPS SUPL data are commu-
The system architecture of the GPS LabVIEW-based devel- nicated using IP channels and wireless network links. In the
opment testbed is shown in Fig. 1, which is an enhanced current implementation, the SUPL server and GPS simulator
version of the system reported in [24]. are colocated.
The transmitter’s RF front-end consists of an antenna and The receiver front-end consists of an antenna, a variable
NI PXIe-5673 RF vector signal generator (VSG), which gain amplifier (variable gain up to 30 dB) [31], and a NI
can be configured to generate various GNSS signals. The PXIe-5663RF vector signal analyzer. It is connected to a
GPS signal is generated using a LabVIEW-based NI GPS computer running a GPS-SDR receiver implemented using
simulation toolkit [21]. Current setup can be configured to LabVIEW. Optional hardware DSP/FPGA peripherals are
simulate various channel distortions. The simulation toolkit accessible through LabVIEW interfaces. Sampled data from
along with the VSG enables concurrent generation of one to the RF front-end are buffered for further processing in a
twelve satellite signals. Signal powers can be adjusted for each snapshot mode [32].
satellite based on testing specifications. The simulator also The LabVIEW environment provides built-in libraries for
supports signals of a wide area augmentation system, trajectory development, analysis, and data visualization. It is convenient
scripts, on-the-fly parameters, and stored files for replicating for the fast algorithm prototyping and testing, comparative
SOGHOYAN et al.: DEVELOPMENT AND TESTING INSTRUMENTATION FOR GPS SDR WITH FAST FPGA PROTOTYPING SUPPORT 2003

TABLE I
A DVANCED D EVELOPMENT-T ESTING T OOLKIT TO FACILITATE R ESEARCH AND D ISSEMINATION [23]

studies, real-time performance evaluation, and dissemination. (BPSK) navigation signal at 50 Hz, and a BPSK modulated
LabVIEW supports multithreading and multicore program- spreading pseudorandom code signal (PRN) at 1.023 Mchips/s.
ming, which are useful for real-time applications. These advan- The spreading sequence is called the coarse acquisition (C/A)
tages already have been used in other radio-communication code [1].
systems [33], [34]. The ultimate goal of a GPS receiver is to provide posi-
Algorithms can be implemented using LabVIEW library tion, velocity, and time information. For that, receivers mea-
modules, mathscript nodes using MATLAB scripts for fast sure range, range-rate, and demodulate navigation data. The
prototyping, and C/C++ language for fast processing. receiver measurements are extracted by synchronizing locally
LabVIEW also has support for external hardware peripherals generated replicas of the code with the received signal.
to accelerate research and simulation of the SDR development. This synchronization is performed in frequency by estimating
As already mentioned, the hardware accelerators, such as Doppler modulation, and in time, by aligning the signal and
DSPs and FPGAs, can be integrated with LabVIEW [35]. replica and estimating their relative shift called code-phase.
There are two different ways to integrate FPGAs with The synchronization is typically performed in two phases:
LabVIEW. One is using a software module called a Lab- acquisition (coarse) and tracking (fine). These two phases
VIEW FPGA module that translates LabVIEW data-flow constitute a baseband processing stage. After synchronization,
schematic into FPGA hardware. Another option is to use navigation data are simply obtained through sinusoidal carrier
IP Integration Node to integrate third party Verilog or and PRN code wipe-off. Navigation data contain timestamps,
Very High Speed Integrated Circuit Hardware Description which along with code-phases are used to estimate ranges
Language (VHDL) designs. to satellites. Navigation data also contain orbital parameters,
LabVIEW FPGA module with its graphical programming ephemeris, and almanac, all of which are used to find satel-
language and predesigned library tools allows for fast proto- lite positions provided time. Orbital parameters alternatively
typing of FPGA solutions. The NI PXIe Flex reconfigurable can be received using assistance from wireless networks as
input/output (FlexRIO) FPGA target module with integrated described in Section II and illustrated in Fig. 1. Satellite posi-
Xilinx Virtex-5 hosts the hardware implementation [35], [36]. tions serve as beacon locations for trilateration using ranges.
It is installed on a NI PXIe 1075 [37] chassis. The periph- The first stage of baseband signal processing is acquisition
eral connects to the LabVIEW environment through a NI of the GPS satellites. Conventional receivers achieve acquisi-
PXI-ExpressCard8360 connector with a throughput of up to tion by searching over a predicted time-frequency uncertainty
110 MB/s [38]. zone. It is a 2-D search process in which the receiver replicates
Debugging tools built into the environment include rapid candidate code and residual carrier modulations attempting to
edit-time error reporting, ability to view code execution, match those of the received signal. Multiple possible signal
and an ability to control the execution (single-stepping). replicas are generated and correlated with received signal to
Another advantage over using traditional hardware description find a match and thus to identify input signal parameters. This
languages (HDLs) is the ability to develop algorithms and assumes an elementwise multiplication of the received samples
rapidly perform direct functional verification on a personal with the samples of each replica. Then, resulting products
computer (PC) in a simulation/emulation mode. are added over the coherent integration length. Typically, a
Table I summarizes strength of the LabVIEW environment statistical test is applied to the correlation results to determine
for implementing software GPS receivers and exploiting exist- if a signal acquisition has been reached or not. If it has been,
ing host-target interfaces for the FPGA accelerations. the acquisition is terminated and the receiver starts the tracking
stage for that satellite; if not, the search continues and moves
III. GPS ACQUISITION M ODULE to the next code-phase/frequency option.
The case study in this paper is applied to the acquisition There are many fast methods of accelerating acquisition.
of a conventional L1 civilian GPS signal, a direct sequence For example, a convolution theorem can be used to apply fast
spread spectrum signal consisting of a multiplication of a Fourier transform (FFT) for parallel fast code-phase search
sinusoidal carrier at 1.57542 GHz, a binary phase shift keying (PCS) algorithms [15].
2004 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 63, NO. 8, AUGUST 2014

conjugated FFT-replicas to samples in each column of

the first stage output matrix. Then, compute Inverse
Fast Fourier Transform or Inverse FFTs (IFFTs) of each
such column-vector. The result is a vector correspond-
ing to one frequency bin, with each vector element
representing a correlation corresponding to one code-
phase, and the whole vector includes N1 correlations
for all code-phases. Repeat elementwise multiplications
and IFFT stages for all columns, i.e., N2 frequency bins
with resolution 1/N2 kHz (total 1-kHz range). Here, the
process is similar to conventional FFT-based correlation.
The difference is only in the long forward FFT, which
is concurrently reused for several fine frequency bins.
4) Coarse frequency bin search: after completing each
1-kHz fine frequency bin search, the next 1-kHz range
is processed by one cyclical shift of FFT-of-replica. For
K shifts, the total number of frequency bins will be KN 2
for K -kHz total frequency range.
5) Stages 1–4 will conclude the coherent correlation stage
for KN 2 frequency bins and N1 code-phase bins, with
total number of bins equal to KN 1 N2 . Maximum cor-
relations can be found from this array, or consecutive
arrays can be further integrated noncoherently [39].
Fig. 2. Block correlator for acquisition, coherent integration length is N2
code periods (N1 N2 samples for N1 samples per code period) and correlation The algorithm implements a massive correlator by combining
result plot. code-phase and frequency searches and shares computations
even for different satellites as forward FFT output is reused
Recently, proposed block correlators extend the PCS con- for all iterations. As indicated, kilohertz resolution frequency
cept by combining it with coherent integrations over sev- search steps are implemented in the frequency domain by
eral code periods exploiting shared computations for reduced cyclically shifting iterations of FFT-replicas. Sub-kilohertz
computational loads [39], [40]. The block correlators for frequency searches are computed concurrently using IFFTs of
acquisition efficiently perform concurrent joint search in multiple vectors after FFT transformation. In our case studies,
three dimensions: 1) code-phase; 2) Doppler frequency; and coherent integration lengths are 1, 2, and 4 ms. The FFTs of
3) satellite number. PRN code replicas for 24 satellite codes are stored in a 2-D
For the case study in this paper, an extended PCS algorithm array for faster access. The correlation results can be plotted
proposed in [39] is selected due to its modular structure, which using LabVIEW visualization tools. As the process is a 2-D
can be easily explained and used for fast prototyping using the search for each satellite over all frequency and code phase
LabVIEW FPGA toolkit and Xilinx core IPs. Fig. 2 illustrates bins, the correlation match between incoming signal and the
a block diagram of the algorithm. local replica exhibits a peak like the one shown in Fig. 2.
Let N1 denote the number of samples per code period, The acquisition algorithm has been implemented in several
which is also the number of code phases. N2 is the number modes: 1) using conventional C/C++ coding and C/C++
of coherently integrated code periods, i.e., correlation lengths modules integrated in LabVIEW; 2) using native LabVIEW
are N1 N2 samples. The algorithm computes correlations for all functional blocks as shown in Fig. 3; 3) as a standalone FPGA
code phases on a grid of frequencies with resolution 1/N2 kHz. implementation connected to the LabVIEW receiver; and 4) as
Following are the steps of this algorithm. a host-target codesign where IFFT computations are delegated
1) Long FFT Stage: compute FFT of the signal for the to the FPGA target.
whole coherent correlation length N1 N2 . This FFT The LabVIEW implementation of Fig. 3 follows the acqui-
is computed once and reused for further processing. sition steps described above and also includes benchmark time
Rearrange the output of the FFT unit into a matrix with readings for performance evaluations in Section V.
columns of size N1 as shown in Fig. 2. This stage is One can observe that most of the iterations for all satellites
common for all satellites and can be shared. and frequency and code-phase bins are performed repeatedly
2) For each satellite, compute FFT of the replica computing the IFFTs. The IFFT operations, in fact, are the
sequence code at input sampling frequency for total highest contributors to the correlator’s computational com-
length of N1 samples. These computations can be done plexity. The proposed host-target fast prototyping codesign
offline, saved, and retrieved when processing given solution delegates IFFT computations to onboard FPGA tar-
satellite signal. gets, and the entire solution is designed without the use of
3) Fine concurrent N2 frequency bins searching (for traditional ASIC design flow. Detailed descriptions of FPGA
each 1-kHz range). Multiply elementwise samples of solutions are described next.
SOGHOYAN et al.: DEVELOPMENT AND TESTING INSTRUMENTATION FOR GPS SDR WITH FAST FPGA PROTOTYPING SUPPORT 2005

Fig. 3. Advanced acquisition algorithm (Fig. 2) implementation using LabVIEW function blocks and its benchmarking.

IV. NI F LEX RIO FPGA M ODULE LabVIEW FPGA module development starts once a FPGA
AS A H ARDWARE ACCELERATOR project is created. The FPGA targets identified in the
LabVIEW project explorer include FPGA programmable
In the past, the FPGA implementation assumed knowledge
I/O nodes to acquire, process, transfer, and output signals
and many intricacies of hardware programming. The popular-
using the FPGA. This can be done either using simulated
ity of high-level design tools, however, is changing the rules of
I/O on a development computer or in real-time mode using
FPGA programming; recently emerged tools convert graphical
various hardware targets. A list of LabVIEW FPGA supported
block diagrams or even C/C++ code into digital hardware
hardware targets can be found in [35].
circuitry.
The target boards can be connected to computers through
As the development testbed presented in this paper is
PCI, cPCI, or PXI/PXIe. Some of these boards have purely
based on the LabVIEW environment, in the following, fast
digital front-ends and others have specialized front-end cir-
FPGA prototyping tools provided in the LabVIEW FPGA
cuitry, e.g., analog I/O channels, IF transceivers.
module [35] are evaluated for FPGA hardware correlator
Software components that are installed and used for the
design to accelerate the GPS-SDR acquisition stage. The tools
application development include: 1) the LabVIEW real-time
can synthesize FPGA-based solutions from the LabVIEW
module; 2) the LabVIEW FPGA module; and 3) the NI recon-
graphical representation of algorithms. This block diagram
figurable input/output (NI-RIO) driver, which are compatible
realization approach into the FPGA is well suited for fast
with Xilinx compilation tools [35].
prototyping, as it is independent of prior knowledge of the
The target used in this project includes a Virtex-5 SX95T
HDL programming.
FPGA programmable board, 512-MB onboard DDR2 DRAM,
Synthesis is the process of translating high-level program-
and 16 DMA channels for high-speed data streaming [36].
ming languages into actual logic-level hardware descriptions.
The host is a PC with Intel(R) Core (2) Duo CPU E8300
For any given piece of synthesizable code, there is a corre-
processor, 2.83GHz (2CPUs), 2020-MB RAM, and Windows
sponding logic circuit that describes how logic gates should
XP Professional OS. The LabVIEW 2011 SP1 version is used
be wired together. The LabVIEW FPGA module generates
as a development environment along with GPS Simulation
all necessary logic for every block diagram function before
Toolkit 2 for the GPS signal generation. Performance evalua-
sending a final schematic to the compiler.
tion of the system in the LabVIEW environment is done using
The LabVIEW FPGA design toolkit has the following
available profiler tools [21] and benchmarking as described
features:
later in this paper. The following sections provide more details
1) supports connection and interfaces to PCI/PXI boards; on various implementation aspects.
2) includes FPGA IP blocks library for fast prototyping;
3) provides fast host-target communication using built- A. LabVIEW FPGA Development Flow
in I/O direct memory access (DMA) first-in-first-out This section proceeds with implementation details. First, an
(FIFO) buffers; FPGA project is created in the LabVIEW environment for the
4) supports various clock rates of 40 MHz, 80 MHz, or FlexRIO board as described in [41]. Once the FPGA target
faster. is specified, then LabVIEW displays compatible functions for
In addition, recent versions of the LabVIEW FPGA module math, signal generation and analysis, comparison logic, array
introduced a new feature called the IP integration node, which and cluster manipulation, occurrences, analog and digital I/O,
embeds third-party HDLs into LabVIEW FPGA. The IP node and timing. A combination of these functions can be used
is used like any other LabVIEW function block with its to design algorithmic logic and embed it onto the FPGA
inputs and outputs. It also runs in both simulation and target device. Math and control in FPGA are limited to fixed-point
execution modes. operations.
2006 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 63, NO. 8, AUGUST 2014

mapped logic blocks to meet minimum timing and I/O

constraints. After this, LabVIEW VI invokes the Xilinx
tool to create binary configuration file saved as a bitfile.
5) Running on the Target: LabVIEW VI invokes the Xilinx
tool to transmit bitfile to program a FPGA target located
on the PXIe FlexRIO integrated board.
Using the described approach, a standalone GPS signal acqui-
sition module described in Section III (Fig. 2) is synthesized
and integrated in LabVIEW FPGA VI for 1, 2, and 4 ms
coherent integration lengths (Fig. 5).
Fig. 5 shows target LabVIEW FPGA VI, where the stand-
alone acquisition unit is shown as an IP node connected to
DMA FIFOs for communicating with the host VI. Fig. 6 shows
a block diagram of the implemented standalone solution. It
Fig. 4. Application development flow with FPGA compilation steps. includes FFT and a data buffer (RAM), and it is configurable
for multiple FFT sizes. Following the steps of Section III
After creating a LabVIEW FPGA virtual instrument (VI), (Fig. 2), long FFT computation follows by an ordered data
the code must be compiled. Similar to other FPGA develop- placement into a matrix, which is saved in RAM. The general
ment tools, compile time for an FPGA VI can range from address generator controls the sequence of shifts (coarse fre-
minutes to several hours depending on the complexity of quency loop) and elementwise multiplications of columns of
the code and specifications of the development system. To the saved FFT matrix with code replica FFTs. The results are
maximize development productivity, a bit-accurate emulation then passed through the IFFT block to obtain an array of cor-
mode can be used so the logic of the design can be verified relations and detect the correlation peak. Coherent integration
before initiating the compile process. When the FPGA device lengths impact FFT and RAM (buffers) sizes. The performance
emulator is used as a target, then LabVIEW accesses I/O of this design and summary of total hardware utilization is
from the device and executes the VI logic on the develop- presented in Section V. For conformity of data comparison
ment computer. In this mode, it is possible to use the same with other implementations, correlators were placed and routed
debugging tools available in LabVIEW for Windows. Once using 160-MHz timing constraint.
the LabVIEW FPGA code is compiled, a LabVIEW Host VI
is created to integrate the hardware into the rest of the test C. Host-Target Codesign Using LabVIEW FPGA
and control system. Fig. 4 illustrates the development process and Xilinx Core Generator IP Libraries
for creating a FPGA application. The Host VI uses controls
The HDLs provide powerful development environments
and indicators on the FPGA VI front panel to transfer data
but they often require an advanced level of programming
between the FlexRIO FPGA device and the host processing
expertise. For fast prototyping, high level programming tools
engine.
are typically used. One example can be the Xilinx system
generator for the DSP that performs system modeling and
B. LabVIEW FPGA IP Integration Node. Integration automatic code generation from Simulink [36], [42]–[44].
of a Standalone FPGA Acquisition Module Similarly, Xilinx Coregen IP is a toolset of the most
Hardware modules that are developed using HDLs can commonly used predesigned IP nodes for LabVIEW FPGA.
be integrated into LabVIEW FPGA using the IP integration The nodes functions include, e.g., basic arithmetic operations,
node function. To integrate, e.g., a Verilog code in general, accumulators, counters, memory elements, shift registers, fil-
FPGA VI is created and compiled according to the following ters, transforms, modulation, IP related to FIFOs, RAMs, and
steps [35], [42]. ROMs. The inputs and outputs of the IP node should be
1) Create Verilog project, e.g., in the Xilinx integrated initialized according to [45]. Thus, the FPGA solutions can
software environment, then use the Xilinx Synthesis be designed using an integration of both predesigned library
Technology tool to synthesize the project into NGC blocks and external modules.
netlist. This section demonstrates a straightforward host-target
2) Integrate NGC netlist inside the LabVIEW FPGA codesign example of fast prototyping for the case study acqui-
project using the IP integration node and configure the sition module. As it is explained in Section III, the significant
node. Connect it to the rest of the VI design. computational load share is due to iterative IFFT operations.
3) Select project execution mode: FPGA target or simula- For this reason, the IFFT is computed on the FPGA target.
tion. Standard FFT/IFFT modules are available in both LabVIEW
4) For FPGA target execution, compile the LabVIEW FPGA and Xilinx Coregen IP libraries. One module is used for
FPGA VI. During compilation, the Xilinx mapping tool both FFT and IFFT, and in the Xilinx module it is configured
configures logic fabric in the target FPGA according by properly setting the FWD_INV input.
to the previously generated netlist. Then, the Xilinx In host-target codesign, there are two VIs, one for host
placing and routing (PR) tool iterates PR of contiguous section and another for the target section. Fig. 7 shows the
SOGHOYAN et al.: DEVELOPMENT AND TESTING INSTRUMENTATION FOR GPS SDR WITH FAST FPGA PROTOTYPING SUPPORT 2007

Fig. 5. Standalone FPGA acquisition module implementation and integration with LabVIEW-based SDR using IP node in LabVIEW FPGA VI. DMA FIFOs
connect FPGA module with the host. Tick counters are included for performance evaluations.

c) Additional selections such as Use 4-multiplier

structure and Use XtremeDSP slices, and so forth.
3) Generate IP node.
4) Set IP node boolean input parameter FWD_INV to True
for FFT or False for IFFT.
5) Connect to the rest of the VI.
A more detailed description of the FFT node from the
Xilinx CORE generator is given in [45]. The clock rate for
the FPGA VI in a single cycle timed loop is 160 MHz. The
host application is benchmarked or profiled using LabVIEW
profiling tools [21] for performance evaluations.
Similar FPGA library modules are available in LabVIEW
FPGA, which provides the same graphical programming envi-
ronment for the creation of FPGA VI as LabVIEW does for
standard VIs. The FPGA modules can also run independently.
Fig. 6. Block diagram of the standalone FPGA acquisition module
(Section III) using Xilinx IP Cores, which is integrated with host section It is possible to implement buffers and FIFOs on target FPGA
as shown in Fig. 5. to store data until the host computer can retrieve it. Another
advantage of the FPGA module is parallel execution capability
section of the acquisition module, which is deployed on the of independent module operations. For example, multiple-
host VI. Fig. 8 shows the target VI section, a single cycle timed independent while loops on a LabVIEW block diagram may
loop block diagram. One can note READ / WRITE DMA FIFOs execute independently when implemented on FPGA.
in both sections, these modules connect both sections. The For performance evaluation, the block diagram in Fig. 8
IFFT IP node in Fig. 7 is from the Xilinx Codegen IP library. includes the start and end tick counts that are taken to bench-
Fig. 7 highlights specific inputs/outputs (1–7) of this module, mark the FPGA VI, as the profiling tools are not available on
which are similar to those of the library IFFT module from the target. IFFT modules of both Coregen IP and LabVIEW
LabVIEW FPGA (Fig. 9). Thus, both library units can be used. FPGA are tested at 160-MHz device clock rate.
A selection and integration of a Xilinx Coregen IP library
module on the example of IFFT can be described using the V. P ERFORMANCE A NALYSIS
following steps.
The proposed designs achieve 160-MHz FPGA operation.
1) In FPGA VI functions palette, select Xilinx Coregen Either profiling or benchmarking methods can be used for
IP → Digital Signal Processing → Transforms → Fast performance evaluations in LabVIEW. Profiling resolution
Fourier Transform. is in microseconds, but one can only evaluate performances
2) Configure IP page is opened. from the host side, including target operations and host-
a) Select Transform Length (e.g., 2048) and Target to-target communication. To evaluate the performance of
Clock frequency (e.g., 160 MHz). the target operations only, a benchmarking concept is used.
b) Define the inputs with their data formats (e.g., Fig. 3 illustrates the concept of code benchmarking for the
Integer 8 data type, Unscaled, Natural Order). acquisition module implemented using native LabVIEW
2008 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 63, NO. 8, AUGUST 2014

Fig. 7. Host VI section of the host-target co-design of the acquisition module described in Section III. The DMA FIFOs connect to the IFFT module, which
is implemented on FPGA target using library blocks. Target VI is in Fig. 8.

Fig. 8. Target VI section of the host-target co-design of the acquisition module described in Section III. The IFFT IP module is from Xilinx Codegen IP
and can be replaced with LabVIEW FPGA IFFT function module of Fig. 9. The IFFT communicated with host VI using DMA FIFOs connect.

function blocks (software). The code is divided into three

parts (so-called frames) using Flat Sequence structure in
the LabVIEW block diagram. The first and the last frames
contain timestamp generators (tick counters) with the code to
be benchmarked in the center. The actual timing figures are
obtained using the clock rate of the timing loop structure.
The performance figures are obtained for the following Fig. 9. IFFT module from LabVIEW FPGA function library. This unit can
implementations. replace IFFT IP node from Codegen IP in Fig. 8, with corresponding inputs
and outputs shown on both figures.
1) Software only: a) standalone C/C++; b) C/C++ inte-
grated in LabVIEW with Call library function node; and computing IFFTs (from Coregen IP) on the target; and
c) implementation using native LabVIEW blocks. d) the same as c) but using IFFTs from LabVIEW FPGA
2) Host-target co-design: a) standalone FPGA implemen- function library.
tation integrated as IP node in LabVIEW FPGA,
evaluated in LabVIEW; b) standalone FPGA imple- A. IFFT Implementation Performance
mentation evaluated using Xilinx tools on Virtex-5 As described in the previous section, two alternative host-
target; c) LabVIEW-based host-target implementation target co-design implementations delegate IFFT computations
SOGHOYAN et al.: DEVELOPMENT AND TESTING INSTRUMENTATION FOR GPS SDR WITH FAST FPGA PROTOTYPING SUPPORT 2009

TABLE II TABLE III

IFFT I MPLEMENTATION P ERFORMANCES P ERFORMANCE OF A CQUISITION I MPLEMENTATION ON THE H OST

TABLE IV
P ERFORMANCE OF THE H OST-TARGET A CQUISITION C ODESIGN
to the target and use IFFT FPGA modules either from Coregen
IP or native LabVIEW FPGA libraries. From this perspective,
it is informative to benchmark IFFT performances. Table II
shows performance figures for IFFT computation on the tar-
get for these two modules along with native software FFT
functions in LabVIEW and in MS Visual Studio. One can see
that the implementation in the MS Visual Studio platform is
slower than the LabVIEW software function due to inherent
multithreading and multicore programming capabilities of the
current LabVIEW environment. The FFT operation is faster on
the FPGA targets, and performance figures show that Coregen
IP node implementation is more optimized.

B. Acquisition Algorithm Performance

In all methods, FFT-based acquisition is used as described in
Section III and Fig. 2. The system searches for 24 satellites, in
±10-kHz Doppler frequency range, receiver sampling rate of
2.048 MHz. As it is described in Section III, the frequency bin
resolution is 1/N2 kHz, where N2 is the coherent integration Table III shows that C/C++ implementation completes in
length in code periods (millisecond). In our experiments, 0.688 s for 4-ms signal duration. The same implementation can
N2 is 1, 2, and 4. Forward long length FFT is computed only run in LabVIEW using dynamic library function integration
once on the host. Inverse FFTs are computed for all frequency with a similar performance. The implementation using native
bins and satellites. For this reason, IFFTs’ share of computa- LabVIEW blocks is significantly faster (0.172 s) because
tion complexity prevails and justifies their computation on the of inherent LabVIEW optimizations exploiting multithreading
FPGA target. The target modules are all implemented in fixed- and multicore operations.
point arithmetic. The actual timing figures are obtained using Table IV shows performance figures for host-FPGA-target
the clock rate of the timing loop structure. codesign. When delegating the IFFT computing from the host
The performance figures are obtained for the following to the FPGA target, the overall runtime of the acquisition
implementations (Tables III and IV). algorithm is approximately twice as fast as the same algorithm
1) Software only: a) standalone C/C++; b) C/C++ inte- implemented using LabVIEW native function blocks only,
grated in LabVIEW with Call library function node; and comparing numbers in Tables III and IV.
c) implementation using native LabVIEW blocks. The implementation using IFFT from the Xilinx CORE
2) Host-target co-design: a) standalone FPGA implemen- generator IP (second entry of Table IV) is two times faster
tation integrated as IP node in LabVIEW FPGA, than the one using IFFT from the LabVIEW FPGA library
evaluated in LabVIEW; b) standalone FPGA implemen- (first entry of Table IV).
tation evaluated using Xilinx tools on Virtex-5 target; For comparison purposes, the third and fourth entries of
c) LabVIEW-based host-target implementation comput- Table IV show a standalone acquisition implementation on the
ing IFFTs (from Coregen IP) on the target; and d) FPGA without host-target separation of the acquisition unit.
the same as c) but using IFFTs from LabVIEW FPGA Their performance is the same and comparable with host-target
function library. codesign using Coregen IP (second entry of Table IV).
2010 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 63, NO. 8, AUGUST 2014

TABLE V
D ETAILED H ARDWARE C OST FOR A CQUISITION C ORRELATORS ON X ILINX V IRTEX -5

Thus, host-target co-designs may serve viable implementation taking tens of second for the simulation. Implementations in
alternatives. [44] and [47] addressed implementation feasibility in Simulink
Table V summarizes FPGA resources for the standalone rather than performance studies. Another FPGA solution using
implementation for coherent correlation lengths of 1, 2, and the Xilinx system generator for the DSP called from Simulink
4 ms. The increase of correlation lengths increases FFT is demonstrated in [48]. We implemented a standalone
calculation and memory usage resources. FFT-based PCS algorithm for 1-ms correlator integration
lengths on Xilinx Virtex-II Pro FPGA. The reported design
VI. D ISCUSSION IN THE C ONTEXT OF S TATE - OF - THE -A RT achieved a clock speed of 100 MHz, and execution time
Various GPS acquisition implementation modes with Lab- is 0.63 s for 21 frequency bins and 16.3676-MHz sampling
VIEW FPGA are demonstrated in previous sections. Par- rate. A similar Simulink-based standalone FPGA solution for
ticularly, by simply delegating IFFT computations to the Virtex4SX35 is reported in [49] mentioning only computation
FPGA target, one can achieve the performance of standalone time of 1 ms for 1.023-MHz sampled signals for a single satel-
FPGA solutions. Proposed LabVIEW FPGA-based host-target lite. We do not indicate if this number is for all Doppler bins.
codesign solutions are not compared with standalone solutions Assuming the all Doppler bins search scenario, 24 satellites
in terms of hardware resources, as only IFFT modules are will be processed in at least 24 ms. Implementations reported
implemented on the target using standard library functions, and in this paper significantly outperform mentioned solutions
any other FFT-based implementation should include similar achieving 160-MHz operation and faster execution times as
modules. Thus, the focus is on computation time. At the shown in Table IV.
same time, use of hardware resources is summarized for the Conventional FPGA implementations are also reported in
standalone solution in Table V. [50]–[52]. [50] operates at frequencies up to 56.14 MHz with
When comparing to other reported FPGA GPS acquisition computing times more than 1ms per frequency bin for each
solutions, one should note that the implemented algorithm satellite on Virtex II Pro. It results in at least 0.5 s to acquire
is an enhanced version of commonly used PCS approach, 24 satellites for a 1.024-MHz sampling rate and more than
which integrates PCS, coherent integrations over several code one second for higher rates. A conventional PCS design for
periods, and search over frequency bins in a modular and Altera Stratix III FPGA was reported in [52]. For a sampling
computationally efficient solution [39]. The overall conclusion frequency of 2.048 MHz, one satellite is processed in ∼1 s
is that presented acquisition modules, standalone and host- for 1-ms correlation length, which is significantly slower than
target co-designs provide competitive performance figures solutions in this paper. Maximum achieved clock frequencies
using fast-prototyping graphical programming environments. are not reported.
Fast prototyping using graphical programming environ- High performance implementation is presented in [51] for
ments. The proposed solutions demonstrate the feasibility of Virtex II Pro FPGA. Here, 4096 samples are fed to an
LabVIEW FPGA SDR development for GPS as it was earlier FFT-based PCS module, and the results are integrated for
shown for Simulink [46] in [44], [47], and [48]. Numeric 10-ms coherent correlation lengths. Maximum achieved clock
performance details for comparisons were not provided in rate is 155 MHz. The settings of this implementation are quite
[47]. Simulink-only implementation was also shown in [44], different from the designs of this paper and are not compared.
SOGHOYAN et al.: DEVELOPMENT AND TESTING INSTRUMENTATION FOR GPS SDR WITH FAST FPGA PROTOTYPING SUPPORT 2011

Overall, the achieved performance of LabVIEW FPGA host- ACKNOWLEDGMENT

target codesigns is competitive with reported approaches.
The authors would like to thank anonymous reviewers
The proposed standalone solution is the fastest achieving
for valuable comments. This work was partly supported by
∼5-ms acquisition computing time for 1-ms coherent integra-
NSF grants 0942852, 0932339 and UTSA-NEEC Center. The
tions. In [50], the number of block RAMs is 17 for 2048 size
authors would like to thank National Instruments for providing
IFFT. In Table V, the same number is ∼30% less. Furthermore,
an FPGA module for this research.
the block RAM comparison for different size FFTs is almost
identical to the FFT-based correlator implementation in [50].
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Sep. 2008, pp. 2293–2303. and mobile applications.

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