Advanced Topics: IDDQ

• Introduction
• Defect-based Testing
 VLV Testing (1982)
 IDDQ Testing (1981)
 Introduction
 Fault models and test patterns
 IDDQ Measurement
 Experimental Results
 Issues & Solutions
• Advanced ATPG
• Conclusion

1 VLSI Test 18.3 © National Taiwan University

 IDDQ Testing
• What is IDDQ Testing?
 Measure static power supply current, with test patterns applied
 IDD = power supply current from VDD
 Q = quiescent
• Widely used but first officially presented by [Levi 81]
 Still commonly used DBT in CMOS technology so far
• Motivations to use IDDQ
 Improve DPM
 Targeted 3 DPM in early 1990’s
 Improve reliability
 Chips pass Boolean test but may fail early in life

IDDQ is Probably the Most Popular DBT

2 VLSI Test 18.3 © National Taiwan University

 Idea of IDDQ Testing
• Good CMOS circuit, very low IDDQ
• Defective CMOS circuit, high IDDQ
• Example:
 gate oxide short provides a conduction path from VDD to Gnd

3 VLSI Test 18.3 © National Taiwan University

 Why IDDQ Better Than Boolean Testing?
• IDDQ sometimes detects defects missed by Boolean testing
• Example: High impedance bridging defect
 may not detectable by SSF test
 Could be detected by IDDQ test
• FFT: Why bother since it passes Boolean test?
5V

0V 3.9V 0.2V

Logic 0

5V 0.8V 4.8V

Logic 1
High IDDQ
4 VLSI Test 18.3 © National Taiwan University
 Defects Could be Detected by IDDQ
• Bridging/shorts
 Signal to signal bridging
 Signal to power short
 Ground to power short
 Gate oxide shorts
• Vt shift
 Cause increased leakage IDDQ
• …Many more

5 VLSI Test 18.3 © National Taiwan University

 Opens May (Not) Detected by IDDQ
• Open defects: IDDQ depends on floating gate voltage
 Floating single transistor gate
 Floating nMOS+pMOS transistor pair
• Experimental results [Stanford 00]
 Total 5.5 K chips tested, 116 defective chips
 7 chips diagnosed to have opens
 4 high IDDQ, 3 low IDDQ [Li 00]

T1 X T1 T1
X
T2 T2 X T2

6 VLSI Test 18.3 © National Taiwan University

 Defects Not Detected by IDDQ
• Resistive open defects
 Transient signal delay won’t cause high IDDQ
5V

• Feedback bridging fault

 Even parity

IDDQ Cannot Defect ALL Defects

7 VLSI Test 18.3 © National Taiwan University
 Advanced Topics: IDDQ
• Introduction
• Defect-based Testing
 VLV Testing (1982)
 IDDQ Testing (1981)
 Introduction
 Fault models and test patterns
 IDDQ Measurement
 Experimental Results
 Issues & Solutions
• Advanced ATPG
• Conclusion

8 VLSI Test 18.3 © National Taiwan University

 Fault Models for IDDQ
• Test pattern generation requires fault models
 However, IDDQ detects different types of defects
 No universal fault model good for all defects
• Popular fault models for IDDQ
 Transistor stuck-on faults
 Pseudo stuck-at faults
 Bridging faults
 Leakage faults
 …

1 X T1 0 T1

T2 X T2

9 VLSI Test 18.3 © National Taiwan University

 Test Patterns for IDDQ
• Test patterns can be either
generated by ATPG or
 selected from existing patterns
• Test length must be short because IDDQ testing is slow
• Commercial ATPG tools can support these test sets
 Toggle test set
 Pseudo Stuck-at (PSA) test set
• Example: 100% toggle test set for NAND gate
PO
PPO
AB C
CL A C
00 1 CL
11 0
CL B

10 VLSI Test 18.3 © National Taiwan University

 Pseudo Stuck-at Test Set
• Definition

Test set that activate SSF
 but fault effects need NOT propagate to PO or PPO
• No propagation because IDDQ can be measured by current
• Example: 100% pseudo stuck-at test set for NAND gate
 AB = 01, 10, 11
PO
AB SSF faults PPO
01 A/1;C/0 CL A C
CL
10 B/1;C/0
11 A/0; B/0; C/1 CL B

IDDQ Test Length Must be Short

11 VLSI Test 18.3 © National Taiwan University

 Quiz
Q: Please select three best toggle test patterns for IDDQ
A:

A B C E H J K
P1 1 1 0 1 1 0 0
P2 0 0 0 0 0 1 0
P3 1 0 1 1 1 0 0
P4 0 0 1 1 0 0 1

12 VLSI Test 18.3 © National Taiwan University

 Advanced Topics: IDDQ
• Introduction
• Defect-based Testing
VLV Testing (1982)
 IDDQ Testing (1981)
 Introduction
 Fault models and test patterns
 IDDQ Measurement
 Experimental Results
 Issues & Solutions
• Advanced ATPG
• Conclusion

13 VLSI Test 18.3 © National Taiwan University

 IDDQ Measurement
• Three ways to measure IDDQ

ATE ATE

Current Supply
Monitor BICS

CUT CUT CUT

I. ATE II. External device III. On-chip

on Test Fixture Built-In
Current Sensor
14 VLSI Test 18.3 © National Taiwan University
 I. ATE
• Most ATE support IDDQ measurements
Precise measurement Unit (PMU)
• Procedures
 1. apply test pattern
 2. pause at pre-selected patterns
 3. wait about 1~10 ms until CUT internal nodes stable
 4. measure IDDQ current
 FAIL if larger than user defined threshold
 5. continue applying patterns, loop back to step 2
• ☺ Advantages
 No extra equipment needed. No design change
•  Disadvantages
 Long test time. Large background leakage current

15 VLSI Test 18.3 © National Taiwan University

 III. BICS
• ☺ Self testable •  Performance degradation
• ☺ Easy to Partition CUT •  Area overhead

VDD'

-
A M
+ Pass
IDD I0
Current /Fail
VDD
CUT measure
Vref
(partitioned) Iref

Vss
Current Mirror IDD ~ I0

16 VLSI Test 18.3 © National Taiwan University

 Advanced Topics: IDDQ
• Introduction
• Defect-based Testing
VLV Testing (1982)
 IDDQ Testing (1981)
 Introduction
 Fault models and test patterns
 IDDQ Measurement
 Experimental Results
 Issues & Solutions
• Advanced ATPG
• Conclusion

17 VLSI Test 18.3 © National Taiwan University

 Experimental Results
• HP experiment [Maxwell 92]
 26,415 dies, CMOS static logic, 8,577 gates
 IDDQ pass/fail threshold = 30mA
 4,171 (15.8%) failed IDDQ, 1,358 (5.1%) failed IDDQ only

IDDQ Distribution

fail

Some Defects Only Detected by IDDQ

18 VLSI Test 18.3 © National Taiwan University
 IBM Experiment [Nigh 00] [Mann 08]

Higher IDDQ, More Unreliable

19 VLSI Test 18.3 © National Taiwan University
 Advanced Topics: IDDQ
• Introduction
• Defect-based Testing
VLV Testing (1982)
 IDDQ Testing (1981)
 Introduction
 Fault models and test patterns
 IDDQ Measurement
 Experimental Results
 Issues & Solutions
• Advanced ATPG
• Conclusion

20 VLSI Test 18.3 © National Taiwan University

 Issues of IDDQ testing
• Long measurement time
Several ms per measurement on a ATE
• Trade off yield loss and reliability
 IDDQ only failure chips
• Not applicable to all designs
 Analog, mixed-signal, memory
• Losing effectiveness in advanced technology
 Increasing background leakage current
 Hard to set single threshold

21 VLSI Test 18.3 © National Taiwan University

 Where Are Leakage Currents?

Gate leakage

Sub-threshold
leakage
Junction
[Keshavarzi 97]
leakage

22 VLSI Test 18.3 © National Taiwan University

 Where is the Threshold?
• Mg-Md get closer [Williams 96]
Year Road map

1995 19.6%

1998 3.15%

2001 1.28%

2004 0.37%

2007 0.07%

23 VLSI Test 18.3 © National Taiwan University

 Possible Solutions for IDDQ (1/2)
• Reducing background Leakage
 FinFET [Hu ‘98]
 Substrate back-biasing (2500x - 4400x improvement)
 Low temperature (350 x improvement)
 Multiple Vt
 high Vt (low leakage) logic gates on non-critical paths
 Circuit Partition
 Built-In Current Sensor

24 VLSI Test 18.3 © National Taiwan University

 Possible Solutions for IDDQ (2/2)
• IDDQ data processing. Avoid single threshold
 Pass/fail decision made by processing collected IDDQ data
 No preset single threshold

• Example data processing techniques

  IDDQ [Powell 00]
  IDDQ = IDDQ max – IDDQ min
 Fail this test if  IDDQ larger than limit
 Current Ratio [Maxwell 00]
 Spatial Analysis [Daasch 00]

Pass Fail

IDDQ IDDQ

25 VLSI Test 18.3 © National Taiwan University

 Current Ratio [Maxwell 00]
• Measure all IDDQ (without single pass/fail threshold)
• Plot IDDQ max v.s. IDDQ min of many chips
 IDDQ max = K IDDQ min + Intercept + 3σ
• Outliers fail the test

outliers

26 VLSI Test 18.3 © National Taiwan University

 Spatial Analysis [Daasch 00]
• Idea: IDDQ correlates to die neighbors
• Nearest Neighbor Residue (NNR) method
 Record all IDDQ data on a whole wafer
 Estimate a die’s IDDQ with the IDDQ of its neighbors
 Fail the test if its measured IDDQ very different from estimated IDDQ

Maybe bad

Maybe good

27 VLSI Test 18.3 © National Taiwan University

 Quiz
Q: Which of following is NOT correct ?

A: IDDQ can still be used with careful data analysis

B: IDDQ is lower at lower temperature

C: Chips fail IDDQ are all defective

28 VLSI Test 18.3 © National Taiwan University

 Summary: IDDQ Testing
• IDDQ testing improve reliability and DPM
• IDDQ test patterns
 Toggle test, Pseudo stuck-at test
• Solutions to enhance effectiveness of IDDQ
  IDDQ , Current Ratios, Spatial Analysis
• Experimental data
 Higher IDDQ more likely to fail after burn in

Each Test Detects Unique Defect

29 VLSI Test 18.3 © National Taiwan University

 FFT
• Why bother to detect this defect since it passes Boolean test?

5V
0 3.9V 0.2V
Logic 0

1 4.8V
0.8V Logic 1
High IDDQ

30 VLSI Test 18.3 © National Taiwan University

 References
• [Daasch 00] Daasch, “Variance Reduction using Wafer Patterns in IDDQ
Data,” ITC pp. 189-198,2000.
• [Keshavarzi 97] A. Keshavarzi and et. Al., “Intrinsic Leakage in Low Power
Deep Submicron CMOS Ics,” ITC, pp.146-155, 1997.
• [Levi 81] M. W. Levi, “CMOS is most testable,” in Int. Test Conf., 1981,
pp.217–220
• [Mann 08] W. R. Mann, “Wafer Test Methods to Improve Semiconductor Die
Reliability,” IEEE Design & Test of Computers, pp528-537, 2008.
• [Maxwell 00] P.Maxwell et al, “Current Ratios: A self Scaling Technique for
Production IDDQ Testing”, ITC 2000
• [Maxwell 92] P.Maxwell, et. al., “The Effectiveness of Iddq, Functional and
Scan Tests: How Many Fault Coverages Do We Need?” Proc. ITC, pp. 168-
177, 1992.
• [Nigh 00] P. Nigh and A. Gattiker, "Test Method Evaluation Experiments and
Data", Proc. Int'l Test Conf. (ITC 00), pp. 454-462, 2000.
• [Williams 96] T. Williams and et. al., “IDDQ Test: Sensitivity Analysis of
Scaling,” ITC, 1996.

31 VLSI Test 18.3 © National Taiwan University