Power-Aware Signal Integrity Analysis of DDR4

Data Bus in Onboard Memory Module

Anil Kumar Pandey
EEsof, Keysight Technologies
Gurgaon, India
[email protected]

Abstract— Designing data channels for the DDR4 memory is a before actual fabrication of board. This reduces board failure
challenging due to high data rates of 3.2GB/s per data signal at a chances significantly and also cut production time.
low-voltage of 1.2V The coupling of simultaneous switching noise
(SSN) in data signals in DDR4 memory modules is a critical In signal integrity, the main objective is to make sure that
signal and power integrity (SI/PI) problem. It is important to transmitted 1s and 0s look like same at the receiver. In power
catch SI and PI problems at an early stage in design that requires
fast and accurate power-aware signal integrity analysis. In this
integrity, the main objective is to make sure that the ICs are
paper, power-aware signal integrity (PI-SI) analysis of data provided with suitable current to send and receive 1s and 0s.
group signals of an onboard DDR4 memory module using power- In DDR4 signaling is single ended like DDR3 but data lines
aware IBIS model is presented. DDR4 power plane and data have moved closer towards point-to-point interconnect and the
signals are analyzed using 3D Electromagnetic based PI-SI solver interface on the controller side. On the power design front,
then the transient simulation is performed on combined PI data DDR4 systems use very-low-voltage signaling (1.2V).
of power plane and data signals to get simultaneously switching
noise (SSN) response of data bus and crosstalk between nearby II. POWER-AWARE ANALYSIS WORKFLOW
channels.
In power-aware SI analysis, the effects of the data signal
and non-ideal power and ground planes are considered when
Keywords— power integrity; power-aware signal integrity
analysis; electromagnetic simulation; channel simulation analyzing high-speed DDR4 memory interfaces. This paper
shows how EDA tool can be used to address power-aware SI
I. INTRODUCTION challenges associated with DDR4 I/O modeling and
Power-Aware signal integrity analysis of DDR4 data bus is interconnect. In power-aware SI analysis, both power plane
(PI Analysis) and data signals (SI Analysis) are analyzed. The
necessary for the channel reliability and robustness. In high-
power-aware SI performance of DDR data bus is evaluated
speed digital (HSD) boards due to simulation tools limitation, using Keysight’s SIPro/PIPro simulation tool.
power integrity, and signal integrity analysis are performed
separately. The complete data channel performance is the HSD board presented in this paper is a 12 layer board with
cumulative effect of whole interconnect environment that 1.2V power distribution networks (PDN) supplying power to
consists of transceiver ICs, power planes, bond wires, board DDR4 controller and 5 memory blocks. The main objective of
PI-SI analysis is to study the SI/PI effects among DDR4 IO
substrate, data lines and board interconnects that’s why it’s
buffers, channel, and DRAM device. The workflow of power-
necessary to consider power plane generated noise effect in aware signal integrity analysis on HSD layout design is shown
data channel signal integrity analysis. in fig. 1. Power plane impedance is optimized within target
impedance level using PI analysis of power plane.
In high-speed digital boards, to reduce the parasitics of the
power supply, as well as to increase high-frequency
decoupling several power and ground planes are placed in an
alternating manner. Data signal lines are routed between these
plane pairs. At high-speed it’s crucial to characterize both
power delivery network and data bus and accurately account
the power supply induced jitter to minimize power supply
noise in the system. Mainly high-speed design failures are data
error rates, cross talk errors, power plane noise coupling to
signal causing errors and EMI errors. SI engineers do power-
aware SI analysis of channel to ensure proper and reliable
operation using Electronic Design Automation tools (EDA) Fig. 1. Power-Aware Analysis workflow

978-1-5090-0349-5/16/$31.00 ©2016 IEEE

 III. POWER INTEGRITY ANALYSIS OF DDR4 POWER PLANE from nominal voltage) is a sum of both DC IR drop and AC
DDR4 1.2V power plane is used in power integrity noise. AC analysis is carried out to find out PDN impedance
analysis. There are 6 I/O devices connected to the 1.2V power seen from the IC. The voltage regulator module (VRM)
plane, controller IC and 5 DDR4 memory blocks as shown in provides 1.2V, the IC pulls total 2 Ampere current and a 5%
fig. 2. tolerance on the supply voltage is allowed up to around 1GHz.
The PDN impedance and target impedance is shown in fig. 4.
Target impedance (30 milliohms) is the green dashed line.
At higher frequency, the target impedance specification is
more relaxed and rises with frequency.

Fig. 2. On Board DDR4 memory blocks and 1.2V power plane

A. DC Simulation
DC-PI guarantees that adequate DC voltage is delivered to
Fig. 4. PND impedance profile of 1.2V power plane
all active devices mounted on a PCB. This simulation helps to
assure that required criteria for current density in power plane The target impedance is not met above 10 kHz and this will
are met. DC-PI is governed by metal resistance and the current
produce voltage ripples. The voltage ripple can be reduced by
pulled from the PDN by each ICs. Voltage distribution of DC
placing decoupling capacitors. AC simulation gets an effective
PI simulation on power plane is shown in fig. 3.Maximum power solution by iterating capacitor quantity and distribution.
voltage drop is 36 millivolt that is within 5% allowed
After placing 7 decoupling capacitors, the result of target
tolerance limit.
impedance 0.1 Ohms is achieved.
IV. POWER-AWARE SIGNAL INTEGRITY ANALYSIS
The noise in the power distribution network mainly affects
the system jitter performance. This causes degradation in
signal quality. The power-Aware signal integrity of DDR4
interfaces, such as inter-symbol interference ISI, reflection,
and signal cross talk, needs to be minimized in order to meet
an ever shrinking timing budget. SI and PI co-design
optimization is driven by both channel performance and
overall system cost. For horizontal & vertical transitions, like
wire bonds, via array, and solder balls of package and PCB,
3D models were generated for SI/PI simulations combining
signal and PDN models together. Combined EM simulated S-
parameter result of 16 Data bus lines (DQ lines), 2 differential
clock pairs, 2 differential strobe line pairs (DQS) and 1.2 V
power plane of DDR4 memory block is shown in fig.5.
Fig. 3. DC simulation Result of 1.2V Plane showing Voltage distribution on
power plane EM simulated data is extracted for DDR4 data group
signals and combined with power-aware IBIS 5.0 model of
controller IC and DDR4 memory in Advance Design System
B. AC Simulation (ADS) for transient simulation. IBIS(Input/output Buffer
AC-PI concerns the delivery of AC current to mounted Information Specification) models are a behavioral model
devices to support their switching activity while meeting using I-V and V-t look-up tables that make simulations
constraints for transient noise voltage levels within the power extremely fast. Power-Aware IBIS v5.0 models are used to
delivery network (PDN). The PDN noise margin (variation
represent the non-ideal power effects. There are two BIRDs is more closed in PI-SI analysis because of power plane noise
related to the power awareness of the IBIS v5.0 models. (jitter) that deteriorate signal quality. The bathtub plot is
- BIRD is 95.6: Power Integrity Analysis using IBIS another way to look at jitter and analyze its timing. By plotting
- BIRD is 98.3: Gate Modulation Effect BER as a function of sampling position within the bit interval,
the bathtub plot represents eye opening versus BER as shown
in fig. 8.

Fig. 5. Extracted DDR4 Data Bus and Power Plane S-parameters from PI-SI

Fig. 8. (a) Bathtub curve plot showing jitters (b) DQ0 data line waveform (c)
Transient simulation setup for one data signal with IO Voltage noise at controller IC (d) Voltage noise at DDR4 memory
drivers IBIS model and VRM connected to power plane is
shown in fig.6. PI-SI analysis considers the effect of direct V. SIMULTANEOUS SWITCHING NOISE (SSN) ANALYSIS
interaction between the currents flowing in the PDN and the Simultaneous switching noise (SSN) is a major component
current flowing through the signal lines.

Fig. 6. Transient simulation setup for DQ0 data line using IBIS 5.0 power-
aware model

The noise is transferred from one signal line to another as a

power-aware IBIS model for the driver is used. The supply
Fig. 9. Transient simulation setup of SSN analysis by exciting all 16 data
current for driving one signal line will cause voltage noise at lines of DDR4 memory
the power pin of the drivers of the other signal lines what will
impact their rise time, this is simultaneous switching noise. in signal and power integrity analysis. Simultaneous switching
noise (SSN) is caused by a number of signals transitioning
simultaneously. This causes an instantaneous current demand
on the power distribution network as well as the signal’s
output pad. In SSN analysis, all data signals along with power
plane are excited simultaneously. Transient simulation setup
of SSN analysis is shown in fig. 9.

Voltage noise on the IO power supply degrades signal

timing and operation and SSN is a major cause of power
Fig. 7. EYE diagram with and without Power-Aware SI simulation supply noise. Simultaneously Switching increases the ground
voltage within the device. This non-zero voltage shift in the
Eye diagram comparison of DDR4 data bus DQ0 with and ground potential is known as simultaneous switching noise
without power-aware SI simulation is shown in fig. 7. The eye (SSN) or ground bounce. The signal waveform at controller
and memory IC is measured to know timing and voltage In Inter Signal Interference (ISI) simulation, only the victim
degradation as shown in fig.10. data signal is transmitting while all other data signals are kept
quiet. In crosstalk analysis, all data signals are transmitting but
aggressor and victim lines transmit different data patterns. In
DDR4 where multiple active lines switch simultaneously,
crosstalk can induce power/ground noise. Crosstalk simulation
setup on 3 nearby data signals DQ0, DQ10, and DQ11 are
shown in fig. 11(a). Here DQ11 is victim signal while DQ0 and
DQ10 are aggressors. Fig. 11(b) shows Far-end Crosstalk
(FEXT) value 21 mV and Near-end Crosstalk (NEXT) value
19 mV that is within an acceptable limit of DDR4 data
signaling.

VII. CONCLUSION

In this work power-aware signal integrity analysis of a 12

layer, onboard DDR4 Data bus is presented. DC and AC
Fig. 10. SSN Analysis Result
simulation are performed in SIPro/PIPro to know maximum
voltage drop and PDN impedance profile. DDR4 1.2V power
VI. DDR4 DATA BUS ISI AND CROSSTALK ANALYSIS plane and data signals are analyzed using 3D electromagnetic
based PI-SI solver then the transient simulation is performed
Crosstalk (XT) refers to any condition by which a signal
by using power-aware IBIS 5.0 models to know the actual
transmitted on one channel creates an undesired effect in
value of power plane noise introduced in the data signal. The
another channel. There is two type of crosstalk
coupling of simultaneous switching noise (SSN) in data signals
a. Near-end Crosstalk (NEXT) - is the noise introduced in a in DDR4 memory modules analyzed by exciting all the 16 data
channel from a neighboring channel on the same end of lines simultaneously. Crosstalk for 3 nearby data signals is
transmission lines analyzed using power-aware IBIS models.
b. Far-end Crosstalk (FEXT) - is the noise introduced in a
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(a)

(b)
Fig. 11. (a) Crosstalk simulation setup (b) Near-end crosstalk (NEXT) and
Far-end crosstalk (FEXT) simulation result