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11-Verilog HDL Coding and Summary of Module-3-12-06-2024

11-Verilog HDL coding and Summary of Module-3-12-06-2024

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51 views

11-Verilog HDL Coding and Summary of Module-3-12-06-2024

11-Verilog HDL coding and Summary of Module-3-12-06-2024

Uploaded by

sedhupathirajendranofficial
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BECE102L – Digital Systems Design

Module 3 – Design of Combinational Logic Circuits

Dr. Rohit Mathur


Assistant Professor Sr. Grade 1
School of Electronics Engineering

Digital System Design 1


Decoder_3x8 with enable

module decoder_3x8en(a,b,c,en,d);
input a,b,c,en;
output [7:0]d;
assign d[0] = en & ~a & ~b & ~c;
assign d[1] = en &~a & ~b & c;
assign d[2] = en &~a & b & ~c;
assign d[3] = en &~a & b & c;
assign d[4] = en &a & ~b & ~c;
assign d[5] = en &a & ~b & c;
assign d[6] = en &a & b & ~c;
assign d[7] = en &a & b & c;
endmodule Digital System Design Lab 2
Test Bench

module decoder_3x8en_tb;
reg a,b,c,en; #20 en=1;a=1;b=1;c=1;
wire [7:0]d; #50 $stop;
decoder_3x8en d4(a,b,c,en,d); end
initial begin endmodule
// Initialize Inputs
#20 en=1;a=0;b=0;c=0;
#20 en=1;a=0;b=0;c=1;
#20 en=1;a=0;b=1;c=0;
#20 en=1;a=0;b=1;c=1;
#20 en=1;a=1;b=0;c=0;
#20 en=1;a=1;b=0;c=1;
#20 en=1;a=1;b=1;c=0; Digital System Design Lab 3
Decoder 4x16 using two 3x8 with enable

module decoder4x16u3x8en(a,b,c,en,d);
input a,b,c,en;
output [16:0]d;
wire nen;
assign nen=~en;
decoder_3x8en d1(a,b,c,nen,d[7:0]);
decoder_3x8en d2(a,b,c,en,d[15:8]);
endmodule

Digital System Design Lab 4


Test Bench

module decoder4x16u3x8en_tb; #20 en=0;a=1;b=1;c=0;


reg a,b,c,en; #20 en=0;a=1;b=1;c=1;
wire [15:0]d; #20 en=1;a=0;b=0;c=0;
decoder4x16u3x8en d4(a,b,c,en,d); #20 en=1;a=0;b=0;c=1;
initial begin #20 en=1;a=0;b=1;c=0;
// Initialize Inputs #20 en=1;a=0;b=1;c=1;
#20 en=0;a=0;b=0;c=0; #20 en=1;a=1;b=0;c=0;
#20 en=0;a=0;b=0;c=1; #20 en=1;a=1;b=0;c=1;
#20 en=0;a=0;b=1;c=0; #20 en=1;a=1;b=1;c=0;
#20 en=0;a=0;b=1;c=1; #20 en=1;a=1;b=1;c=1;
#20 en=0;a=1;b=0;c=0; #50 $stop;
#20 en=0;a=1;b=0;c=1; end
Digital System Design Lab endmodule 5
Full adder using 3x8 decoder

Module fa_decoder_3x8(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire [7:0]d;
decoder_3x8 d1(a,b,c,d);
assign sum= d[1] | d[2] | d[4]| d[7];
assign carry= d[3] | d[5] | d[6]| d[7];
endmodule

Digital System Design Lab 6


4:1 MUX

Data flow Modelling


module m41_df(ab,c,d,s0,s1,y) ;
input a,b,c,d,s0,s1;
output y;
assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule

Digital System Design Lab 7


Behavioural Modelling (Case statement)

module m41_beh_case(a, b, c, d, s0, s1, y);


input wire a, b, c, d;
input wire s0, s1;
output reg y;
always @ (a or b or c or d or s0, s1)
begin
case (s0 | s1)
2'b00 : y = a;
2'b01 : y = b;
2'b10 : y = c; endcase
2'b11 : y = d; end
endmodule
Digital System Design Lab 8
8:3 encoder

Structural Modelling
module encoder_str
(d0,d1,d2,d3,d4,d5,d6,d7,q0,q1,q2);
input d0,d1,d2,d3,d4,d5,d6,d7:
output q0,q1,q2;
or g1(q0,d1,d3,d5,d7);
or g2(q1,d2,d3,d6,d7);
or g3(q2,d4,d5,d6,d7);
endmodule

Digital System Design Lab 9


8:3 encoder

Dataflow Modelling
module encoder83df(din, a, b, c);
input [0:7] din;
output a,b,c;
assign a=din[4] | din[5] | din[6] | din[7];
assign b=din[2] | din[3] | din[6] | din[7];
assign c=din[2] | din[4] | din[6] | din[7];
endmodule

Digital System Design Lab 10


8:3 encoder

Behavioural Modelling
module encoder _beh(din, dout);
input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
always @(din)
begin
if (din ==8'b00000001) dout=3'b000;
else if (din==8'b00000010) dout=3'b001;
else if (din==8'b00000100) dout=3'b010;
else if (din==8'b00001000) dout=3'b011;
else if (din==8'b00010000) dout=3'b100;
else if (din ==8'b00100000) dout=3'b101;
else if (din==8'b01000000) dout=3'b110;
else if (din==8'b10000000) dout=3'b111;
else dout=3'bX;
end
endmodule
Digital System Design Lab 11
FULL SUBTRACTOR USING 4:1 MUX

module fS_mux(diff,Bout,a,b,Bin);
output diff,Bout;
input a,b,Bin;
wire x1;
not N1(x1,a);
m41_str M1(diff,a,x1,x1,a,cin,b);
m41_str M2(Bout,0,x1,x1,1,cin,b);
endmodule

Digital System Design Lab 12


4:1 MUX USING 2:1 MUX

module m41_using21(y, a, b, c, d, s0,


s1);
output Y;
input a,b,c,d,s0,s1;
wire x1;
m21_str M1(a,b,s1,x1);
m21_str M2(c,d,s1,x2);
m21_str M3(x1,x2,s0,y);
endmodule

Digital System Design Lab 13

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