Flip flops in sequential circuits

Arpan Baul

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BCA - 1 year
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CA - 2 Report writing
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Digital Electronics
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 Acknowledgement
I am obliged to be a part of this project; this has been a helpful
learning experience for me throughout the planning and Writing
this report .I would like to express my gratitude and Special
Thanks to our teacher Mrs. Reshmi Maulik for giving me this
opportunity and guiding me in every step towards the success of
this project.

Contents
Introduction
SR Latch
SR Flip-flop
JK Flip-flop
D Flip-flop or Delay Flip-flop
T Flip-flop
Conclusion
Bibliography
 Introduction
Flip flops in sequential circuits
What is a sequential circuit?
A sequential circuit is a combinational logic circuit, where the Output depends on current
inputs as well as past inputs. The sequential circuits are also known as Latches because they
function as memory cells and can hold one bit of information. A typical Sequential circuit
consists of two parts which are a Combinational circuit and a Feedback circuit. The feedback
mechanism depends on the history and hence has “memory” property. The past input is
encoded into a set of state variables and stored. When the next sets of inputs are fed to the
circuit it uses the feedback mechanism to feed the state variables to get new set of outputs
and state variables.

Fig: Sequential circuit block diagram

Types of sequential circuits

There are two types of sequential circuits, Asynchronous and Synchronous sequential circuits.
In Asynchronous sequential circuits the output of the logic circuit can change state at any time,
as soon as any input changes its state whereas in the case of synchronous systems a signal
namely clock signal is used to determine/control the exact time at which any output can
change its state. These are also called as clocked sequential circuits.

Fig : Synchronous sequential circuit Fig : Asynchronous sequential circuit

Flip-flops
 A flip flop is a binary storage device. It can store binary bit either 0 or 1. It has two stable states HIGH
and LOW i.e. 1 and 0. It has the property to remain in one state indefinitely until it is directed by an
input signal to switch over to the other state.
  It is also called bistable multivibrator.
 The basic formation of flip flop is to store data.

There are four types of Flip Flops:

 S-R ("set-reset")
 D ("data" or "delay")
 T ("toggle")
 J-K
Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous); the
transparent ones are commonly called latches. The word latch is mainly used for storage
elements, while clocked devices are described as
flip-flops.

S-R Latch
Method of cicuit building
 The SR (Set-Reset) Latch is one of the simplest sequential circuits and consists of two gates
connected. It is the building block of all types of flip-flops.
 The output of each gate is connected to one of the inputs of the other gate.
 The circuit has two active low inputs marked S' and R', as well as two outputs, Q and Q'.

Fig : S-R latch Circuit diagram

Results
 SR latch have two inputs, S and R. S is called set and R is called reset.
 The S input is used to produce HIGH on Q (i.e. store binary 1 in flip-flop).
 The R input is used to produce LOW on Q' (i.e. store binary 0 in flip-flop). Q' is Q complementary
output, so it always holds the opposite value of Q.
 The output of the S-R latch depends on current as well as previous inputs or state, and its state
(value stored) can change as soon as its inputs change.

Truth table
 S-R flip-flop
Method of cicuit building
 The SR latch flip flop required the direct input but no clock to chage its state. It is very use full to add
clock to control precisely the time at which the flip flop changes the state of its output.
 In the clocked RS flip flop the appropriate levels applied to their inputs are blocked till the receipt of a
pulse from an other source called clock. The flip flop changes state only when clock pulse is applied
depending upon the inputs.
 This circuit is formed by adding two AND gates at inputs to the RS flip flop. In addition to control
inputs Set (S) and Reset (R), there is a clock input (C) also.

Fig : S-R Flip-flop circuit diagram

Results
 When S = 0 and R = 0: If we assume Q= 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R+Q')' = 1 and Q' = (S+Q)' = 0.
 Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied would be Q =
(R+Q')' = 0 and Q' = (S+Q)' = 1. So it is clear that when both S and R inputs are LOW, the output is
retained as before the application of inputs. (i.e. there is no state change).
 When S = 1 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R+Q')' = 1 and Q' = (S + Q)' = 0. Assuming Q = 0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R+Q')' = 1 and Q' = (S+Q)' = 0. So in simple words
when S is HIGH and R is LOW, output Q is HIGH.
 When S = 0 and R = 1: If we assume Q= 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R+Q')' = 0 and Q' = (S+Q)' = 1. Assuming Q = 0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R+Q')' = 0 and Q' = (S+Q)' = 1. So in simple words
when S is LOW and R is HIGH, output Q is LOW.
 When S = 1 and R =1: No matter what state Q and Q' are in, application of 1 at input of NOR gate
always results in 0 at output of NOR gate, which results in both Q and Q' set to LOW (i.e. Q = Q').
LOW in both the outputs basically is wrong, so this case is invalid.

Truth table
 JK Flip-Flop
 One of the most useful and versatile flip flop is the JK flip flop due to unique features.
 If the J and K input are both at 1 and the clock pulse is applied, then the output will change state,
regardless of its previous condition.
 If both J and K inputs are at 0 and the clock pulse is applied there will be no change in the output.
 There is no indeterminate condition, in the operation of JK flip flop i.e. it has no ambiguous state.
 It is also known as universal flip-flop because it can be configured to work as a SR, D, T flip-flops.

Method of circuit building

 The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents
the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level
“1”.
 Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”,
“logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to that of an SR Bitable
Latch as seen in the previous tutorial except for the addition of a clock input.

Fig: JK Flip-flop circuit diagram

Results
 When J = 0 and K = 0, These J and K inputs disable the NAND gates, therefore clock pulse have no
effect on the flip flop. In other words, Q returns it last value.
 When J = 0 and K = 1, the upper NAND gate is disabled the lower NAND gate is enabled if Q is 1
therefore, flip flop will be reset (Q = 0, Q' =1) if not already in that state.
 When J = 1 and K = 0, the lower NAND gate is disabled and the upper NAND gate is enabled if is at 1,
As a result we will be able to set the flip flop (Q = 1, Q' = 0) if not already set.
 When J and K are both high, the clock pulses cause the JK flip flop to toggle/Race around.

Truth table
Delay Flip-Flop or D Flip-Flop
 The D type flip-flop has one data input 'D' and a clock input. The circuit edge triggers the
clock input. The flip-flop also has two outputs Q and Q' (where Q' is the reverse of Q).
 Such type of flip flop is a modification of clocked RS flip flop gates from a basic Latch flip
flop and NOR gates modify it in to a clock RS flip flop.
 The D input goes directly to S input and its complement through NOT gate is applied to
the R input.

Method of circuit building

 A D flip-flop, also known as a data flip-flop or delay flip-flop, can be built using SR flip
flops. This is done by connecting a not gate between the S and R inputs and tying them
together. The not gate helps eradicating the possibility of invalid state by inverting the
only signal D, hence maintaining complementarity.

Fig: D Flip-flop circuit diagram

Results
 When the clock is low, both AND gates are disabled, therefore D can change values
without affecting the value of Q.
 When the clock is high, both AND gates are enabled. In this case, Q is forced equal to D.
 When the clock again goes low, Q retains or stores the last value of D.

Truth table
 Toggle Flip Flop or T-Flip-Flop
 A T flip-flop is a two input flip-flop with the inputs being the toggle (T) and a clock (CLK)
input. If the toggle input is HIGH, the T flip-flop changes state (toggles) when the clock
signal is applied. If the toggle input is LOW, the T flip-flop holds the previous state. The T
flip-flop is a synchronous device that switches from one state (high) to the other state
(low) when you toggle. T flip-flops are edge-triggered devices.
 The operation of the T type flip-flop is as follows:
 A '0' input to 'T' will make the next state the same as the present state (i.e. T = 0 present
state = 0 therefore next state = 0).
 However a '1' input to 'T' will change the next state to the inverse of the present state
(i.e. T = 1 present state = 0 therefore next state = 1).

Method of circuit building

 A T flip flop is a modification of the j-k flip-flop. A T flip flop has a single input called T. It can
be constructed by connecting the input of a JK flip-flop. This is sometimes referred to as
converting a JK flip-flop.

Fig: T Flip-flop circuit diagram

Result
 When the T signal is set low (0), it will not affect the present state of the output and the
response will not change.
 When the T signal is set high (1), if the present output status is also high (1), it converts into
low (0); if the present output status is low (0), it converts it into high (1). It means it will
toggle the output signal.

Truth table
 Conclusion
 Flip-flops can be used as a memory element and also as a delay element in
various digital circuits such as :
1. Frequency dividers.
2. Counters.
3. Storage registers.
4. Shift registers.
5. Data storage.
6. Bounce elimination switch.
7. Latch.
8. Data transfer.
 Flip-flop based circuits have advantages such as bistability, memory storage, and
sequential circuit implementation. They're vital in digital systems for data
storage and clocked operations. However, their disadvantages include power
consumption, complexity, and susceptibility to glitches in certain configurations.
 Flip-flops are advantageous over latches as Flip-flops are always stable, while
latches can be unstable. They can also store data even when the power is off,
making them useful for storing data in memory.

Bibliography
 DIGITAL DESIGN - M. MORRIS MANO
 https://www.geeksforgeeks.org/