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15 views5 pages

Coa Exp6

Uploaded by

anshkasaudhan71463
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Experiment No-7

Aim:Design and Verification of the Truth Tables for SRJK,D and T Flip Flops.

Apparatus Used: Simulator.io is an online CAD tool for logic circuits. We will use this platform to
design and Verification of the Truth Tables for SRJK,D and T Flip Flops.
Theory:

Flip-Flops:

Flip flop is popularly known as the basic digital memory circuit. It has its two states as logic 1(High) and
logic 0(low) states. A flip flop is a sequential circuit which consist of single binary state of information or
data. The digital circuit is a flip flop which has two outputs and are of opposite states. It is also known as
a Bistable Multivibrator.

The flip-flops are basically the circuits that maintain a certain state unless and until directed by the input for
changing that state. We can construct a basic flip-flop using four-NOR and four-NAND gates.

Types of Flip-Flops

The flip-flops are of the following types:

1. S-R Flip Flop

2. J-K Flip Flop

3. T Flip Flop

4. D Flip Flop

S-R Flip Flop:

Operations:

Case 1:
PR=CLR=1 The asynchronous inputs are inactive and the flip flop responds freely to the S,R and the CLK
inputs in the normal way.
Case 2:
PR=0 and CLR=1 This is used when the Q is set to 1.
Case 3:
PR=1 and CLR=0 This is used when the Q’ is set to 1.
Case 4:
PR=CLR=0 This is an invalid state.
Characteristics Equation for SR Flip Flop: Q N+1 = QNR’ + SR’

J-K Flip Flop:

Operations:

Case 1:
PR=CLR=0 This condition is in its invalid state.
Case 2:
PR=0 and CLR=1 The PR is activated which means the output in the Q is set to 1. Therefore, the flip
flop is in the set state.
Case 3:
PR=1 and CLR=0 The CLR is activated which means the output in the Q’ is set to 1. Therefore, the
flip flop is in the reset state.
Case 4:
PR=CLR=1 In this condition the flip flop works in its normal way whereas the PR and CLR gets
deactivated.

Race around condition:

When the J and K both are set to 1, the input remains high for a longer duration of time, then the output
keeps on toggling. Toggle means that switching in the output instantly i.e. Q=0, Q’=1 will immediately
change to Q=1 and Q’=0 and this continuation keeps on changing. This change in output leads to race
around condition.
Characteristics Equation for JK Flip Flop: Q N+1 = JQ’N + K’QN

T Flip Flop
Characteristics Equation for T Flip Flop: Q N+1 = Q’NT + QNT’ = QN XOR T

D Flip Flop:
Characteristics Equation for D Flip Flop: Q N+1 = D

Procedure:

1. Place elements on the board like NAND gates.

2. There are several input/output elements to interact with the user during the simulation (likes
buttons or displays).

3. Afterwards connect your elements using the wire tool.

4. Verify the Truth Tables.

Results: The Truth Tables of SRJK,D and T Flip Flops are verified.

Precautions:

1. Connect All the wires carefully.


2. Align the elements properly on the board.
3. Label all the elements properly.

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