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Model Question DS

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Model Question DS

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Roll Number: Register Number:

St.Xavier’s Catholic College of Engineering


Chunkankadai, Nagercoil – 629 003
Model Examination, October 2023
Degree: B.Tech. Department: IT Year/Semester : III/II
Time: 3 Hrs IT22302 – DIGITAL SYSTEMS Maximum Marks: 100
Course Outcomes (COs) for Assessment in this test
CO1 Apply the fundamentals of number system, binary codes, logic gates, Karnaugh Map and memory system.
CO2 Design combinational logic circuits.
CO3 Design synchronous sequential logic circuits.
CO4 Design asynchronous sequential logic circuits.
CO5 Design memory arrays using programmable logic devices.
CL-Cognitive Level; Re-Remember; Un-Understand; Ap-Apply; An-Analyze; Ev-Evaluate; Cr-Create
CO
Q.No. PART – A (10  2 = 20 Marks) CL
Mapping
Mark

1 What is a state diagram? Re CO3 2

2 State the excitation table of JK Flip Flop. Re CO3 2

3 What is a universal shift register? Re CO3 2

4 What is a Mealy circuit? Re CO3 2

5 Define the critical race and non critical race. Un CO4 2

6 What is a Hazard? Re CO4 2

7 Define Merger diagram. Re CO4 2

8 Draw the waveforms showing static 1 hazard? Un CO4 2

9 What is a volatile memory? Give example. Un CO5 2

10 Distinguish between PAL and PLA. Un CO5 2


CO
Q.No. PART – B (5  13 = 65 Marks) CL
Mapping
Mark

i) A sequential circuit with two D flip-flops A and B, one input x and one output z
is specified by the following next-state and output equations:
A(t+1)= A′+B, B(t+1)=B′x, z=A+B′
(1) Draw the logic diagram of the circuit
11.a. Ap CO3 16
(2) Draw the state table
(3) Draw the state diagram of the circuit
ii) Explain the difference between a state table,
characteristics table and excitation table.
OR
Design a synchronous counter that counts the sequence
11.b. 000,001,010,011,100,101,110,111,000 Ap CO3 16
Using D flipflop
12.a. Design an asynchronous sequential circuit with 2 inputs X and Y and with one Ap CO4 16
output Z Wherever Y is 1, input X is transferred to Z. When Y is 0; the output
does not change for any change in X. Use SR latch for implementation of the
circuit.
OR
(a) Explain the Race- free state assignment procedure.
(b) Reduce the number of states in the following state diagram. Tabulated the
reduced state table and draw the reduced state diagram.

12.b. Ap CO4 16

13.a. Implement the switching function F=Σm(1,3,5,7,8,9,14,15) by a static hazard free Ap CO4 16
two level AND OR gate network.
OR
A synchronous sequential circuit is described by the following excitation and
output function Y=X1X2+(X1+X2)Y, Z=Y.
13.b (i) Draw the logic diagram of the circuit. Ap CO4 16
(ii) derive the transition table and output map.
(iii) describe the behaviour of the circuit.
14.a. Implement the following function using PAL F1 (A, B,C) = Σ(1, 2, 4, 6); F2 (A, Ap CO5 16
B, C) = Σ(0, 1, 6, 7); F3 (A, B, C) = Σ(1, 2, 3, 5, 7).

Implement the switching functions.


Z1=ab’d’e+a’b’c’d’e’+bc+de
14.b. Z2=a’c’e Ap CO5 16
Z3=bc+de+c’d’e’+bd
Z4=a’c’e+ce using 5 x 8 x 4 PLA
Design a combinational circuit using ROM that accepts a three bit binary number CO5
15.a Ap 16
and outputs a binary number equal to the square of the input number.

i) Implement the following Boolean functions using 8 x 2 PROM. F1= Σm


15.b. (3,5,6,7) and F2= Σm(1,2,3,4) Ap CO5 16
ii) Implement the following Boolean functions using PLA with 3 inputs, 4 product
terms and 2 outputs. ‘ F1=Σm(3,5,6,7) and F2= Σm (1,2,3,4)

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