OS - Module Question Bank
OS - Module Question Bank
QUESTION-1
Which of the following logical address will produce trap addressing error?
1. 0, 430
2. 1, 11
3. 2, 100
4. 3, 425
5. 4, 95
Calculate the physical address if no trap is produced.
b) Consider six memory partitions of size 200 KB, 400 KB, 600 KB, 500 KB, 300 KB and 250 KB.
These partitions need to be allocated to four processes of sizes 357 KB, 210 KB, 468 KB and 491
KB in that order.
Perform the allocation of processes using-
1. First Fit Algorithm
2. Best Fit Algorithm
3. Worst Fit Algorithm
c) Consider a single level paging scheme. The virtual address space is 4 MB and page size is 4 KB.
What is the maximum page table entry size possible such that the entire page table fits well in one
page?
QUESTION-2
Which of the following logical address will produce trap addressing error?
1. 0, 455
2. 1, 18
3. 2, 99
4. 3, 355
5. 4, 189
b) Let the page fault service time be 10 ms in a computer with average memory access time being 20
ns. If one-page fault is generated for every 106 memory accesses, what is the effective access time
for the memory?
a) 21 ns
b) 30 ns
c) 23 ns
d) 35 ns
c) Consider a single level paging scheme. The virtual address space is 4 GB and page size is 128
KB. What is the maximum page table entry size possible such that the entire page table fits well in
one page?
QUESTION-3
Which of the following logical addresses will not produce a trap addressing error?
1. 0, 200
2. 1, 250
3. 2, 400
4. 3, 50
5. 4, 600
b) Suppose the time to service a page fault is on the average 10 milliseconds, while a memory access
takes 1 microsecond. Then, a 99.99% hit ratio results in average memory access time of-
a) 1.9999 milliseconds
b) 1 millisecond
c) 9.999 microseconds
d) 1.9999 microseconds
c) Consider a single level paging scheme. The virtual address space is 128 TB and page size is 32
MB. What is the maximum page table entry size possible such that the entire page table fits well in
one page?
QUESTION-4
Which of the following logical addresses will not produce a trap addressing error?
1. 0, 250
2. 1, 1000
3. 2, 500
4. 3, 700
5. 4, 200
b) Consider a system with a two-level paging scheme in which a regular memory access takes 150
nanoseconds and servicing a page fault takes 8 milliseconds. An average instruction takes 100
nanoseconds of CPU time and two memory accesses. The TLB hit ratio is 90% and the page fault
rate is one in every 10,000 instructions. What is the effective average instruction execution time?
a) 645 nanoseconds
b) 1050 nanoseconds
c) 1215 nanoseconds
d) 1230 nanoseconds
c) Consider a single level paging scheme. The virtual address space is 256 MB and page table entry
size is 4 bytes. What is the minimum page size possible such that the entire page table fits well in
one page?
QUESTION-5
a) Consider the following heap (figure) in which blank regions are not in use and colored regions are
in use:
The sequence of requests for blocks of size 520, 45, 155, 100 can be satisfied if we use:
a) Either first fit or best fit policy (any one)
b) First fit but not best fit policy
c) Best fit but not first fit policy
b) A demand paging system takes 100 time units to service a page fault and 300 time units to replace
a dirty page. Memory access time is 1-time unit. The probability of a page fault is p. In case of a
page fault, the probability of page being dirty is also p. It is observed that the average access time is
3 time units. Then the value of p is-
a) 0.194
b) 0.233
c) 0.514
d) 0.981
c) Consider a single level paging scheme. The virtual address space is 512 KB and page table entry
size is 2 bytes. What is the minimum page size possible such that the entire page table fits well in
one page?
QUESTION-6
a) Consider the following heap (figure) in which blank regions are not in use and colored regions are
in use:
The sequence of requests for blocks of size 220, 60, 140, 70 can be satisfied if we use:
i. Either first fit or best fit policy (any one)
ii. First fit but not best fit policy
iii. Best fit but not first fit policy
b) Consider a system with byte-addressable memory, 32 bit logical addresses, 4 kilobyte page size
and page table entries of 4 bytes each. The size of the page table in the system in megabytes is?
i. 2
ii. 4
iii. 8
iv. 16
c) Consider a single level paging scheme. The virtual address space is 16 GB and page table entry
size is 4 bytes. What is the minimum page size possible such that the entire page table fits well in
one page?
QUESTION-7
a) Consider the following reference string representing the sequence of page requests:
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1. Suppose you have 3 frames available. Apply the FIFO (First-In-First-Out) page replacement
algorithm to this reference string and determine the number of page faults.
2. Assuming there are 4 frames available, apply the optimal page replacement algorithm (OPT) to
this reference string and calculate the number of page faults.
3. If the number of frames available is 3, apply the LRU (Least Recently Used) page replacement
algorithm to this reference string and determine the number of page faults.
b) Consider a machine with 64 MB physical memory and a 32bit virtual address space. If the page
size is 4 KB, what is the approximate size of the page table?
a) 16 MB
b) 8 MB
c) 2 MB
d) 24 MB
c) Consider a single level paging scheme. The virtual address space is 32 GB and page table entry
size is 8 bytes. What is the minimum page size possible such that the entire page table fits well in
one page?
QUESTION-8
a) Consider the following reference string representing the sequence of page requests:
7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1
1. If the number of frames available is 5, apply the LRU (Least Recently Used) page replacement
algorithm to this reference string and determine the number of page faults.
2. Suppose you have 5 frames available. Apply the FIFO (First-In-First-Out) page replacement
algorithm to this reference string and determine the number of page faults.
3. Assuming there are 3 frames available, apply the optimal page replacement algorithm (OPT) to
this reference string and calculate the number of page faults.
Which of the following logical address will produce trap addressing error?
1. 0, 650
2. 1, 14
3. 2, 110
4. 3, 555
5. 4, 91
Calculate the physical address if no trap is produced.
QUESTION-9
Which of the following logical address will produce trap addressing error?
1. 0, 700
2. 1, 25
3. 2, 180
4. 3, 730
5. 4, 115
Calculate the physical address if no trap is produced.
b) Consider a system using multilevel paging scheme. The page size is 1 GB. The memory is byte
addressable and virtual address is 72 bits long. The page table entry size is 4 bytes.
Find:
1. How many levels of page table will be required?
2. Give the divided physical address and virtual address.
c) Consider a two-level paging scheme where the virtual address space is 64 TB, and each page table
entry occupies 8 bytes. What is the minimum page size required for the second-level page tables
such that the entire page table structure fits well within the virtual address space?
QUESTION-10
a) Consider the following heap (figure) in which blank regions are not in use and colored regions are
in use:
The sequence of requests for blocks of size 205, 45, 120, 70 can be satisfied if we use:
i. Either first fit or best fit policy (any one)
ii. First fit but not best fit policy
iii. Best fit but not first fit policy
b) Consider a system using multilevel paging scheme. The page size is 256 MB. The memory is byte
addressable and virtual address is 72 bits long. The page table entry size is 4 bytes.
Find:
1. How many levels of page table will be required?
2. Give the divided physical address and virtual address.
c) Consider a single level paging scheme. The virtual address space is 128 MB and page size is 8
KB. What is the maximum page table entry size possible such that the entire page table fits well in
one page?