Arquitectura FPGA zybo
The ZYBO (ZYnq BOard) is a feature-rich, ready-to-use, entry-level embedded software
and digital circuit development platform built around the smallest member of the Xilinx
Zynq-7000 family, the Z-7010. The Z-7010 is based on the Xilinx All Programmable
System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core ARM Cortex-
A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. When
coupled with the rich set of multimedia and connectivity peripherals available on the
ZYBO, the Zynq Z-7010 can host a whole system design. The on-board memories, video
and audio I/O, dual-role USB, Ethernet, and SD slot will have your design up-and-ready
with no additional hardware needed. Additionally, six Pmod ports are available to put any
design on an easy growth path.
Zynq AP SoC Architecture
The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS),
and the Programmable Logic (PL). Figure 3 shows an overview of the Zynq AP SoC
architecture, with the PS colored light green and the PL in yellow. Note that the PCIe
Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7010 device.
The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several
dedicated ports and buses that tightly couple it to the PS. The PL also does not contain
the same configuration hardware as a typical 7-series FPGA, and it must be configured
either directly by the processor or via the JTAG port.
The PS consists of many components, including the Application Processing Unit (APU,
which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture
(AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with
their inputs and outputs multiplexed to 54 dedicated pins (called MultiplexedI/O, or MIO
pins). Peripheral controllers that do not have their inputs and outputs connected to MIO
pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface.
The peripheral controllers are connected to the processors as slaves via the AMBA
interconnect and contain readable/writable control registers that are addressable in the
processors’ memory space. The programmable logic is also connected to the
interconnect as a slave, and designs can implement multiple cores in the FPGA fabric
that each also contain addressable control registers. Furthermore, cores implemented in
the PL can trigger interruptions to the processors (connections not shown in Fig. 3) and
perform DMA accesses to DDR3 memory.
Parts of the FPGA
